MC68HC11F1

MOTOROLA
SEMICONDUCTOR
Order this document

by MC68HC11FTS/D
TECHNICAL DATA
MC68HC11F1
MC68HC11FC0
Technical Summary
8-Bit Microcontroller
1 Introduction
The MC68HC11F1 is a high-performance member of the M68HC11 family of microcontroller units
(MCUs). High-speed expanded systems required the development of this chip with its extra input/output
(I/O) ports, an increase in static RAM (one Kbyte), internal chip-select functions, and a non-multiplexed
bus which reduces the need for external interface logic. The timer, serial I/O, and analog-to-digital (A/
D) converter enable functions similar to those found in the MC68HC11E9.
The MC68HC11FC0 is a low cost, high-speed derivative of the MC68HC11F1. It does not have
EEPROM or an analog-to-digital converter. The MC68HC11FC0 can operate at bus speeds as high as
six MHz.
This document provides a brief overview of the structure, features, control registers, packaging information and availability of the MC68HC11F1 and MC68HC11FC0. For detailed information on
M68HC11 subsystems, programming and the instruction set, refer to the M68HC11 Reference Manual
(M68HC11RM/AD).
1.1 Features
MC68HC11 CPU
512 Bytes of On-Chip Electrically Erasable Programmable ROM (EEPROM) with Block Protect
(MC68HC11F1 only)
1024 Bytes of On-Chip RAM (All Saved During Standby)
Enhanced 16-Bit Timer System
3 Input Capture (IC) Functions
4 Output Compare (OC) Functions
4th IC or 5th OC (Software Selectable)
On-Board Chip-Selects with Clock Stretching
Real-Time Interrupt Circuit
8-Bit Pulse Accumulator
Synchronous Serial Peripheral Interface (SPI)
Asynchronous Nonreturn to Zero (NRZ) Serial Communication Interface (SCI)
Power saving STOP and WAIT Modes
Eight-Channel 8-Bit A/D Converter (MC68HC11F1 only)
Computer Operating Properly (COP) Watchdog System and Clock Monitor
Bus Speeds of up to 6 MHz for the MC68HC11FC0 and up to 5 MHz for the MC68HC11F1
68-Pin PLCC (MC68HC11F1 only), 64-Pin QFP (MC68HC11FC0 only), and 80-pin TQFP package options
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MOTOROLA INC., 1997
1.2 Ordering Information

The following devices all have 1024 bytes of RAM. In addition, the MC68HC11F1 devices have 512
bytes of EEPROM. None of the devices contain on-chip ROM.
Table 1 MC68HC11F1 Standard Device Ordering Information
Package
Temperature
Frequency
MC Order Number
0 to +70
5 MHz
MC68HC11F1PU5
2 MHz
MC68HC11F1CPU2
3 MHz
MC68HC11F1CPU3
4 MHz
MC68HC11F1CPU4
5 MHz
MC68HC11F1CPU5
2 MHz
MC68HC11F1VPU2
3 MHz
MC68HC11F1VPU3
-40 to +85C
80-Pin Thin Quad Flat Pack
(TQFP)
(14 mm X 14 mm,
1.4 mm thick)
40 to + 105 C
40 to + 125 C
0 to +70
40 to + 85 C
68-Pin PLCC
40 to + 105 C
40 to + 125 C
4 MHz
MC68HC11F1VPU4
2 MHz
MC68HC11F1MPU2
3 MHz
MC68HC11F1MPU3
4 MHz
MC68HC11F1MPU4
5 MHz
MC68HC11F1FN5
2 MHz
MC68HC11F1CFN2
3 MHz
MC68HC11F1CFN3
4 MHz
MC68HC11F1CFN4
5 MHz
MC68HC11F1CFN5
2 MHz
MC68HC11F1VFN2
3 MHz
MC68HC11F1VFN3
4 MHz
MC68HC11F1VFN4
2 MHz
MC68HC11F1MFN2
3 MHz
MC68HC11F1MFN3
4 MHz
MC68HC11F1MFN4
Table 2 MC68HC11F1 Extended Voltage (3.0 to 5.5 V) Device Ordering Information

Package
Temperature
Frequency
MC Order Number
68-Pin Plastic Leaded Chip

Carrier (PLCC)
0 to +70C
3 MHz
MC68L11F1FN3
40 to +85C
3 MHz
MC68L11F1CFN3

(TQFP)
0 to +70C
3 MHz
MC68L11F1PU3
40 to +85C
3 MHz
MC68L11F1CPU3
MOTOROLA
2
MC68HC11F1/FC0
MC68HC11FTS/D
Table 3 MC68HC11FC0 Standard Device Ordering Information

Package
64-Pin Quad Flat Pack
(QFP)

(TQFP)
Temperature
40 to +85C
0 to 70 C
40 to +85C
0 to 70 C
Frequency
MC Order Number
4 MHz
MC68HC11FC0CFU4
5 MHz
MC68HC11FC0CFU5
6 MHz
MC68HC11FC0FU6
4 MHz
MC68HC11FC0CPU4
5 MHz
MC68HC11FC0CPU5
6 MHz
MC68HC11FC0PU6
Table 4 MC68HC11FC0 Extended Voltage (3.0 to 5.5 V) Device Ordering Information

Package
64-Pin Quad Flat Pack
(QFP)
(TQFP)
MC68HC11F1/FC0
MC68HC11FTS/D
Temperature
0 to +70C
Frequency
MC Order Number
3 MHz
MC68L11FC0FU3
4 MHz
MC68L11FC0FU4
3 MHz
MC68L11FC0PU3
4 MHz
MC68L11FC0PU4
MOTOROLA
3
TABLE OF CONTENTS
Section
Page
Introduction
1.1
1.2
1.3
1
Features ......................................................................................................................................1
Ordering Information ...................................................................................................................2
Block Diagrams ..........................................................................................................................6
Pin Assignments and Signal Descriptions
12.1
12.2
8
MC68HC11F1 Pin Assignments ..................................................................................................8
MC68HC11FC0 Pin Assignments .............................................................................................10
Pin Descriptions ........................................................................................................................12
Control Registers
14
MC68HC11F1 Control Registers ...............................................................................................14
MC68HC11FC0 Control Registers ............................................................................................16
Operating Modes and System Initialization
18
Operating Modes .......................................................................................................................18
Memory Maps ............................................................................................................................19
System Initialization Registers ..................................................................................................20
Resets and Interrupts
25
Interrupt Sources .......................................................................................................................25
Reset and Interrupt Registers ...................................................................................................26
Electrically Erasable Programmable ROM
29
EEPROM Operation ..................................................................................................................29
EEPROM Registers ...................................................................................................................29
EEPROM Programming and Erasure ........................................................................................31
CONFIG Register Programming ...............................................................................................32
Parallel Input/Output
33
Port A ........................................................................................................................................33
Port B ........................................................................................................................................33
Port C ........................................................................................................................................33
Port D ........................................................................................................................................33
Port E ........................................................................................................................................33
Port F .........................................................................................................................................33
Port G ........................................................................................................................................34
Parallel I/O Registers ................................................................................................................34
Chip-Selects
38
Chip-Select Operation ...............................................................................................................38
Chip-Select Registers ................................................................................................................38
Serial Communications Interface (SCI)
42
SCI Block Diagrams ..................................................................................................................42
SCI Registers ............................................................................................................................44
Serial Peripheral Interface
49
SPI Block Diagram ....................................................................................................................49
SPI Registers ............................................................................................................................50
Analog-to-Digital Converter
53
Input Pins ..................................................................................................................................54
Conversion Sequence ...............................................................................................................54
A/D Registers ............................................................................................................................55
Main Timer
57
Timer Operation ........................................................................................................................57
Timer Registers .........................................................................................................................59
13.1
13.2
Pulse Accumulator
64
Pulse Accumulator Block Diagram ............................................................................................64
Pulse Accumulator Registers ....................................................................................................64
2.1
2.2
2.3
3
3.1
3.2
4
4.1
4.2
4.3
5
5.1
5.2
6
6.1
6.2
6.3
6.4
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
8.1
8.2
9
9.1
9.2
10
10.1
10.2
11
11.1
11.2
11.3
12
13
MOTOROLA
4
MC68HC11F1/FC0
MC68HC11FTS/D
REGISTER INDEX
Register
Address
Page
ADCTL ................ A/D Control/Status .........................................................$1030 ..........................55

BAUD .................. Baud Rate......................................................................$102B ..........................44
BPROT................ Block Protect..................................................................$1035 ..........................29
CFORC ............... Timer Force Compare....................................................$100B ..........................59
CONFIG .............. EEPROM Mapping, COP, EEPROM Enables ...............$103F ............. 24, 28, 30
COPRST ............. Arm/Reset COP Timer Circuitry.....................................$103A ..........................27
CSCTL ................ Chip-Select Control........................................................$105D ..........................39
CSGADR............. General-Purpose Chip-Select Address Register ........... $105E .........................40
CSGSIZ............... General-Purpose Chip-Select Size Register ................$105F ..........................40
CSSTRH ............. Clock Stretching.............................................................$105C ..........................38
DDRA .................. Port A Data Register......................................................$1001 ..........................34
DDRC.................. Data Direction Register for Port C .................................$1007 ..........................35
DDRD.................. Data Direction Register for Port D .................................$1009 ..........................36
DDRG.................. Data Direction Register for Port G .................................$1003 ..........................35
HPRIO................. Highest Priority Interrupt and Miscellaneous ................$103C ................... 20, 27
INIT ..................... RAM and I/O Mapping ...................................................$103D ................... 21, 22
OC1D .................. Output Compare 1 Data ................................................$100D ..........................59
OC1M.................. Output Compare 1 Mask ...............................................$100C ..........................59
OPT2................... System Configuration Option Register 2 .......................$1038 ............. 22, 36, 52
OPTION .............. System Configuration Options .......................................$1039 ............. 23, 26, 56
PACNT ................ Pulse Accumulator Count ..............................................$1027 ..........................66
PACTL................. Pulse Accumulator Control ...........................................$1026 ................... 63, 65
PORTA................ Port A Data ....................................................................$1000 ..........................34
PORTB................ Port B Data ....................................................................$1004 ..........................35
PORTC................ Port C Data ....................................................................$1006 ..........................35
PORTD................ Port D Data ....................................................................$1008 ..........................36
PORTE................ Port E Data ....................................................................$100A ..........................36
PORTF ................ Port F Data ....................................................................$1005 ..........................35
PORTG ............... Port G Data....................................................................$1002 ..........................34
PPROG ............... EEPROM Programming Control ....................................$103B ..........................30
SCCR1 ................ SCI Control 1 ................................................................$102C ..........................46
SCCR2 ................ SCI Control 2 ................................................................$102D ..........................46
SCDR .................. Serial Communications Data Register...........................$102F ..........................48
SCSR .................. SCI Status......................................................................$102E ..........................47
SPCR .................. Serial Peripheral Control ...............................................$1028 ..........................50
SPDR .................. SPI Data .......................................................................$102A ..........................51
SPSR .................. Serial Peripheral Status .................................................$1029 ..........................51
TCNT................... Timer Count ..................................................................$100E, $100F ..............59
TCTL1 ................. Timer Control 1 ..............................................................$1020 ..........................60
TCTL2 ................. Timer Control 2 ..............................................................$1021 ..........................61
TEST1 ................. Factory Test ..................................................................$103E ..........................24
TFLG1 ................. Timer Interrupt Flag 1 ...................................................$1023 ..........................61
TFLG2 ................. Timer Interrupt Flag 2 ...................................................$1025 ................... 62, 65
TI4O5 .................. Timer Input Capture 4/Output Compare 5 ....................$101E, $101F ..............60
TIC1TIC3........... Timer Input Capture ......................................................$1010$1015 ..............60
TMSK1 ................ Timer Interrupt Mask 1 ..................................................$1022 ..........................61
TMSK2 ................ Timer Interrupt Mask 2 ..................................................$1024 ................... 62, 64
TOC1TOC4 ....... Timer Output Compare .................................................$1016$101D ..............60
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
5
1.3 Block Diagrams
VDD
VSS
XTAL
4XOUT
IRQ
EXTAL
XIRQ RESET
MODA/
LIR
MODB/
VSTBY
OSCILLATOR
DDRA
PORT A
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PULSE
ACCUMULATOR
OC2/OC1
OC3/OC1
OC4/OC1
IC4/OC5/OC1
IC3
IC2
IC1
COP
TIMER
SYSTEM
PERIODIC INTERRUPT
A/D
CONVERTER
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
512 BYTES EEPROM
CSPROG
CSGEN
CSIO1
CSIO2
1024 BYTES STATIC RAM
VRH
VRL
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PORT E
PAI/0C1
PA7
MODE
CONTROL
INTERRUPT
LOGIC
DDRG
POWER
PORT G
CLOCK
LOGIC
CHIP
SELECTS
DATA BUS
MISO
MOSI
SCK
SS
SPI
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDRESS BUS
PD0
PD1
RxD
TxD
DDRD
SCI
PORT D
CPU
CORE
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
PD2
PD3
PD4
PD5
PORT C
R/W
DDRC
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PORT F
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PORT B
Figure 1 MC68HC11F1 Block Diagram
MOTOROLA
6
MC68HC11F1/FC0
MC68HC11FTS/D
VDD
VSS
DS
E 4XOUT XTAL
EXTAL
IRQ
MODA /
LIR
XIRQ RESET
MODB /
VSTBY
OSCILLATOR
CSPROG
CSGEN
CSIO1
CSIO2
TIMER
SYSTEM
CHIP
SELECTS
PERIODIC INTERRUPT
SCI
PD2
PD3
PD4
PD5
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
PORT C
DDRC
R/W
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PORT F
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PORT B
PD0
PD1
RxD
TxD
DATA BUS
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDRESS BUS
WAIT
MISO
MOSI
SCK
SS
SPI
CPU
CORE
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PE6
PE5
PE4
PE3
PE2
PE1
PORT E
1024 BYTES STATIC RAM
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
DDRG
OC2/OC1
OC3/OC1
OC4/OC1
IC4/OC5/OC1
IC3
IC2
IC1
COP
PORT G
DDRA
PORT A
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PULSE
ACCUMULATOR
DDRD
PAI/0C1
PA7
MODE
CONTROL
INTERRUPT
LOGIC
PORT D
CLOCK
LOGIC
POWER
Figure 2 MC68HC11FC0 Block Diagram
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
7
2 Pin Assignments and Signal Descriptions
PE7/AN7
PE3/AN3
PE6/AN6
PE2/AN2
PE5/AN5
PE1/AN1
64
63
62
61
MODB/VSTBY
2
65
MODA/LIR
3
66
E
4
VRL
R/W
5
67
EXTAL
6
VRH
XTAL
7
VSS
4XOUT
8
68
PC0/DATA0
9
2.1 MC68HC11F1 Pin Assignments
10
60
PE4/AN4
PC2/DATA2
11
59
PE0/AN0
PC3/DATA3
12
58
PF0/ADDR0
PC4/DATA4
13
57
PF1/ADDR1
PC5/DATA5
14
56
PF2/ADDR2
PC6/DATA6
15
55
PF3/ADDR3
PC7/DATA7
16
RESET
17
XIRQ
18
IRQ
19
PG7/CSPROG
20
PG6/CSGEN
21
PG5/CSIO1
22
PG4/CSIO2
23
PG3
24
PG2
25
PG1
26
PC1/DATA1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
PG0
PD0/RxD
PD1/TxD
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
VDD
PA7/PAI/OC1
PA6/OC2/OC1
PA5/OC3/OC1
PA4/OC4/OC1
PA3/OC5/IC4/OC1
PA2/IC1
PA1/IC2
PA0/IC3
PB7/ADDR15
MC68HC11F1
54
PF4/ADDR4
53
PF5/ADDR5
52
PF6/ADDR6
51
PF7/ADDR7
50
PB0/ADDR8
49
PB1/ADDR9
48
PB2/ADDR10
47
PB3/ADDR11
46
PB4/ADDR12
45
PB5/ADDR13
44
PB6/ADDR14
Figure 3 MC68HC11F1 68-Pin PLCC Pin Assignments
MOTOROLA
8
MC68HC11F1/FC0
MC68HC11FTS/D
NC
NC
PB7/ADDR15
PA0/IC3
PA1/IC2
PA2/IC1
PA3/OC5/IC4/OC1
PA4/OC4/OC1
PA5/OC3/OC1
PA6/OC2/OC1
PA7/PAI/OC1
VDD
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TXD
PD0/RXD
PG0
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
NC
60
NC
NC
59
PG1
PB6/ADDR14
58
PG2
PB5/ADDR13
57
PG3
PB4/ADDR12
56
PG4/CSIO2
PB3/ADDR11
55
PG5/CSIO1
PB2/ADDR10
54
PG6/CSGEN
PB1/ADDR9
53
PG7/CSPROG
PB0/ADDR8
52
IRQ
PF7/ADDR7
10
51
XIRQ
PF6/ADDR6
11
50
RESET
PF5/ADDR5
12
49
PC7/DATA7
PF4/ADDR4
13
48
PC6/DATA6
PF3/ADDR3
14
47
PC5/DATA5
PF2/ADDR2
15
46
PC4/DATA4
PF1/ADDR1
16
45
PC3/DATA3
PF0/ADDR0
17
44
PC2/DATA2
PE0/AN0
18
43
PC1/DATA1
PE4/AN4
19
42
NC
NC
20
41
NC
39
40
4XOUT
33
MODA/LIR
PC0/DATA0
32
38
31
VSS
MODB/VSTBY
NC
30
VRL
VRH
37
29
PE7/AN7
36
28
PE3/AN3
XTAL
27
PE6/AN6
EXTAL
26
PE2AN2
34
25
PE5/AN5
35
24
PE1/AN1
23
NC
R/W
21
22
NC
MC68HC11F1
Figure 4 Pin Assignments for the MC68HC11F1 80-Pin QFP
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
9
PB7/ADDR15
PA0/IC3
PA1/IC2
PA2/IC1
PA3/IC4/OC5/OC1
PA4/OC4/OC1
PA5/OC3/OC1
PA6/OC2/OC1
PA7/PAI/OC1
VDD
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TxD
PD0/RxD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
2.2 MC68HC11FC0 Pin Assignments
48
PG2
PB5/ADDR13
47
PG3
PB4/ADDR12
46
PG4/CSIO2
PB3/ADDR11
45
PG5/CSIO1
PB2/ADDR10
44
PG6/CSGEN
PB1/ADDR9
43
PG7/CSPROG
PB0/ADDR8
42
IRQ
PF7/ADDR7
41
XIRQ
PB6/ADDR14
MC68HC11FC0
29
30
31
32
R/W
XTAL
PC0/DATA0
PE2
EXTAL
PC1/DATA1
28
33
16
27
VSS
26
PC2/DATA2
DS
PC3/DATA3
34
MODB/VSTBY
35
15
25
14
PF0/ADDR0
24
PF1/ADDR1
VSS
PC4/DATA4
MODA/LIR
PC5/DATA5
36
23
37
13
22
12
PF2/ADDR2
WAIT
PF3/ADDR3
21
PC6/DATA6
PE3
38
VDD
11
20
PF4/ADDR4
PE6
PC7/DATA7
18
19
RESET
39
17
40
10
PE5
PF5/ADDR5
PE1
PF6/ADDR6
Figure 5 MC68HC11FC0 64-Pin QFP Pin Assignments
MOTOROLA
10
MC68HC11F1/FC0
MC68HC11FTS/D
PD5/SS
PD4/SCK
PD3/MOSI
68
67
66
NC
VDD
69
PG0
PA7/PAI/OC1
70
61
PA6/OC2/OC1
71
62
PA5/OC3/OC1
72
PD0/RXD
PA4/OC4/OC1
73
63
PA3/IC4/OC5/OC1
74
64
PA2/IC1
75
PD2/MISO
PA1/IC2
76
PD1/TXD
PA0/IC3
77
65
PB7/ADDR15
78
NC
79
80
NC
60
NC
NC
59
PG1
PB6/ADDR14
58
PG2
PB5/ADDR13
57
PG3
PB4/ADDR12
56
PG4/CSIO0
PB3/ADDR11
55
PG5/CSIO1
PB2/ADDR10
54
PG6/CSGEN
PB1/ADDR9
53
PG7/CSPROG
PB0/ADDR8
52
IRQ
PF7/ADDR7
10
51
XIRQ
PF6/ADDR6
11
50
RESET
PF5/ADDR5
12
49
PC7/DATA7
PF4/ADDR4
13
48
PC6/DATA6
PF3/ADDR3
14
47
PC5/DATA5
PF2/ADDR2
15
46
PC4/DATA4
PF1/ADDR1
16
45
PC3/DATA3
PF0/ADDR0
17
44
PC2/DATA2
VSS
18
43
PC1/DATA1
PE4
19
42
NC
NC
20
41
NC
40
34
4XOUT
33
DS
PC0/DATA0
32
39
31
VSS
MODB/VSTBY
38
30
WAIT
MODA/LIR
NC
29
37
28
VDD
36
27
PE3
XTAL
26
PE6
EXTAL
25
PE2
35
24
PE5
R/W
22
23
PE1
NC
NC
21
MC68HC11FC0
Figure 6 MC68HC11FC0 80-Pin TQFP Pin Assignments
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
11
2.3 Pin Descriptions

VDD and VSS
VDD is the positive power input to the MCU, and VSS is ground.
RESET
This active-low input initializes the MCU to a known startup state. It also acts as an open-drain
output to indicate that an internal failure has been detected in either the clock monitor or the COP
watchdog circuits.
XTAL and EXTAL
These two pins provide the interface for either a crystal or a CMOS-compatible clock to drive the
internal clock circuitry. The frequency applied to these pins is four times the desired bus
frequency (E clock).
E
This pin provides an output for the E clock, the basic timing reference signal for the bus circuitry.
The address bus is active when E is low, and the data bus is active when E is high.
DS
The data strobe output is the inverted E clock. DS is present on the MC68HC11FC0 only.
WAIT
This input is used to stretch the bus cycle to accomodate slower devices. The MCU samples the
logic level at this pin on the rising edge of E clock. If it is high, the MCU holds the E clock high for
the next four EXTAL clock cycles. If it is low, the E clock responds normally, going low two
EXTAL cycles later. The WAIT pin is present on the MC68HC11FC0 only.
4XOUT
This pin provides a buffered oscillator signal to drive another M68HC11 MCU. The 4XOUT pin is
not present on the 64-pin QFP MC68HC11FC0 package.
IRQ
This active-low input provides a means of generating asynchronous, maskable interrupt requests
for the CPU.
XIRQ
This interrupt request input can be made non-maskable by clearing the X bit in the MCUs
condition code register.
MODA/LIR and MODB/VSTBY
The logic level applied to the MODA and MODB pins at reset determines the MCUs opreating
mode (see Table 7 in 4 Operating Modes and System Initialization). After reset, MODA
functions as LIR, an open-drain output that indicates the start of an instruction cycle. MODB
functions as VSTBY, providing a backup battery to maintain the contents of RAM when VDD falls.
R/W
In expanded and test modes, R/W indicates the direction of transfers on the external data bus.
VRH and VRL
These pins provide the reference voltage for the analog-to-digital converter. Use bypass
capacitors to minimize noise on these signals. Any noise on VRH and VRL will directly affect A/D
accuracy. These pins are not present on the MC68HC11FC0.
MOTOROLA
12
MC68HC11F1/FC0
MC68HC11FTS/D
Port Signals
On the MC68HC11F1, 54 pins are arranged into six 8-bit ports (ports A, B, C, E, F, and G) and
one 6-bit port (port D). On the MC68HC11FC0, either 52 or 49 pins are available, depending on
the package. General-purpose I/O port signals are discussed briefly in the following pragraphs.
For additional information, refer to 7 Parallel Input/Output.
Port A Pins
Port A is an 8-bit general-purpose I/O port (PA[7:0]) with a data register (PORTA) and a data
direction register (DDRA). Port A pins share functions with the 16-bit timer system. Out of reset,
PA[7:0] are general-purpose high-impedance inputs.
Port B Pins
Port B is an 8-bit output-only port. In single-chip modes, port B pins are general-purpose output
pins (PB[7:0]). In expanded modes, port B pins act as the high-order address lines ADDR[15:8].
Port C Pins
Port C is an 8-bit general-purpose I/O port with a data register (PORTC) and a data direction
register (DDRC). In single-chip modes, port C pins are general-purpose I/O pins PC[7:0]. In
expanded modes, port C pins are configured as data bus pins DATA[7:0].
Port D Pins
Port D is a 6-bit general-purpose I/O port with a data register (PORTD) and a data direction
register (DDRD). The six port D lines PD[5:0] can be used for general-purpose I/O or for the serial
communications interface (SCI) or serial peripheral interface (SPI) subsystems.
Port E Pins
Port E is an 8-bit input-only port that is also used as the analog input port for the analog-to-digital
converter. Port E pins that are not used for the A/D system can be used as general-purpose
inputs. However, PORTE should not be read during the sample portion of an A/D conversion
sequence.
NOTE
The A/D system is not available on the MC68HC11FC0. PE7 and PE0 are not
available on the 80-pin MC68HC11FC0. PE7, PE4, and PE0 are not available on
the 64-pin MC68HC11FC0.
Port F Pins
Port F is an 8-bit output-only port. In single-chip mode, port F pins are general-purpose output
pins PF[7:0]. In expanded mode, port F pins act as the low-order address outputs ADDR[7:0].
Port G Pins
Port G is an 8-bit general-purpose I/O port. When enabled, four chip select signals are alternate
functions of PG[7:4].
NOTE
PG[1:0] are not available on the 64-pin MC68HC11FC0.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
13
3 Control Registers
The MC68HC11F1 and MC68HC11FC0 control registers determine most of the systems operating
characteristics. They occupy a 96-byte relocatable memory block. Their names and bit mnemonics are
summarized in the following table. Addresses shown are the default locations out of reset.
3.1 MC68HC11F1 Control Registers
Table 5 MC68HC11F1 Register and Control Bit Assignments
$1000
Bit 7
PA7
6
PA6
5
PA5
4
PA4
3
PA3
2
PA2
1
PA1
Bit 0
PA0
$1001
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
$1002
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
$1003
DDG7
DDG6
DDG5
DDG4
DDG3
DDG2
DDG1
DDG0
DDRG
$1004
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PORTB
$1005
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PORTF
$1006
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PORTC
$1007
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
$1008
PD5
PD4
PD3
PD2
PD1
PD0
$1009
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
DDRD
$100A
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PORTE
$100B
FOC1
FOC2
FOC3
FOC4
FOC5
CFORC
$100C
OC1M7
OC1M6
OC1M5
OC1M4
OC1M3
OC1M
$100D
OC1D7
OC1D6
OC1D5
OC1D4
OC1D3
OC1D
$100E
$100F
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TCNT (High)
TCNT (Low)
$1010
$1011
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TIC1 (High)
TIC1 (Low)
$1012
$1013
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TIC2 (High)
TIC2 (Low)
$1014
$1015
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TIC3 (High)
TIC3 (Low)
$1016
$1017
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TOC1 (High)
TOC1 (Low)
$1018
$1019
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TOC2 (High)
TOC2 (Low)
$101A
$101B
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TOC3 (High)
TOC3 (Low)
$101C
$101D
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TOC4 (High)
TOC4 (Low)
$101E
$101F
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TI4/O5 (High)
TI4/O5 (Low)
$1020
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
TCTL1
$1021
EDG4B
EDG4A
EDG1B
EDG1A
EDG2B
EDG2A
EDG3B
EDG3A
TCTL2
MOTOROLA
14
PORTA
DDRA
PORTG
DDRC
PORTD
MC68HC11F1/FC0
MC68HC11FTS/D
Table 5 MC68HC11F1 Register and Control Bit Assignments (Continued)

Bit 7
Bit 0
$1022
$1023
OC1I
OC1F
OC2I
OC2F
OC3I
OC3F
OC4I
OC4F
I4/O5I
I4/O5F
IC1I
IC1F
IC2I
IC2F
IC3I
IC3F
TMSK1
TFLG1
$1024
TOI
RTII
PAOVI
PAII
PR1
PR0
TMSK2
$1025
TOF
RTIF
PAOVF
PAIF
TFLG2
$1026
PAEN
PAMOD
PEDGE
I4/05
RTR1
RTR0
PACTL
$1027
Bit 7
Bit 0
PACNT
$1028
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
SPCR
$1029
SPIF
WCOL
MODF
SPSR
$102A
Bit 7
Bit 0
SPDR
$102B
TCLR
SCP2
SCP1
SCP0
RCKB
SCR2
SCR1
SCR0
BAUD
$102C
R8
T8
WAKE
SCCR1
$102D
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
SCCR2
$102E
TDRE
TC
RDRF
IDLE
OR
NF
FE
SCSR
$102F
Bit 7
Bit 0
SCDR
$1030
CCF
SCAN
MULT
CD
CC
CB
CA
ADCTL
$1031
Bit 7
Bit 0
ADR1
$1032
Bit 7
Bit 0
ADR2
$1033
Bit 7
Bit 0
ADR3
$1034
Bit 7
Bit 0
ADR4
$1035
PTCON
BPRT3
BPRT2
BPRT1
BPRT0
BPROT
$1036
Reserved
$1037
Reserved
$1038
GWOM
CWOM
CLK4X
LIRDV
SPRBYP
$1039
IRQE
DLY
CME
FCME
CR1
CR0
OPTION
$103A
Bit 7
Bit 0
COPRST
$103B
ODD
EVEN
BYTE
ROW
ERASE
EELAT
EEPGM
PPROG
$103C
RBOOT
SMOD
MDA
IRV
PSEL3
PSEL2
PSEL1
PSEL0
HPRIO
$103D
RAM3
RAM2
RAM1
RAM0
REG3
REG2
REG1
REG0
INIT
$103E
TILOP
OCCR
CBYP
DISR
FCM
FCOP
$103F
EE3
EE2
EE1
EE0
NOCOP
EEON
$1040
to
$105B
OPT2
TEST1
CONFIG
Reserved
Reserved
$105C
I01SA
I01SB
I02SA
I02SB
GSTHA
GSTGB
PSTHA
PSTHB
CSSTRH
$105D
I01EN
I01PL
I02EN
I02PL
GCSPR
PCSEN
PSIZA
PSIZB
CSCTL
$105E
GA15
GA14
GA13
GA12
GA11
GA10
CSGADR
$105F
I01AV
I02AV
GNPOL
GAVLD
GSIZA
GSIZB
GSIZC
CSGSIZ
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
15
3.2 MC68HC11FC0 Control Registers

Table 6 MC68HC11FC0 Register and Control Bit Assignments
$1000
Bit 7
PA7
6
PA6
5
PA5
4
PA4
3
PA3
2
PA2
1
PA1
Bit 0
PA0
$1001
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
$1002
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
$1003
DDG7
DDG6
DDG5
DDG4
DDG3
DDG2
DDG1
DDG0
DDRG
$1004
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PORTB
$1005
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PORTF
$1006
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PORTC
$1007
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
$1008
PD5
PD4
PD3
PD2
PD1
PD0
$1009
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
DDRD
$100A
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PORTE
$100B
FOC1
FOC2
FOC3
FOC4
FOC5
CFORC
$100C
OC1M7
OC1M6
OC1M5
OC1M4
OC1M3
OC1M
$100D
OC1D7
OC1D6
OC1D5
OC1D4
OC1D3
OC1D
$100E
$100F
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TCNT (High)
TCNT (Low)
$1010
$1011
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TIC1 (High)
TIC1 (Low)
$1012
$1013
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TIC2 (High)
TIC2 (Low)
$1014
$1015
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TIC3 (High)
TIC3 (Low)
$1016
$1017
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TOC1 (High)
TOC1 (Low)
$1018
$1019
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TOC2 (High)
TOC2 (Low)
$101A
$101B
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TOC3 (High)
TOC3 (Low)
$101C
$101D
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TOC4 (High)
TOC4 (Low)
$101E
$101F
Bit 15
Bit 7
14
6
13
5
12
4
11
3
10
2
9
1
Bit 8
Bit 0
TI4/O5 (High)
TI4/O5 (Low)
$1020
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
TCTL1
$1021
EDG4B
EDG4A
EDG1B
EDG1A
EDG2B
EDG2A
EDG3B
EDG3A
TCTL2
$1022
$1023
OC1I
OC1F
OC2I
OC2F
OC3I
OC3F
OC4I
OC4F
I4/O5I
I4/O5F
IC1I
IC1F
IC2I
IC2F
IC3I
IC3F
TMSK1
TFLG1
$1024
TOI
RTII
PAOVI
PAII
PR1
PR0
TMSK2
$1025
TOF
RTIF
PAOVF
PAIF
TFLG2
MOTOROLA
16
PORTA
DDRA
PORTG
DDRC
PORTD
MC68HC11F1/FC0
MC68HC11FTS/D
Table 6 MC68HC11FC0 Register and Control Bit Assignments (Continued)

Bit 7
Bit 0
$1026
PAEN
PAMOD
PEDGE
I4/05
RTR1
RTR0
PACTL
$1027
Bit 7
Bit 0
PACNT
$1028
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
SPCR
$1029
SPIF
WCOL
MODF
SPSR
$102A
Bit 7
Bit 0
SPDR
$102B
TCLR
SCP2
SCP1
SCP0
RCKB
SCR2
SCR1
SCR0
BAUD
$102C
R8
T8
WAKE
SCCR1
$102D
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
SCCR2
$102E
TDRE
TC
RDRF
IDLE
OR
NF
FE
SCSR
$102F
Bit 7
Bit 0
SCDR
$1030
to
$1037
Reserved
Reserved
$1038
GWOM
CWOM
CLK4X
LIRDV
SPRBYP
$1039
IRQE
DLY
CME
FCME
CR1
CR0
OPTION
$103A
Bit 7
Bit 0
COPRST
$103B
OPT2
Reserved
$103C
RBOOT
SMOD
MDA
IRV
PSEL3
PSEL2
PSEL1
PSEL0
HPRIO
$103D
RAM5
RAM4
RAM3
RAM2
RAM1
RAM0
REG1
REG0
INIT
$103E
TILOP
OCCR
CBYP
DISR
FCM
FCOP
TEST1
$103F
NOCOP
CONFIG
$1040
to
$105B
Reserved
Reserved
$105C
I01SA
I01SB
I02SA
I02SB
GSTHA
GSTGB
PSTHA
PSTHB
CSSTRH
$105D
I01EN
I01PL
I02EN
I02PL
GCSPR
PCSEN
PSIZA
PSIZB
CSCTL
$105E
GA15
GA14
GA13
GA12
GA11
GA10
CSGADR
$105F
I01AV
I02AV
GNPOL
GAVLD
GSIZA
GSIZB
GSIZC
CSGSIZ
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
17
4 Operating Modes and System Initialization

The 16-bit address bus can access 64 Kbytes of memory. Because the MC68HC11F1 and
MC68HC11FC0 are intended to operate principally in expanded mode, there is no internal ROM and
the address bus is non-multiplexed. Both devices include 1 Kbyte of static RAM, a 96-byte control register block, and 256 bytes of bootstrap ROM. The MC68HC11F1 also includes 512 bytes of EEPROM.
RAM and registers can be remapped on both the MC68HC11F1 and the MC68HC11FC0. On both the
MC68HC11F1 and the MC68HC11FC0, out of reset RAM resides at $0000 to $03FF and registers reside at $1000 to $105F. On the MC68HC11F1, RAM and registers can both be remapped to any 4Kbyte boundary. On the MC68HC11FC0, RAM can be remapped to any 1-Kbyte boundary, and registers can be remapped to any 4-Kbyte boundary in the first 16 Kbytes of address space.
RAM and control register locations are defined by the INIT register, which can be written only once within the first 64 E-clock cycles after a reset in normal modes. It becomes a read-only register thereafter.
If RAM and the control register block are mapped to the same boundary, the register block has priority
of the first 96 bytes.
In expanded and special test modes in the MC68HC11F1, EEPROM is located from $xE00 to $xFFF,
where x represents the value of the four high-order bits of the CONFIG register. EEPROM is enabled
by the EEON bit of the CONFIG register. In single-chip and bootstrap modes, the EEPROM is located
from $FE00 to $FFFF.
4.1 Operating Modes
Bootstrap ROM resides at addresses $BF00$BFFF, and is only available when the MCU operates in
special bootstrap operating mode. Operating modes are determined by the logic levels applied to the
MODB and MODA pins at reset.
In single-chip mode, the MCU functions as a self-contained microcontroller and has no external address
or data bus. Ports B, C and F are available for general-purpose I/O (GPIO). Ports B and F are outputs
only; each of the port C pins can be configured as input or output.
CAUTION
The MC68HC11FC0 must not be configured to boot in single-chip mode because
it has no internal ROM or EEPROM. Operation of the device in single-chip mode
will result in erratic behavior.
In expanded mode, the MCU can access external memory. Ports B and F provide the address bus, and
port C is the data bus.
Special bootstrap mode is a variation of single chip mode that provides access to the internal bootstrap
ROM. In this mode, the user can download a program into on-chip RAM through the serial communication interface (SCI).
Special test mode, a variation of expanded mode, is primarily used during Motorolas internal production
testing, but can support emulation and debugging during program development.
Table 7 shows a summary of operating modes, mode select pins, and control bits in the HPRIO register.
Table 7 Hardware Mode Select Summary
Input Pins
MODB
MODA
1
0
1
1
0
0
0
1
MOTOROLA
18
Mode Description
Single Chip
Expanded
Special Bootstrap
Special Test
Control Bits in HPRIO (Latched at Reset)

RBOOT
SMOD
MDA
0
0
0
0
0
1
1
1
0
0
1
1
MC68HC11F1/FC0
MC68HC11FTS/D
4.2 Memory Maps
$0000
x000
1024 BYTES RAM1

$03FF
EXTERNAL
x3FF
EXTERNAL
$1000
$105F
y000
96-BYTE REGISTER FILE2
y05F
EXTERNAL
EXTERNAL
$BFC0
$BF00
$BFFF
256 BYTES
BOOTSTRAP
ROM
$BFFF
RESERVED4
512
BYTES
EEPROM5
$FE00
$FFC0
$FFFF
SPECIAL
MODE
INTERRUPT
VECTORS3
SINGLE
CHIP
EXPANDED
SPECIAL
BOOTSTRAP
SPECIAL
TEST
MODA = 0
MODB = 1
MODA = 1
MODB = 1
MODA = 0
MODB = 0
MODA = 1
MODB = 0
$FFC0
NORMAL
MODE
INTERRUPT
VECTORS
$FFFF
NOTES:
1. RAM can be remapped to any 4-Kbyte boundary ($x000). x represents the value contained in RAM[3:0] in the
INIT register.
2. The register block can be remapped to any 4-Kbyte boundary ($y000). y represents the value contained in
REG[3:0] in the INIT register.
3. Special test mode vectors are externally addressed.
4. In special test mode the address locations $zD00$zDFF are not externally addressable. z represents the value of bits EE[3:0] in the CONFIG register.
5. EEPROM can be remapped to any 4-Kbyte boundary ($z000). z represents the value contained in EE[3:0] in
the CONFIG register.
Figure 7 MC68HC11F1 Memory Map
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
19
$0000
1024 BYTES RAM1
$03FF
EXTERNAL
EXTERNAL
$1000
$105F
EXTERNAL
96-BYTE REGISTER FILE2
EXTERNAL
$BFC0
$BF00
$BFFF
SPECIAL
MODE
INTERRUPT
VECTORS
256 BYTES
BOOTSTRAP
ROM
$BFFF
$FFC0
NORMAL
MODE
INTERRUPT
VECTORS
$FFFF
$FE00
$FFC0
$FFFF
SINGLE
CHIP
EXPANDED
SPECIAL
BOOTSTRAP
SPECIAL
TEST
MODA = 0
MODB = 1
MODA = 1
MODB = 1
MODA = 0
MODB = 0
MODA = 1
MODB = 0
NOTES:
1. RAM can be remapped to any 1-Kbyte boundary, depending on the value contained in the RAM field in the INIT
register.
2. The register block can be remapped to $0000, $2000, or $3000, depending on the value contained in REG[1:0]
in the INIT register.
Figure 8 MC68HC11FC0 Memory Map

4.3 System Initialization Registers
HPRIO Highest Priority Interrupt and Miscellaneous
$x03C
Bit 7
Bit 0
RBOOT
SMOD
MDA
IRV
PSEL3
PSEL2
PSEL1
PSEL0
Single-Chip
Expanded
Bootstrap
Special Test
RESET:
MOTOROLA
20
MC68HC11F1/FC0
MC68HC11FTS/D
RBOOT Read Bootstrap ROM

RBOOT is valid only when SMOD is set to one (special bootstrap or special test mode). RBOOT can
only be written in special modes but can be read anytime.
0 = Boot loader ROM disabled and not in memory map
1 = Boot loader ROM enabled and in memory map at $BF00$BFFF
SMOD and MDA Special Mode Select and Mode Select A
The initial value of SMOD is the inverse of the logic level present on the MODB pin at the rising edge
of reset. The initial value of MDA equals the logic level present on the MODA pin at the rising edge of
reset. These two bits can be read at any time. They can be written at any time in special modes. Neither
bit can be written in normal modes. SMOD cannot be set once it has been cleared. Refer to Table 8.
Table 8 Hardware Mode Select Summary
Input Pins
Mode Description
Control Bits in HPRIO (Latched at Reset)
MODB
MODA
RBOOT
SMOD
MDA
Single Chip
Expanded
Special Bootstrap
Special Test
IRV Internal Read Visibility

This bit can be read at any time. It can be written at any time in special modes, but only once in normal
modes. In single-chip and bootstrap modes, IRV has no meaning or effect.
0 = Internal reads not visible
1 = Data from internal reads is driven on the external data bus
PSEL[3:0] See 5.2 Reset and Interrupt Registers, page 27.
INIT RAM and I/O Mapping (MC68HC11FC0 only)
RESET:
$x03D
Bit 7
Bit 0
RAM5
RAM4
RAM3
RAM2
RAM1
RAM0
REG1
REG0
The INIT register can be written only once in first 64 cycles out of reset in normal modes, or at any time
in special modes.
NOTE
The register diagram above applies to the MC68HC11FC0 only. A diagram and bit
descriptions of the INIT register in the MC68HC11F1 are provided elsewhere in
this section.
RAM[5:0] Internal RAM Map Position
These bits determine the upper six bits of the RAM address and allow mapping of the RAM to any oneKbyte boundary.
REG[1:0] Register Block Map Position
These bits determine the location of the register block, as shown in Table 9.
Table 9 Register Block Location
MC68HC11F1/FC0
MC68HC11FTS/D
REG[1:0]
Register Block Address
00
$0000 $005F
01
$1000 $105F
10
$2000 $205F
11
$3000 $305F
MOTOROLA
21
INIT RAM and I/O Mapping (MC68HC11F1 only)
$x03D
Bit 7
Bit 0
RAM3
RAM2
RAM1
RAM0
REG3
REG4
REG1
REG0
RESET:
The INIT register can be written only once in first 64 cycles out of reset in normal modes, or at any time
in special modes.
NOTE
The register diagram above applies to the MC68HC11F1 only. A diagram and bit
descriptions of the INIT register in the MC68HC11FC0 are provided elsewhere in
this section.
RAM[3:0] Internal RAM Map Position
These bits determine the upper four bits of the RAM address and allow mapping of the RAM to any fourKbyte boundary. Refer to Table 10.
REG[3:0] 96-Byte Register Block Map Position
These bits determine bits the upper 4 bits of the register block and allow mapping of the register block
to any four-Kbyte boundary. Refer to Table 10.
Table 10 RAM and Register Mapping
RAM[3:0]
Location
REG[3:0]
Location
0000
$0000-$03FF
0000
$0000-$005F
0001
$1000-$13FF
0001
$1000-$105F
0010
$2000-$23FF
0010
$2000-$205F
0011
$3000-$33FF
0011
$3000-$305F
0100
$4000-$43FF
0100
$4000-$405F
0101
$5000-$53FF
0101
$5000-$505F
0110
$6000-$63FF
0110
$6000-$605F
0111
$7000-$73FF
0111
$7000-$705F
1000
$8000-$83FF
1000
$8000-$805F
1001
$9000-$93FF
1001
$9000-$905F
1010
$A000-$A3FF
1010
$A000-$A05F
1011
$B000-$B3FF
1011
$B000-$B05F
1100
$C000-$C3FF
1100
$C000-$C05F
1101
$D000-$D3FF
1101
$D000-$D05F
1110
$E000-$E3FF
1110
$E000-$E05F
1111
$F000-$F3FF
1111
$F000-$F05F
OPT2 System Configuration Option Register 2
$x038
Bit 7
Bit 0
GWOM
CWOM
CLK4X
LIRDV
SPRBYP
RESET
GWOM Port G Wired-OR Mode Option

Refer to 7.8 Parallel I/O Registers, page 36.
MOTOROLA
22
MC68HC11F1/FC0
MC68HC11FTS/D
CWOM Port C Wired-OR Mode Option

Refer to 7.8 Parallel I/O Registers, page 37.
CLK4X 4XCLK Output Enable
This bit can only be written once after reset in all modes.
0 = 4XOUT clock output is disabled
1 = Buffered oscillator is driven on the 4XOUT clock output
LIRDV Load Instruction Register Driven
In order to detect consecutive instructions in a high-speed application, LIR can be driven high for one
quarter of an E-clock cycle during each instruction fetch.
0 = LIR signal is not driven high.
1 = LIR signal is driven high.
Bits 3, 1, 0 Not implemented. Reads always return zero and writes have no effect.
SPRBYP See 10.2 SPI Registers, page 52.
OPTION System Configuration Options
RESET:
$x039
Bit 7
Bit 0
ADPU
CSEL
IRQE*
DLY*
CME
FCME*
CR1*
CR0*
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.
ADPU A/D Power-Up

This bit is implemented on the MC68HC11F1 only. On the MC68HC11FC0, reads always return zero
and writes have no effect.
0 = A/D system disabled
1 = A/D system enabled
CSEL Clock Select
This bit is implemented on the MC68HC11F1 only. On the MC68HC11FC0, reads always return zero
and writes have no effect.
0 = A/D and EEPROM use system E clock
1 = A/D and EEPROM use internal RC clock
IRQE IRQ Select Edge Sensitive Only
0 = Low level recognition
1 = Falling edge recognition
DLY Enable Oscillator Start-Up Delay on Exit from STOP
0 = No stabilization delay on exit from STOP
1 = Stabilization delay of 4064 E-clock cycles is enabled on exit from STOP
CME Clock Monitor Enable
0 = Clock monitor disabled; slow clocks can be used
1 = Slow or stopped clocks cause clock failure reset
FCME Force Clock Monitor Enable
0 = Clock monitor circuit follows the state of the CME bit
1 = Clock monitor circuit is enabled until the next reset
In order to use both STOP and the clock monitor, the CME bit should be written to zero prior to executing
a STOP instruction and rewritten to one after recovery from STOP. FCME should be kept cleared if the
user intends to use the STOP instruction.
CR[1:0] COP Timer Rate Select
Refer to 5.2 Reset and Interrupt Registers, page 27.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
23
CONFIG EEPROM Mapping, COP, EEPROM Enables
RESET
$x03F
Bit 7
Bit 0
EE3
EE2
EE1
EE0
NOCOP
EEON
U = Unaffected by reset
Bits 7:3 See 6.2 EEPROM Registers, page 30. (These bits are implemented on the MC68HC11F1 only.)
NOCOP COP System Disable
0 = COP enabled (forces reset on time-out)
1 = COP disabled (does not force reset on time-out)
TEST1 Factory Test
$x03E
Bit 7
Bit 0
TILOP
OCCR
CBYP
DISR
FCM
FCOP
RESET:
These bits can only be written in test and bootstrap modes.

TILOP Test Illegal Opcode
This test mode allows serial testing of all illegal opcodes without servicing an interrupt after each illegal
opcode is fetched.
0 = Normal operation (trap on illegal opcodes)
1 = Inhibit LIR when an illegal opcode is found
Bit 6 Not implemented. Reads always return zero and writes have no effect.
OCCR Output Condition Code Register to Timer Port
0 = Normal operation
1 = Condition code bits H, N, Z, V and C are driven on PA[7:3] to allow a test system to monitor
CPU operation
CBYP Timer Divider Chain Bypass
1 = The 16-bit free-running timer is divided into two 8-bit halves and the prescaler is bypassed. The
system E clock drives both halves directly.
DISR Disable Resets from COP and Clock Monitor
In test and bootstrap modes, this bit is reset to one to inhibit clock monitor and COP resets. In normal
modes, DISR is reset to zero.
1 = COP and Clock Monitor failure do not generate a system reset
FCM Force Clock Monitor Failure
1 = Generate an immediate clock monitor failure reset. Note that the CME bit in the OPTION register
must also be set in order to force the reset.
FCOP Force COP Watchdog Failure
1 = Generate an immediate COP failure reset. Note that the NOCOP bit in the CONFIG register
must be cleared (COP enabled) in order to force the reset.
MOTOROLA
24
MC68HC11F1/FC0
MC68HC11FTS/D
5 Resets and Interrupts

There are three sources of reset on the MC68HC11F1 and MC68HC11FC0, each having its own reset
vector:
RESET pin
Clock monitor failure
Computer operating properly (COP) failure
There are 22 interrupt sources serviced by 18 interrupt vectors. (The SCI interrupt vector services five
SCI interrupt sources.) Three of the interrupt vectors are non-maskable:
Illegal opcode trap
Software interrupt
XIRQ pin (pseudo non-maskable interrupt)
The other 19 interrupts, generated mostly by on-chip peripheral systems, are maskable. Maskable interrupts are recognized only if the global interrupt mask bit (I) in the condition code register (CCR) is
clear. Maskable interrupts have a default priority arrangement out of reset. However, any one interrupt
source can be elevated to the highest maskable priority position by writing to the HPRIO register. This
register can be written at any time, provided the I bit in the CCR is set.
In addition to the global I bit, all maskable interrupt sources except the external interrupt (IRQ pin) are
subject to local enable bits in control registers. Each of these interrupt sources also sets a corresponding flag bit in a control register that can be polled by software.
Several of these flags are automatically cleared during the normal course of responding to the interrupt
requests. For example, the RDRF flag is set when a byte has been received in the SCI. The normal
response to an RDRF interrupt request is to read the SCI status register to check for receive errors,
then to read the received data from the SCI data register. It is precisely these two steps that are required
to clear the RDRF flag, so no further instructions are necessary.
5.1 Interrupt Sources
The following table summarizes the interrupt sources, vector addresses, masks, and flag bits.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
25
Table 11 Interrupt and Reset Vector Assignments

Vector Address
Interrupt Source
CCR Mask
Local Mask
Flag Bit
Reserved
TCIE
TC
FFC0, C1
to
FFD4, D5
FFD6, D7
SCI Serial System

SCI Transmit Complete
SCI Transmit Data Register Empty
TIE
TDRE
ILIE
IDLE
SCI Receiver Overrun
RIE
OR
SCI Receive Data Register Full
RIE
RDRF
SCI Idle Line Detect
I Bit
FFD8, D9
SPI Serial Transfer Complete
I Bit
SPIE
SPIF
FFDA, DB
Pulse Accumulator Input Edge
I Bit
PAII
PAIF
FFDC, DD
Pulse Accumulator Overflow
I Bit
PAOVI
PAOVF
FFDE, DF
Timer Overflow
I Bit
TOI
TOF
FFE0, E1
Timer Input Capture 4/Output Compare 5
I Bit
I4/O5I
I4/O5F
FFE2, E3
Timer Output Compare 4
I Bit
OC4I
OC4F
FFE4, E5
I Bit
OC3I
OC3F
FFE6, E7
I Bit
OC2I
OC2F
FFE8, E9
I Bit
OC1I
OC1F
FFEA, EB
Timer Input Capture 3
I Bit
IC3I
IC3F
FFEC, ED
I Bit
IC2I
IC2F
FFEE, EF
I Bit
IC1I
IC1F
FFF0, F1
Real-Time Interrupt
I Bit
RTII
RTIF
FFF2, F3
IRQ
I Bit
None
None
FFF4, F5
XIRQ Pin
X Bit
None
None
FFF6, F7
Software Interrupt
None
None
None
FFF8, F9
Illegal Opcode Trap
None
None
None
FFFA, FB
COP Failure
None
NOCOP
None
FFFC, FD
Clock Monitor Fail
None
CME
None
FFFE, FF
RESET
None
None
None
5.2 Reset and Interrupt Registers

$x039
Bit 7
Bit 0
ADPU
CSEL
IRQE*
DLY*
CME
FCME*
CR1*
CR0*
RESET:
Bits [7:6], [4:2]

Refer to 4.3 System Initialization Registers, page 23, and 11.3 A/D Registers, page 56.
IRQE IRQ Select Edge Sensitive Only
0 = Low level recognition
1 = Falling edge recognition
MOTOROLA
26
MC68HC11F1/FC0
MC68HC11FTS/D
CR[1:0] COP Timer Rate Select

The COP system is driven by a constant frequency of E/215. CR[1:0] specify an additional divide-by factor to arrive at the COP time-out rate.
Table 12 COP Watchdog Time-Out Periods
Frequency
Tolerance
CR[1:0] = 00
CR[1:0] = 01
CR[1:0] = 10
CR[1:0] = 11
1 MHz
-0/+32.768 ms
32.768 ms
131.072 ms
524.288 ms
2.097 s
2 MHz
-0/+16.384 ms
16.384 ms
65.536 ms
262.144 ms
1.049 s
3 MHz
-0/+10.923 ms
10.923 ms
43.691 ms
174.763 ms
699.051 ms
4 MHz
-0/+8.192 ms
8.192 ms
32.768 ms
131.072 ms
524.288 ms
5 MHz
-0/+6.554 ms
6.554 ms
26.214 ms
104.858 ms
419.430 ms
6 MHz
-0/+5.461 ms
5.461 ms
21.845
87.381 ms
349.525 ms
Any E
-0/+215/E
215/E
217/E
219/E
221/E
COPRST Arm/Reset COP Timer Circuitry
RESET:
$x03A
Bit 7
Bit 0
Write $55 to COPRST to arm the COP watchdog clearing mechanism. Then write $AA to COPRST to
reset the COP timer. Performing instructions between these two steps is possible provided both steps
are completed in the correct sequence before the timer times out.
HPRIO Highest Priority I-Bit Interrupt and Miscellaneous
$x03C
Bit 7
Bit 0
RBOOT
SMOD
MDA
IRV
PSEL3
PSEL2
PSEL1
PSEL0
RESET:
Bits [7:4] See 4.3 System Initialization Registers, page 20.

PSEL[3:0] Interrupt Priority Select Bits
Can be written only while the I bit in the CCR is set (interrupts disabled). These bits select one interrupt
source to have priority over other I-bit related sources.
Table 13 Highest Priority Interrupt Selection
PSEL[3:0]
MC68HC11F1/FC0
MC68HC11FTS/D
Interrupt Source Promoted
0000
Timer Overflow
0001
Pulse Accumulator Overflow
0010
Pulse Accumulator Input Edge
0011
SPI Serial Transfer Complete
0100
SCI Serial System
0101
Reserved (Default to IRQ)
0110
IRQ (External Pin)
0111
Real-Time Interrupt
1000
1001
1010
MOTOROLA
27
Table 13 Highest Priority Interrupt Selection (Continued)

PSEL[3:0]
Interrupt Source Promoted
1011
1100
1101
1110
1111
Timer Output Compare 5/Input Capture 4
RESET
$x03F
Bit 7
Bit 0
EE3
EE2
EE1
EE0
NOCOP
EEON
Bits 7:3, 1:0 See 6.2 EEPROM Registers, page 30.

MOTOROLA
28
MC68HC11F1/FC0
MC68HC11FTS/D
6 Electrically Erasable Programmable ROM

The MC68HC11F1 has 512 bytes of electrically erasable programmable ROM (EEPROM). A nonvolatile, EEPROM-based configuration register (CONFIG) controls whether the EEPROM is present or absent and determines its position in the memory map. In single-chip and bootstrap modes the EEPROM
is positioned at $FE00$FFFF. In expanded and special test modes, the EEPROM can be repositioned
to any 4-Kbyte boundary ($xE00$xFFF).
NOTE
EEPROM is available on the MC68HC11F1 only.
6.1 EEPROM Operation
The EEON bit in CONFIG controls whether the EEPROM is present in the memory map. When
EEON = 1, the EEPROM is enabled. When EEON = 0, the EEPROM is disabled and removed from the
memory map. EEON is forced to one out of reset in single-chip and special bootstrap modes to enable
EEPROM. EEON is forced to zero out of reset in special test mode to remove EEPROM from the memory map, although test software can turn it back on. In normal expanded mode, EEON is reset to the
value last programmed into CONFIG.
An on-chip charge pump develops the high voltage required for programming and erasing. When the
E-clock frequency is 1 MHz or above, the charge pump is driven by the E-clock. When the E-clock frequency is less than 1 MHz, select the internal RC oscillator to drive the EEPROM charge pump by writing one to the CSEL bit in the OPTION register. Refer to the discussion of the OPTION register in 4.3
System Initialization Registers, page 23.
6.2 EEPROM Registers
BPROT Block Protect
RESET
$x035
Bit 7
Bit 0
PTCON
BPRT3
BPRT2
BPRT1
BPRT0
Bits [7:5] Not implemented. Reads always return zero and writes have no effect.
PTCON Protect for CONFIG
0 = CONFIG register can be programmed or erased normally
1 = CONFIG register cannot be programmed or erased
BPRT[3:0] Block Protect Bits for EEPROM
0 = Protection disabled
1 = Protection enabled
Table 14 Block Protect Bits for EEPROM
Bit Name
Block Protected
Block Size
BPRT3
$xEE0xFFF
288 Bytes
BPRT2
$xE60xEDF
128 Bytes
PBRT1
$xE20xE5F
64 Bytes
BPRT0
$xE00xE1F
32 Bytes
NOTE
Block protect register bits can be written to zero (protection disabled) only once
within 64 cycles of a reset in normal modes, or at any time in special modes. Block
protect register bits can be written to one (protection enabled) at any time.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
29
PPROG EEPROM Programming Control
RESET
$x03B
Bit 7
Bit 0
ODD
EVEN
BYTE
ROW
ERASE
EELAT
EEPGM
ODD Program Odd Rows (TEST)

EVEN Program Even Rows (TEST)
ROW and BYTE Row Erase Select Bit and Byte Erase Select
The value of these bits determines the manner in which EEPROM is erased. Bit encodings are shown
in 6.2 EEPROM Registers, page 30.
Table 15 ROW and BYTE Encodings
BYTE
ROW
Action
Bulk Erase (All 512 Bytes)
Row Erase (16 Bytes)
Byte Erase
Byte Erase
ERASE Erase/Normal Control for EEPROM

0 = Normal read or program mode
1 = Erase mode
EELAT EEPROM Latch Control
0 = EEPROM address and data bus configured for normal reads
1 = EEPROM address and data bus configured for programming or erasing
EEPGM EEPROM Program Command
0 = Program or erase voltage to EEPROM array switched off
1 = Program or erase voltage to EEPROM array switched on
RESET
$x03F
Bit 7
Bit 0
EE3
EE2
EE1
EE0
NOCOP
EEON
U = Unaffected by reset.
The CONFIG register is used to assign EEPROM a location in the memory map and to enable or disable
EEPROM operation. Bits in this register are user-programmed except when forced to certain values, as
noted in the following bit descriptions.
EE[3:0] EEPROM Map Position
EEPROM is located at $xE00 $xFFF, where x is the value represented by these four bits. In singlechip and bootstrap modes, EEPROM is forced to $FE00 $FFFF, regardless of the state of these bits.
On factory-fresh devices, EE[3:0] = $0.
Bit 3 Not implemented. Reads always return one and writes have no effect.
MOTOROLA
30
MC68HC11F1/FC0
MC68HC11FTS/D
Bit 1 Not implemented. Reads always return one and writes have no effect.
EEON EEPROM Enable
This bit is forced to one in single-chip and bootstrap modes. In test mode, EEON is forced to zero out
of reset. In expanded mode, the EEPROM obeys the state of this bit.
0 = EEPROM is removed from the memory map.
1 = EEPROM is present in the memory map.
Refer to 6.4 CONFIG Register Programming for instructions on programming this register.
6.3 EEPROM Programming and Erasure
Programming and erasing the EEPROM is controlled by the PPROG register, subject to the block protect (BPROT) register value. To erase the EEPROM, ensure that the proper bits of the BPROT register
are cleared, and then complete the following steps:
1. Write to PPROG with the ERASE and EELAT bits set and the BYTE and ROW bits set or
cleared as appropriate.
2. Write to the appropriate EEPROM address with any data. Row erase ($xE00$xE0F, $xE10
$xE1F,... $xFF0$xFFF) requires a single write to any location in the row. Perform bulk erase
by writing to any location in the array.
3. Write to PPROG with the ERASE, EELAT, and EEPGM bits set and the BYTE and ROW bits
set or cleared as appropriate.
4. Delay for 10 ms (20 ms for low-voltage operation).
5. Clear the EEPGM bit in PPROG to turn off the high voltage.
6. Clear the PPROG register to reconfigure EEPROM address and data buses for normal operations.
To program the EEPROM, ensure that the proper bits of the BPROT register are cleared, and then complete the following steps:
1.
2.
3.
4.
5.
6.
Write to PPROG with the EELAT bit set.

Write data to the desired address.
Write to PPROG with the EELAT and EEPGM bits set.
Delay for 10 ms (20 ms for low-voltage operation).
Clear the EEPGM bit in PPROG to turn off the high voltage.
Clear the PPROG register to reconfigure EEPROM address and data buses for normal operations.
6.3.1 Programming a Byte

The following example shows how to program an EEPROM byte. This example assumes that the appropriate bits in BPROT are cleared and that the data to be programmed is present in accumulator A.
PROG
LDAB
STAB
STAA
LDAB
STAB
JSR
CLR
#$02
$103B
$FE00
#$03
$103B
DLY10
$103B
EELAT=1, EEPGM=0
Set EELAT bit
Store data to EEPROM address
EELAT=1, EEPGM=1
Turn on programming voltage
Delay 10 ms
Turn off high voltage and set to READ mode
6.3.2 Bulk Erase

The following example shows how to bulk erase the 512-byte EEPROM. The CONFIG register is not
affected in this example. Note that when the CONFIG register is bulk erased, CONFIG and the 512-byte
array are all erased.
BULKE
LDAB
STAB
MC68HC11F1/FC0
MC68HC11FTS/D
#$06
$103B
ERASE=1, EELAT=1, EEPGM=0

Set EELAT bit
MOTOROLA
31
STAB
LDAB
STAB
JSR
CLR
$FE00
#$07
$103B
DLY10
$103B
Store any data to any EEPROM address

EELAT=1, EEPGM=1
Turn on programming voltage
Delay 10 ms
6.3.3 Row Erase

The following example shows how to perform a fast erase of large sections of EEPROM. This example
assumes that index register X contains the address of a location in the desired row.
ROWE
LDAB
STAB
STAB
LDAB
STAB
JSR
CLR
#$0E
$103B
$xxxx
#$0F
$103B
DLY10
$103B
ROW=1, ERASE=1, EELAT=1, EEPGM=0

Set to ROW erase mode
Store any data to any address in ROW
ROW=1, ERASE=1, EELAT=1, EEPGM=1
Turn on high voltage
Delay 10 ms
6.3.4 Byte Erase

The following is an example of how to erase a single byte of EEPROM. This example assumes that index register X contains the address of the byte to be erased.
BYTEE
LDAB
STAB
STAB
LDAB
STAB
JSR
CLR
#$16
$103B
$0,X
#$17
$103B
DLY10
$103B
BYTE=1, ROW=0, ERASE=1, EELAT=1, EEPGM=0

Set to BYTE erase mode
Store any data to address to be erased
BYTE=1, ROW=0, ERASE=1, EELAT=1, EEPGM=1
Turn on high voltage
Delay 10 ms
6.4 CONFIG Register Programming

Because the CONFIG register is implemented with EEPROM cells, use EEPROM procedures to erase
and program this register. The procedure for programming is the same as for programming a byte in
the EEPROM array, except that the CONFIG register address is used. CONFIG can be programmed or
erased (including byte erase) while the MCU is operating in any mode, provided that PTCON in BPROT
is clear. To change the value in the CONFIG register, complete the following procedure. Do not initiate
a reset until the procedure is complete. The new value will not take effect until after the next reset sequence.
1. Erase the CONFIG register.
2. Program the new value to the CONFIG address.
3. Initiate reset.
MOTOROLA
32
MC68HC11F1/FC0
MC68HC11FTS/D
7 Parallel Input/Output
On the MC68HC11F1, either 54 or 51 pins are available for general-purpose I/O, depending on the
package. These pins are arranged into ports A, B, C, D, E, F, and G. On the MC68HC11FC0, either 52
or 49 pins are available, depending on the package.
I/O functions on some ports (B, C, F, and G) are affected by the mode of operation selected. In the single-chip and bootstrap modes, they are configured as parallel I/O data ports. In expanded and test
modes, they are configured as follows:
Ports B and F are configured as the address bus.
Port C is configured as the data bus.
Port G bit 7 is configured as the optional program chip select CSPROG.
In addition, in expanded and test modes the R/W signal is configured as data bus direction control. The
remaining ports (A, D, and E) are unaffected by mode changes.
7.1 Port A
Port A is an eight-bit general-purpose I/O port (PA[7:0]) with a data register (PORTA) and a data direction register (DDRA). Port A pins are available for shared use among the main timer, pulse accumulator,
and general I/O functions, regardless of mode. Four pins can be used for timer output compare functions (OC), three for input capture (IC), and one as either a fourth IC or a fifth OC.
7.2 Port B
Port B is an eight-bit general-purpose output-only port in single-chip modes. In expanded modes, port
B pins act as high-order address lines ADDR[15:8], and accesses to PORTB (the port B data register)
are mapped externally.
7.3 Port C
Port C is an eight-bit general-purpose I/O port with a data register (PORTC) and a data direction register
(DDRC). In single-chip modes, port C pins are general-purpose I/O pins PC[7:0]. Port C can be configured for wired-OR operation in single-chip modes by setting the CWOM bit in the OPT2 register. In expanded modes, port C is the data bus DATA[7:0], and accesses to PORTC (the port C data register)
are mapped externally.
7.4 Port D
Port D is a six-bit general-purpose I/O port with a data register (PORTD) and a data direction register
(DDRD). In all modes, the six port D lines (PD[5:0]) can be used for general-purpose I/O or for the serial
communications interface (SCI) or serial peripheral interface (SPI) subsystems. Port D can also be configured for wired-OR operation.
7.5 Port E
Port E is an eight-bit input-only port that is also used (on the MC68HC11F1 only) as the analog input
port for the analog-to-digital converter. Port E pins that are not used for the A/D system can be used as
general-purpose inputs. However, PORTE should not be read during the sample portion of an A/D conversion sequence.
NOTE
PE7 and PE0 are not available on the 80-pin MC68HC11FC0. PE7, PE4, and PE0
are not available on the 64-pin MC68HC11FC0.
7.6 Port F
Port F is an eight-bit output-only port. In single-chip mode, port F pins are general-purpose output pins
PF[7:0]. In expanded mode, port F pins act as low-order address outputs ADDR[7:0].
MC68HC11F1/FC0
MC68HC11FTS/D
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7.7 Port G
Port G is an eight-bit general-purpose I/O port with a data register (PORTG) and a data direction register
(DDRG). When enabled, the upper four lines (PG[7:4] can be used as chip-select outputs in expanded
modes. When any of these pins are not being used for chip selects, they can be used for general-purpose I/O. Port G can be configured for wired-OR operation by setting the GWOM bit in the OPT2 register.
NOTE
PG[1:0] are not available on the 64-pin MC68HC11FC0.
7.8 Parallel I/O Registers
Port pin function is mode dependent. Do not confuse pin function with the electrical state of the pin at
reset. Port pins are either driven to a specified logic level or are configured as high impedance inputs.
I/O pins configured as high-impedance inputs have port data that is indeterminate. The contents of the
corresponding latches are dependent upon the electrical state of the pins during reset. In port descriptions, an I indicates this condition. Port pins that are driven to a known logic level during reset are
shown with a value of either one or zero. Some control bits are unaffected by reset. Reset states for
these bits are indicated with a U.
PORTA Port A Data Register
$x000
Bit 7
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
RESET:
Alternate
Function:
PAI
OC2
OC3
OC4
OC5/IC4
IC1
IC2
IC3
And/or:
OC1
OC1
OC1
OC1
OC1
I = Indeterminate value
DDRA Port A Data Direction Register
$x001
Bit 7
Bit 0
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
RESET:
For DDRx bits, 0 = input and 1 = output.

PORTG Port G Data Register
$x002
Bit 7
Bit 0
PG7
PG6
PG5
PG4
PG3
PG2
PG1*
PG0*
RESET:
Alternate
Function:
CSPROG
CSGEN
CSIO1
CSIO2
*These bits are not present on the 64-pin QFP version of the MC68HC11FC0.
MOTOROLA
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MC68HC11F1/FC0
MC68HC11FTS/D
DDRG Port G Data Direction Register
RESET:
$x003
Bit 7
Bit 0
DDG7*
DDG6
DDG5
DDG4
DDG3
DDG2
DDG1
DDG0
* Following reset in expanded and test modes, PG7/CSPRG is configured as a program chip select, forcing the pin
to be an output pin, even though the value of the DDG7 bit remains zero.

PORTB Port B Data Register
$x004
Bit 7
Bit 0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
RESET:
Alternate
Function:
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
The reset state of port B is mode dependent. In single-chip or bootstrap modes, port B pins are generalpurpose outputs. In expanded and test modes, port B pins are high-order address outputs and PORTB
is not in the memory map.
PORTF Port F Data Register
RESET:
Alternate
Function:
$x005
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
The reset state of port F is mode dependent. In single-chip or bootstrap modes, port F pins are generalpurpose outputs. In expanded and test modes, port F pins are low-order address outputs and PORTF
is not in the memory map.
PORTC Port C Data Register
RESET:
Alternate
Function:
$x006
Bit 7
Bit 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
The reset state of port C is mode dependent. In single-chip and bootstrap modes, port C pins are highimpedance inputs. In expanded or test modes, port C pins are data bus inputs/outputs and PORTC is
not in the memory map. The R/W signal is used to control the direction of data transfers.
DDRC Port C Data Direction Register
RESET:
$x007
Bit 7
Bit 0
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
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PORTD Port D Data Register
RESET:
Alternate
Function:
$x008
Bit 7
Bit 0
PD5
PD4
PD3
PD2
PD1
PD0
SS
SCK
MOSI
MISO
TxD
RxD
DDRD Port D Data Direction Register
RESET:
$x009
Bit 7
Bit 0
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0

NOTE
When the SPI system is in slave mode, DDD5 has no meaning or effect. When the
SPI system is in master mode, DDD5 determines whether bit 5 of PORTD is an error detect input (DDD5 = 0) or a general-purpose output (DDD5 = 1). If the SPI system is enabled and expects one or more of bits [4:2] to be inputs, those bits will be
inputs regardless of the state of the associated DDR bits. If one or more of bits [4:2]
are expected to be outputs, those bits will be outputs only if the associated DDR
bits are set.
PORTE Port E Data
$x00A
Bit 7
Bit 0
PE6
PE5
PE42
PE3
PE2
PE1
PE01
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
PE71
RESET:
Alternate
Function
NOTES:
1. These bits are not present on the MC68HC11FC0 and will always read zero.
2. This bit is not present on the 64-pin QFP version of the MC68HC11FC0 and will always read zero.
U = Unaffected by rest.
PORTE is an input-only register. Reads return the digital state of the I/O pins, and writes have no effect.
On the MC68HC11F1, port E is shared with the analog-to-digital converter. (The A/D converter is not
present on the MC68HC11FC0.)
$x038
Bit 7
Bit 0
GWOM
CWOM
CLK4X
LIRDV
SPRBYP
RESET
GWOM Port G Wired-OR Mode Option

This bit affects all port G pins together.
0 = Port G outputs are normal CMOS outputs
1 = Port G outputs act as open-drain outputs
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MC68HC11F1/FC0
MC68HC11FTS/D
CWOM Port C Wired-OR Mode Option

This bit affects all port C pins together.
0 = Port C outputs are normal CMOS outputs
1 = Port C outputs act as open-drain outputs
CLK4X 4XCLK Output Enable
Refer to 4.3 System Initialization Registers, page 23
LIRDV Load Instruction Register Driven
Refer to 4.3 System Initialization Registers, page 23
SPRBYP Refer to 10.2 SPI Registers, page 52.
MC68HC11F1/FC0
MC68HC11FTS/D
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8 Chip-Selects
Chip selects eliminate the need for additional external components to interface with peripherals in expanded non-multiplexed modes. Chip-select registers control polarity, address block size, base address, and clock stretching.
8.1 Chip-Select Operation
There are four programmable chip selects on the MC68HC11F1 and MC68HC11FC0: two for external
I/O (CSIO1 and CSIO2), one for external program space (CSPROG), and one general-purpose chip select (CSGEN).
CSPROG is active low and becomes active at address valid time. CSPROG is enabled by the PCSEN
bit of the chip-select control register (CSCTL). Its address block size is selected by the PSIZA and
PSIZB bits of CSCTL.
Use the I/O chip selects (CSIO1 and CSIO2) for external I/O devices. These chip-select addresses are
found in the memory map block that contains the status and control registers. CSIO1 is mapped from
$x060 to $x7FF, and CSIO2 is mapped from $x800 to $xFFF, where x represents the REG[3:0] bits of
the INIT register on the MC68HC11F1 or the REG[1:0] bits of the INIT register on the MC68HC11FC0.
Polarity and enable-disable selections are controlled by CSCTL register bits IO1EN, IO1PL, IO2EN, and
IO2PL. The IO1AV and IO2AV bits of the CSGSIZ register determine whether the chip selects are valid
during address or E-clock valid times.
The general-purpose chip select is the most flexible of the four chip selects. Polarity, valid assertion
time, and block size are determined by the GNPOL, GAVLD, GSIZA, GSIZB, and GSIZC bits of the
CSGSIZ register. The starting address is selected with the CSGADR register.
Each of the four chip selects has two associated bits in the chip-select clock stretch register (CSSTRH).
These bits allow clock stretching from zero to three cycles (full E-clock periods) to accommodate slow
device interfaces. Any of the chip selects can be programmed to cause a clock stretch to occur only
during access to addresses that fall within that particular chip selects address range.
During the stretch period, the E-clock is held high and the bus remains in the state that it is normally in
at the end of E high time. Internally, the clocks continue to run, which maintains the integrity of the timers
and baud-rate generators.
Priority levels are assigned to prevent the four chip selects from conflicting with each other or with internal memory and registers. There are two sets of priorities controlled by the value of the general-purpose chip-select priority bit (GCSPR) of the CSCTL register. Refer to Table 17.
8.2 Chip-Select Registers
CSSTRH Clock Stretching
$x05C
Bit 7
Bit 0
IO1SA
IO1SB
IO2SA
IO2SB
GSTHA
GSTHB
PSTHA
PSTHB
RESET:
IO1SA, IOS1B I/O Chip-Select 1 Clock Stretch

IO2SA, IO2SB I/O Chip-Select 2 Clock Stretch
GSTHA, GSTHB General-Purpose Chip-Select Clock Stretch
PSTHA, PSSTHB Program Chip-Select Clock Stretch
Each pair of bits selects the number of clock cycles of stretch for the corresponding chip select.
MOTOROLA
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MC68HC11F1/FC0
MC68HC11FTS/D
Table 16 Chip Select Clock Stretch Control

Clock Stretch
Bits A, B
Clock Stretch
00
0 Cycles
01
1 Cycle
10
2 Cycles
11
3 Cycles
CSCTL Chip-Select Control
RESET:
$x05D
Bit 7
Bit 0
IO1EN
IO1PL
IO2EN
IO2PL
GCSPR
PCSEN*
PSIZA
PSIZB
* PCSEN is set out of reset in expanded modes and cleared in single-chip modes.
IO1EN I/O Chip-Select 1 Enable

0 = CSIO1 disabled
1 = CSIO1 enabled
IO1PL I/O Chip-Select 1 Polarity
0 = CSIO1 active low
1 = CSIO1 active high
IO1EN I/O Chip-Select 2 Enable
0 = CSIO2 disabled
1 = CSIO2 enabled
IO2PL I/O Chip-Select 2 Polarity
0 = CSIO2 active low
1 = CSIO2 active high
GCSPR General-Purpose Chip-Select Priority
0 = Program chip-select has priority over general-purpose chip-select
1 = General-purpose chip-select has priority over program chip-select
Refer to Table 17.
Table 17 Chip Select Priorities
GCSPR = 0
GCSPR = 1
On-Chip Registers
On-Chip Registers
On-Chip RAM
On-Chip RAM
Bootloader ROM
Bootloader ROM
1
On-Chip EEPROM
On-Chip EEPROM1
I/O Chip Selects
I/O Chip Selects
Program Chip Select
General-Purpose Chip Select
General-Purpose Chip Select
Program Chip Select
NOTES:
1. EEPROM is present on the MC68HC11F1 only.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
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PCSEN Program Chip-Select Enable

Reset clears PCSEN in single-chip modes and sets PCSEN in expanded modes.
0 = CSPROG disabled
1 = CSPROG enabled
PSIZA, PSIZB Select Size of Program Chip-Select
Table 18 Program Chip Select Size Control
PSIZA
PSIZB
Size
Address Range
64 Kbytes
$0000$FFFF
32 Kbytes
$8000$FFFF
16 Kbytes
$C000$FFFF
8 Kbytes
$E000$FFFF
CSGADR General-Purpose Chip-Select Address Register
$x05E
Bit 7
Bit 0
GA15
GA14
GA13
GA12
GA11
GA10
RESET:
GA[15:10] General-Purpose Chip-Select Starting Address

These bits determine the starting address of the CSGEN valid address space and correspond to the
high-order address bits ADDR[15:10]. Table 19 illustrates how the block size selected determines
which of this register's bits are valid.
Table 19 General Purpose Chip Select Starting Address
CSGEN Block Size
CSGADR Bits Valid
0 Kbytes
None
1 Kbyte
GA15 GA10
2 Kbytes
GA15 GA11
4 Kbytes
GA15 GA12
8 Kbytes
GA15 GA13
16 Kbytes
GA15 GA14
32 Kbytes
GA15
64 Kbytes
None
CSGSIZ General-Purpose Chip-Select Size Register
$x05F
Bit 7
Bit 0
IO1AV
IO2AV
GNPOL
GAVLD
GSIZA
GSIZB
GSIZC
RESET:
IO1AV I/O Chip-Select 1 Address Valid

0 = CSIO1 is valid during E-clock valid time (E-clock high)
1 = CSIO1 is valid during address valid time
IO2AV I/O Chip-Select 2 Address Valid
0 = CSIO2 is valid during E-clock valid time (E-clock high)
1 = CSIO2 is valid during address valid time
MOTOROLA
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MC68HC11F1/FC0
MC68HC11FTS/D
GNPOL General-Purpose Chip-Select Polarity
0 = CSGEN is active low
1 = CSGEN is active high
GAVLD General-Purpose Chip-Select Address Valid
0 = CSGEN is valid during E-clock valid time (E-clock high)
1 = CSGEN is valid during address valid time
GSIZ[A:C] Block Size for CSGEN
Refer to Table 20 for bit values.
Table 20 General-Purpose Chip Select Size Control
MC68HC11F1/FC0
MC68HC11FTS/D
GSIZ[A:C]
Address Size
000
64 Kbytes
001
32 Kbytes
010
16 Kbytes
011
8 Kbytes
100
4 Kbytes
101
2 Kbytes
110
1 Kbyte
111
0 Kbytes (disabled)
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9 Serial Communications Interface (SCI)

The SCI, a universal asynchronous receiver transmitter (UART) serial communications interface, is one
of two independent serial I/O subsystems in the MC68HC11F1 and MC68HC11FC0. The SCI has a
standard non-return to zero (NRZ) format (one start bit, eight or nine data bits, and one stop bit) and
several selectable baud rates. The transmitter and receiver are independent but use the same data format and bit rate.
9.1 SCI Block Diagrams
TRANSMITTER
BAUD RATE
CLOCK
(WRITE ONLY)
SCDR Tx BUFFER
DDD1
10 (11) - BIT Tx SHIFT REGISTER

2
SIZE 8/9
PIN BUFFER
AND CONTROL
PD1
TxD
BREAKJAM 0s
PREAMBLEJAM 1s
JAM ENABLE
SHIFT ENABLE
TRANSFER Tx BUFFER
H (8) 7
FORCE PIN
DIRECTION (OUT)
SCCR1
SCSR1
SCI CONTROL 1
FE
NF
OR
IDLE
RDRF
TC
TDRE
WAKE
T8
R8
TRANSMITTER
CONTROL LOGIC
SCI STATUS 1
TDRE
TIE
TC
SCCR2
SCI Rx
QUESTS
SBK
RWU
RE
TE
ILIE
RIE
TCIE
TIE
TCIE
SCI CONTROL 2
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
Figure 9 SCI Transmitter Block Diagram
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MC68HC11F1/FC0
MC68HC11FTS/D
RECEIVER
BAUD RATE
CLOCK
STOP
PD0
RxD
PIN BUFFER
AND CONTROL
DATA
RECOVERY
START
16
DDD0
10 (11) - BIT
Rx SHIFT REGISTER
8
MSB
ALL
ONES
DISABLE
DRIVER
RE
SCCR1
SCSR1
SCI CONTROL 1
FE
NF
OR
IDLE
RDRF
TC
TDRE
WAKE
T8
R8
WAKEUP
LOGIC
SCDR
SCI STATUS 1
Rx BUFFER
(READ ONLY)
RDRF
RIE
IDLE
ILIE
OR
SCCR2
SBK
RWU
RE
TE
ILIE
RIE
TCIE
TIE
RIE
SCI CONTROL 2
SCI Tx
SCI INTERRUPT
REQUESTS
REQUEST
INTERNAL
DATA BUS
Figure 10 SCI Receiver Block Diagram
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
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9.2 SCI Registers

BAUD Baud Rate
$x02B
Bit 7
Bit 0
TCLR
SCP2
SCP1
SCP0
RCKB
SCR2
SCR1
SCR0
RESET:
TCLR Clear Baud Rate Counters (TEST)

RCKB SCI Baud-Rate Clock Check (TEST)
SCP[2:0] SCI Baud Rate Prescaler Selects
These bits determine the baud rate prescaler frequency. Refer to Table 21 and Figure 11.
SCR[2:0] SCI Baud Rate Selects
These bits determine the receiver and transmitter baud rate. Refer to Table 22 and Figure 11.
Table 21 Baud Rate Prescaler Selection
Prescaler Output1
SCP[2:0]
Divide
Internal
Clock By
XTAL =
4.0 MHz
XTAL =
4.9152 MHz
X00
62500
76800
125000
156250
187500
250000
312500
375000
001
20833
25600
41667
52083
62500
83333
104167
125000
XTAL = XTAL = XTAL = XTAL = XTAL = XTAL =

8.0 MHz 10.0 MHz 12.0 MHz 16.0 MHz 20.0 MHz 24.0 MHz
X10
15625
19200
31250
38400
46875
62500
76800
93750
X11
13
4800
5908
9600
12019
14423
19200
24038
28846
101
20830
NOTES:
1. A blank table cell indicates that an uncommon rate results.
Table 22 Baud Rate Selection

Baud Rate
SCR[2:0]
Divide
Prescaler By
Prescaler
Output =
4800
Prescaler
Output =
9600
Prescaler
Output =
19200
Prescaler
Output =
38400
Prescaler
Output =
76800
000
4800
9600
19200
38400
76800
001
2400
4800
9600
19200
38400
010
1200
2400
4800
9600
19200
011
600
1200
2400
4800
9600
100
16
300
600
1200
2400
4800
101
32
150
300
600
1200
2400
110
64
75
150
300
600
1200
111
128
75
150
300
600
The prescaler bits SCP[2:0] determine the highest baud rate, and the SCR[2:0] bits select an additional
binary submultiple (divide by 1, 2, 4,..., through 128) of this highest baud rate. The result of these two
dividers in series is the 16X receiver baud rate clock. The SCR[2:0] bits are not affected by reset and
can be changed at any time. They should not be changed, however, when an SCI transfer is in progress.
MOTOROLA
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MC68HC11F1/FC0
MC68HC11FTS/D
Figure 11 illustrates the SCI baud rate timing chain. The prescaler select bits determine the highest
baud rate. The rate select bits determine additional divide-by-two stages to arrive at the receiver timing
(RT) clock rate. The baud rate clock is the result of dividing the RT clock by 16.
EXTAL
XTAL
OSCILLATOR
AND
CLOCK GENERATOR
INTERNAL BUS CLOCK (PH2)
(4)
3
E
X00
4
001
13
X10
9
X11
101
SCR[2:0]
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
SCI Receive Baud Rate (16x)
16
SCI Transmit Baud Rate (1x)
Figure 11 SCI Baud Rate Generator Block Diagram
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
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SCCR1 SCI Control Register 1
RESET:
$x02C
Bit 7
Bit 0
R8
T8
WAKE
R8 Receive Data Bit 8

If M is set, R8 stores the ninth bit of the receive data character.
T8 Transmit Data Bit 8
If M is set, T8 stores the ninth bit of the transmit data character.
M Mode (Select Character Format)
0 = 1 start bit, 8 data bits, 1 stop bit
1 = 1 start bit, 9 data bits, 1 stop bit
WAKE Wake Up by Address Mark/Idle
0 = Wake up by IDLE line recognition
1 = Wake up by address mark
SCCR2 SCI Control Register 2
RESET:
$x02D
Bit 7
Bit 0
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
TIE Transmit Interrupt Enable

0 = TDRE interrupts disabled
1 = SCI interrupt requested when the TDRE flag is set
TCIE Transmit Complete Interrupt Enable
0 = TC interrupts disabled
1 = SCI interrupt requested when the TC flag is set
RIE Receiver Interrupt Enable
0 = RDRF and OR interrupts disabled
1 = SCI interrupt requested when the RDRF flag or the OR flag is set
ILIE Idle Line Interrupt Enable
0 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
TE Transmitter Enable
When TE goes from zero to one, one unit of idle character time (logic one) is queued as a preamble.
0 = Transmitter disabled
1 = Transmitter enabled
RE Receiver Enable
0 = Receiver disabled
1 = Receiver enabled
MOTOROLA
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MC68HC11F1/FC0
MC68HC11FTS/D
RWU Receiver Wake Up Control

0 = Normal SCI receiver
1 = Wake up enabled and receiver interrupt inhibited
SBK Send Break
0 = Break generator off
1 = Break codes generated as long as SBK = 1
SCSR SCI Status Register
RESET:
$x02E
Bit 7
Bit 0
TDRE
TC
RDRF
IDLE
OR
NF
FE
TDRE Transmit Data Register Empty Flag

This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with TDRE set and then
writing to SCDR.
0 = SCDR is busy
1 = SCDR is empty
TC Transmit Complete Flag
This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear
the TC flag by reading SCSR with TC set and then writing to SCDR.
0 = Transmitter is busy
1 = Transmitter is idle
RDRF Receive Data Register Full Flag
This flag is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading
SCSR with RDRF set and then reading SCDR.
0 = SCDR empty
1 = SCDR full
IDLE Idle Line Detected Flag
This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD line has been
active and becomes idle again. The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR
with IDLE set and then reading SCDR.
0 = RxD line is active
1 = RxD line is idle
OR Overrun Error Flag
OR is set if a new character is received before a previously received character is read from SCDR. Clear
OR by reading SCSR with OR set and then reading SCDR.
0 = No overrun detected
1 = Overrun detected
NF Noise Error Flag
NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading
SCSR with NF set and then reading SCDR.
0 = Unanimous decision
1 = Noise detected
FE Framing Error
FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by reading SCSR
with FE set and then reading SCDR.
0 = Stop bit detected
1 = Zero detected
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
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SCDR Serial Communications Data Register
RESET:
$x02F
Bit 7
Bit 0
Bit 7
Bit 0
Reading SCDR retrieves the last byte received in the receive data buffer. Writing to SCDR loads the
transmit data buffer with the next byte to be transmitted.
MOTOROLA
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MC68HC11F1/FC0
MC68HC11FTS/D
10 Serial Peripheral Interface

The serial peripheral interface (SPI) allows the MCU to communicate synchronously with peripheral devices and other microprocessors. The SPI protocol facilitates rapid exchange of serial data between devices in a control system. The MC68HC11F1 and MC68HC11FC0 can be set up for master or slave
operation. Standard data rates can be as high as one half of the E-clock rate when configured as master, and as fast as the E-clock when configured as slave.
The MC68HC11FC0 has an additional control bit that allows the SPI baud rate counter to be bypassed.
This allows a master mode baud rate equal to the E-clock frequency.
10.1 SPI Block Diagram
SPI STATUS REGISTER
SPI CONTROL REGISTER
SPIF
WCOL
MODF
MODF
SPIF
WCOL
DOTTED LINE CONNECTIONS

PRESENT ON MC68HC11FC0 ONLY
SPIE
SPE
DWOM
MSTR
CPHA
CPOL
SPR1
SPR0
SPIE
SPE
MSTR
SPI
CONTROL
SPI INTERRUPT
REQUEST
INTERNAL DATA BUS
SPE
DWOM
MSTR
M
S
SYSTEM CONFIGURATION
OPTION 2 REGISTER
CLOCK
CLOCK LOGIC
S
M
PIN CONTROL LOGIC
SPR0
SPR1
MSTR
CPHA
CPOL
INTERNAL
MCU CLOCK
2
4
16
32
SELECT
DIVIDER
SS
PD5
SCK
PD4
MOSI
PD3
SPRBYP
MSB
LSB
8-BIT SHIFT REGISTER
READ DATA BUFFER
M
S
MISO
PD2
Figure 12 SPI Block Diagram
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
49
10.2 SPI Registers

SPCR SPI Control Register
RESET:
$x028
Bit 7
Bit 0
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
SPIE SPI Interrupt Enable

When SPI interrupts are enabled, a hardware interrupt sequence is requested each time the SPIF or
MODF status flag is set. SPI interrupts are inhibited if this bit is cleared or if the I bit in the condition code
register is one.
0 = SPI interrupt disabled
1 = SPI interrupt enabled
SPE SPI Enable
When the SPE bit is set, PD[5:2] are dedicated to the SPI function. If the SPI is in master mode and the
DDRD bit 5 is set, then PD5/SS becomes a general-purpose output instead of the SS input.
0 = SPI off
1 = SPI on
DWOM Port D Wired-OR Mode Option for SPI Pins PD[5:2]
0 = Normal CMOS outputs
1 = Open-drain outputs
MSTR Master Mode Select
0 = Slave mode
1 = Master mode
CPOL Clock Polarity
When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master device
has a steady state low value. When CPOL is set, SCK idles high. Refer to Figure 13.
CPHA Clock Phase
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between master and slave. The CPHA bit selects one of two clocking protocols. Refer to Figure 13.
SCK CYCLE #
(FOR REFERENCE)
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE INPUT
(CPHA = 0) DATA OUT
MSB
LSB
SAMPLE INPUT
(CPHA = 1) DATA OUT
MSB
LSB
SS (TO SLAVE)
Figure 13 SPI Data Clock Timing Diagram
MOTOROLA
50
MC68HC11F1/FC0
MC68HC11FTS/D
SPR[1:0] SPI Clock Rate Selects

These two bits select the SPI clock (SCK) rate when the device is configured as a master. When the
device is configured as a slave, the bits have no effect. Refer to Table 23.
Table 23 SPI Baud Rates
Input
Frequency
SPR[1:0] = 00
SPR[1:0] = 01
SPR[1:0] = 10
SPR[1:0] = 11
1 MHz
500 kbps
250 kbps
62.5 kbps
31.25 kbps
2 MHz
1 Mbps
500 kbps
125 kbps
62.5 kbps
3 MHz
1.5 Mbps
750 kbps
187.5 kbps
93.75 kbps
4 MHz
2 Mbps
1 Mbps
250 kbps
125 kbps
5 MHz
2.5 Mbps
1.25 Mbps
312.5 kbps
156.25 kbps
6 MHz
3 Mbps
1.5 Mbps
375 kbps
187.5 kbps
Any E
E/2
E/4
E/16
E/32
NOTE
The SPRBYP bit in OPT2 on the MC68HC11FC0 allows the SPI baud rate counter
to be bypassed. This permits a maximum master mode baud rate equal to the Eclock frequency on the MC68HC11FC0. SPRBYP is not present on the
MC68HC11F1.
SPSR SPI Status Register
RESET:
$x029
Bit 7
Bit 0
SPIF
WCOL
MODF
SPIF SPI Transfer Complete Flag

SPIF is set when an SPI transfer is complete. It is cleared by reading SPSR with SPIF set, followed by
a read or write of SPDR.
WCOL Write Collision
WCOL is set when SPDR is written while a transfer is in progress. It is cleared by reading SPSR with
WCOL set, followed by a read or write of SPDR.
0 = No write collision
1 = Write collision
Bit 5 Not Implemented. Reads always return zero and writes have no effect.
MODF Mode Fault
A mode fault terminates SPI operation. Set when SS is pulled low while MSTR = 1. MODF is cleared
by reading SPSR read with MODF set, followed by a write to SPCR.
0 = No mode fault
1 = Mode fault
Bits [3:0] Not Implemented. Reads always return zero and writes have no effect.
SPDR SPI Data Register
$x02A
Bit 7
Bit 0
Bit 7
Bit 0
Incoming SPI data is double buffered. Outgoing SPI data is single buffered.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
51
$x038
Bit 7
Bit 0
GWOM
CWOM
CLK4X
LIRDV
SPRBYP
RESET
Bits [7:4] See 4.3 System Initialization Registers, page 22.

SPRBYP SPI Baud Rate Counter Bypass
0 = Enable SPI baud rate counter
1 = Bypass SPI baud rate counter
When the SPI baud rate counter is bypassed, the SPI can transmit at a maximum master mode baud
rate equal to the E-clock frequency. SPRBYP is present only on the MC68HC11FC0 and overrides
the setting of SPR[1:0] in SPCR.
MOTOROLA
52
MC68HC11F1/FC0
MC68HC11FTS/D
11 Analog-to-Digital Converter
The MC68HC11F1 analog-to-digital (A/D) converter system uses an all-capacitive charge-redistribution
technique to convert analog signals to digital values. The A/D system is an 8-channel, 8-bit, multiplexedinput, successive-approximation converter, accurate to 1 least significant bit (LSB). Because the capacitive charge redistribution technique used includes a built-in sample-and-hold, no external sampleand-hold is required.
Dedicated lines VRH and VRL provide the reference supply voltage inputs. Systems operating at clock
rates of 750 kHz or below must use an internal RC oscillator. The CSEL bit in the OPTION register selects the clock source for the A/D system. (The CSEL bit is described in 11.3 A/D Registers, page 56.)
A multiplexer allows the single A/D converter to select one of 16 analog signals, as shown in Table 24.
NOTE
The A/D converter is present on the MC68HC11F1 only.
PE0
AN0
VRH
8-BIT CAPACITIVE DAC
WITH SAMPLE AND HOLD
PE1
AN1
VRL
PE2
AN2
SUCCESSIVE APPROXIMATION
REGISTER AND CONTROL
PE3
AN3
PE4
AN4
RESULT
ANALOG
MUX
PE5
AN5
INTERNAL
DATA BUS
CA
PE7
AN7
SCAN
MULT
CD
CC
CB
CCF
PE6
AN6
ADCTL A/D CONTROL
RESULT REGISTER INTERFACE
ADR1 A/D RESULT 1
ADR2 A/D RESULT 2
ADR3 A/D RESULT 3
ADR4 A/D RESULT 4
EA9 A/D BLOCK
Figure 14 A/D Converter Block Diagram
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
53
11.1 Input Pins

Port E pins can also be used as digital inputs. Reads of port E pins are not recommended during the
sample portion of an A/D conversion cycle, when the gate signal to the N-channel input gate is on. Because no P-channel devices are directly connected to either input pins or reference voltage pins, voltages above VDD do not cause a latchup problem, although current should be limited according to
maximum ratings. Figure 15 is a functional diagram of an input pin.
DIFFUSION/POLY
COUPLER
ANALOG
INPUT
PIN
+ ~20V
~0.7V
< 2 pF
INPUT
PROTECTION
DEVICE
4 K
+ ~12V
~0.7V
~ 20 pF
400 nA
JUNCTION
LEAKAGE
DUMMY N-CHANNEL
OUTPUT DEVICE
DAC
CAPACITANCE
VRL
* THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME.
Figure 15 Electrical Model of an Analog Input Pin (Sample Mode)

11.2 Conversion Sequence
A/D converter operations are performed in sequences of four conversions each. A conversion sequence
can be repeated continuously or stop after one iteration. The conversion complete flag (CCF) is set after
the fourth conversion in a sequence to show the availability of data in the result registers. Figure 16
shows the timing of a typical sequence. Synchronization is referenced to the system E clock.
MSB
4
CYCLES
SAMPLE ANALOG INPUT
CONVERT FIRST
CHANNEL, UPDATE
ADR1
32
BIT 6
2
CYC
BIT 5
2
CYC
BIT 4
2
CYC
BIT 3
2
CYC
BIT 2
2
CYC
BIT 1
2
CYC
LSB
2
CYC
2
CYC
END
SUCCESSIVE APPROXIMATION SEQUENCE
CONVERT SECOND
CHANNEL, UPDATE
ADR2
64
CONVERT THIRD
CHANNEL, UPDATE
ADR3
CONVERT FOURTH
CHANNEL, UPDATE
96
ADR4
SET CC FLAG
WRITE TO ADCTL
12 E CYCLES
REPEAT SEQUENCE, SCAN = 1
E CLOCK
128 E CYCLES
Figure 16 A/D Conversion Sequence
MOTOROLA
54
MC68HC11F1/FC0
MC68HC11FTS/D
11.3 A/D Registers

ADCTL A/D Control/Status
RESET:
$x030
Bit 7
Bit 0
CCF
SCAN
MULT
CD
CC
CB
CA
CCF Conversions Complete Flag

A read-only status indicator, this bit is set when all four A/D result registers contain valid conversion results. Each time the ADCTL register is overwritten, this bit is automatically cleared to zero and a conversion sequence is started. In the continuous mode, CCF is set at the end of the first conversion
sequence.
SCAN Continuous Scan Control
0 = Do four conversions and stop
1 = Convert four channels in selected group continuously
MULT Multiple Channel/Single Channel Control
0 = Convert single channel selected
1 = Convert four channels in selected group
CDCA Channel Select D through A
Refer to Table 24. When a multiple channel mode is selected (MULT = 1), the two least significant channel select bits (CB and CA) have no meaning and the CD and CC bits specify which group of four channels is to be converted.
Table 24 A/D Converter Channel Assignments
Channel Select Control Bits
CD:CC:CB:CA
Channel Signal
Result in ADRx if MULT = 1
0000
AN0
ADR1
0001
AN1
ADR2
0010
AN2
ADR3
0011
AN3
ADR4
0100
AN4
ADR1
0101
AN5
ADR2
0110
AN6
ADR3
0111
AN7
ADR4
10XX
Reserved
ADR1ADR4
1100
VRH1
ADR1
1101
VRL1
ADR2
1110
(VRH)/21
ADR3
1111
Reserved1
ADR4
NOTES:
1. Used for factory testing.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
55
ADR1 ADR4 A/D Results
$x031 $x034
$x031
Bit 7
Bit 0
ADR1
$x032
Bit 7
Bit 0
ADR2
$x033
Bit 7
Bit 0
ADR3
$x034
Bit 7
Bit 0
ADR4
Each read-only result register holds an eight-bit conversion result. Writes to these registers have no effect. Data in the A/D converter result registers is valid when the CCF flag in the ADCTL register is set,
indicating a conversion sequence is complete. If conversion results are needed sooner, refer to Figure
16, which shows the A/D conversion sequence diagram.
Table 25 Analog Input to 8-Bit Result Translation Table
Bit 7
Bit 0
50%
25%
12.5%
6.25%
3.12%
1.56%
0.78%
0.39%
2.500
1.250
0.625
0.3125
0.1562
0.0781
0.0391
0.0195
Percentage
2
Volts
NOTES:
1. % of VRHVRL
2. Volts for VRL = 0; VRH = 5.0 V
$x039
Bit 7
Bit 0
ADPU
CSEL
IRQE*
DLY*
CME
FCME*
CR1*
CR0*
RESET:
ADPU A/D Power Up

0 = A/D powered down
1 = A/D powered up
CSEL Clock Select
0 = A/D and EEPROM use system E-Clock
1 = A/D and EEPROM use internal RC clock
Bits [5:0] Refer to 4.3 System Initialization Registers, page 23.
MOTOROLA
56
MC68HC11F1/FC0
MC68HC11FTS/D
12 Main Timer
The main timer is based on a free-running 16-bit counter with a four-stage programmable prescaler. The
timer drives the three input capture (IC) channels, four output compare (OC) channels, one channel programmable for either IC or OC, and the pulse accumulator (PA). All of these functions share port A. The
main timer also drives the pulse accumulator, real-time interrupt (RTI), and computer operating properly
(COP) watchdog circuits.
12.1 Timer Operation
The following tables summarize timing periods for various M68HC11 functions derived from the main
timer for several crystal frequencies.
Table 26 Timer Subsystem Count and Overflow Periods
PR[1:0] = 00
PR[1:0] = 01
PR[1:0] = 10
PR[1:0] = 11
E-Clock
Frequency
1 Count
TCNT
Overflow
1 Count
TCNT
Overflow
1 Count
1 MHz
1.000 s
65.536 ms
4.000 s
262.144 ms
8.000 s
524.288 ms 16.000 s
2 MHz
0.500 s
32.768 ms
2.000 s
131.072 ms
4.000 s
262.144 ms
8.000 s
524.288 ms
3 MHz
0.333 s
21.845 ms
1.333 s
87.381 ms
2.667 s
174.763 ms
5.333 s
349.525 ms
4 MHz
0.250 s
16.384 ms
1.000 s
65.536 ms
2.000 s
131.072 ms
4.000 s
262.144 ms
5 MHz
0.200 s
13.107 ms
0.800 s
52.429 ms
1.600 s
104.858 ms
3.200 s
209.715 ms
6 MHz
0.167 s
10.923 ms
0.667 s
43.691 ms
1.333 s
87.381 ms
2.667 s
174.763 ms
Any E
1/E
216/E
4/E
218/E
8/E
219/E
16/E
220/E
TCNT
Overflow
1 Count
TCNT
Overflow
1.049 s
Table 27 Real-Time Interrupt Periods

E-Clock
Frequency
RTR[1:0] = 00
RTR[1:0] = 01
RTR[1:0] = 10
RTR[1:0] = 11
1 MHz
8.192 ms
16.384 ms
32.768 ms
65.536 ms
2 MHz
4.096 ms
8.192 ms
16.384 ms
32.768 ms
3 MHz
2.731 ms
5.461 ms
10.923 ms
21.845 ms
4 MHz
2.048 ms
4.096 ms
8.192 ms
16.384 ms
5 MHz
1.638 ms
3.277 ms
6.554 ms
13.107 ms
6 MHz
1.366 ms
2.731 ms
5.461 ms
10.923 ms
Any E
213/E
214/E
215/E
221/E
Table 28 COP Watchdog Time-Out Periods

E-Clock
Frequency
RTR[1:0] = 00
RTR[1:0] = 01
RTR[1:0] = 10
RTR[1:0] = 11
1 MHz
32.768 ms
131.072 ms
524.288 ms
2.097 s
2 MHz
16.384 ms
65.536 ms
262.144 ms
1.049 s
3 MHz
10.923 ms
43.691 ms
174.763 ms
699.051 ms
4 MHz
8.192 ms
32.768 ms
131.072 ms
524.288 ms
5 MHz
6.554 ms
26.214 ms
104.858 ms
419.430 ms
6 MHz
5.461 ms
21.845 ms
87.381 ms
349.525 ms
217/E
219/E
221/E
Any E
MC68HC11F1/FC0
MC68HC11FTS/D
15/E
MOTOROLA
57
PRESCALER
Divide by
1, 4, 8 or 16
E CLOCK
PR1
TCNT (HI)
TCNT (LO)
TOI
16-BIT FREE RUNNING

COUNTER
TOF
PR0
Interrupt
Requests
16-BIT TIMER BUS
OC1I
(HI) TOC1 (LO)
(HI) TOC2 (LO)
(HI) TOC3 (LO)
(HI) TOC4 (LO)
16-BIT COMPARATOR =
OC5
I4O5F
(HI) TI4O5 (LO)
IC1I
TIC2
(HI) TIC2
TIC3
(HI) TIC3
PA3
IC4/OC5
OC1
Bit 2
PA2
IC1
Bit 1
PA1
IC2
Bit 0
PA0
IC3
(LO)
CLK
IC2F
(LO)
IC3I
16-BIT LATCH
Bit 3
IC1F
IC2I
16-BIT LATCH
PA4
OC4/OC1
FOC5
CFORC
(HI) TIC1
Bit 4
IC4
CLK
I4/O5
TIC1
PA5
OC3/OC1
FOC4
I4O5I
CLK
Bit 5
OC4F
16-BIT COMPARATOR =
16-BIT LATCH
PA6
OC2/OC1
FOC3
OC4I
16-BIT LATCH
Bit 6
OC3F
16-BIT COMPARATOR =
TI4O5
PA7
OC1
FOC2
OC3I
TOC4
Bit 7
OC2F
16-BIT COMPARATOR =
TOC3
PORT A
Pins
FOC1
OC2I
TOC2
To Pulse
Accumulator
OC1F
16-BIT COMPARATOR =
TOC1
CLK
IC3F
(LO)
TFLG 1
Status
Flags
TMSK 1
Interrupt
Enables
Port A
Pin
Control
(Note 1)
IC/OC BLOCK
NOTE: Registers that control port A action include DDRA, OC1M, OC1D, PACTL, TCTL1 and TCTL2.
Figure 17 Main Timer
MOTOROLA
58
MC68HC11F1/FC0
MC68HC11FTS/D
12.2 Timer Registers

CFORC Timer Force Compare
RESET:
$x00B
Bit 7
Bit 0
FOC1
FOC2
FOC3
FOC4
FOC5
FOCx Force Output Compare x Action

0 = Not affected
1 = Output compare x action occurs, but OCxF flag bit is not set
OC1M Output Compare 1 Mask
RESET:
$x00C
Bit 7
Bit 0
OC1M7
OC1M6
OC1M5
OC1M4
OC1M3
Bits set in OC1M allow OC1 to output the corresponding OC1D bits in port A when a successful compare event occurs.
OC1M[7:3] Output Compare Masks
0 = Control of the corresponding port A pin is disabled
1 = Control of the corresponding port A pin is enabled
OC1D Output Compare 1 Data
RESET:
$x00D
Bit 7
Bit 0
OC1D7
OC1D6
OC1D5
OC1D4
OC1D3
OC1D[7:3] Output Compare Data

Data in OC1Dx is output to port A bit x on successful OC1 compares if OC1Mx is set.
TCNT Timer Count
$x00E, $x00F
$x00E
Bit 15
14
13
12
11
10
Bit 8
High
$x00F
Bit 7
Bit 0
Low
RESET:
The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A full counter read
addresses the most significant byte (MSB) first. A read of this address causes the least significant byte
to be latched into a buffer for the next CPU cycle so that a double-byte read returns the full 16-bit state
of the counter at the time of the MSB read cycle.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
59
TIC1TIC3 Timer Input Capture
$x010$x015
$x010
Bit 15
14
13
12
11
10
Bit 8
High
$x011
Bit 7
Bit 0
Low
$x012
Bit 15
14
13
12
11
10
Bit 8
High
$x013
Bit 7
Bit 0
Low
$x014
Bit 15
14
13
12
11
10
Bit 8
High
$x015
Bit 7
Bit 0
Low
TICx registers are not affected by reset.

TOC1TOC4 Timer Output Compare
$x016$x01D
$x016
Bit 15
14
13
12
11
10
Bit 8
High
$x017
Bit 7
Bit 0
Low
$x018
Bit 15
14
13
12
11
10
Bit 8
High
$x019
Bit 7
Bit 0
Low
$x01A
Bit 15
14
13
12
11
10
Bit 8
High
$x01B
Bit 7
Bit 0
Low
$x01C
Bit 15
14
13
12
11
10
Bit 8
High
$x01D
Bit 7
Bit 0
Low
All TOCx register pairs are reset to ones ($FFFF).

TI4/O5 Timer Input Capture 4/Output Compare 5
$x01E, $x01F
$x01E
Bit 15
14
13
12
11
10
Bit 8
High
$x01F
Bit 7
Bit 0
Low
TI4/O5 is reset to ones ($FFFF).

TCTL1 Timer Control 1
$x020
Bit 7
Bit 0
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
RESET:
OM2OM5 Output Mode

OL2OL5 Output Level
Each OMxOLx bit pair determines the output action taken on the corresponding OCx pin after a successful compare, as shown in Table 29. OC5 functions only if the I4/O5 bit in the PACTL register is
cleared.
MOTOROLA
60
MC68HC11F1/FC0
MC68HC11FTS/D
Table 29 Output Compare Actions

OMx
OLx
Action Taken on Successful Compare
Timer disconnected from output pin logic
Toggle OCx output line
Clear OCx output line to zero
Set OCx output line to one
TCTL2 Timer Control 2
RESET:
$x021
Bit 7
Bit 0
EDG4B
EDG4A
EDG1B
EDG1A
EDG2B
EDG2A
EDG3B
EDG3A
EDGxB, EDGxA Input Capture Edge Control

Each EDGxB, EDGxA pair determines the polarity of the input signal on the corresponding ICx that will
trigger an input capture, as shown in Table 30. IC4 functions only if the I4/O5 bit in the PACTL register
is set.
Table 30 Input Capture Configuration
EDGxB
EDGxA
Capture disabled
Configuration
Capture on rising edges only
Capture on falling edges only
Capture on any edge
TMSK1 Timer Interrupt Mask 1
RESET:
$x022
Bit 7
Bit 0
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Each bit that is set in TMSK1 enables the
corresponding interrupt source.
OCxI Output Compare x Interrupt Enable
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested.
I4/O5I Input Capture 4/Output Compare 5 Interrupt Enable
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit. When I4/O5 in PACTL
is zero, I4/O5I is the output compare 5 interrupt enable bit.
ICxI Input Capture x Interrupt Enable
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested.
TFLG1 Timer Interrupt Flag 1
RESET:
$x023
Bit 7
Bit 0
OC1F
OC2F
OC3F
OC4F
I4/O5F
IC1F
IC2F
IC3F
Bits in TFLG1 are cleared by writing a one to the corresponding bit positions.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
61
OCxF Output Compare x Flag

Set each time the counter matches output compare x value.
I4/O5F Input Capture 4/Output Compare 5 Flag
Set by IC4 or OC5, depending on which function was enabled by I4/O5 of PACTL.
ICxF Input Capture x Flag
Set each time a selected active edge is detected on the ICx input line.
RESET:
$x024
Bit 7
Bit 0
TOI
RTII
PAOVI
PAII
PR1
PR0
Bits [7:4] in TMSK2 correspond bit for bit with flag bits in TFLG2. Setting any of these bits enables the
corresponding interrupt source. TMSK2 can be written only once in the first 64 cycles out of reset in
normal modes, or at any time in special modes.
TOI Timer Overflow Interrupt Enable
0 = Timer overflow interrupt disabled
1 = Interrupt requested when TOF is set
RTII Real-Time Interrupt Enable
0 = Real-time interrupt disabled
1 = Interrupt requested when RTIF is set
Bits [5:4] See 13.2 Pulse Accumulator Registers, page 64.
PR[1:0] Timer Prescaler Select
Determines the main timer prescale factor as shown in Table 31. See Table 26 for specific frequencies.
Table 31 Main Timer Prescale Control
PR[1:0]
Prescaler
00
01
10
11
16
RESET:
$x025
Bit 7
Bit 0
TOF
RTIF
PAOVF
PAIF
Bits in this register indicate when certain timer system events have occurred. Coupled with the four
high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled or
interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position.
TOF Timer Overflow Flag
Set when TCNT rolls over from $FFFF to $0000.
MOTOROLA
62
MC68HC11F1/FC0
MC68HC11FTS/D
RTIF Real-Time Interrupt Flag

Set periodically at a rate based on bits RTR[1:0] in the PACTL register.
PACTL Pulse Accumulator Control
RESET:
$x026
Bit 7
Bit 0
PAEN
PAMOD
PEDGE
I4/O5
RTR1
RTR0
I4/O5 Configure TI4/O5 Register for IC or OC
0 = OC5 function enabled
1 = IC4 function enabled
RTR[1:0] RTI Interrupt Rate Selects
These two bits select one of four rates for the real-time interrupt circuit, as shown in Table 32.
Table 32 Real-Time Interrupt Periods
E-Clock
Frequency
RTR [1:0] = %00
RTR [1:0] = 01
RTR [1:0] = 10
RTR [1:0] = 11
1 MHz
8.192 ms
16.384 ms
32.768 ms
65.536 ms
2 MHz
4.906 ms
8.192 ms
16.384 ms
32.768 ms
3 MHz
2.731 ms
5.461 ms
10.923 ms
21.845 ms
4 MHz
2.048 ms
4.096 ms
8.192 ms
16.384 ms
5 MHz
1.638 ms
3.277 ms
6.554 ms
13.107 ms
6 MHz
1.366 ms
2.731 ms
5.461 ms
10.923 ms
214/E
215/E
216/E
Any E
MC68HC11F1/FC0
MC68HC11FTS/D
13/E
MOTOROLA
63
13 Pulse Accumulator
The pulse accumulator can be used either to count events or measure the duration of a particular event.
In event counting mode, the pulse accumulators 8-bit counter increments each time a specified edge
is detected on the pulse accumulator input pin, PA7. The maximum clocking rate for this mode is the Eclock divided by two. In gated time accumulation mode, an internal clock increments the 8-bit counter
at a rate of E-clock 64 while the input at PA7 remains at a predetermined logic level.
13.1 Pulse Accumulator Block Diagram
1
INTERRUPT
REQUESTS
PAIF
PAOVF
PAII
PAOVI
TMSK2
TFLG2
INTERRUPT ENABLES
STATUS FLAGS
PAI EDGE
E 64 CLOCK
(FROM MAIN TIMER)
PAEN
2:1
MUX
INPUT BUFFER
&
EDGE DETECTION
PA7/
PAI/OC1
OVERFLOW
CLOCK
PACNT
8-BIT COUNTER
ENABLE
OUTPUT
BUFFER
PEDGE
PAEN
FROM
MAIN TIMER
OC1
PAMOD
PAEN
PACTL
FROM
DDRA
CONTROL
INTERNAL
DATA BUS
Figure 18 Pulse Accumulator Block Diagram

13.2 Pulse Accumulator Registers
RESET:
$x024
Bit 7
Bit 0
TOI
RTII
PAOVI
PAII
PR1
PR0
Bits [7:4] in TMSK2 correspond bit for bit with flag bits in TFLG2. Setting any of these bits enables the
corresponding interrupt source.
MOTOROLA
64
MC68HC11F1/FC0
MC68HC11FTS/D
Bits[7:6] See 12.2 Timer Registers, page 62.

PAOVI Pulse Accumulator Overflow Interrupt Enable
0 = Pulse accumulator overflow interrupt disabled
1 = Interrupt requested when PAOVF in TFLG2 is set
PAII Pulse Accumulator Interrupt Enable
0 = Pulse accumulator interrupt disabled
1 = Interrupt requested when PAIF in TFLG2 is set
Bits [1:0] See 12.2 Timer Registers, page 62.
RESET:
$x025
Bit 7
Bit 0
TOF
RTIF
PAOVF
PAIF
PAOVF Pulse Accumulator Overflow Flag
Set when PACNT rolls over from $FF to $00
PAIF Pulse Accumulator Input Edge Flag
Set each time a selected active edge is detected on the PAI input line
PACTL Pulse Accumulator Control
RESET:
$x026
Bit 7
Bit 0
PAEN
PAMOD
PEDGE
I4/O5
RTR1
RTR0
PAEN Pulse Accumulator System Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD Pulse Accumulator Mode
0 = Event counter
1 = Gated time accumulation
PEDGE Pulse Accumulator Edge Control
This bit has different meanings depending on the state of the PAMOD bit, as shown in Table 33.
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
65
Table 33 Pulse Accumulator Edge Control

PAMOD
PEDGE
Action on Clock
PAI falling edge increments the counter.
PAI rising edge increments the counter.
A zero on PAI inhibits counting.
A one on PAI inhibits counting.
PACNT Pulse Accumulator Count
RESET:
$x027
Bit 7
Bit 0
Bit 7
Bit 0
This eight-bit read/write register contains the count of external input events at the PAI input, or the accumulated count. The PACNT is readable even if PAI is not active in gated time accumulation mode.
The counter is not affected by reset and can be read or written at any time. Counting is synchronized
to the internal PH2 clock so that incrementing and reading occur during opposite half cycles.
MOTOROLA
66
MC68HC11F1/FC0
MC68HC11FTS/D
MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
67
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability
of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and
all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and
do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended
for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify
and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
MCUinit, MCUasm, MCUdebug, and RTEK are trademarks of Motorola, Inc. M O T O R O L A and ! are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
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MOTOROLA INC., 1997

1.2 Ordering Information

Table 2 MC68HC11F1 Extended Voltage (3.0 to 5.5 V) Device Ordering Information

68-Pin Plastic Leaded Chip

80-Pin Thin Quad Flat Pack

Table 3 MC68HC11FC0 Standard Device Ordering Information

80-Pin Thin Quad Flat Pack

Table 4 MC68HC11FC0 Extended Voltage (3.0 to 5.5 V) Device Ordering Information

Pin Assignments and Signal Descriptions

ADCTL ................ A/D Control/Status .........................................................$1030 ..........................55

1.3 Block Diagrams

512 BYTES EEPROM

1024 BYTES STATIC RAM

Figure 1 MC68HC11F1 Block Diagram

1024 BYTES STATIC RAM

Figure 2 MC68HC11FC0 Block Diagram

2 Pin Assignments and Signal Descriptions

2.1 MC68HC11F1 Pin Assignments

Figure 3 MC68HC11F1 68-Pin PLCC Pin Assignments

Figure 4 Pin Assignments for the MC68HC11F1 80-Pin QFP

2.2 MC68HC11FC0 Pin Assignments

Figure 5 MC68HC11FC0 64-Pin QFP Pin Assignments

Figure 6 MC68HC11FC0 80-Pin TQFP Pin Assignments

2.3 Pin Descriptions

Table 5 MC68HC11F1 Register and Control Bit Assignments (Continued)

3.2 MC68HC11FC0 Control Registers

Table 6 MC68HC11FC0 Register and Control Bit Assignments (Continued)

4 Operating Modes and System Initialization

Control Bits in HPRIO (Latched at Reset)

4.2 Memory Maps

1024 BYTES RAM1

Figure 7 MC68HC11F1 Memory Map

1024 BYTES RAM1

96-BYTE REGISTER FILE2

Figure 8 MC68HC11FC0 Memory Map

RBOOT Read Bootstrap ROM

Control Bits in HPRIO (Latched at Reset)

IRV Internal Read Visibility

Register Block Address

INIT RAM and I/O Mapping (MC68HC11F1 only)

OPT2 System Configuration Option Register 2

GWOM Port G Wired-OR Mode Option

CWOM Port C Wired-OR Mode Option

ADPU A/D Power-Up

CONFIG EEPROM Mapping, COP, EEPROM Enables

These bits can only be written in test and bootstrap modes.

5 Resets and Interrupts

Table 11 Interrupt and Reset Vector Assignments

SCI Serial System

SCI Receiver Overrun

SCI Receive Data Register Full

SCI Idle Line Detect

SPI Serial Transfer Complete

Pulse Accumulator Input Edge

Pulse Accumulator Overflow

Timer Input Capture 4/Output Compare 5

Timer Output Compare 4