COE 305 Syllabus - SHH

King Fahd University of Petroleum and Minerals
College of Computer Sciences and Engineering

Department of Computer Engineering
COE 305.02: Microcomputer System Design (3-3-4)
Term: 072 (2nd Term 2007/8)
Section: 02
Class Day & Time: UT 10:00 11:15 am
Class Location:
24-165
Pre-requisite: COE 205 (Computer Organization and Assembly Language).
Textbook:
Barry B. Brey, The Intel Microprocessors, Processor Architecture, Programming, and Interfacing,
Seventh Edition, 2006, Prentice Hall
John Uffenbeck, The 80x96 Family: Design, Programming, and Interfacing, Third Edition, 2002,
Prentice Hall
Instructor:
Office:
Phone:
E-mail:
Web Site:
Office Hours:
Grading Policy:
Quizzes:
10%
Homeworks:
10%
Lab:
20%
Self Learning Group Assignment (Report + Presentation): 5% (Presentations: Wed 7 May 2008, Ev.)
Major Exam I:
15% (Wed 26 March 2008, Evening)
Major Exam II:
15% (Wed 14 May 2008, Evening)
Final Exam:
25%
Course Objectives:
After successfully completing the course, students will be able to
- Describe the functions of various processor pins and processor Memory/IO Read and Write bus cycle
operations.
- Identify main types of memory technology, describe memory internal organization and design memory
interfaces.
- Specify and design simple computer serial and parallel interfaces.
- Describe how interrupts are used to implement I/O control and data transfers, design small interrupt
service routines and I/O drivers using assembly language.
- Describe method for data access from magnetic and optical disk drives using DMA
- Recognize various types of bus interfaces in a computer system
- Design and implement a medium-sized 8086 based microcomputer system.
Topics Covered:
80x86 Processor Architecture: Processor Model, Programmers model, Designers Model: 8086
hardware details, Clock generator 8284A, Bus buffering and latching, Processor Read & Write bus
cycles, Ready and wait state generation, Coprocessor NDP 8087 interface, 8288 bus controller,
Pentium processor architecture
Memory Interfacing:80x86 processor-Memory interfacing, Address decoding techniques, Memory
Devices ROM, EPROM, SRAM, FLASH, DRAM devices, Memory internal organization, Memory
read and write timing diagrams, DRAM Controller
Basic I/O Interfacing: Parallel I/O, I/O port address decoding, 8255A PPI programming, Operation
modes, Interface examples. Timer Interfacing: 8254 PIT, Timing applications. Serial I/O Interface:
Asynchronous communication, EIA RS232 standard, UART 16650, Interface examples.
Interrupts: Interrupt driven I/O, Software & Hardware interrupts, Interrupt processing, 8259A PIC
programming, cascading, Interrupt examples.
Direct Memory Access: DMA Controlled I/O, 8237 DMA Controller, Disk Memory Systems- Floppy
disk, Hard disk, optical disk memory systems.
Bus Interfaces: PC bus standards & interfaces PCI, USB, Firewire, AGP.
Course Outcomes:
Course Learning
Outcomes
O1. Ability to apply

knowledge of mathematics,
probability and engineering
in microprocessor based
system design
O2. Ability to design and

conduct experiments
related to microprocessor
based system design and to
analyze their outcomes.
Outcome Indicators and Details
Analysis of bus Fan-in and Fan-out

requirements, analysis of bus and processor
timing, performance evaluation.
CPU execution time
Memory access time and bandwidth
Wait state computation
Computation of timing delays
I/O performance such as interrupt latency and
DMA speed
Design & conduct experiments on
clock
generation, power-on-reset generation, ready
synchronization, address decoding, memory
interfacing and I/O interfacing
Assessment
Methods and
Metrics
Min. Weight
Quizzes
Assign
ments
Exams
10%
5%
Lab
work
O3. Ability to design,

Design of Clock generation, Reset
debug and test a small scale
generation & synchronization, Wait state
microprocessor based
computation & generation, Ready
system.
synchronization,
Address bus latching, data bus buffering,
Design of Memory Map, Memory Address
decoder, Memory Read and write logic.
Design of Clock generation, Reset
generation & synchronization, Wait state
computation & generation, Ready
synchronization,
Address bus latching, data bus buffering,
Design of Memory Map, Memory Address
decoder, Memory Read and write logic
Interfacing of RAM and EPROM memories.
to processor(appropriate selection and
connection of address bus, data bus,
read/write control and chip select). Modes of
I/O data transfer Programmed or Polled I/O,
Interrupt driven I/O, DMA
Design of I/O Map, I/O address decoder and
I/O Read and Write logic. Interfacing of
Parallel & Serial I/O devices to processor
using peripheral chips 8255 PPI, 8254 PIT,
8259 PIC, 8237 DMAC, 16650 UART:
- Appropriate selection and connection of
address bus, data bus, read/write control,
chip select between processor and peripheral
chips.
- Data, control and status signal
interconnections between peripheral chips
and I/O devices
- Programming of Peripheral interfacing
chips
debug and test the design as well as to
develop small
test program to test the
design correctness and timing versus some
requirements.
Revise the design appropriately
Report and document the design.
O4. Ability to function as
an effective team member
Working in a team to design, assemble and

test a small microprocessor based system
prototype
Quizzes
Assign
ments
Exams
Lab
work
Lab work
30%
5%
O5. Ability to identify,

formulate, and solve
engineering problems in
microprocessor based
system design
Identify, formulate and solve engineering

problems in the microprocessor based
system design considering the following :
- Enhancements in the processor internal
architecture, processor address & data bus width
- Latest trends and developments in Memory
Technology (SRAM, DRAM, SDRAM,
RDRAM, DDR/DDR2)
- Recent developments in I/O interfacing
standards and I/O devices
O6. Ability to use design

tools for microprocessor
system design, test and
evaluation..
Use of tools for debugging, develop

techniques for testing, and use of trace
analysis and timing for evaluation
Use of Logic analyzers, oscilloscopes, logic
probes, multimeters
Use of 8086 Flight Electronics kits to
conduct I/O interfacing experiments.
O7. Ability to engage in

self-learning.
Demonstrates reading and writing skills

Identifying, retrieving, and organizing
information
Following a learning plan
Demonstrate critical thinking skills such as
applying the facts, formulae, theories, etc. to
everyday situations.
Quizzes
Assign
ments
Exams
Lab
work
20%
i.
Lab
work
Assign
ments
Quizzes
Exams
5%
2%
Tentative Course schedule

Topics
80x86 Processor Architecture : Introduction to Intel x86 CPU Architecture Processor Model :
instruction fetching & Execution, Programmers model, Segmentation and Paging, Designers
Model : 8086 hardware details Pin-outs, 8086 minimum mode Pin functions, Clock generator
(8284A)- Pin functions, operation of Clock section, Reset section and Ready section; Bus buffering
and latching Demultiplexing the buses, Buffering the buses, System bus timing - Processor Read
& Write bus cycles, Ready and wait state generation, Minimum versus Maximum mode operations,
Coprocessor NDP 8087 interface, 8288 bus controller. Pentium processor architecture.
(Chapters 2 & 9, Part of 14) - 14 lectures
Major 1 (Wed 26 March 2008, Evening)
Memory Interfacing : Basic Concepts, 8086 processor-Memory interfacing even and odd
memory banks. Address decoding techniques Random logic (using Logic gates) decoding, block
decoding (using 74LS138, 74LS139 decoders), PROM address decoding, PLD programmable
decoding(using PLAs & PALs), Memory organization of the Pentium through Pentium 4
microprocessors. Memory Devices ROM, EPROM, SRAM, FLASH, DRAM (FPM, EDO, SDRAMSDR,DDR,DDR2, RDRAM)devices, Memory internal organization, Memory pin connections,
Memory read and write timing diagrams, DRAM Controller.
(Chapter 10) 9 lectures
I/O Interfacing : Basic Concepts, I/O addresses, instructions, and data widths, Isolated vs.
memory-mapped I/O, The PC I/O space, Basic read and write ports, Interfacing switches, LEDs,
and motors, I/O port address decoding.
.
(Chapter 11.1 & 11.2) 3 lectures
Major 2 (Wed 14 May 2008, Evening)
I/O Interfacing, Continued : The 8255A Programmable Peripheral Interface(PPI), programming
8255, Operation modes Mode 0 (Simple I/O), Mode 1(Strobed I/O with handshaking), Mode 2
(Bidirectional I/O with handshaking), Interface examples Keyboard matrix interface, 7-Segment
Display interface, Printer interface, stepper motor interface,
Timer Interfacing : The 8254 Programmable Interval Timer(PIT), Timing applications.
Serial I/O Interface : Basic concepts, Asynchronous communication, Physical communication
standard-EIA RS232, Programmable Communication Interface - Universal Asynchronous Receiver/
Transmitter 16650, Interfacing serial I/O devices- mouse, modem, PC Keyboard.
(Ch
Interrupts : Basic concepts, Interrupt driven I/O, Software & Hardware interrupts, Interrupt
vectors and vector table, Interrupt processing, The 8259A Programmable Interrupt Controller(PIC)general description, connecting single and multiple 8259s, programming the 8259, Interrupt
example Printer, Real-Time Clock, PC Keyboard.
Direct Memory Access : Basic DMA operation, DMA Controlled I/O, The 8237 DMA Controller,
Bus Interfaces : PC bus standards & interfaces PCI (Peripheral Component Interconnect) bus,
USB (Universal Serial Bus)
Final Exam
5

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King Fahd University of Petroleum and Minerals

College of Computer Sciences and Engineering

O1. Ability to apply

O2. Ability to design and

Outcome Indicators and Details

Analysis of bus Fan-in and Fan-out

O3. Ability to design,

Working in a team to design, assemble and

O5. Ability to identify,

Identify, formulate and solve engineering

O6. Ability to use design

Use of tools for debugging, develop

O7. Ability to engage in

Demonstrates reading and writing skills

Tentative Course schedule

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