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8 0 5 1 C o R E: 100MIPS, 128K Flash, 12-Bit ADC, 100-Pin MCU

This document describes the C8051F120 microcontroller, which features a 100MIPS 8051 core, 128K flash memory, 12-bit and 8-bit ADCs, 12-bit DACs, timers, serial interfaces, and on-chip debug circuitry. It operates from 2.7V to 3.6V and has analog and digital peripherals, including temperature and voltage monitoring, for embedded applications. Development kits are available to support design and debugging.

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PATEL SWAPNEEL
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83 views2 pages

8 0 5 1 C o R E: 100MIPS, 128K Flash, 12-Bit ADC, 100-Pin MCU

This document describes the C8051F120 microcontroller, which features a 100MIPS 8051 core, 128K flash memory, 12-bit and 8-bit ADCs, 12-bit DACs, timers, serial interfaces, and on-chip debug circuitry. It operates from 2.7V to 3.6V and has analog and digital peripherals, including temperature and voltage monitoring, for embedded applications. Development kits are available to support design and debugging.

Uploaded by

PATEL SWAPNEEL
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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C8051F120

100MIPS, 128K Flash, 12-bit ADC, 100-Pin MCU


PRELIMINARY

ANALOG PERIPHERALS
-

12-bit ADC
1LSB INL; No Missing Codes
Programmable Throughput up to 100ksps
Eight External Inputs; Programmable as Single-Ended or
Differential
Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
Data Dependent Windowed Interrupt Generator
Built-in Temperature Sensor ( 3C)
8-bit ADC
1LSB INL; No Missing Codes
Programmable Throughput up to 500ksps
Eight External Inputs
Programmable Amplifier Gain: 4, 2, 1, 0.5
Two 12-bit DACs
Can Synchronize Outputs to Timers for Jitter-Free Waveform
Generation
Two Comparators
Internal Voltage Reference
VDD Monitor/Brown-out Detector

ON-CHIP JTAG DEBUG & BOUNDRY SCAN


-

On-Chip Debug Circuitry Facilitates Full Speed, Non-Intrusive InSystem Debug (No Emulator Required!)
Provides Breakpoints, Single Stepping, Watchpoints, Stack Monitor
Inspect/Modify Memory and Registers
Superior Performance to Emulation Systems Using ICE-Chips,
Target Pods, and Sockets
IEEE1149.1 Compliant Boundary Scan
Low Cost, Complete Development Kit

VDD
VDD
VDD
DGND
DGND
DGND

Digital Power

AV+
AV+
AGND
AGND

Analog Power

TCK
TMS
TDI
TDO

Boundary Scan

JTAG
Logic

Debug HW

XTAL1
XTAL2

VDD
Monitor

WDT

External
Oscillator
Circuit

System
Clock

Internal
2%
Oscillator

N/M
PLL

8448 Bytes Internal Data RAM (256 + 8k)


128k Bytes FLASH; In-System Programmable in 1024-Byte Sectors
External Parallel Data Memory Interface

DIGITAL PERIPHERALS
-

64 Port I/O (All are 5V Tolerant with High Sink Current)


Hardware SMBusTM (I2CTM Compatible), SPITM, and Two UART Serial
Ports Available Concurrently
Programmable 16-bit Counter/Timer Array with Six Capture/Compare
Modules
Five General Purpose 16-bit Counter/Timers
Dedicated Watch-Dog Timer; Bi-directional Reset
Real-Time Clock Mode using Timer 3 or PCA

CLOCK SOURCES
-

Internal Oscillator: 24.5Mhz, 2% Accuracy Supports UART Operation


On-Chip Programmable PLL: up to 100MHz
External Oscillator: Crystal, RC, C, or Clock

SUPPLY VOLTAGE ........................ 2.7V to 3.6V


-

Typical Operating Current: 50mA @ 100MHz


Typical Stop Mode Current: 0.4uA

100-Pin TQFP
Temperature Range: 40C to +85C

UART0
UART1

256 Byte
Branch
Target Buffer

Prefetch
HW
32

C
o
r
e

Pipelined Instruction Architecture; Executes 70% of Instructions in 1 or 2


System Clocks
Up to 100MIPS Throughput with 100MHz System Clock
16 x 16 Multiply/Accumulate Engine (2-cycle)

MEMORY

SFR Bus

Reset

/RST

MONEN

8
0
5
1

HIGH SPEED 8051 C CORE

128kB
FLASH

256 B
RAM

C
R
O
S
S
B
A
R

SMBus

SPI Bus

6 Chnl
PCA

Timers
0, 1, 2, 4

Timer 3
P0, P1,
P2, P3
Latches

ADC
500ksps
(8-Bit)

16 x 16 Mult/Acc
(2-cycle)

C
T
L

VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7

A
M
U
X

Prog
Gain

TEMP
SENSOR

CP0+

CP0

CP0-

CP1+

P1.0/AIN1.0

P2
Drv

P2.0

P3
Drv

P3.0

P1.7/AIN1.7

P2.7

P3.7

Prog
Gain

A
M 8:1
U
X

P4.0

Bus Control

DAC0
(12-Bit)

DAC0

P1
Drv

P0.7

External Data Memory Bus

DAC1
(12-Bit)

DAC1

P0.0

VREF1

8kB
XRAM

VREF

VREF

VREFD

P0
Drv

ADC
100ksps
(12-Bit)

Address Bus

Data Bus

A
d
d
r
D
a
t
a

P4 Latch

P4
DRV

P4.4
P4.5/ALE
P4.6/RD
P4.7/WR

P5 Latch

P5
DRV

P5.0/A0

P6 Latch

P6
DRV

P6.0/A8

P7
DRV

P7.0/D0

P7 Latch

P5.7/A7

P6.7/A15

P7.7/D7

CP1

CP1-

9.2.2003

C8051F120

100MIPS, 128K Flash, 12-bit ADC, 100-Pin MCU


PRELIMINARY

SELECTED ELECTRICAL SPECIFICATIONS TA = -40C to +85C unless otherwise specified.


PARAMETER
CONDITIONS
MIN
TYP
GLOBAL CHARACTERISTICS
Supply Voltage
2.7
Supply Current (CPU active)
Clock=100MHz
50
Clock=1MHz
0.6
Clock=32kHz
16
Supply Current (shutdown)
Oscillator off; VDD Monitor Enabled
10
Oscillator off; VDD Monitor Disabled
0.4
Clock Frequency Range
DC
INTERNAL CLOCKS
Oscillator Frequency
24.0
24.5
PLL Frequency
96
98
A/D CONVERTER
Resolution
12
Integral Nonlinearity
Differential Nonlinearity
Guaranteed Monotonic
Signal-to-Noise Plus Distortion
66
69
Throughput Rate
D/A CONVERTERS
Resolution
12
Differential Nonlinearity
Guaranteed Monotonic
Output Settling Time
10

PACKAGE INFORMATION

MAX

UNITS

3.6

100

V
mA
mA
A
A
A
MHz

25.0
100

MHz
MHz

1
1
100
1

bits
LSB
LSB
dB
ksps
bits
LSB
S

C8051F120DK DEVELOPMENT KIT

MIN NOM MAX


(mm) (mm) (mm)

D1

A1 0.05

1.20

0.15

A2 0.95 1.00 1.05


b

E1

0.17 0.22 0.27

16.00

D1

14.00

0.50

16.00

E1

14.00

100
PIN 1
DESIGNATOR

A2

1
e
A
b

A1

SMBus is a trademark of Intel Corp.; I2C is a trademark of Philips Semiconductors, Inc.; SPI is a trademark of Motorola, Inc.

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