19-4709; Rev 0; 8/09

KIT
ATION
EVALU BLE
AVA ILA
Low-Cost, Multiple-Output
Power Supply for LCD TVs
General Description Features

MAX17113
The MAX17113 multiple-output power-supply controller o Optimized for 10.8V to 13.2V Input Supply
generates all the supply rails for thin-film transistor o 8V to 16.5V Input Supply Range
(TFT) liquid-crystal display (LCD) panels in TVs and o Selectable Frequency (450kHz/600kHz)
monitors operating from a regulated 12V input. It
includes a step-down and a step-up regulator, a posi- o Current-Mode Step-Up Regulator
tive and a negative charge pump, a Dual Mode logic- Built-In 24V, 3.3A, 80m n-Channel MOSFET
High-Accuracy Output Voltage (1%)
controlled high-voltage switch control block, and an
True Shutdown
adjustable-timing power-good output. The MAX17113 Fast Load-Transient Response
can operate from 8V to 16.5V input voltages and is opti- High Efficiency
mized for LCD TV panel and LCD monitor applications 10ms Internal Soft-Start
running directly from 12V supplies.
o Current-Mode Step-Down Regulator
The step-up and step-down regulators feature internal Built-In 24V, 3A, 100m n-Channel MOSFET
power MOSFETs and high-frequency operation allow- Fast Load-Transient Response
ing the use of small inductors and capacitors, resulting Adjustable Output Voltage Down to 1.5V
in a compact solution. Both switching regulators use Skip Mode at Light Load (EN2 = AGND)
fixed-frequency current-mode control architectures, High Efficiency
providing fast load-transient response and easy com- 3ms Internal Soft-Start
pensation. A current-limit function for internal switches o Adjustable Positive and Negative Charge-Pump
and output-fault shutdown protect the step-up and Regulators
step-down power supplies against fault conditions. The o Soft-Start and Timer-Delay Fault Latch for All
MAX17113 provides soft-start functions to limit inrush Outputs
current during startup. The MAX17113 provides o Logic-Controlled High-Voltage Integrated
adjustable power-up timing. Switches with Adjustable Delay
The positive and negative charge-pump regulators pro- o 120m p-Channel FET for AVDD Sequencing
vide TFT gate-driver supply voltages. Both output volt- o Input Undervoltage Lockout and Thermal-
ages can be adjusted with external resistive voltage- Overload Protection
dividers. The switch control block allows the manipula-
tion of the positive TFT gate-driver voltage. o 40-Pin, 5mm x 5mm Thin QFN Package
A series p-channel MOSFET is integrated to sequence Pin Configuration
power to AVDD after the MAX17113 has proceeded
through normal startup, and provides True Shutdown.
PGND

DEL2

FSEL

OUT
EN2

EN1

VIN

TOP VIEW
IN2
IN2
VL

The MAX17113 is available in a small (5mm x 5mm),

low-profile (0.8mm), 40-pin thin QFN package and 30 29 28 27 26 25 24 23 22 21
operates over a -40C to +85C temperature range. PGND 31 20 LX2
LX1 32 19 LX2

Applications LX1 33 18 BST

LCD TV Panels SWI 34 17 FB2

LCD Monitor Panels SWO 35 16 DEL1

FB1 36 MAX17113 15 REF
Ordering Information COMP 37 14 FBN
PART TEMP RANGE PIN-PACKAGE PGOOD 38 13 AGND

MAX17113ETL+ -40C to +85C 40 Thin QFN-EP* CRST 39 12 DRVN

+Denotes a lead(Pb)-free/RoHS-compliant package. AGND 40 11 CTL

*EP = Exposed pad. 1 2 3 4 5 6 7 8 9 10

THR
DRVP
GND2
SRC
GON
DRN
MODE
DLP
FBP
CPGND

Simplified Operating Circuit appears at end of data sheet.

Dual Mode is a trademark of Maxim Integrated Products, Inc.
THIN QFN
True Shutdown is a trademark of Maxim Integrated Products, Inc. 5mm x 5mm

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxims website at www.maxim-ic.com.
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
ABSOLUTE MAXIMUM RATINGS
MAX17113

VIN, IN2, EN1, EN2, FSEL to AGND.......................-0.3V to +24V RMS LX1 Current (total for both pins) ...................................3.2A
CPGND, GND2, PGND to AGND ........................................0.3V RMS PGND Current (total for both pins) ...............................3.2A
MODE, DLP, CTL, THR, DEL1, DEL2, VL, RMS IN2 Current (total for both pins)....................................3.2A
PGOOD to AGND .............................................-0.3V to +7.5V RMS LX2 Current (total for both pins) ...................................3.2A
REF, FBP, FBN, FB1, FB2, COMP, OUT, RMS GND2, CPGND Current................................................0.8A
CRST to AGND .......................................-0.3V to (VVL + 0.3V) RMS SWI Current ..................................................................2.4A
LX1, SWI, SWO to AGND .......................................-0.3V to +24V RMS SWO Current ................................................................2.4A
SWI to SWO ............................................................-0.3V to +24V RMS DRVN, DRVP Current ...................................................0.8A
DRVN to AGND ..........................................-0.3V to (VIN2 + 0.3V) RMS VL Current ..................................................................50mA
DRVP to AGND ........................................-0.3V to (VSWO + 0.3V) Continuous Power Dissipation (TA = +70C)
LX2 to GND2 ..............................................-0.3V to (VIN2 + 0.3V) 40-Pin Thin QFN
BST to VL................................................................-0.3V to +24V (derate 35.7mW/C above +70C) .........................2857.1mW
SRC to AGND .........................................................-0.3V to +48V Operating Temperature Range ...........................-40C to +85C
GON, DRN to AGND.................................-0.3V to (VSRC + 0.3V) Junction Temperature ......................................................+160C
SRC to DRN............................................................-0.3V to +40V Storage Temperature Range .............................-65C to +165C
DRN to AGND.........................................................-0.3V to +40V Lead Temperature (soldering, 10s)....................................+300
GON to DRN...........................................................-0.3V to +48V
REF Short Circuit to AGND.........................................Continuous

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VVIN = VIN2 = 12V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

GENERAL
VIN, IN2 Input Voltage Range 8.5 16.5 V
Only LX2 switching (VFB1 = VFBP = 1.5V, VFBN = 0V);
VIN + IN2 Quiescent Current 10 mA
EN1 = EN2 = VL, VFSEL = 0V
LX2 not switching (VFB1 = VFB2 = VFBP = 1.5V,
VIN + IN2 Standby Current 3 mA
VFBN = 0V); EN1 = EN2 = VL, VFSEL= 0V
VIN + IN2 Shutdown Current EN1 = EN2 = AGND (shutdown) 300 600 A
SWO Shutdown Current EN1 = EN2 = AGND (shutdown) 0.25 2 A
FSEL = VIN 510 600 690
SMPS Operating Frequency kHz
FSEL = AGND 390 450 510
Phase Difference Between Step-
Down/Positive and Step-Up/Negative 180 Degrees
Regulators
VIN Undervoltage Lockout Threshold VIN rising edge, 100mV typical hysteresis 6.0 7.0 8.3 V
VL REGULATOR
IVL = 25mA, VFB1 = VFB2 = VFBP = 1.1V, VFBN = 0.4V
VL Output Voltage 4.9 5.0 5.15 V
(all regulators switching)
VL Undervoltage Lockout Threshold VL rising edge, 100mV typical hysteresis 3.6 4.0 4.5 V

2 _______________________________________________________________________________________
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
ELECTRICAL CHARACTERISTICS (continued)

MAX17113
(Circuit of Figure 1, VVIN = VIN2 = 12V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

REFERENCE
REF Output Voltage No external load 1.235 1.250 1.265 V
REF Load Regulation 0 < ILOAD < 50A 10 mV
REF Sink Current In regulation 10 A
REF Undervoltage-Lockout Threshold Rising edge; 25mV typical hysteresis 1.0 1.2 V
STEP-DOWN REGULATOR
FB2 = AGND, no load 0C < TA < +85C 3.25 3.30 3.35
OUT Voltage in Fixed Mode V
(Note 1) TA = +25C 3.267 3.333
VOUT = 2.5V, no load 0C < TA < +85C 1.23 1.25 1.27
FB2 Voltage in Adjustable Mode V
(Note 1) TA = +25C 1.2375 1.2625
FB2 Adjustable-Mode
Dual-mode comparator 0.10 0.15 0.20 V
Threshold Voltage
Output-Voltage Adjust Range Step-down output 1.5 5.0 V
FB2 Fault Trip Level Falling edge 0.94 1.00 1.06 V
FB2 Input Bias Current VFB2 = 1.5V, TA = +25C 50 125 200 nA
DC Load Regulation 0.4A < ILOAD < 2A 0.5 %
DC Line Regulation No load, 10.8V < VIN2 < 13.2V 0.05 %/V
LX2-to-IN2 nMOS Switch
100 200 m
On-Resistance
LX2-to-CPGND nMOS Switch
7 12 25
On-Resistance
BST-to-VL pMOS Switch
7 12 25
On-Resistance
Low-Frequency Operation
Step-down only 0.8 V
OUT Threshold
Low-Frequency Operation FSEL = VIN 100
kHz
Switching Frequency FSEL = AGND 75
LX2 Positive Current Limit 2.50 3 3.50 A
Soft-Start Period 3.3 ms
VREF/
Soft-Start Step Size V
128
Maximum Duty Factor 65 75 90 %
POWER-GOOD
FB2 Power-Good Threshold FB2 rising 0.94 1.00 1.06 V
FB2 Threshold Hysteresis 12 mV
PGOOD Output Low Voltage IPGOOD = 1mA 0.1 0.3 V
PGOOD Leakage Current VPGOOD = 3V, TA = +25C 1 A
CRST Charge Current VCRST = 1V 0.8 1.0 1.2 A
CRST Voltage Threshold 1.2 1.25 1.3 V
CRST Pulldown Resistance VCRST = 1V 150 300

_______________________________________________________________________________________ 3
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
ELECTRICAL CHARACTERISTICS (continued)
MAX17113

(Circuit of Figure 1, VVIN = VIN2 = 12V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

STEP-UP REGULATOR
Output-Voltage Range VVIN 18 V
Minimum tON 70 100 ns
FB1 = COMP, TA = +25C 1.2375 1.250 1.2625
FB1 Regulation Voltage V
CCOMP = 1mF 0C < TA < +85C 1.225 1.275
FB1 Fault Threshold FB rising, hysteresis = 12mV 0.96 1.0 1.06 V
FB1 UVLO Threshold 0.05 0.125 0.2 V
FB1 Load Regulation 0A < ILOAD < full 0.5 %
FB1 Line Regulation 10.8V < VIN < 13.2V 0.08 0.15 %/V
FB1 Input Bias Current VFB1 = 1.25V 20 125 300 nA
FB1 Transconductance I = 2.5A at COMP, FB1 = COMP 125 320 600 S
FB1 Voltage Gain FB1 to COMP 1400 V/V
LX1 Leakage Current VFB1 = 1.5V, VLX1 = 20V 10 25 A
LX1 Current Limit VFB1 = 1.1V, duty cycle = 25% 2.8 3.3 3.8 A
Current-Sense Transresistance 0.1 0.2 0.30 V/A
LX1 On-Resistance 80 200 m
Soft-Start Period 10 ms
ILIM/
Soft-Start Step Size A
128
POSITIVE AND NEGATIVE CHARGE-PUMP REGULATORS
0C < TA < +85C 1.23 1.25 1.27
FBP Regulation Voltage V
TA = +25C 1.2375 1.2625
FBP Line-Regulation Error 11V < VSUP < 16V, not in dropout 0.01 0.2 %/V
FBP Input Bias Current VFBP = 1.5V, TA = +25C -50 +50 nA
DRVP p-Channel MOSFET
2.0 4.0
On-Resistance
DRVP n-Channel MOSFET
0.8 1.5
On-Resistance
FBP Fault Trip Level Falling edge 0.96 1.02 1.08 V
Positive Charge-Pump Soft-Start Period 3.3 ms
Positive Charge-Pump VREF/
V
Soft-Start Step Size 128
0C < TA < +85C 0.985 1.000 1.015
FBN Regulation Voltage VREF VFBN V
TA = +25C 0.99 1.00 1.01
FBN Input Bias Current VFBN = 250mV, TA = +25C -50 +50 nA
FBN Line Regulation Error 11V < VSUP < 16V, not in dropout 0.01 0.2 %/V
DRVN p-Channel On-Resistance 2.0 4.0
DRVN n-Channel On-Resistance 0.8 1.5
FBN Fault Trip Level Rising edge 450 500 550 mV

4 _______________________________________________________________________________________
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
ELECTRICAL CHARACTERISTICS (continued)

MAX17113
(Circuit of Figure 1, VVIN = VIN2 = 12V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Negative Charge-Pump
2 ms
Soft-Start Period
Negative Charge-Pump (VREF -
V
Soft-Start Step Size VFBN/128
AVDD SWITCH
SWI Supply Range 8.0 18.5 V
SWI Overvoltage Fault Threshold SWI rising edge, 300mV typical hysteresis (Note 2) 18.50 19.2 19.90 V
SWI-SWO Switch Resistance 120 250 m
HIGH-VOLTAGE SWITCH ARRAY
SRC Supply Range 44 V
SRC Supply Current 250 500 A
GON-to-SRC Switch On-Resistance VDLP = 2V, CTL = VL 10 20
GON-to-SRC Switch Saturation Current (VSRC - VGON) > 5V 180 390 mA
GON-to-DRN Switch On-Resistance VDLP = 2V, CTL = AGND 25 50
GON-to-DRN Switch Saturation Current (VGON - VDRN) > 5V 40 180 mA
GON-to-GND Switch On-Resistance DLP = AGND, VGON = 5V 5 10 k
CTL Input Low Voltage 0.6 V
CTL Input High Voltage 1.6 V
CTL Input Current CTL = AGND or VL, TA = +25C -1 +1 A
1k from DRN to GND, CTL = AGND to VL step, no
CTL-to-GON Rising Propagation Delay 100 ns
load on GON, measured from VCTL = 2V to GON = 20%
1k from DRN to GND, CTL = VL to AGND step, no load
CTL-to-GON Falling Propagation Delay 200 ns
on GON, measured from VCTL = 0.6V to GON = 80%
MODE Switch On-Resistance 1200
Mode 1 Voltage Threshold VMODE rising 3.8 4.1 V
MODE Capacitor Charge Current
VMODE = 1V 40 50 65 A
(Mode 2)
MODE Voltage Threshold for Enabling
GON connects to DRN 1.15 1.25 1.35 V
DRN Switch Control in Mode 2
MODE Current-Source Stop
MODE rising 2 3 V
Voltage Threshold
THR-to-GON Voltage Gain 9.4 10.0 10.6 V/V
SEQUENCE CONTROL
EN1, EN2 Input Low Voltage 0.6 V
EN1, EN2 Input High Voltage 1.6 V
EN1, EN2 Pulldown Resistance 1 M
DEL1, DEL2, DLP Charge Current VDEL1 = VDEL2 = VDLP = 1V 7 8 9 A
DEL1, DEL2, DLP Turn-On Threshold 1.2 1.25 1.32 kV
DEL1, DEL2, DLP Discharge
EN1 = AGND or fault tripped 10
Switch On-Resistance
FBN Discharge Switch On-Resistance EN2 = AGND or fault tripped 3 k
_______________________________________________________________________________________ 5
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
ELECTRICAL CHARACTERISTICS (continued)
MAX17113

(Circuit of Figure 1, VVIN = VIN2 = 12V, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
FAULT DETECTION
Duration to Trigger Fault 45 55 65 ms
Duration to Restart After Fault 240 ms
Number of Restart Attempts
3 Times
Before Shutdown
Thermal-Shutdown Threshold 15C typical hysteresis +160 C
SWITCHING FREQUENCY SELECTION
FSEL Input Low Voltage 450kHz 0.6 V
FSEL Input High Voltage 600kHz 1.6 V
FSEL Pulldown Resistance 1 M

ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VVIN = VIN2 = 12V, TA = -40C to +85C. Typical values are at TA = +25C, unless otherwise noted.) (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
GENERAL
VIN + IN2 Input-Voltage Range 8.5 16.5 V
VIN + IN2 Shutdown Current EN1 = EN2 = AGND (shutdown) 600 A
SWO Shutdown Current EN1 = EN2 = AGND (shutdown) 2 A
FSEL = VIN 510 690
SMPS Operating Frequency kHz
FSEL = AGND 390 510
VIN Undervoltage-Lockout Threshold VIN rising edge, 100mV typical hysteresis 5.75 7.25 V
VL REGULATOR
IVL = 25mA, VFB1 = VFB2 = VFBP = 1.1V,
VL Output Voltage 4.9 5.15 V
VFBN = 0.4V (all regulators switching)
VL Undervoltage-Lockout Threshold VL rising edge, 100mV typical hysteresis 3.6 4.5 V
REFERENCE
REF Output Voltage No external load 1.235 1.265 V
REF Load Regulation 0 < ILOAD < 50A 10 mV
REF Undervoltage-Lockout Threshold Rising edge; 25mV typical hysteresis 1.2 V
STEP-DOWN REGULATOR
OUT Voltage in Fixed Mode FB2 = GND, no load (Note 1) 3.25 3.35 V
FB2 Voltage in Adjustable Mode VOUT = 2.5V, no load (Note 1) 1.23 1.27 V
FB2 Adjustable-Mode
Dual-mode comparator 0.10 0.20 V
Threshold Voltage
Output-Voltage Adjust Range Step-down output 1.5 5.0 V

6 _______________________________________________________________________________________
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
ELECTRICAL CHARACTERISTICS (continued)

MAX17113
(Circuit of Figure 1, VVIN = VIN2 = 12V, TA = -40C to +85C. Typical values are at TA = +25C, unless otherwise noted.) (Note 3)

PARAMETER CONDITIONS MIN TYP MAX UNITS

LX2-to-IN2 nMOS Switch
200 m
On-Resistance
LX2-to-CPGND nMOS Switch
7 25
On-Resistance
BST-to-VL pMOS Switch On-Resistance 7 25
LX2 Positive Current Limit 2.50 3.50 A
Maximum Duty Factor 65 90 %
FB2 Power-Good Threshold FB2 rising 0.94 1.06 V
PGOOD Output Low Voltage IPGOOD = 1mA 0.3 V
CRST Charge Current VCRST = 1V 0.8 1.2 A
CRST Voltage Threshold 1.2 1.3 V
CRST Pulldown Resistance VCRST = 1V 300
STEP-UP REGULATOR
Output-Voltage Range VVIN 18 V
Oscillator Maximum Duty Cycle 65 90 %
FB1 Regulation Voltage FB1 = COMP, CCOMP = 1nF 1.225 1.275 V
LX1 Current Limit VFB1 = 1.1V, duty cycle = 25% 3.2 4.2 A
Current-Sense Transresistance 0.10 0.30 V/A
LX1 On-Resistance 200 m
POSITIVE AND NEGATIVE CHARGE-PUMP REGULATORS
FBP Regulation Voltage 1.23 1.27 V
DRVP p-Channel MOSFET
4
On-Resistance
DRVP n-Channel MOSFET
1.5
On-Resistance
FBN Regulation Voltage VREF - VFBN 0.985 1.015 V
DRVN p-Channel On-Resistance 3
DRVN n-Channel On-Resistance 1.5
AVDD SWITCH
SWI Supply Range 8.0 18.5 V
SWI Overvoltage Fault Threshold VSWI = rising, 300mV typical hysteresis (Note 3) 18.5 19.9 V
SWI-SWO Switch Resistance 360 m
HIGH-VOLTAGE SWITCH ARRAY
SRC Supply Range 44 V
GON-to-SRC Switch On-Resistance VDLP = 2V, CTL = VL 20
GON-to-DRN Switch On-Resistance VDLP = 2V, CTL = AGND 50
GON-to-GND Switch On-Resistance DLP = AGND, VGON = 5V 2.5 10 k
CTL Input Low Voltage 0.6 V
CTL Input High Voltage 1.6 V
Mode 1 Voltage Threshold VMODE rising edge 4.1 V

_______________________________________________________________________________________ 7
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
ELECTRICAL CHARACTERISTICS (continued)
MAX17113

(Circuit of Figure 1, VVIN = VIN2 = 12V, TA = -40C to +85C. Typical values are at TA = +25C, unless otherwise noted.) (Note 3)

PARAMETER CONDITIONS MIN TYP MAX UNITS

MODE Voltage Threshold for Enabling
GON connects to DRN 1.15 1.35 V
DRN Switch Control in Mode 2
MODE Current-Source Stop Voltage
MODE rising 2 3 V
Threshold
THR-to-GON Voltage Gain 9.4 10.6 V/V
SEQUENCE CONTROL
EN1, EN2 Input Low Voltage 0.6 V
EN1, EN2 Input High Voltage 1.6 V
SWITCHING FREQUENCY SELECTION
FSEL Input Low Voltage 600kHz 0.6 V
FSEL Input High Voltage 1.2MHz 1.6 V
Note 1: When the inductor is in continuous conduction (EN2 = VL or heavy load), the output voltage has a DC regulation level lower than
the error comparator threshold by 50% of the output-voltage ripple. In discontinuous conduction (EN2 = GND with light load), the
output voltage has a DC regulation level higher than the error comparator threshold by 50% of the output-voltage ripple.
Note 2: Disables boost switching if either SUP, SWI, or OVIN exceeds the threshold. Switching resumes when no threshold is exceeded.
Note 3: Specifications to TA = -40C are guaranteed by design, not production tested.

Typical Operating Characteristics

(Circuit of Figure 1. VIN = VINL = VSUPP = 12V, AVDD = 16V, VGON = 34.5V, VGOFF = -6V, VOUT1 = 3.3V, TA = +25C, unless other-
wise noted.)

STEP-DOWN REGULATOR EFFICIENCY STEP-DOWN REGULATOR OUTPUT STEP-DOWN REGULATOR

vs. LOAD CURRENT VOLTAGE vs. LOAD CURRENT LOAD-TRANSIENT RESPONSE
MAX17113 toc03
85 3
MAX17113 toc01

MAX17113 toc02

80 IOUT
2 2A/div
OUTPUT-VOLTAGE ERROR (%)

EN1 = VL, EN2 = GND 50mA

75 EN2 = GND
V
3.3V OUT
EFFICIENCY (%)

1 200mV/div
70
AC-COUPLED

65
0

60 EN1 = VL, EN2 = VL INDUCTOR

EN2 = VL
-1 CURRENT
55 0A 2A/div
L = 4.7FH
50 -2
0.01 0.10 1 10 0 0.40 0.80 1.20 1.60 2.00 2.40 20Fs/div
LOAD CURRENT (A) LOAD CURRENT (A)

8 _______________________________________________________________________________________
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
Typical Operating Characteristics (continued)

MAX17113
(Circuit of Figure 1. VIN = VINL = VSUPP = 12V, AVDD = 16V, VGON = 34.5V, VGOFF = -6V, VOUT1 = 3.3V, TA = +25C, unless other-
wise noted.)

STEP-DOWN REGULATOR STEP-UP REGULATOR EFFICIENCY

SOFT-START (HEAVY LOAD) vs. LOAD CURRENT
MAX17113 toc04
100

MAX17113 toc05
VIN
5V/div 95
90

VOUT 85
0V

EFFICIENCY (%)
2V/div 80
0V 75
INDUCTOR
CURRENT 70
500mA/div 65
0A
60
3.3V VLX2
55
10V/div
0V 50
2ms/div 0.01 0.1 1 10
LOAD CURRENT (A)

STEP-UP REGULATOR STEP-DOWN REGULATOR

OUTPUT VOLTAGE vs. LOAD CURRENT SOFT-START (HEAVY LOAD)
MAX17113 toc07
0.8
MAX17113 toc06

EN2
0.6 5V/div
OUTPUT-VOLTAGE ERROR (%)

0V
VSRC
20V/div
0.4
0V DEL2
5V/div
0.2 0V
VAVDD
10V/div
0
0V INDUCTOR
CURRENT
0A 1A/div
-0.2
0 0.5 1.0 1.5 2.0 10ms/div
LOAD CURRENT(A)

STEP-UP REGULATOR STEP-UP REGULATOR PULSED

LOAD-TRANSIENT RESPONSE LOAD-TRANSIENT RESPONSE
MAX17113 toc08 MAX17113 toc09

LOAD LOAD
CURRENT CURRENT
1A/div 2A/div
100mA 0.2A

VAVDD VAVDD
500mV/div 200mV/div
0V 16V

INDUCTOR INDUCTOR
CURRENT CURRENT
2A/div 2A/div
0A 0A

100Fs/div 10Fs/div
RCOMP = 50.5kI
CCOMP = 330pF

_______________________________________________________________________________________ 9
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
Typical Operating Characteristics (continued)
MAX17113

(Circuit of Figure 1. VIN = VINL = VSUPP = 12V, AVDD = 16V, VGON = 34.5V, VGOFF = -6V, VOUT1 = 3.3V, TA = +25C, unless other-
wise noted.)
STEP-UP REGULATOR CURRENT LIMIT TIME-DELAY LATCH
vs. INPUT VOLTAGE RESPONSE TO OVERLOAD
MAX17113 toc11
4.0

MAX17113 toc10
L1 = 10FH
VOUT
5V/div
0V
VAVDD
STEP-UP REGULATOR
CURRENT LIMIT (A)

3.5 10V/div
0V
VGON
0V 50V/div
3.0 VGOFF
50V/div

L2 INDUCTOR
CURRENT
2.5 0A 5A/div
8 9 10 11 12 13 14 200ms/div
INPUT VOLTAGE (V)

SWITCHING FREQUENCY
vs. INPUT VOLTAGE VL LOAD REGULATION
610 2
MAX17113 toc12

MAX17113 toc13
608
606
OUTPUT-VOLTAGE ERROR (%)
SWITCHING FREQUENCY (kHz)

1
604
602
600 0
598
596
-1
594
592
590 -2
8 9 10 11 12 13 14 0 20 40 60 80 100
VIN (V) LOAD CURRENT (mA)

NORMALIZED REFERENCE VOLTAGE POSITIVE CHARGE-PUMP REGULATOR

LOAD REGULATION NORMALIZED LINE REGULATION
0.2 0.05
MAX17113 toc15
MAX17113 toc14

0.02
OUTPUT-VOLTAGE ERROR (%)

OUTPUT-VOLTAGE ERROR

0.1
POSITIVE CHARGE-PUMP

ISRC = 0A
-0.01
0
-0.04
ISRC = 25mA
-0.1
-0.07

-0.2 -0.10
0 50 100 150 200 10 11 12 13 14 15 16 17 18
LOAD CURRENT (FA) VIN (V)

10 ______________________________________________________________________________________
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
Typical Operating Characteristics (continued)

MAX17113
(Circuit of Figure 1. VIN = VINL = VSUPP = 12V, AVDD = 16V, VGON = 34.5V, VGOFF = -6V, VOUT1 = 3.3V, TA = +25C, unless other-
wise noted.)

POSITIVE CHARGE-PUMP REGULATOR POSITIVE CHARGE-PUMP REGULATOR

NORMALIZED LOAD REGULATION LOAD-TRANSIENT RESPONSE
MAX17113 toc17
0.8

MAX17113 toc16
VSRC
0.4
500mV/div
OUTPUT-VOLTAGE ERROR (%)

34.8V
0

-0.4
70mA
-0.8
LOAD
-1.2 CURRENT
20mA/div
-1.6 10mA

-2.0
0 25 50 75 100 125 150 100Fs/div
LOAD CURRENT (mA)

NEGATIVE CHARGE-PUMP REGULATOR NEGATIVE CHARGE-PUMP REGULATOR

NORMALIZED LINE REGULATION NORMALIZED LOAD REGULATION
0.25 0.4
MAX17113 toc18

MAX17113 toc19
0.2
0.05
OUTPUT-VOLTAGE ERROR (%)

OUTPUT-VOLTAGE ERROR (%)

-0.15 -0.2

-0.4
-0.35 -0.6

-0.8
-0.55
-1.0

-0.75 -1.2
9 10 11 12 13 14 15 16 0 50 100 150 200 250
VIN (V) LOAD CURRENT (mA)

NEGATIVE CHARGE-PUMP REGULATOR

LOAD-TRANSIENT RESPONSE POWER-UP SEQUENCE
MAX17113 toc20 MAX17113 toc21
VEN1
VGOFF 5V/div
0V VOUT
200mV/div 5V/div
-6V 0V VDEL1
0V 5V/div
VGOFF
5V/div
VAVDD
10V/div
VDEL2
110mA
LOAD 5V/div
CURRENT 0V
50mA/div 0V
VSRC
10mA 20V/div
0V
100Fs/div 20ms/div

______________________________________________________________________________________ 11
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
Typical Operating Characteristics (continued)
MAX17113

(Circuit of Figure 1. VIN = VINL = VSUPP = 12V, AVDD = 16V, VGON = 34.5V, VGOFF = -6V, VOUT1 = 3.3V, TA = +25C, unless other-
wise noted.)

POWER-GOOD FUNCTION VIN SUPPLY CURRENT vs. VIN VOLTAGE

MAX17113 toc22
VOUT 6

MAX17113 toc23
1V/div
5

VIN SUPPLY CURRENT (mA)

VCRST
1V/div 4
EN1 = EN2 = VL
0V 3

0V
VIN 2
5V/div EN1 = EN2 = GND
VPGOOD
0V 5V/div 1

0V 0
4ms/div 8 9 10 11 12 13 14 15 16
VIN VOLTAGE (V)

VIN SUPPLY CURRENT HIGH-VOLTAGE SWITCH

vs. TEMPERATURE CONTROL FUNCTION (MODE 1)
MAX17113 toc25
3.0
MAX17113 toc24

VCTL
2.5 5V/div
VIN SUPPLY CURRENT (mA)

0V
2.0 VMODE
5V/div
EN1 = VL, EN2 = GND 0V
1.5

VGON
1.0
EN1 = EN2 = GND 10V/div

0.5

0V
0
-40 -15 10 35 60 85 4Fs/div
RDRN = 1kI
TEMPERATURE (NC) CGON = 0.1FF

HIGH-VOLTAGE SWITCH
CONTROL FUNCTION (MODE 2)
MAX17113 toc26

VCTL
5V/div
0V
VMODE
2V/div
0V

VGON
10V/div

0V
4ms/div
RDRN = 1kI
CGON = 0.1FF

12 ______________________________________________________________________________________
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
Pin Description

MAX17113
PIN NAME FUNCTION
GON Low-Level Regulation Set-Point Input. Connects THR to the center of a resistive voltage-divider
1 THR between AVDD and GND to set the VGON falling regulation level. The actual level is 10 VTHR. See the
High-Voltage Switch Control section for details.
2 DRVP Positive Charge-Pump Driver Output. Connects DRVP to the positive charge-pump flying capacitor(s).
3 GND2 Internal Buck LSS Power Ground
4 SRC Switch Input. Source of the internal high-voltage p-channel MOSFET between SRC and GON.
Internal High-Voltage MOSFET Switch Common Terminal. GON is the output of the high-voltage switch-
5 GON
control block.
6 DRN Switch Input. Drain of the internal high-voltage p-channel MOSFET connected to GON.
High-Voltage Switch-Control Block Mode Selection Input and Timing-Adjustment Input. See the High-
Voltage Switch Control section for details. MODE is high impedance when it is connected to VL. MODE
7 MODE
is internally pulled to GND by a 10 resistor for 0.1s (typ) when the high-voltage switch-control block
is enabled.
8 DLP GON Output Enable. See the High-Voltage Switch Control section for details.
Positive Charge-Pump Regulator Feedback Input. Connects FBP to the center of a resistive voltage-
9 FBP divider between the positive charge-pump regulator output and AGND to set the positive charge-pump
regulator output voltage. Place the resistive voltage-divider within 5mm of FBP.
10 CPGND Charge Pump and Internal Step-Down Regulator Pulldown Switch Power Ground
11 CTL High-Voltage Switch-Control Block Timing Control Input. See the High-Voltage Switch Control section
12 DRVN Negative Charge-Pump Driver Output. Connects DRVN to the negative charge-pump flying capacitor(s).
13, 40 AGND Analog Ground
Negative Charge-Pump Regulator Feedback Input. Connects FBN to the center of a resistive voltage-
14 FBN divider between the negative output and REF to set the negative charge-pump regulator output voltage.
Place the resistive voltage-divider within 5mm of FBN.
Reference Output. Connects a 0.22F capacitor from REF to AGND. All power outputs are disabled
15 REF
until REF exceeds its UVLO threshold. REF is active whenever VIN is above its UVLO threshold.
Negative Charge-Pump Delay Input. Connects a capacitor from DEL1 and AGND to set the delay time
16 DEL1 between the step-down output and the negative output. An 8A current source charges CDEL1. DEL1 is
internally pulled to AGND through 10 resistance when EN1 is low or VL is below its UVLO threshold.
Step-Down Regulator Feedback Input. Connects FB2 to GND to select the step-down converters 3.3V
fixed mode. For adjustable mode, connect FB2 to the center of a resistive voltage-divider between the
17 FB2
step-down regulator output and GND to set the step-down regulator output voltage. Place the resistive
voltage-divider within 5mm of FB2.
Step-Down Regulator Bootstrap Capacitor Connection for High-Side Gate Driver. Connects a 0.1F
18 BST
ceramic capacitor from BST to LX2.
Step-Down Regulator Switching Node. LX2 is the source of the internal n-channel MOSFET connected
19, 20 LX2 between IN2 and LX2. Connect the inductor and Schottky catch diode to both LX2 pins to minimize the
trace area for low EMI.
21 OUT Step-Down Regulator Output-Voltage Sense Input. Connects OUT to the step-down regulator output.
Step-Down Regulator Power Input. Drain of the internal n-channel MOSFET connected between IN2 and
22, 23 IN2
LX2.
Input of the Internal 5V Linear Regulator and the Startup Circuitry. Bypass VIN to AGND with 0.22F
24 VIN
close to the IC.

______________________________________________________________________________________ 13
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
Pin Description (continued)
MAX17113

PIN NAME FUNCTION

Frequency Select Pin. Connect FSEL to AGND for 450kHz operation. Connect to VL or VIN for 600kHz
25 FSEL
operation.
Step-Down and Negative Charge-Pump Regulator Enable Input. Input high also enables DLY1 pullup
26 EN1
current.
Step-Up Regulator and Positive Charge-Pump Delay Input. Connects a capacitor from DEL2 and
AGND to set the delay time between EN2 and the startup of these regulators, or between the step-
27 DEL2 down startup and the startup of these regulators if EN1 is high before the step-down starts. An 8A
current source charges CDEL2. DEL2 is internally pulled to AGND through 10
resistance when EN1
or EN2 is low or when VL is below its UVLO threshold.
5V Internal Linear Regulator Output. Bypass VL to AGND with 1
F minimum. Provides power for the
internal MOSFET driving circuit, the PWM controllers, charge-pump regulators, logic, and reference
28 VL
and other analog circuitry. Provides 25mA load current when all switching regulators are enabled. VL
is active whenever VIN is above its UVLO threshold.
Step-Up and Positive Charge-Pump Regulator Enable Input. Input high also enables DLY2 pullup
29 EN2
current. EN2 is inactive when EN1 is low.
30, 31 PGND Step-Up Regulator Power Ground. Source of the internal power n-channel MOSFET.
Step-Up Regulator Power MOSFET n-Channel Drain and Switching Node. Connects the inductor and
32, 33 LX1
Schottky catch diode to both LX1 pins and minimize the trace area for the lowest EMI.
Step-Up Regulator Internal PMOS Pass Switch Source Input. Connects to the anode of the step-up
34 SWI
regulator Schottky catch diode.
35 SWO Step-Up Regulator Internal pMOS Pass Switch Drain Output
Boost Regulator Feedback Input. Connects FB1 to the center of a resistive voltage-divider between
36 FB1 the boost regulator output and AGND to set the boost regulator output voltage. Place the resistive
voltage-divider within 5mm of FB1.
Compensation Pin for the Step-Up Error Amplifier. Connects a series resistor and capacitor from
37 COMP
COMP to AGND.
38 PGOOD Open-Drain Power-Good Output. Monitors the step-down output voltage.
Power-Good Reset Timing Pin. Connects a capacitor from CRST to AGND to set the step-down
39 CRST
output-rising PGOOD delay.
EP Exposed Pad = AGND

14 ______________________________________________________________________________________
 Low-Cost, Multiple-Output
Power Supply for LCD TVs

MAX17113
L1
4.7H
VIN
12V C2 C3
10F 10F

22 23 D1
30 31 32 33
10F
IN2 IN2 PGND PGND LX1 LX1
34
18 SWI
BST C24
10F AVDD
0.1F
OUT 16V
19 1.5A
3.3V LX2 35
2A L2 20 LX2 SWO
C5 2.4H C15, C16
22F D2 2x
3 10F 158k
GND2

21 FB1 36
OUT
17 37
FB2 COMP
13.3k
100k
330pF
24 40
VIN AGND 33.3k
VIN
0.1F 1
THR
28 VL 11 FROM GON
VL CTL
25 6 CONTROL 2.2k
1F FSEL DRN
7 1k
MODE
15 MAX17113 5 GON
REF REF GON 35V
100mA
0.22F 3.3V
13
AGND
27
DEL2
38
0.1F PGOOD PGOOD
39
16 CRST
DEL1
0.15F 1F
4
STEP-DOWN, NEGATIVE 26 EN1 SRC
ON/OFF
STEP-UP, POSITIVE 29 SRC
EN2 0.22F
CHARGE PUMP ON/OFF 8 2
DLP DRVP D4
0.15F

GOFF
-6V 0.1F 0.22F
12 0.22F
100mA 1F DRVN D5
367k
150k FBN CPGND FBP
EP AVDD
D3 14 10 9

23k 13.3k

REF

Figure 1. Typical Operating Circuit

______________________________________________________________________________________ 15
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
Typical Operating Circuit Detailed Description
MAX17113

The typical operating circuit (Figure 1) of the The MAX17113 is a multiple-output power supply
MAX17113 is a complete power-supply system for TFT designed primarily for TFT LCD panels used in monitors
LCD panels in monitors and TVs. The circuit generates and TVs. It contains a step-down switching regulator to
a +3.3V logic supply, a +16V source driver supply, a generate the logic supply rail, a step-up switching regu-
+34.5V positive gate driver supply, and a -6V negative lator to generate the source driver supply, and two
gate driver supply from a 12V 10% input supply. charge-pump regulators to generate the gate driver
Table 1 lists some selected components and Table 2 supplies. Each regulator features adjustable output volt-
lists the contact information for component suppliers. age, digital soft-start, and timer-delayed fault protection.
Both the step-down and step-up regulators use a fixed-
Table 1. Component List frequency current-mode control architecture. The two
switching regulators are 180 out-of-phase to minimize
DESIGNATION DESCRIPTION
the input ripple. The internal oscillator offers two pin-
10F 20%, 16V X5R ceramic capacitors selectable frequency options (450kHz/600kHz), allowing
(1206) users to optimize their designs based on the specific
C1, C2, C3
Taiyo Yuden EMK325BJ106MD application requirements. In addition, the MAX17113
TDK C3225X7R1C106M features a high-voltage switch-control block, a PGOOD
22F 10%, 6.3V X5R ceramic capacitor logic block, an internal 5V linear regulator, a 1.25V refer-
(1206) ence output, well-defined power-up and power-down
C5 sequences, and thermal-overload protection. Figure 2
Taiyo Yuden JMK316BJ226KL
Murata GRM31CR60J226M shows the MAX17113 functional diagram.

10F 20%, 25V X5R ceramic capacitors Step-Down Regulator

C15, C16, C24 (1210) The step-down regulator consists of an internal n-chan-
TDK C3225X5R1E106M nel MOSFET with gate driver, a lossless current-sense
network, a current-limit comparator, and a PWM con-
3A, 30V Schottky diodes (M-Flat) troller block. The external power stage consists of a
D1, D2 Toshiba CMS02 (TE12L,Q) Schottky diode rectifier, an inductor, and output capac-
Central Semiconductor itors. The output voltage is regulated by changing the
200mA, 100V dual ultra-fast diodes duty cycle of the n-channel MOSFET. A bootstrap cir-
(SOT23) cuit that uses a 0.1F flying capacitor between LX2 and
D3, D4, D5 Fairchild MMBD4148SE (top mark D4) BST provides the supply voltage for the high-side gate
Central Semiconductor CMPD1001S lead driver. Although the MAX17113 also includes a 10
free (top mark L21) (typ) low-side MOSFET, this switch is used to charge
Low-profile 4.7H, 3.5A inductor the bootstrap capacitor during startup and maintains
L1 (2mm height) fixed-frequency operation at light load and cannot be
TOKO FDV0620-4R7M used as a synchronous rectifier. An external Schottky
diode (D2 in Figure 1) is always required.
Low-profile 2.4H, 2.6A inductor
(1.8mm height)
L2
TOKO 1124BS-2R4M (2.4H)
Wrth 744052002 (2.5H)

Table 2. Component Suppliers

SUPPLIER PHONE FAX WEBSITE
Fairchild Semiconductor 408-822-2000 408-822-2102 www.fairchildsemi.com
Sumida Corp. 847-545-6700 847-545-6720 www.sumida.com
TDK Corp. 847-803-6100 847-390-4405 www.component.tdk.com
Toshiba America Electronic Components, Inc. 949-455-2000 949-859-3963 www.toshiba.com/taec

16 ______________________________________________________________________________________
 Low-Cost, Multiple-Output
Power Supply for LCD TVs

MAX17113
VIN (12V)

BST
IN2 VL
MAX17113 LX1

3.3V
2A LX2 STEP-UP
STEP-DOWN OSC
PGND

GND2 FB1
COMP
OUT

AGND
FSEL
VL
SWI

P
150mV SWO AVDD
FB2 16V
1.5A
VIN 3.3V
VIN

VL VL
VL PGOOD
PGOOD
RESET CRST

REF
REF REF
AGND DRN

STEP-DOWN, NEGATIVE EN1 THR

ON/OFF
EN2 MODE
STEP-UP, POSITIVE
HV
CHARGE PUMP ON/OFF DEL1 POWER-UP SWITCH
DEL2 SEQUENCE BLOCK CTL GON
CONTROL
DLP
GON VGON
35V
50% OSC SRC 50mA
VIN
VGOFF SWO
-6V DRVN DRVP
100mA NEGATIVE POSITIVE SRC
REG REG
CPGND CPGND

FBN FBP

AVDD

REF

Figure 2. Functional Diagram

______________________________________________________________________________________ 17
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
PWM Controller Block AGND with the center tap connected to FB2 to adjust
MAX17113

The heart of the PWM control block is a multi-input, the output voltage. Choose RB (resistance from FB2 to
open-loop comparator that sums three signals: the out- AGND) to be between 5k and 50k, and solve for RA
put-voltage signal with respect to the reference voltage, (resistance from OUT1 to FB1) using the equation:
the current-sense signal, and the slope compensation.
V
The PWM controller is a direct-summing type, lacking a RA = RB OUT - 1
traditional error amplifier and the phase shift associated VFB2
with it. This direct-summing configuration approaches
ideal cycle-by-cycle control over the output voltage. where VFB2 = 1.25V, and VOUT can vary from 1.25V to 5V.
When EN1 and EN2 are high, the controller always Because of FB2s (pin 17) close proximity to the noisy
operates in fixed-frequency PWM mode. Each pulse BST (pin 18), a noise filter is required for FB2
from the oscillator sets the main PWM latch that turns adjustable-mode operation. Place a 100pF capacitor
on the high-side switch until the PWM comparator from FB2 to AGND to prevent unstable operation. No fil-
changes state. ter is required for 3.3V fixed-mode operation.
When EN1 is high and EN2 is low, the controller oper- Soft-Start
ates in skip mode. The skip mode dramatically The step-down regulator includes a 7-bit soft-start DAC
improves light-load efficiency by reducing the effective that steps its internal reference voltage from 0 to 1.25V in
frequency, which reduces switching losses. It keeps 128 steps. The soft-start period is 3ms (typ) and FB2 fault
the peak inductor current at about 0.9A (typ) in an detection is disabled during this period. The soft-start fea-
active cycle, allowing subsequent cycles to be ture effectively limits the inrush current during startup (see
skipped. Skip mode transitions seamlessly to fixed- the Step-Down Regulator Soft-Start (Heavy Load) wave-
frequency PWM operation as load current increases. forms in the Typical Operating Characteristics).
Current Limiting and Lossless Current Sensing Step-Up Regulator
The current-limit circuit turns off the high-side MOSFET The step-up regulator employs a current-mode, fixed-
switch whenever the voltage across the high-side frequency PWM architecture to maximize loop band-
MOSFET exceeds an internal threshold. The actual width and provide fast-transient response to pulsed
current limit is 3A (typ). loads typical of TFT LCD panel source drivers. The inte-
For current-mode control, an internal lossless sense grated MOSFET and the built-in digital soft-start func-
network derives a current-sense signal from the induc- tion reduce the number of external components
tor DCR. The time constant of the current-sense net- required while controlling inrush currents. The output
work is not required to match the time constant of the voltage can be set from VIN to 20V with an external
inductor and has been chosen to provide sufficient cur- resistive voltage-divider. The regulator controls the out-
rent ramp signal for stable operation at both operating put voltage and the power delivered to the output by
frequencies. The current-sense signal is AC-coupled modulating the duty cycle (D) of the internal power
into the PWM comparator, eliminating most DC output- MOSFET in each switching cycle. The duty cycle of the
voltage variation with load current. MOSFET is approximated by:
V -V
Low-Frequency Operation D AVDD IN
The step-down regulator of the MAX17113 enters into VAVDD
low-frequency operating mode if the voltage on OUT is
below 0.8V. In the low-frequency mode, the switching where VAVDD is the output voltage of the step-up regulator.
frequency of the step-down regulator is 1/6 the oscilla- PWM Controller Block
tor frequency. This feature prevents potentially uncon- An error amplifier compares the signal at FB1 to 1.25V
trolled inductor current if OUT is overloaded or shorted and changes the COMP output. The voltage at COMP
to ground. sets the peak inductor current. As the load varies, the
Dual-Mode Feedback error amplifier sources or sinks current to the COMP
The step-down regulator of the MAX17113 supports output accordingly to produce the inductor peak cur-
both fixed and adjustable output voltages. Connect rent necessary to service the load. To maintain stability
FB2 to AGND to enable the 3.3V fixed output voltage. at high duty cycles, a slope compensation signal is
Connect a resistive voltage-divider between OUT and summed with the current-sense signal.

18 ______________________________________________________________________________________
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
On the rising edge of the internal clock, the controller in 128 steps. This DAC also controls linearly the gate of

MAX17113
sets a flip-flop, turning on the n-channel MOSFET and the pMOS switch, which is in between SWI and SWO,
applying the input voltage across the inductor. The cur- and the output AVDD goes up smoothly, and when the
rent through the inductor ramps up linearly, storing AVDD reaches the input voltage, the step-up regulator
energy in its magnetic field. Once the sum of the current- takes over seamlessly and the output-voltage AVDD
feedback signal and the slope compensation exceed the reaches its regulation point. The soft-start period is
COMP voltage, the controller resets the flip-flop and turns 10ms (typ) and FB1 fault detection is disabled during
off the MOSFET. Since the inductor current is continuous, this period. The soft-start feature effectively limits the
a transverse potential develops across the inductor that inrush current during startup.
turns on the diode (D1). The voltage across the inductor
then becomes the difference between the output voltage Positive Charge-Pump Regulator
and the input voltage. This discharge condition forces The positive charge-pump regulator is typically used to
the current through the inductor to ramp back down, generate the positive supply rail for the TFT LCD gate
transferring the energy stored in the magnetic field to the driver ICs. The output voltage is set with an external
output capacitor and the load. The MOSFET remains off resistive voltage-divider from its output to GND with the
for the rest of the clock cycle. midpoint connected to FBP. The number of charge-
pump stages and the setting of the feedback divider
Step-Up Regulator Internal determine the output voltage of the positive charge-
p-Channel MOSFET Pass Switch pump regulator. The charge pump includes a high-side
The MAX17113 includes an integrated 130m high- p-channel MOSFET (P1) and a low-side n-channel
voltage p-channel MOSFET to allow true shutdown of MOSFET (N1) to control the power transfer as shown in
the step-up converter output (AVDD). This switch is typ- Figure 3.
ically connected in series between the step-up regula- During the first half-cycle, N1 turns on and charges fly-
tors Schottky catch diode and its output capacitors. In ing capacitors C20 and C21 (Figure 3). During the sec-
addition to allowing step-up output to discharge com- ond half cycle, N1 turns off and P1 turns on, level
pletely when disabled, this switch also controls the shifting C20 and C21 by VAVDD volts. If the voltage
startup inrush current into the step-up regulators out- across C23 plus a diode drop (VOUT + VD) is smaller
put capacitors. than the level-shifted flying capacitor voltage (VC20 +
Soft-Start VAVDD), charge flows from C20 to C23 until the diode
The step-up regulator includes a 7-bit soft-start DAC (D5) turns off. The amount of charge transferred to the
that steps its internal reference voltage from 0 to 1.25V output is determined by the error amplifier that controls
N1s on-resistance.

SWO AVDD
MAX17113
OSC
P1
C21
C22
ERROR
AMPLIFIER DRVP
REF
1.25V C20

N1 D5 OUTPUT

CPGND C23

POSITIVE CHARGE-PUMP REGULATOR

FBP

Figure 3. Positive Charge-Pump Regulator Block Diagram

______________________________________________________________________________________ 19
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
The positive charge-pump regulators startup can be During the first half cycle, P2 turns on, and flying
MAX17113

delayed by connecting an external capacitor from capacitor C13 charges to VIN minus a diode drop
DEL2 to AGND. An internal constant-current source (Figure 4). During the second half cycle, P2 turns off,
begins charging the DEL2 capacitor when EN2 is logic- and N2 turns on, level shifting C13. This connects C13
high, and the step-down regulator reaches regulation. in parallel with reservoir capacitor C12. If the voltage
When the DEL2 voltage exceeds V REF, the positive across C12 minus a diode drop is greater than the volt-
charge-pump regulator is enabled. Each time it is age across C13, charge flows from C12 to C13 until the
enabled, the positive charge-pump regulator goes diode (D3) turns off. The amount of charge transferred
through a soft-start routine by ramping up its internal from the output is determined by the error amplifier,
reference voltage from 0 to 1.25V in 128 steps. The which controls N2s on-resistance.
soft-start period is 3ms (typ) and FBP fault detection is The negative charge-pump regulator is enabled when
disabled during this period. The soft-start feature effec- EN1 is logic-high and the step-down regulator reaches
tively limits the inrush current during startup. regulation. Each time it is enabled, the negative
Negative Charge-Pump Regulator charge-pump regulator goes through a soft-start rou-
The negative charge-pump regulator is typically used to tine by ramping down its internal reference voltage
generate the negative supply rail for the TFT LCD gate from 1.25V to 250mV in 102 steps. The soft-start period
driver ICs. The output voltage is set with an external resis- is 3ms (typ) and FBN fault detection is disabled during
tive voltage-divider from its output to REF with the mid- this period. The soft-start feature effectively limits the
point connected to FBN. The number of charge-pump inrush current during startup.
stages and the setting of the feedback divider determine
the output of the negative charge-pump regulator. The
charge-pump controller includes a high-side p-channel
MOSFET (P2) and a low-side n-channel MOSFET (N2) to
control the power transfer as shown in Figure 4.

VIN
MAX17113

OSC
P2

ERROR C13
AMPLIFIER DRVN
REF
0.25V
D3
OUTPUT
N2
C12
CPGND
R1

NEGATIVE CHARGE-PUMP REGULATOR FBN REF

R2

Figure 4. Negative Charge-Pump Regulator Block Diagram

20 ______________________________________________________________________________________
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
High-Voltage Switch Control Select the first mode by connecting MODE to VL. When

MAX17113
The MAX17113s high-voltage switch control block CTL is logic-high, Q1 turns on and Q2 turns off, con-
(Figure 5) consists of two high-voltage p-channel necting GON to SRC. When CTL is logic-low, Q1 turns
MOSFETs: Q1, between SRC and GON and Q2, between off and Q2 turns on, connecting GON to DRN. GON
GON and DRN. The switch control block is enabled when can then be discharged through a resistor connected
VDLP exceeds VREF. Q1 and Q2 are controlled by CTL between DRN and GND or AV DD . Q2 turns off and
and MODE. There are two different modes of operation stops discharging GON when VGON reaches 10 times
(see the Typical Operating Characteristics). the voltage on THR.

REF
SWITCH CONTROL
8A
MAX17113
DLP
FAULT

Q4 SHDN

SUI DONE
SRC

VREF Q1

GON

VL /2 6k 9R

50A
VL Q2
Q5 R

R
DRN
THR

2R

MODE

1.25k R

Q3

CTL

Figure 5. Switch Control

______________________________________________________________________________________ 21
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
When VMODE is less than 0.8 x VVL, the switch control Once the step-down regulator reaches regulation, the
MAX17113

block works in the second mode. The rising edge of FB2 fault-detection circuit and the negative charge-
VCTL turns on Q1 and turns off Q2, connecting GON to pump delay block are enabled. An 8A current source
SRC. An internal n-channel MOSFET, Q3, between at DEL1 charges CDEL1 linearly. The negative charge-
MODE and AGND is also turned on to discharge an pump regulator soft-starts when VDEL1 reaches VREF.
external capacitor between MODE and AGND. The FBN fault detection is enabled once the negative
falling edge of VCTL turns off Q3, and an internal 50A charge-pump soft-start is done. See Figure 6.
current source starts charging the MODE capacitor. The step-up regulator, p-channel MOSFET pass switch,
Once VMODE exceeds VVL/4, the switch control block and positive charge-pump startup sequence begin
turns off Q1 and turns on Q2, connecting GON to DRN. when the step-down regulator reaches regulation and
GON can then be discharged through a resisor con- EN2 is logic-high. An 8A current source at DEL2
nected between DRN and PGND or AVDD. Q2 turns off charges CDEL2 linearly and the positive charge pump
and stops discharging GON when VGON reaches 10 is enabled when VDEL2 reaches VREF. When the posi-
times the voltage on THR. tive charge pump is in regulation, an 8A current
The switch control block is disabled and DLP is held source charges CDLP linearly and when VDLP reaches
low when EN1 or EN2 is low or the IC is in a fault state. VREF, the high-voltage switch is enabled and GON can
be controlled by CTL.
Linear Regulator (VL)
The MAX17113 includes an internal linear regulator. VIN The FB1 fault-detection circuit is enabled after the step-
is the input of the linear regulator. The input voltage up regulator reaches regulation, and similarly the FBP
range is between 8V and 16.5V. The output voltage is set fault-detection circuit is enabled after the positive charge
to 5V. The regulator powers the internal MOSFET drivers, pump reaches regulation. For nondelayed startups,
PWM controllers, charge-pump regulators, and logic cir- capacitors can be omitted from DEL1, DEL2, and DLP.
cuitry. The total external load capability is 25mA. Bypass When their current sources pull the pins above their
VL to AGND with a minimum 1F ceramic capacitor. thresholds, the associated outputs start.

Reference Voltage (REF) Power-Down Control

The reference output is nominally 1.25V, and can The MAX17113 disables the step-up regulator, positive-
source at least 50A (see the Typical Operating charge-pump regulator input switch control block,
Characteristics). VL is the input of the internal reference delay block, and high-voltage switch control block
block. Bypass REF with a 0.22F ceramic capacitor when EN2 is logic-low, or when the fault latch is set.
connected between REF and AGND. The step-down regulator and negative charge-pump
regulator are disabled only when EN1 is logic-low or
Frequency Selection (FSEL) when the fault latch is set.
The step-down regulator and step-up regulator use the
same internal oscillator. The FSEL input selects the Fault Protection
switching frequency. Table 3 shows the switching fre- During steady-state operation, if any output of the four
quency based on the FSEL connection. High-frequency regulators (step-down regulator, step-up regulator,
(600kHz) operation optimizes the application for the positive charge-pump regulator, and negative charge-
smallest component size, trading off efficiency due to pump regulator) does not exceed its respective fault-
higher switching losses. Low-frequency (450kHz) oper- detection threshold, the MAX17113 activates an inter-
ation offers the best overall efficiency at the expense of nal fault timer. If any condition or the combination of
component size and board space. conditions indicates a continuous fault for the fault timer
duration (50ms, typ), the MAX17113 triggers a non-
Table 3. Frequency Selection latching output undervoltage fault. After triggering, the
MAX17113 turns off for 160ms (typ) and then restarts
FSEL SWITCHING FREQUENCY (kHz) according to the EN1 and EN2 logic states. If, after
VIN 600 restarting, another 50ms fault timeout occurs, the
AGND 450 MAX17113 shuts down for 160ms again, and then
restarts. The restart sequence is repeated 3 times and
Power-Up Sequence after the 50ms fault timeout, the MAX17113 shuts down
The step-down regulator starts up when the MAX17113s and latches off. Once the fault condition is removed,
internal reference voltage (REF) is above its undervolt- toggle either EN1 or EN2, or cycle the input voltage to
age lockout (UVLO) threshold and EN1 is logic-high. clear the fault latch and restart the supplies.

22 ______________________________________________________________________________________
 Low-Cost, Multiple-Output
Power Supply for LCD TVs

MAX17113
VIN
EN1
VIN VL/REF
UVLO tSS
BUCK OUTPUT
SWO TURNS ON AND DEL2 CHARGES WHEN EN2 IS HIGH AND BUCK SS IS DONE.
EN2

TIME

NEGATIVE CHARGE-PUMP
tSS REGULATOR OUTPUT

DEL1
DEL2
REF REF

TIME
POSITIVE CHARGE-PUMP
REGULATOR OUTPUT
BOOST
SWITCHING

SWO AVDD
TURN-ON
VIN SUI (INTERNAL SIGNAL)

tSS(BOOST) tSS TIME

DLP

REF

TIME
GON

GON DEPENDS ON CTL

GON CONNECTED TO GROUND

TIME

DLP ABOVE REF. START

HIGH-VOLTAGE SWITCH BLOCK.

DEL2 ABOVE REF. START POSITIVE CP AND DLP.

BUCK SS DONE AND EN2 HIGH. START SUI/BOOST AND CHARGE DEL2.

DEL1 ABOVE REF. START NEGATIVE-CHARGE PUMP.

EN1 HIGH, REF, AND VL OKAY. START BUCK THEN DEL1 AFTER BUCK SS.

VIN > UVLO. START VL AND REF.

Figure 6. Startup Sequence

______________________________________________________________________________________ 23
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
Thermal-Overload Protection The inductors DC resistance should be low for good
MAX17113

The thermal-overload protection prevents excessive efficiency. Find a low-loss inductor having the lowest
power dissipation from overheating the MAX17113. possible DC resistance that fits in the allotted dimen-
When the junction temperature exceeds TJ = +160C, a sions. Ferrite cores are often the best choice. Shielded-
thermal sensor immediately activates the fault protec- core geometries help keep noise, EMI, and switching
tion that shuts down all the outputs except the refer- waveform jitter low.
ence and latches off, allowing the device to cool down. Considering the typical operating circuit in Figure 1, the
Once the device cools down by at least approximately maximum load current (IOUT(MAX)) is 2A with a 3.3V
15C, cycle the input voltage to clear the fault latch and output and a typical 12V input voltage. Choosing an
restart the MAX17113. LIR of 0.4 at this operating point:
The thermal-overload protection protects the controller
3.3V (12V - 3.3V )
in the event of fault conditions. For continuous opera- LOUT = 5.0H
tion, do not exceed the absolute maximum junction 12V 600kHz 2 A 0.4
temperature rating of TJ = +150C.
At that operating point, the ripple current and the peak
Design Procedure current are:
Step-Down Regulator 3.3V (12V - 3.3V )
IOUT _ RIPPLE = 0.8 A
600kHz 5.0H 12
Inductor Selection
Three key inductor parameters must be specified: 0.8 A
inductance value (L), peak current (IPEAK), and DC IOUT _ PEAK = 2 A + = 2.4 A
resistance (RDC). The following equation includes a 2
constant, LIR, which is the ratio of peak-to-peak induc-
tor ripple current to DC load current. A higher LIR value Input Capacitors
allows smaller inductance, but results in higher losses The input filter capacitors reduce peak currents drawn
and higher ripple. A good compromise between size from the power source and reduce noise and voltage
and losses is typically found at about 20% to 50% rip- ripple on the input caused by the regulators switching.
ple-current to load-current ratio (LIR): They are usually selected according to input ripple cur-
rent requirements and voltage rating, rather than
VOUT ( VIN2 - VOUT ) capacitance value. The input voltage and load current
LOUT = determine the RMS input ripple current (IRMS):
VIN2 fSW IOUT(MAX) LIR

where IOUT(MAX) is the maximum DC load current, and VOUT ( VIN2 - VOUT )
IRMS = IOUT
the switching frequency fSW is 600kHz when FSEL is VIN2
connected to VL or 450kHz when FSEL is connected to
AGND. The exact inductor value is not critical and can The worst case is IRMS = 0.5 x IOUT, which occurs at
be adjusted to make trade-offs among size, cost, and VIN2 = 2 x VOUT.
efficiency. Lower inductor values minimize size and For most applications, ceramic capacitors are used
cost, but they also increase the output ripple and because of their high ripple current and surge current
reduce the efficiency due to higher peak currents. On capabilities. For optimal circuit long-term reliability,
the other hand, higher inductor values increase effi- choose an input capacitor that exhibits less than +10C
ciency, but at some point resistive losses due to extra temperature rise at the RMS input current corresponding
turns of wire exceed the benefit gained from lower AC to the maximum load current.
current levels.
The inductors saturation current must exceed the peak Output Capacitor Selection
inductor current. The peak current can be calculated by: Since the MAX17113s step-down regulator is internally
compensated, it is stable with any reasonable amount
V ( VIN2 - VOUT ) of output capacitance. However, the actual capacitance
IOUT _ RIPPLE = OUT
fSW LOUT VIN2 and equivalent series resistance (ESR) affect the regu-
lators output ripple voltage and transient response. The
IOUT _ RIPPLE rest of this section deals with how to determine the out-
IOUT _ PEAK = IOUT(MAX) + put capacitance and ESR needs according to the
2
ripple-voltage and load-transient requirements.

24 ______________________________________________________________________________________
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
The output-voltage ripple has two components: varia-

MAX17113
LOUT (IOUT )2
tions in the charge stored in the output capacitor, and VOUT _ SAG =
the voltage drop across the capacitors ESR caused by (
2 COUT VIN(MIN) DMAX - VOUT )
the current into and out of the capacitor:
The amplitude of the capacitive soar is a function of the
VOUT _ RIPPLE = VOUT _ RIPPLE(ESR) + VOUT _ RIPPLE(C) load step, the output capacitor value, the inductor
value, and the output voltage:
VOUT _ RIPPLE(ESR) = IOUT _ RIPPLE RESR _ OUT
L (IOUT )2
IOUT _ RIPPLE VOUT _ SOAR = OUT
VOUT _ RIPPLE(C) = 2 COUT VOUT
8 COUT fSW
Keeping the full-load overshoot and undershoot less
where IOUT_RIPPLE is defined in the Inductor Selection than 3% ensures that the step-down regulators natural
of the Step-Down Regulator section, COUT is the output integrator response dominates. Given the component
capacitance, and RESR_OUT is the ESR of the output values in the circuit of Figure 1 and assuming a full 1.5A
capacitor COUT. In Figure 1s circuit, the inductor ripple step load transient, the voltage step due to capacitor
current is 0.8A. If the voltage-ripple requirement of ESR is negligible. The voltage sag and soar are 76mV
Figure 1s circuit is 1% of the 3.3V output, then the and 73mV, or a little over 1% and 2%, respectively.
total peak-to-peak ripple voltage should be less than
66mV. Assuming that the ESR ripple and the capacitive Rectifier Diode
ripple each should be less than 50% of the total peak- The MAX17113s high switching frequency demands a
to-peak ripple, then the ESR should be less than 43m high-speed rectifier. Schottky diodes are recommended
and the output capacitance should be more than 5F to for most applications because of their fast recovery time
meet the total ripple requirement. A 22F capacitor with and low forward voltage. In general, a 2A Schottky diode
ESR (including PCB trace resistance) of 10m is select- works well in the MAX17113s step-down regulator.
ed for the standard application circuit in Figure 1, which
easily meets the voltage-ripple requirement. Step-Up Regulator
The step-down regulators output capacitor and ESR can Inductor Selection
also affect the voltage undershoot and overshoot when The inductance value, peak current rating, and series
the load steps up and down abruptly. The step-down resistance are factors to consider when selecting the
regulators transient response is typically dominated by inductor. These factors influence the converters effi-
its loop response and the time constant of its internal ciency, maximum output load capability, transient
integrator. However, excessive inductance or insufficient response time, and output-voltage ripple. Physical size
output capacitance can degrade the natural transient and cost are also important factors to be considered.
response. Calculating the ideal transient response of The maximum output current, input voltage, output volt-
the inductor and capacitor, which assumes an ideal age, and switching frequency determine the inductor
response from the regulator, can ensure that these value. Very high inductance values minimize the cur-
components do not degrade the ICs natural response. rent ripple, and therefore, reduce the peak current,
The ideal undershoot and overshoot have two compo- which decreases core losses in the inductor and I2R
nents: the voltage steps caused by ESR, and the voltage losses in the entire power path. However, large induc-
sag and soar due to the finite capacitance and the induc- tor values also require more energy storage and more
tor current slew rate. Use the following formulas to check turns of wire that increase physical size and can
if the ESR is low enough and the output capacitance is increase I2R losses in the inductor. Low inductance val-
large enough to prevent excessive soar and sag. ues decrease the physical size, but increase the cur-
rent ripple and peak current. Finding the best inductor
The amplitude of the ESR step is a function of the load involves choosing the best compromise among circuit
step and the ESR of the output capacitor: efficiency, inductor size, and cost.
VOUT _ ESR _ STEP = IOUT RESR _ OUT The equations used here include a constant, LIR, which
is the ratio of the inductor peak-to-peak ripple current to
The amplitude of the capacitive sag is a function of the the average DC inductor current at the full-load current.
load step, the output capacitor value, the inductor The best trade-off between inductor size and circuit effi-
value, the input-to-output voltage differential, and the ciency for step-up regulators generally has an LIR
maximum duty cycle: between 0.2 and 0.5. However, depending on the AC

______________________________________________________________________________________ 25
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
characteristics of the inductor core material and ratio of LIR of 0.6 and estimating efficiency of 90% at this oper-
MAX17113

inductor resistance to other power path resistances, the ating point:

best LIR can shift up or down. If the inductor resistance
is relatively high, more ripple can be accepted to 2
12V 16V - 12V 0.9 90
L AVDD = 5.6H
16V 1A 600kHz 0.6
reduce the number of turns required and increase the
wire diameter. If the inductor resistance is relatively low,
increasing inductance to lower the peak current can Using the circuits minimum input voltage (10.8V) and
decrease losses throughout the power path. If extremely estimating efficiency of 90% at that operating point:
thin high-resistance inductors are used, as is common
for smaller LCD panel applications, the best LIR can 1.0 A 16V
IVIN(DC,MAX) = 1.64 A
increase to between 0.5 and 1.0. 10.8V 0.9
Once a physical inductor is chosen, higher and lower
values of the inductor should be evaluated for efficiency Choosing a 4.7H inductor, the ripple current and the
improvements in typical operating regions. peak current are:
Calculate the approximate inductor value using the 10.8V (16V - 10.8V )
typical input voltage (VVIN), the maximum output cur- IRIPPLE = 1.2A
4.7H 16V 600kHz
rent (IAVDD(MAX)), the expected efficiency (TYP) taken
from an appropriate curve in the Typical Operating 1.2 A
IPEAK = 1.64 A + 2.24 A
Characteristics, and an estimate of LIR based on the 2
above discussion:
2 Output Capacitor Selection
V VAVDD - VVIN TYP
L AVDD = VIN The total output-voltage ripple has two components: the
VAVDD IAVDD(MAX) fSW LIR capacitive ripple caused by the charging and dis-
charging of the output capacitance, and the ohmic rip-
Choose an available inductor value from an appropriate ple due to the capacitors ESR:
inductor family. Calculate the maximum DC input cur-
rent at the minimum input voltage VIN(MIN) using con- VAVDD _ RIPPLE = VAVDD _ RIPPLE(C) + VAVDD _ RIPPLE(ESR)
servation of energy and the expected efficiency at that
operating point (MIN) taken from an appropriate curve
I V -V
in the Typical Operating Characteristics: VAVDD _ RIPPLE(C) AVDD AVDD VIN
IAVDD(MAX) VAVDD CAVDD VAVDDfSW
IVIN(DC,MAX) =
VVIN(MIN) MIN and:

Calculate the ripple current at that operating point and VAVDD _ RIPPLE(ESR) IAVDD _ PEAKRESR _ AVDD
the peak current required for the inductor:
where IAVDD_PEAK is the peak inductor current (see the

IAVDD _ RIPPLE =
(
VVIN(MIN) VAVDD - VVIN(MIN) ) Inductor Selection section). For ceramic capacitors, the
output-voltage ripple is typically dominated by
L AVDD VAVDD fSW VAVDD_RIPPLE(C). The voltage rating and temperature
characteristics of the output capacitor must also be
IAVDD _ RIPPLE considered. Note that all ceramic capacitors typically
IAVDD _ PEAK = IVIN(DC,MAX) + have large temperature coefficient and bias voltage
2 coefficients. The actual capacitor value in circuit is typi-
The inductors saturation current rating and the cally significantly less than the stated value.
MAX17113s LX1 current limit should exceed IAVDD_PEAK Input Capacitor Selection
and the inductors DC current rating should exceed The input capacitor reduces the current peaks drawn
IVIN(DC,MAX). For good efficiency, choose an inductor from the input supply and reduces noise injection into
with less than 0.05 series resistance. the IC. Two 10F ceramic capacitors are used in the typ-
Considering the typical operating circuit in Figure 1, the ical operating circuit (Figure 1) because of the high
maximum load current (IAVDD(MAX)) is 1.0A with a 16V source impedance seen in typical lab setups. Actual
output and a typical 12V input voltage. Choosing an applications usually have much lower source impedance

26 ______________________________________________________________________________________
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
since the step-up regulator often runs directly from the regulator, VSWO is the supply voltage of the positive

MAX17113
output of another regulated supply. Typically, the input charge-pump regulators, VD is the forward voltage drop
capacitance can be reduced below the values used in of the charge-pump diode, and VDROPOUT is the dropout
the typical operating circuit. margin for the regulator. Use VDROPOUT = 300mV.
Rectifier Diode The number of negative charge-pump stages is given by:
The MAX17113s high switching frequency demands a -VGOFF + VDROPOUT
high-speed rectifier. Schottky diodes are recommend- nNEG =
VVIN - 2 VD
ed for most applications because of their fast recovery
time and low forward voltage. In general, a 2A Schottky where nNEG is the number of negative charge-pump
diode complements the internal MOSFET well. stages and VGOFF is the output of the negative charge-
pump regulator.
Output-Voltage Selection
The output voltage of the step-up regulator can be The above equations are derived based on the
adjusted by connecting a resistive voltage-divider from assumption that the first stage of the positive charge
the output (VAVDD) to AGND with the center tap con- pump is connected to VAVDD and the first stage of the
nected to FB1 (see Figure 1). Select R4 in the 10k to negative charge pump is connected to ground.
50k range. Calculate R3 with the following equation: Sometimes fractional stages are more desirable for bet-
ter efficiency. This can be done by connecting the first
V stage to VOUT or another available supply. If the first
R3 = R4 AVDD - 1 charge-pump stage is powered from VOUT, then the
VFB1
above equations become:
where VFB1, the step-up regulators feedback set point, V + VDROPOUT - VOUT
is 1.25V. Place R4 and R3 close to the IC. nPOS = GON
VSWO - 2 VD
Loop Compensation -VGOFF + VDROPOUT + VOUT
Choose RCOMP (R5 in Figure 1) to set the high-frequen- nNEG =
cy integrator gain for fast transient response. Choose VVIN - 2 VD
CCOMP (C17 in Figure 1) to set the integrator zero to
maintain loop stability. Flying Capacitors
Increasing the capacitance of the flying capacitors
For low-ESR output capacitors, use the following equa-
(connected to DRVN and DRVP) value lowers the effec-
tions to obtain stable performance and good transient
tive source impedance and increases the output-current
response:
capability. Increasing the capacitance indefinitely has a
125 VVIN VAVDD CAVDD negligible effect on output-current capability because
RCOMP
L AVDD IAVDD(MAX) the internal switch resistance and the diode impedance
place a lower limit on the source impedance. A 0.1F
VAVDD CAVDD ceramic capacitor works well in most low-current appli-
CCOMP cations. The flying capacitors voltage rating must
1250 IAVDD(MAX) RCOMP
exceed the following:
To further optimize transient response, vary RCOMP in VCX > n VSWO
20% steps and CCOMP in 50% steps while observing
transient response waveforms. where n is the stage number in which the flying capaci-
tor appears.
Charge-Pump Regulators
Charge-Pump Output Capacitor
Selecting the Number of Charge-Pump Stages Increasing the output capacitance or decreasing the
For highest efficiency, always choose the lowest number ESR reduces the output ripple voltage and the peak-to-
of charge-pump stages that meet the output requirement. peak transient voltage. With ceramic capacitors, the
The number of positive charge-pump stages is given by: output-voltage ripple is dominated by the capacitance
V + VDROPOUT - VAVDD value. Use the following equation to approximate the
nPOS = GON required capacitor value:
VSWO - 2 VD
ILOAD _ CP
where nPOS is the number of positive charge-pump COUT _ CP
2fOSCVRIPPLE _ CP
stages, VGON is the output of the positive charge-pump
______________________________________________________________________________________ 27
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
where COUT_CP is the output capacitor of the charge input capacitor ground terminals. Connect these
MAX17113

pump, I LOAD _ CP is the load current of the charge loop components with short, wide connections.
pump, and VRIPPLE_CP is the peak-to-peak value of the Avoid using vias in the high-current paths. If vias
output ripple. are unavoidable, use many vias in parallel to
reduce resistance and inductance.
Output-Voltage Selection
Adjust the positive charge-pump regulators output volt- Create a power ground island for the step-down reg-
age by connecting a resistive voltage-divider from the ulator, consisting of the input and output capacitor
SRC output to AGND with the center tap connected to grounds and the diode ground. Connect all these
FBP (Figure 1). Select the lower resistor of divider R17 together with short, wide traces or a small ground
in the 10k to 30k range. Calculate the upper resis- plane. Similarly, create a power ground island
tor, R16, with the following equation: (PGND) for the step-up regulator, consisting of the
input and output capacitor grounds and the PGND
V pin. Create a power ground island (CPGND) for the
R17 = R16 GON - 1
VFBP positive and negative charge pumps, consisting of
the output (SRC, VGOFF) capacitor grounds, and
where VFBP = 1.25V (typ). negative charge-pump diode ground. Connect
Adjust the negative charge-pump regulators output CPGND ground plane to PGND together with wide
voltage by connecting a resistive voltage-divider from traces. Maximizing the width of the power ground
VGOFF to REF with the center tap connected to FBN traces improves efficiency and reduces output-volt-
(Figure 1). Select R2 in the 20k to 50k range. age ripple and noise spikes.
Calculate R1 with the following equation: Create an analog ground plane (AGND) consisting
of the AGND pin, all the feedback divider ground
V -V connections, the COMP and DEL capacitor ground
R1 = R2 FBN GOFF
VREF - VFBN connections, and the devices exposed backside
pad. Connect PGND and AGND islands by con-
where VFBN = 250mV, VREF = 1.25V. Note that REF can necting the two ground pins directly to the exposed
only source up to 50A, using a resistor less than 20k backside pad. Make no other connections between
for R1 results in higher bias current than REF can supply. the PGND and AGND ground planes.
PCB Layout and Grounding Place all feedback voltage-divider resistors as
Careful PCB layout is important for proper operation. close as possible to their respective feedback pins.
Use the following guidelines for good PCB layout: The dividers center trace should be kept short.
Minimize the area of respective high-current loops Placing the resistors far away causes their FB
by placing each DC-DC converters inductor, traces to become antennas that can pick up switch-
diode, and output capacitors near its input capaci- ing noise. Care should be taken to avoid running
tors and its LX_ and GND_ pins. For the step-down any feedback trace near LX1, LX2, DRVP, or DRVN.
regulator, the high-current input loop goes from the Place VIN pin, VL pin, and REF pin bypass capaci-
positive terminal of the input capacitor to the ICs IN tors as close as possible to the device. The ground
pin, out of LX2, to the inductor, to the positive termi- connection of the VL bypass capacitor should be
nals of the output capacitors, reconnecting the out- connected directly to the AGND pin with a wide
put capacitor and input capacitor ground terminals. trace.
The high-current output loop is from the inductor to Minimize the length and maximize the width of the
the positive terminals of the output capacitors, to traces between the output capacitors and the load
the negative terminals of the output capacitors, and for best transient responses.
to the Schottky diode (D2). For the step-up regula-
tor, the high-current input loop goes from the posi- Minimize the size of the LX1 and LX2 nodes while
tive terminal of the input capacitor to the inductor, keeping them wide and short. Keep the LX1 and
to the ICs LX1 pin, out of PGND, and to the input LX2 nodes away from feedback nodes (FB1, FB2,
capacitors negative terminal. The high-current out- FBP, and FBN) and analog ground. Use DC traces
put loop is from the positive terminal of the input as a shield, if necessary.
capacitor to the inductor, to the output diode (D1), Refer to the MAX17113 evaluation kit for an example of
to the positive terminal of the output capacitors, proper board layout.
reconnecting between the output capacitor and

28 ______________________________________________________________________________________
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
Simplified Operating Circuit

MAX17113
VIN

IN2 IN2 PGND PGND LX1 LX1 SW

SWI
BST

AVDD
OUT SWO
LX2
LX2

GND2 FB1
COMP
OUT
FB2 AGND

VIN VIN THR

CTL FROM GON

CONTROL
VL DRN
VL
FSEL
GON GON
MODE
3.3V
REF REF

MAX17113
AGND

PGOOD PGOOD
DEL2

CRST

DEL1

SRC
ON/OFF EN1 SRC
ON/OFF EN2
DRVP
DLP

GOFF

DRVN
AVDD

FBN FBP
CPGND
EP

REF

______________________________________________________________________________________ 29
 Low-Cost, Multiple-Output
Power Supply for LCD TVs
Chip Information Package Information
MAX17113

PROCESS: BiCMOS For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

40 TQFN-EP T4055+1 21-0140

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products. Inc.