International Journal of Engineering and Technical Research (IJETR)

ISSN: 2321-0869, Volume-2, Issue-7, July 2014

VLSI Power Efficiency, Leakage, Dissipation and

Management Techniques: A Survey
Sandeep Kaur, Sarabdeep Singh
industry crisis, threatening the survival of CMOS
Abstract Modern processor and controlling systems are technology itself [4]. Further, the number of processor cores
using increasingly sized-up on-chip cache memory. With this on a single chip has greatly increased over years and future
there has been significant increase in leakage power chips are expected to have much larger number of cores [5].
consumption. This reason, accounts for overall and cache power Finally, to bridge the gap between the speed of processor and
management research issue in processor design. The
main memory, modern processors are using caches of
System-On-Chip (SoC) revolution challenges both design and
test engineers, especially in the area of power dissipation. A
increasingly larger sizes.
circuit or system consumes more power in test mode than in Electronic systems can be viewed as collections of
normal mode. This extra power consumption can give rise to components, which may be heterogeneous in nature. Some
severe hazards in circuit reliability or, in some cases, can components may have mechanical parts, e.g., hard-disk drives
provoke instant circuit damage. It can create problems such as (HDDs), or optical parts, e.g., displays. For example, a
increased product cost, difficulty in performance verification, cellular telephone has a digital very large scale integration
reduced autonomy of portable systems, and decrease of overall (VLSI) component, an analog radio-frequency (RF)
yield. Technological advances have improved the performance component, and a display. Such components may be active at
and features of embedded systems development. We also
different times, and correspondingly consume different
describe sources of power dissipation and leakage in CMOS
circuits and there varying degrees of freedom in the low power fractions of the telephone power budget. Similarly, main
design. This survey will enable engineers and researchers to get components of portable computers are VLSI chips, HDD, and
insights into the techniques for improving cache power display. It is often the case that the HDD and the display are
efficiency, power management techniques, about the available the most power-hungry components [6], and thus their
low power testing techniques during testing. and motivate them effective use is key to achieving long operating times between
to invent novel solutions for enabling low-power operation of battery recharges. To be competitive, an electronic design
caches. must be able to deliver peak performance when requested.
Nevertheless, peak performance is required only during some
Index Terms CMOS, DRAM, HDD, MRU, LRU, LFSR.
time intervals. Similarly, system components are not always
required to be in the active state. The ability to enable and
disable components, as well as of tuning their performance to
I. INTRODUCTION
the workload (e.g., users requests), is key in achieving
As we are entering into an era of green computing, the energy-efficient designs.
design of energy efficient IT solutions has become a topic of VLSI circuit designers are excited by the prospect of
paramount importance [1]. Recently, the primary objective in addressing these challenges efficiently, but these challenges
chip design has been shifting from achieving highest peak are becoming increasingly hard to overcome [7] Test
performance to achieving highest performance-energy currently ranks among the most expensive and problematic
efficiency. Achieving energy efficiency is important in the aspects in a circuit design cycle, revealing the ceaseless need
design of all range of processors, such as battery-driven for innovative, test-related solutions. As a result, researchers
portable devices, desktop or server processors to have developed several techniques that enhance a designs
supercomputers. To meet the dual and often conflicting goals testability through DFT modifications and improve the test
of achieving best possible performance and best energy generation and application processes. Traditionally, test
efficiency, several researchers have proposed architectural engineers evaluated these techniques according to various
techniques for different components of the processor, such as parameters: area overhead, fault coverage, test application
processor core, caches, DRAM (dynamic random access time, test development effort, and so forth. But now, the
memory) etc. For several reasons, managing energy recent development of complex, high-performance,
consumption of caches is a crucial issue in modern processor low-power devices implemented in deep-submicron
design. With each CMOS (complementary metal oxide technologies creates a new class of more sophisticated
semiconductor) technology generation, there is a significant electronic products, such as laptops, cellular telephones,
increase in the leakage energy consumption [2], [3]. audio- and video-based multimedia products, energy
According to the estimates of International Technology efficient desktops, and so forth. This new class of systems
Roadmap for Semiconductors (ITRS); with technology makes power management a critical parameter that test
scaling, leakage power consumption will become a major engineers cannot ignore during test development. Testing
We believe that this survey will help the researchers and
Manuscript received July 20, 2014. designers in understanding the state-of-the-art in power
Sandeep Kaur, Research Scholar, Chandigarh Engineering College, management of embedded systems and also motivate them to
Landran, Mohali.
further improve the energy efficiency of embedded systems.
Sarabdeep Singh, Asstt. Professor, ECE Department, Chandigarh
Engineering College, Landran, Mohali. In a paper of this length, it is not possible to do justice
to the broad range of developments in the field of embedded

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 VLSI Power Efficiency, Leakage, Dissipation and Management Techniques: A Survey

systems and hence, we take the following approach to limit E. Average Power
the scope of the paper. We include only those research works Average power is the total distribution of power over a time
that propose methods for improving energy efficiency and period. The ratio of energy to test time gives the average
also evaluate it. Those works which only evaluate power. Elevated average power increases the thermal load
performance improvement are not included although they that must be vented away from the device under test to prevent
may also lead to better energy efficiency. We review structural damage (hot spots) to the silicon, bonding wires, or
application and architectural level techniques and not package.
circuit-level techniques. Since different techniques have been
evaluated using different platforms and methodologies, we F. Instantaneous Power
only focus on their fundamental research idea and do not Instantaneous power is the value of power consumed at any
present the qualitative results. given instant. Usually, it is defined as the power consumed
right after the application of a synchronizing clock signal.
A. Energy and Power Modelling
Elevated instantaneous power might overload the power
Power consumption in CMOS circuits can be static or distribution systems of the silicon or package, causing
dynamic. Current used from the power supply causes static brown-out.
power dissipation in the system. Dynamic dissipation occurs
during output switching because of short circuit current, and G. Peak Power
charging and discharging of load capacitance. For existing The highest power value at any given instant, peak power
CMOS technology, dynamic power is the dominant source of determines the components thermal and electrical limits and
power consumption, although this might change for future system packaging requirements. If peak power exceeds a
high-scale integration. certain limit, designers can no longer guarantee that the entire
circuit will function correctly. In fact, the time window for
B. Sources of Power Consumption
defining peak power is related to the chips thermal capacity,
We briefly review the sources of power consumption in and forcing this window to one clock period is sometimes just
embedded systems and refer the reader to previous work [8, a simplifying assumption. For example, consider a circuit that
9] for more details. The power consumption of embedded has peak power consumption during only one cycle but
systems can be broadly divided in two categories, namely consumes power within the chips thermal capacity for all
dynamic power and static power. The dynamic power (Pdyn ) other cycles. In this case, the circuit is not damaged, because
consumption arises from charging and discharging of the load the energy consumed which corresponds to the peak power
capacitance, and the short circuit currents. The leakage power consumption times one cycle will not be enough to elevate
(Pleak ) arises due to leakage currents that flow even when the temperature over the chips thermal capacity limit
the device is inactive. Thus, we have (unless the peak power consumption is far higher than
Pdyn = CV 2 F (1) normal).
Pleak = IleakV (2)
Here shows the switching activity, F shows the H. Sources of Power Dissipation
operating frequency and V shows the operating voltage. I Power dissipation in digital CMOS circuits is caused by
leak shows the leakage current. With CMOS scaling the sources such as the leakage current, dependent on the
leakage power is increasing dramatically [7]. DVFS based fabrication technology, consists of reverse current in the
techniques work by reducing dynamic energy, while the parasitic diodes between source and drain junction diffusions
techniques which transition the system to low-power aim to and the bulk substrate region in a MOS transistor, and
reduce leakage energy. For a given CMOS technology sub-threshold current which arises due to inversion charge
generation, dynamic power consumption can be reduced by that exists at the gate voltages which are the threshold voltage,
adjusting voltage and frequency of operation or by reducing the standby current which is the DC current drawn
the activity factor. It is clear that, for a given CMOS continuously from Vdd to ground, the short-circuit
technology generation, the opportunity of saving leakage (rush-through) current which is due to the DC path between
energy lies in redesigning the circuit to use low-power cells, the supply rails during output transitions, the capacitance
reducing the total number of transistors or putting some parts current which flows to charge and discharge capacitive loads
of caches into low (or zero) leakage mode. Based on these during logic changes.
essential principles, several architectural techniques have
been proposed II. POWER MANAGEMENT FOR LIMITED SIZE AND BATTERY
C. Terminology
Test power is a possible major engineering problem in the Power management in embedded systems is important for
future of SoC development. As both the SoC designs and the battery-operated mobile embedded system; energy supply is a
deep-submicron geometry become prevalent, larger designs, crucial limitation. Power consumption in systems leads to
tighter timing constraints, higher operating frequencies, and heating, which should not exist in several domains such as
lower applied voltages all affect the power consumption embedded systems. Further, the small size of these systems
systems of silicon devices. [4] also limits the amount of heat-dissipation that can be
managed. Smaller power consumption enables use of smaller
D. Energy power supplies and reduced heat dissipation overhead, which
The total switching activity generated during test application, also reduces the cost, weight and area of embedded systems.
energy affects the battery lifetime during power up or periodic Thus power management can lead to easier system design.
self-test of battery-operated devices.

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 International Journal of Engineering and Technical Research (IJETR)
ISSN: 2321-0869, Volume-2, Issue-7, July 2014
III. LEAKAGE ENERGY SAVING APPROACHES caches using the selective-ways approach, program response
for different number of cache ways needs to be estimated.
A. An Overview For this purpose, researchers generally utilize utility
As explained before, leakage energy saving approaches monitors based on Mattson stack algorithm. Similarly, for
work by turning off a part of the cache to reduce the leakage utilizing selective-sets approach, researchers generally use
energy consumption of the cache. Based on the data set-sampling method and multiple auxiliary tags for getting
retentiveness of turned-off blocks, the leakage energy saving profiling information.
techniques are classified into two broad types, namely
state-preserving and state-destroying techniques. The IV. APPROACHES FOR SAVING BOTH DYNAMIC
state-preserving techniques turn off a block while AND LEAKAGE ENERGY
preserving its state (e.g., [10], [11]). This means that when Several studies present reconfigurable cache architectures
the block is reactivated, it does not need to be fetched from which offer flexibility to change one or more parameters of
next level of memory. The energy saving techniques turn off cache. By taking advantage of the flexibility offered by these
cache at the granularity (unit) of certain cache space, such as architectures, both dynamic and leakage energy can be saved.
a single way or a single block at a time. Based on this Several researchers have presented techniques for
granularity, leakage energy saving techniques can be synergistically using both leakage and dynamic energy saving
classified as way-level [12], [13], cache sub-block level [14]. techniques. For example, Giorgi and Bennati [24]
To demonstrate the typical values of the different cache demonstrate that using filter cache [23] reduces the number of
parameters, we take the example of an 8-way set-associative accesses to L1 cache, which, in turn, enables effectively using
cache of 2MB size with 64B block size and 8-byte sub-block. leakage energy saving techniques in L1 caches. Similarly,
To achieve high granularity with selective-ways approach Keramidas et al. [25] propose a way-selection based
requires use of highly-associative caches, which also have technique for additionally saving dynamic energy in the
high access time and energy. Selective-sets approach can caches which use decay-based leakage energy management.
potentially provide large granularity, however, in practice, it Their technique works on the observation that in a cache,
is observed that reducing the cache size below 1/8 or 1/16 using cache-decay mechanism [26] for saving leakage
significantly increases the miss-rate [15], [16]. Since leakage energy, several cache-blocks may be dead. Thus, by making
energy varies exponentially with the temperature, an increase an early determination of these dead blocks, the accesses to
in chip temperature increases the leakage energy dissipation these cache blocks can be avoided, which leads to saving of
in caches, which, in turn, further increases the chip dynamic energy of the cache. Since way-selection
temperature. To take chip temperature into account while mechanism, unlike way-prediction mechanism, gives definite
modelling and minimizing leakage energy, several techniques information about a cache miss, it always leads to uniform
have been proposed [17], [18], [19]. cache hit latency.
For both state-preserving and state-destroying leakage
control, architectural techniques make use of some A. Enabling Green Computing
well-known circuit-level mechanisms. Powell et al. [20] It has been estimated that the ICT (Information and
propose a circuit design named gated Vdd , which facilitates communications technology) contributes nearly 3% in the
state-destroying leakage control. This technique adds an extra overall carbon footprint [27]. Thus, power management in
transistor in the supply voltage path or ground path of the embedded systems is also important for achieving the goals of
SRAM (static random access memory) cell. For reducing the green computing.
leakage energy of the SRAM cell, this transistor is turned off
B. Using Power Modes
and by stacking effect of the transistor, the leakage current is
reduced by orders of magnitude. For reducing the leakage In embedded systems, the hardware typically provides a range
energy of the SRAM cell, the cache controller switches the of operating modes which can be used to save energy.
operating voltage of the cell to low voltage, thus putting the Different modes consume different amount of power and
cell in low-leakage mode. When this line is accessed the next take different time to return back to the normal mode. In
time, the supply voltage is again switched to high, thus the general, the modes with lower energy consumption also take
cache-block consumes normal power. Kim et al. [10] propose the largest time to return to the normal mode and vice versa.
a super-drowsy circuit design and Agarwal et al. [21] For saving energy while keeping the performance loss
propose a gated-ground circuit design, both of which behave bounded, these modes should be judiciously used. Also, while
similar to the drowsy cache, except that they only require a a low-power mode can be used when the system is idle, the
single voltage supply. Similarly, another state-preserving system must return to the normal mode for actually servicing a
circuit design, named multi-threshold CMOS (MTCMOS), request or performing the task.
dynamically changes the threshold voltage of the SRAM cell Hoeller et al. [28] propose an interface for power
by modulating the back-gate bias voltage to transition the cell management of hardware and software components. They
to low-leakage mode. method allows applications to express when certain
Mohyuddin et al. [22] propose a technique for saving components are not being used and based on this
leakage energy by maintaining different ways of a cache at information, individual components, subsystems or the whole
different state-preserving power saving modes depending on system can be transitioned to low-power modes. This frees the
their replacement priorities. Going from the MRU way to the programmer from the task of individually managing the
LRU way, cache lines are kept in increasingly aggressive power consumption of each component. Huang et al. [29]
power saving mode which also have increasingly larger propose an energy saving technique which works by
penalties of cache line wakeup. To dynamically reconfigure adaptively controlling the power mode of the embedded
system according to historical arrivals of tasks. Their

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 VLSI Power Efficiency, Leakage, Dissipation and Management Techniques: A Survey

technique takes decision regarding when to transition the inside the scan-chain for scan-based BIST. An example of
system to low-power from normal-power mode or vice versa, the low transition TPG for test-per-clock schemes is the
based on the relative time overhead and energy advantage approach presented in [23]. This approach, called
from mode transition and the consideration of meeting the DS-LFSR. The proposed design, called low transition random
deadlines of the tasks. test pattern generator (LT-RTPG), is composed of an LFSR, a
Awan et al. [30] Propose an approach for saving energy in k-input AND gate, and a toggle flip-flop T-FF. Some cells of
embedded systems using multiple low-power modes. Their the LFSR are connected with the inputs of the k-input AND
technique computes the break-even time for each mode using gate, the output of the AND gate is connected with the CUT
offline analysis. Further, since early completion of (the T-FF output will not toggle in m-cells will have the same
high-priority task creates slack, their technique accumulates value in most cases. Thus the power while scanning-in a test
this task and uses it to save extra leakage energy in lower vector not while scanning out the captured response. Also, in
priority tasks by allowing the device to stay in low-power order to get a high fault-coverage, a long test sequence is
mode for longer time. needed. put of the T-FF, and the output of the T-FF is
connected with the scan-chain input Sin). Since the output of
C. Saving Energy in Specific Components
the AND gate (input of the T-FF) is 0 in most of the cases, of
Several researchers propose micro-architectural techniques the clock cycles, and hence the transition probability in the
for saving energy in specific components of embedded CUT will decrease. The main drawback of this system is that
systems. These techniques leverage application properties or it reduces the average power while scanning-in a test vector
variation in workload to dynamically reconfigure the not while scanning out the captured response. Also, in order to
component of the system to save energy. The technique uses get a high fault-coverage, a long test sequence is needed.
software-based RAM compression to increase the effective
size of the memory. The memory compression is used only for B. Test Vectors Reordering
those applications which may gain benefit in performance or The test vectors reordering techniques aim to reduce the
energy from the compression. For such applications, switching activity by modifying the order in which the test the
compression of memory data and swapped-out pages is number of transitions between two consecutive vectors is
performed in an online manner, thus dynamically adjusting reduced (i.e. the Hamming distance between two consecutive
the size of the compressed RAM area. vectors is minimum), then the WSA will be reduced in the
whole CUT [32].
D. Problems Induced by Excessive Test Power
When dealing with high-density systems such as modern C. Scan Cells Reordering Techniques
ASICs and SoCs, a non-destructive test must satisfy all the Another category of techniques used to reduce the power
power constraints defined in the design phase. In addition to consumption in scan-based BIST is the use of scan-chain cells
preventing destruction of the CUT, cost, reliability, ordering techniques [33]. Changing the order of the scan cells
autonomy, performance-verification, and yield-related issues in each scan-chain can reduce the switching activity, and
motivate power consumption minimization during test.[31] hence power dissipation, in scan designs. In the case of a
The cost constraints of consumer electronic products typically deterministic set of test patterns, the best order of cells is the
require plastic packages, which impose a tight limitation on one that gives the best compromise between reducing the
power dissipation. Unfortunately, excessive switching transitions in the scan cells both while scanning in test
activity during test leads to increased current flows in the patterns and while scanning out captured responses.
CUT, making the use of expensive packages for the removal
D. Vector Filtering Techniques
of excessive heat imperative. Moreover, electro migration
causes the erosion of conductors and subsequently leads to The test vectors that are generated by TPGs such as
circuit failure. As the temperature and current density are LFSRs are pseudorandom vectors. The fault detection
major factors that determine electro migration rate, the capability of these vectors quickly reaches diminishing
elevated temperature and current density severely decrease returns. Hence, after running a sequence of test vectors and
CUT reliability. This phenomenon is even more severe in detecting many faults, then only a few of the subsequent test
circuits equipped with BIST because such circuits might be vectors can still detect new faults. The vectors that do not
tested frequently in, for example, online BIST strategies. Not detect new faults, but do consume power when applied to the
only the reliability but also the autonomy of battery-powered CUT, can be filtered or inhibited from being applied to the
remote and portable systems suffers from increased activity. CUT [34]. These algorithms, in general, use extra logic (e.g.
Remote system operation occurs mostly in standby mode with decoder circuitry). Using prior knowledge of the sequences
almost no power consumption, interrupted by periodic of test vectors generated by TPGs such as the LFSR, they can
self-tests. Hence, power savings during test mode directly prevent some sequences from being transmitted to the
prolong battery lifetime. CUT by knowing the first and last vectors in this sequence.
Thus they reduce the power consumption in the CUT.
V. METHODS FOR POWER TESTING E. Low Power Test Vector Compaction
A. Low Transition TPGs In scan-based circuits, in order to reduce the test data volume,
compacting techniques are introduced to merge several test
One common technique to reduce test power consumption is cubes. However, compacting test vectors greatly increases the
the design of low transition TPGs. Most of these techniques power dissipation (it could be several times higher). Thus,
modify the design of the LFSR (or other forms of TPGs such low power test vector compaction techniques have been
as cellular automata) in such a way as to reduce the transitions introduced to minimize the number of test cubes generated by
in the primary inputs of the CUT for test-per-clock BIST or

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 International Journal of Engineering and Technical Research (IJETR)
ISSN: 2321-0869, Volume-2, Issue-7, July 2014
the ATPG tool by merging test cubes that are compatibles in chip-design level, micro architectural level, application level
all bit positions under a power constraint [35]. By carefully and system level. We believe that our survey will enable
merging the test cubes in a specific manner, the number of researchers and engineers to understand the state-of-the-art in
transitions in the scan-chain can be minimized. micro architectural techniques for improving cache energy
efficiency, motivating them to design novel solutions for
F. Scan Architecture Modification
addressing the challenges posed by future trends of CMOS
This technique involves modifying the scan architecture by fabrication and processor design and in addressing the
inserting new elements and partitioning the scan-chain into challenges of power consumption and architecting
segments. In [36] the scan-chain is partitioned into N highly-energy efficient embedded systems of tomorrow.
segments where only one segment is active at a time. This
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