Flip Flops,RegistersandCounters:

FlipFlops, Registers and Counters:

Anotherclassoflogiccircuitshavethepropertythattheoutputsdependnot
onlyonthecurrentinputs,butalsoonthepastbehaviorofthecircuit
y p , p

Suchcircuitsincludestorageelementsthatstorethevaluesoflogicsignals

Sequential circuits
Sequentialcircuits

Contentsofthestorageelementsrepresentthestateofthecircuit

Inputvaluechangesmayleavethecircuitinthesamestateorcauseitto
changetoanewstate

Overtime,thecircuitchangesthroughasequenceofstatesasaresultof
changesintheinputs

Circuits that exhibit this behavior are referred to as sequential circuits

Atypicalcaralarmisrepresentativeofthistypeofcircuit

Thecircuitrequiresamemoryelementtorememberthatthealarmhastobeactive
untilaresetsignalarrives

Thealsrmsystemrespondtocontrolinputon/off,on/off
The alsrm system respond to control input on/off, on/off=1,
1,alarmon,on/off
alarm on , on/off=0
0itisoff.
it is off.
Thedesiredoperationisthatthealarmturnsonwhenthesensorgeneratesapositivevoltage
signalsetinresponsetotheundesirableevent.
Asimplememoryelement
Simplememoryelement:feedbackpathprovidesbasisforthe
rememberingofdataindefinitely

Onetransmissiongate,TG1,isusedtoconnectthe
DatainputterminaltopointAinthecircuit.

Thesecond,TG2,isusedasaswitchinthefeedback
The second TG2 is used as a switch in the feedback
loopthatmaintainsthestateofthecircuit.The
transmissiongatesarecontrolledbytheLoadsignal.

IfLoad=1,thenTG1isonandthepointAwillhavethesamevalueasthe
f d h d h ll h h l h
Datainput.SincethevaluepresentlystoredatOutputmaynotbethesame
valueasData,thefeedbackloopisbrokenbyhavingTG2turnedoffwhen
Load=1.

WhenLoadchangestozero,thenTG1turnsoffandTG2turnson.The
feedbackpathisclosedandthememoryelementwillretainits
stateaslongasLoad=0.
t t l L d 0
Load=0,TG2=onprovidingafeedbackpathTG2
Load=1,TG1=onprovidingawaytoloadnewdata
 BasicSRlatch

Asimilarcircuit,constructedwithNORgatescanalsobeconstructed

Inputs,SetandReset,providethemeanstochangingthestate,Q,ofthecircuit

Thiscircuitisreferredtoasabasiclatch
 R S R Qa Qb
Qa
0 0 0/1 1/0 (no change)
0 1 0 1
1 0 1 0
Qb 1 1 0 0
S

(a) Circuit (b) Truth table

WhenR=S=0thecircuitremainsinitscurrentstate(eitherQ
( Qa=1andQ
Qb=0orQ
Qa=0andQ
Qb=1))

WhenS=1andR=0,thelatchissetintoastatewhereQa=1andQb=0

WhenS=0andR=1,thelatchisresetintoastatewhereQ
When S 0 and R 1 the latch is reset into a state where Qa=0andQ
0 and Qb=1
1

WhereS=1andR=1,Qa=Qb=0(thereareactuallyproblemswiththisstateaswewillsee)
Fromt9tot10wehaveQa =Qb =0becauseR=S=1.NowifbothRandSchangeto0att10,
bothQa andQb willgoto1.
ButhavingbothQa andQb equalto1willimmediatelyforceQa =Qb =0.Therewill
b
beanoscillationbetweenQ
ll b a =Qb =0andQ
d a =Qb =1.Ifthedelaysthroughthetwo
f h d l h h h
NORgatesareexactlythesame,theoscillationwillcontinueindefinitely.ThustheS=R=1
combinationisgenerallyconsideredanunallowedcombinationintheSRlatch
Inarealcircuittherewillinvariablybesomedifferenceinthedelaysthroughthesegates,
In a real circuit there will invariably be some difference in the delays through these gates
andthelatchwilleventuallysettleintooneofitstwostablestates,butwedontknow
whichstateitwillbe.Thisuncertaintyisindicatedinthewaveformsbydashedlines
GatedSRlatch
ThebasicSRlatchchangesitsstatewheneveritsinputschange

ItmaybedesirabletoaddanenablesignaltothebasicSRlatchthat
allowsustocontrolwhenthecircuitcanchangestates

SuchacircuitisreferredtoasagatedSRlatch

ThelatchwillmaintainitsexistingstateaslongasClk=0.WhenClkchanges
to1,theSandRsignalswillbethesameastheSandRsignals,respectively.

Itisdesirabletoallowthechangesinthestatesofmemoryelementstooccuronly
atwelldefinedtimeintervals,asiftheywerecontrolledbyaclock.
Thelastrowofthetruthtable,whereS=R=1,showsthatthestateQ(t+1)isundefined
becausewedontknowwhetheritwillbe0or1.
Thiscorrespondstothesituationdescribedinbeforeinconjunctionwiththetimingdiagram
attimet10.
AtthistimebothSandRinputsgofrom1to0,whichcausestheoscillatorybehaviorthatwe
discussed. If S =R
discussed.IfS R =1,thissituationwilloccurassoonasClkgoesfrom1to0.Toensurea
1, this situation will occur as soon as Clk goes from 1 to 0. To ensure a
meaningfuloperationofthegatedSRlatch,itisessentialtoavoidthepossibilityofhaving
boththeSandRinputsequalto1whenClkchangesfrom1to0.
GatedSRlatchwithNANDgates
Gated D latch
Another useful latch has a single data input, D, and it stores the value of this input
under the control of a clock signal
This is referred to as a gated D latch
Useful
U f l iin circuits
i it where
h we wantt tto store
t some value
l
The output of an adder/subtractor circuit would be one example
If D = 1,
1 then
h S = 1 and dR=0 0, which
hi h fforces th
the llatch
t h iinto
t th
the state
t t Q=1
1. If D = 0
0,
then S = 0 and R = 1, which causes Q = 0. Of course, the changes in state occur only
when Clk = 1.
It is important to observe that in this circuit it is impossible to have the troublesome
situation where S = R = 1. In the gated D latch, the output Q merely tracks the value of
the input D while Clk = 1.
As soon as Clk goes to 0, the state of the latch is frozen until the next time the clock signal goes to
1 Therefore,
1. Th f the
h gatedd D llatch
h stores the
h valuel off the
h D input
i seen at the
h time
i the
h clock
l k changes
h
from 1 to 0.
The key point to observe is that as long as the clock has
the value 1, the Q output follows the D input.