Uaa 2022
Uaa 2022
Uaa 2022
@ Cascadable P SUFFIX
PLASTIC PACKAGE
CASE 724
CO
OUTPUT BUFFERS
LED
TEST
LATCHES
1
GND
VOR
CLOCK DATA
16 BIT SHIFT REGISTER
OUT
DATA
July 1983
FIGURE 4 - TYPICAL APfLICATION
+5v
q
1
LED
DISPLAY
CLK U A A 2 0 2 2
6.8k
DATA
22fJf
DATA OUT
OUTLINE DIMENSIONS
P SUF FIX
PLASTIC PACUACE
CASE 724
I flfl(ifil-?fT.Plflflflfl 1
NOTE:
1. LEAOS. TAUE fOSITIONE0 WITHIN
0.25 mrn fO.OlOl OIA ATSEATING
e
I- I PLANE AT MAXIMUM MATERIAL
CONOITION (OIM. 0-T
J--
-n- -G- - - Y
,cr. 1lYG Pl Irrt
This information has beert carefully checked and is believed to be entirely reliable. However. no responsibility is assumed for inaccuracies. Motorola reserves
the right to make changes to any products herein to improve reliability. function or design. Motorola does not assume any liability arising out of the apptication
or use of any product or circuit described herein. No license is conveyed under patent rights in any form. When this document contains information on a new
product. specifications herein are subject to Change without notice.
, -.
MOIrcip3OLA Semiconductor Products Inc.
Avenue G&dral-Eisenhower - 31023 Toulouse CEDEX - FRANCE Printed in Switrerland
FIGURE 2 - CIRCUlT CONFIGURATIONS
OUT 17
lto6
8 to 15,
23.24
cc
DATA
OUT
LOGIC 1
DATA
- 8lJFFER ON
he -UAA2022 is intended to control common anode from the shift register and new information is shifted in.
EDs and allows brightness Variation from an external On the positive VDR-edge the latches are reconnected,
ontrol voltage. Since it is not multiplexed it is particularly thus transferring new information to the Outputs. (See
Jited for hi-fi applications etc. f igure 2a.)
he circuit receives 16 bit serial data by means of the
igital inputs Vm (Chip select), Glock and Data (TTL- The shift register also has a data output. (See figure 2b.)
:vels). The information is fed into a shift-register, and This allows the microprocessor to pass data through the
len is stored in latches which in turn control the output UAA 2022, and thus drive further circuits from the same
uffers. These output buffers (Segment driversl h a v e d a t a a n d Chip-select Pins. T h e U A A 2 0 2 2 s h i f t s a n d
urrent Source characteristics (See figure 2a), thus no Outputs data on the positive going clock edge. Thus for
xternal resitors are needed to set up the Segment currents reliable data transfer, it has to be the first circuit in the
for 100 % luminosity). line, when connected in series with circuits which shift on
the negative going clock edge. The circuit is cascad-
igure 3 Shows the timing diagram of the circuit. On the a b l e a n d tan b e c a s c a d e d w i t h t h e U A A 2 0 0 0 a n d
negative going VOR-edge the latches are disconnected UAA2001/2010.
INPUT/OUTPUT FUNCTIONS
3UFFER OUTPUTS - (Pins 1 to 6,8 to 15,23,24) which accepts shifts and Outputs data on the positive
going edge. It should be noted that within the VDR-
These Outputs have current Source characteristics to drive window, when VDR is low, the clock has to be high at
:he LED Segments without external resistances. the beginning and the end of the clock pulse train.
Data is entered into the device serially via this pin and
L E D - TEST - (Pin 181
passed directly into the shift register- In turn, this controls
This pin supplies t@he logic section of the circuit, when the latches and output buffers. (Logic 1 = Buffer ON)
connected to ground all output buffers are switched on.
D A T A O U T - (Pin 22)
CL$XK - (pin 191
Is the data output of the shift register- Allows cascading
I with circuits operating on the Same VDR and clock Signals.
Thrs pin delivers the clock Signal to the shift register,
High State
Logic Input Currents
LowState
High State
(CO = cc, LE = 0)
Buffer Current Variation around 1BB
Saturation Voltage
Output Impedance
Supply Current
Supply Voltage
Control Voltage
Buffers 1 to6
8to 15
Output Voltage Wcc = VCo = 5.5VI v13B 6 V
23,24
All Buffers ON
Storage Temperature
I I TSTG I
-5oto +150 I Oc I
Operating Ambient Temperature
Charactaristic Symbol
... .
I Data Change to positive going Glock Edge
1 LDC Ill 14
I
I l I 121usl
- -
Fall Timet of Digital Inputs VOR, Glock, Data FV4 FC* F D