Stc12c5620ad English

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com Mobile:(86)13922809991 Tel:86-755-82948412 Fax:86-755-82905966
t ed .
STC12C5620AD series
i m i MCU
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STC12LE5620AD series MCU
C U
M Sheet
Data
S T C
STC MCU Limited

www.STCMCU.com
Update date: 2011-7-15
STC MCU Limited. websitewww.STCMCU.com

CONTENTS
Chapter 1. Introduction..................................................................7
1.1 Features................................................................................................... 7
1.2 Block diagram......................................................................................... 8
1.3 Pin Configurations . ................................................................................ 9
1.4 STC12C5620AD series Selection Table................................................11
1.5 STC12C5620AD series Minimum Application System........................ 12
1.6 STC12C5620AD series MCU Typical Application Circuit for ISP...... 13
1.6.1 STC12C5620AD series MCU (28 pin) Typical Application Circuit for ISP....... 13
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1.7 Pin Descriptions.................................................................................... 18
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1.8 Package Dimension Drawings............................................................... 20
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1.9 STC12C5620AD series MCU naming rules......................................... 26
M C
1.10 Global Unique Identification Number (ID)......................................... 27
Chapter 2. Clock, Power Management and Reset.....................30
2.1.1
2.1.2 S T C
2.1 Clock..................................................................................................... 30
On-Chip R/C Clock and External Crystal/Clcok are Optional in STC-ISP.exe .. 30
Divider for System Clock .................................................................................... 31
2.1.3 How to Know Internal RC Oscillator frequency(Internal clock frequency) ....... 32
2.1.4 Programmable Clock Output................................................................................ 35
2.1.4.1 Timer 0 Programmable Clock-out on P1.0..........................................................................36
2.1.4.2 Timer 1 Programmable Clock-out on P1.1..........................................................................37
2.2 Power Management Modes................................................................... 38
2.2.1 Slow Down Mode................................................................................................. 39
2.2.2 Idle Mode.............................................................................................................. 40
2.2.3 Stop / Power Down (PD) Mode and Demo Program (C and ASM)..................... 41
2.3 RESET Sources..................................................................................... 47
2.3.1 RESET Pin............................................................................................................ 47
2.3.2 Software RESET................................................................................................... 47
2.3.3 Power-On Reset (POR)......................................................................................... 48
2.3.4 MAX810 power-on-Reset delay........................................................................... 48
2.3.5 Internal Low Voltage Detection Reset.................................................................. 49
2.3.6 Watch-Dog-Timer................................................................................................. 52
2.3.7 Warm Boot and Cold Boot Reset.......................................................................... 56
Chapter 3. Memory Organization...............................................57
3.1 Program Memory.................................................................................. 57
3.2 Data Memory(SRAM)........................................................................... 58
3.2.1 On-chip Scratch-Pad RAM................................................................................... 58
3.2.2 Auxiliary RAM..................................................................................................... 61
3.3 Special Function Registers.................................................................... 65
3.3.1 Special Function Registers Address Map............................................................. 65
d
3.3.2 Special Function Registers Bits Description........................................................ 66
Chapter 4. Configurable I/O Ports of STC12C5620AD series 71
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4.1 I/O Ports Configurations....................................................................... 71
4.2 I/O ports Modes..................................................................................... 74
4.2.1
C U
Quasi-bidirectional I/O......................................................................................... 74
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4.2.2 Push-pull Output................................................................................................... 75
4.2.3 Input-only (High-Impedance)Mode..................................................................... 75
C
4.2.4 Open-drain Output................................................................................................ 75
S T
4.3 I/O port application notes...................................................................... 76
4.4 Typical transistor control circuit............................................................ 76
4.5 Typical diode control circuit.................................................................. 76
4.6 3V/5V hybrid system............................................................................. 77
4.7 How to make I/O port low after MCU reset.......................................... 78
4.8 I/O status while PWM outputing........................................................... 78
4.9 I/O drive LED application circuit.......................................................... 79
4.10 I/O immediately drive LCD application circuit.................................. 80
4.11 Using A/D Conversion to scan key application circuit........................ 81
Chapter 5. Instruction System.....................................................82
5.1 Addressing Modes................................................................................. 82
5.2 Instruction Set Summary....................................................................... 83
5.3 Instruction Definitions........................................................................... 88
Chapter 6. Interrupt System......................................................125
6.1 Interrupt Structure............................................................................... 127
6.2 Interrupt Register................................................................................. 129
6.3 Interrupt Priorities............................................................................... 139
6.4 How Interrupts Are Handled............................................................... 140
6.5 External Interrupts.............................................................................. 141
6.6 Response Time................................................................................... 145
6.7 Demo Programs about Interrupts (C and ASM).................................. 146
6.7.1 External Interrupt 0 (INT0 ) Demo Programs (C and ASM)............................. 146
6.7.2 External Interrupt 1 (INT1 ) Demo Programs (C and ASM)............................. 150
6.7.3 Programs of P3.4/T0 Interrupt(falling edge) used to wake up PD mode........... 154
6.7.4 Programs of P3.5/T1 Interrupt(falling edge) used to wake up PD mode........... 156
6.7.5 Program of P3.0/RxD Interrupt(falling edge) used to wake up PD mode.......... 158
6.7.6 Program of PCA Interrupt used to wake up Power Down mode........................ 161
Chapter 7. Timer/Counter 0/1...................................................165
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7.1 Special Function Registers about Timer/Counter................................ 165
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7.2 Timer/Counter 0 Mode of Operation (Compatible with traditional 8051 MCU).......... 169
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7.2.1 Mode 0 (13-bit Timer/Counter)....................................................................................... 169
7.2.2
7.2.3
7.2.4 M C
Mode 1 (16-bit Timer/Counter) and Demo Programs (C and ASM)............................... 170
Mode 2 (8-bit Auto-Reload Mode) and Demo Programs (C and ASM).......................... 174
C
Mode 3 (Two 8-bit Timers/Couters)................................................................................ 177
T
7.3 Timer/Counter 1 Mode of Operation................................................... 178
S
7.3.1 Mode 0 (13-bit Timer/Counter)....................................................................................... 178
7.3.2 Mode 1 (16-bit Timer/Counter) and Demo Programs (C and ASM)............................... 179
7.3.3 Mode 2 (8-bit Auto-Reload Mode) and Demo Programs (C and ASM).......................... 183
7.4 Programmable Clock Output and Demo Programs (C and ASM)...... 186
7.4.1 Timer 0 Programmable Clock-out on P1.0 and Demo Program......................... 188
7.4.2 Timer 1 Programmable Clock-out on P1.1 and Demo Program......................... 191
7.5 Application note for Timer in practice................................................ 194
Chapter 8. UART with Enhanced Function.............................195
8.1 Special Function Registers about UART............................................. 195
8.2 UART1 Operation Modes .................................................................. 200
8.2.1 Mode 0: 8-Bit Shift Register.............................................................................. 200
8.2.2 Mode 1: 8-Bit UART with Variable Baud Rate.................................................. 202
8.2.3 Mode 2: 9-Bit UART with Fixed Baud Rate...................................................... 204
8.2.4 Mode 3: 9-Bit UART with Variable Baud Rate.................................................. 206
8.3 Frame Error Detection......................................................................... 208
8.4 Multiprocessor Communications........................................................ 208
8.5 Automatic Address Recognition.......................................................... 209
8.6 Buad Rates............................................................................................211
8.7 Demo Programs about UART (C and ASM)....................................... 212
Chapter 9. Analog to Digital Converter....................................218
9.1 A/D Converter Structure...................................................................... 218
9.2 Registers for ADC............................................................................... 220
9.3 Application Circuit of A/D Converter ................................................ 223
9.4 ADC Application Circuit for Key Scan............................................... 224
9.5 A/D reference voltage source.............................................................. 225
9.6 Program using interrupts to demostrate A/D Conversion .................. 226
9.7 Program using polling to demostrate A/D Conversion ...................... 232
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Chapter 10. Programmable Counter Array(PCA)..................238
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10.1 SFRs related with PCA...................................................................... 238
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10.2 PCA/PWM Structure......................................................................... 245
10.3.1
M C
10.3 PCA Modules Operation Mode........................................................ 247
PCA Capture Mode........................................................................................... 247
C
10.3.2 16-bit Software Timer Mode............................................................................ 248
10.3.3
10.3.4
10.4 S T
High Speed Output Mode................................................................................. 249
Pulse Width Modulator Mode (PWM mode)................................................... 250
Programs for PCA module extended external interrupt ................... 251
10.5 Demo Programs for PCA module acted as 16-bit Timer................... 255
10.6 Programs for PCA module as 16-bit High Speed Output.................. 259
10.7 Demo Programs for PCA module as PWM Output . ........................ 263
10.8 Demo Program for PCA clock base on Timer 1 overflow rate........ 267
10.9 Using PWM achieve D/A Conversion function reference circuit..... 271
Chapter 11. Serial Peripheral Interface (SPI)..........................272
11.1 Special Function Registers related with SPI...................................... 272
11.2 SPI Structure...................................................................................... 275
11.3 SPI Data Communication.................................................................. 276
11.3.1 SPI Configuration............................................................................................. 276
11.3.2 SPI Data Communication Modes..................................................................... 277
11.3.3 SPI Data Modes................................................................................................ 279
11.4 SPI Function Demo Programs (Single Master Single Slave)....... 281
11.4.1 SPI Function Demo Programs using Interrupts (C and ASM).......................... 281
11.4.2 SPI Function Demo Programs using Polling (C and ASM).............................. 287
11.5 SPI Function Demo Programs (Each other as the Master-Slave)...... 293
11.5.1 SPI Function Demo Programs using Interrupts (C and ASM).......................... 293
11.5.2 SPI Function Demo Programs using Polling.................................................... 299
Chapter 12. IAP / EEPROM......................................................305
12.1 IAP / EEPROM Special Function Registers..................................... 306
12.2 STC12C5620AD series Internal EEPROM Allocation Table........... 309
12.3 IAP/EEPROM Assembly Language Program Introduction.............. 310
12.4 EEPROM Demo Program (C and ASM)........................................... 313
Chapter 13. STC12 series Development/Programming Tool..321
13.1 In-System-Programming (ISP) principle........................................... 321
13.2 STC12C5620AD series Typical Application Circuit for ISP............ 322
13.3 PC side application usage.................................................................. 324
13.4 Compiler / Assembler Programmer and Emulator............................ 326
13.5 Self-Defined ISP download Demo................................................... 326
Appendix A: Assembly Language Programming.....................330
Appendix B: 8051 C Programming...........................................352
Appendix C: STC12C5620AD series Electrical Characteristics..
................................................................................362
Appendix D: Program for indirect addressing inner 256B RAM
................................................................................364
Appendix E: Using Serial port expand I/O interface..............365
Appendix F: Use STC MCU common I/O driving LCD Display
................................................................................367
Appendix G: LED driven by an I/O port and Key Scan..........374
Appendix H: How to reduce the Length of Code through Keil C
................................................................................375
Appendix I: Notes of STC12C5620AD series Application......376
Appendix J: Notes of STC12 series Replaced Traditional 8051...
................................................................................377
www.STCMCU.com Mobile:(86)13922809991 Tel:86-755-82948412 Fax:86-755-82905966
Chapter 1. Introduction
STC12C5620AD is a single-chip microcontroller based on a high performance 1T architecture 8051 CPU, which
is produced by STC MCU Limited. With the enhanced kernel, STC12C5620AD executes instructions in 1~6
clock cycles (about 8~12 times the rate of a standard 8051 device), and has a fully compatible instruction set with
industrial-standard 8051 series microcontroller. In-System-Programming (ISP) and In-Application-Programming
(IAP) support the users to upgrade the program and data in system. ISP allows the user to download new code
without removing the microcontroller from the actual end product; IAP means that the device can write non-
valatile data in Flash memory while the application program is running. The STC12C5620AD retains all features
of the standard 80C51. In addition, the STC12C5620AD has a 9-sources, 4-priority-level interrupt structure,
10-bit ADC(100 thousands times per second), on-chip crystal oscillator, MAX810 special reset circuit, 4-channel
PCA and PWM, SPI, a one-time enabled Watchdog Timer and so on.
1.1 Features
ed .
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Enhanced 8051 Central Processing Unit ,1T per machine cycle, faster 8~12 times than the rate of a standard
8051.
Li
Operating voltage range: 5.5V ~ 3.5V or 2.2V ~ 3.6V (STC12LE5620AD).
Operating frequency range: 0- 35MHz, is equivalent to standard 8051:0~420MHz
U
On-chip 30K/28K/24K/20K/16K/12K/8K/4K... FLASH program memory with flexible ISP/IAP capability
On-chip 768 byte RAM
M C
Power control: idle mode(can be waked up by any interrupt) and power-down mode(can be waked up by
C
external interrupts).
T
Code protection for flash memory access
S
Excellent noise immunity, very low power consumption
six 16-bit timer/counter, be compatible with Timer0/Timer1 of standard 8051, 4-channel PCA can be
available as four timers.
9 vector-address, 4 level priority interrupt capability
One enhanced UART with hardware address-recognition and frame-error detection function
One 15 bits Watch-Dog-Timer with 8-bit pre-scaler (one-time-enabled)
SPI Master/Slave communication interface
Four channel Programmable Counter Array (PCA)
10-bit, 8-channel high-speed Analog-to-Digital Converter (ADC), up to 100 thousands times per second
Simple internal RC oscillator and external crystal clock
Three power management modes: idle mode, slow down mode and power-down mode
Power down mode can be woken-up by P3.2/INT0, P3.3/INT1, P3.4/T0, P3.5/T1, P3.0/RxD, P3.7/PCA0, and
P3.5/PCA1, PCA2/P2.0, PCA3/P2.4
Operation Temperature: -40 ~ + 85 (industrial) / 0 ~ 75 (Commercial)
Common (27/23/15) programmable I/O ports are available
Programmable clock output Function. T0 output the clock on P1.0, T1 output the clock on P1.1.
Five package type : LQFP-32, SOP-32, SOP-28, SKDIP-28, SOP-20, DIP-20, LSSOP-20.

1.2 Block diagram

The CPU kernel of STC12C5620AD is fully compatible to the standard 8051 microcontroller, maintains all
instruction mnemonics and binary compatibility. With some great architecture enhancements, STC12C5620AD
executes the fastest instructions per clock cycle. Improvement of individual programs depends on the actual
instructions used.
AUX-RAM RAM ADDR RAM

512B Register 256B
FLASH
B Register ACC Stack
t ed .
i
Pointer
ISP/IAP
TMP2 TMP1
Li m Timer 0/1
Address
CU
Generator
Enhanced
UART
M
ALU Program
Counter
C
WDT
PSW
T
PCA
S
(4-channel)
LVD/LVR
SPI
Control Port 0,2,3
Port1 Latch
RESET Unit Latch
ADC
XTAL1 XTAL2 Port 0,2,3
Port 1 Driver Driver
8
P1.0 ~ P1.7
P0,P2,P3
P1.0 ~ P1.7
STC12C5620AD Block Diagram

1.3 Pin Configurations

All packages meet the European Union RoHS standards. LQFP-32 also conform to the Green standard.
Packages such as SOP-20/28/32 and LQFP-32 are strongly recommended though the traditional DIP packages are
steady supplied.
P2.2 1 32 VCC P2.2 1 32 VCC

P2.3 2 31 P2.1 P2.3 2 31 P2.1
RST 3 30 P2.0/PCA2/PWM2 RST 3 30 P2.0/PCA2/PWM2
RxD/P3.0 4 29 P1.7/SCLK/ADC7 RxD/P3.0 4 29 P1.7/SCLK
TxD/P3.1 5 28 P1.6/MISO/ADC6 TxD/P3.1 5 28 P1.6/MISO
P0.0 6 27 P1.5/MOSI/ADC5 P0.0 6 27 P1.5/MOSI
SOP-32
SOP-32
.
XTAL2 7 26 P0.3 XTAL2 7 26 P0.3
d
XTAL1 8 25 P1.4/SS/ADC4 XTAL1 8 25 P1.4/SS
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INT0/P3.2 9 24 P1.3/ADC3 INT0/P3.2 9 24 P1.3
m
P0.1 10 23 P0.2 P0.1 10 23 P0.2
i
INT1/P3.3 11 22 P1.2/ADC2 INT1/P3.3 11 22 P1.2
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ECI/T0/P3.4 12 21 P1.1/ADC1/CLKOUT1 ECI/T0/P3.4 12 21 P1.1/CLKOUT1
PWM1/PCA1/T1/P3.5 13 20 P1.0/ADC0/CLKOUT0 PWM1/PCA1/T1/P3.5 13 20 P1.0/CLKOUT0
CU
PWM3/PCA3/P2.4 14 19 P3.7/PCA0/PWM0 PWM3/PCA3/P2.4 14 19 P3.7/PCA0/PWM0
P2.5 15 18 P2.7 P2.5 15 18 P2.7
M
16 17 16 17
Gnd P2.6 27 I/O ports Gnd P2.6
STC12C5620AD series (with A/D Converter), SOP-32 STC12C5620 series (without A/D Converter), SOP-32
S T C
LQFP-32 Package : lengthwidth = 9mm9mmheight < 1.6mm
P1.1/ADC1/CLKOUT1
P1.6/MISO/ADC6
P1.5/MOSI/ADC5
P1.6/MISO/ADC6
P1.5/MOSI/ADC5
P1.1/CLKOUT1
P1.4/SS/ADC4
P1.3/ADC3
P1.2/ADC2
P1.4/SS
P0.3
P0.2
P0.3
P1.3
P0.2
P1.2
24
23
22
21
20
19
18
17
24
23
22
21
20
19
18
17
ADC7/SCLK/P1.7 25 16 P1.0/ADC0/CLKOUT0 ADC7/SCLK/P1.7 25 16 P1.0/CLKOUT0

P2.1 27 14 P2.7 P2.1 27 14 P2.7
Vcc P2.6 Vcc P2.6
P2.2
28
29
LQFP-32 13
12 Gnd P2.2
28
29
LQFP-32 13
12 Gnd
P2.3 30 11 P2.5 P2.3 30 11 P2.5
RxD/P3.0 32 9 P3.5/T1/PCA1/PWM1 RxD/P3.0 32 9 P3.5/T1/PCA1/PWM1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
27 I/O ports
ECI/T0/P3.4
ECI/T0/P3.4
TxD/P3.1
XTAL2
XTAL1
INT0/P3.2
P0.1
INT1/P3.3
TxD/P3.1
XTAL2
XTAL1
INT0/P3.2
P0.1
INT1/P3.3
P0.0
P0.0
STC12C5620AD series (with A/D Converter), LQFP-32 STC12C5620 series (without A/D Converter), LQFP-32

P2.2 1 28 VCC P2.2 1 28 VCC

P2.3 2 27 P2.1 P2.3 2 27 P2.1
SOP-28 / SKDIP-28
SOP-28 / SKDIP-28
RxD/P3.0 4 25 P1.7/SCLK/ADC7 RxD/P3.0 4 25 P1.7/SCLK
XTAL2 6 23 P1.5/MOSI/ADC5 XTAL2 6 23 P1.5/MOSI
INT0/P3.2 8 21 P1.3/ADC3 INT0/P3.2 8 21 P1.3
INT1/P3.3 9 20 P1.2/ADC2 INT1/P3.3 9 20 P1.2

PWM1/PCA1/T1/P3.5 11 18 P1.0/ADC0/CLKOUT0 PWM1/PCA1/T1/P3.5 11 18 P1.0/CLKOUT0
P2.5 13 16 P2.7 P2.5 13 16 P2.7
23 I/O ports
.
Gnd 14 15 P2.6 Gnd 14 15 P2.6
STC12C5620AD series (with A/D Converter)28-Pin
i t ed
STC12C5620 series (without A/D Converter)28-Pin
Li m
RST
RxD/P3.0
1
2
20
19
VCC
M
P1.7/SCLK/ADC7
CU RST
RxD/P3.0
1
2
20
19
VCC
P1.7/SCLK
SOP-20 / DIP-20
SOP-20 / DIP-20
C
TSSOP-20
TSSOP-20
T
XTAL2 4 17 P1.5/MOSI/ADC5 XTAL2 4 17 P1.5/MOSI
S
INT0/P3.2 6 15 P1.3/ADC3 INT0/P3.2 6 15 P1.3
INT1/P3.3 7 14 P1.2/ADC2 INT1/P3.3 7 14 P1.2
PWM1/PCA1/T1/P3.5 9 12 P1.0/ADC0/CLKOUT0 PWM/PCA1/T1/P3.5 9 12 P1.0/CLKOUT0
Gnd 10 11 P3.7/PCA0/PWM0 15 I/O ports Gnd 10 11 P3.7/PCA0/PWM0
STC12C5620AD series (with A/D Converter)20-Pin STC12C5620 series (without A/D Converter)20-Pin
Super small package : TSSOP-20, 6.4mm6.4mm
10 STC MCU Limited. websitewww.STCMCU.com

1.4 STC12C5620AD series Selection Table

16-bit
Type U Package of Package of
Operation PCA/ W Package of
1T 8051 Flash SRAM Timer PCA Programmable A EEP A/D Built-in 28-Pin 32-Pin
Voltage 8-bit D SPI 20-Pin
MCU (Byte) (Byte) T0&T1 Timer Clock Output R ROM 8-ch Reset (23 I/O (27 I/O
(V) PWM T (15 I/O ports)
T ports) ports)
D/A
STC12C5620AD series Selection Table

STC12C5604 5.5-3.5 4K 768 Y 4 Y Y Y 2/4-ch Y Y Y SOP/LSSOP/DIP SOP/SKDIP SOP/LQFP
STC12C5604AD 5.5-3.5 4K 768 Y 4 Y Y Y 2/4-ch 10-bit Y Y Y SOP/LSSOP/DIP SOP/SKDIP SOP/LQFP
STC12C5612 5.5-3.5 12K 768 Y 4 Y Y IAP 2/4-ch Y Y Y Application program can be modified in
STC12C5612AD 5.5-3.5 12K 768 Y 4 Y Y IAP 2/4-ch 10-bit Y Y Y application program area (AP area)
d .
mit e
Li
U
C
Application program can be modified in
M
STC12C5628 5.5-3.5 28K 768 Y 4 Y Y IAP 2/4-ch Y Y Y
application program area (AP area)
STC12C5628AD 5.5-3.5 28K 768 Y 4 Y Y IAP 2/4-ch 10-bit Y Y Y
T C
STC12C5630 5.5-3.5 30K 768 Y 4 Y Y IAP 2/4-ch Y Y Y
S
STC12C5630AD 5.5-3.5 30K 768 Y 4 Y Y IAP 2/4-ch 10-bit Y Y Y
STC12LE5620AD series Selection Table

STC12LE5604 3.6-2.2 4K 768 Y 4 Y Y Y 2/4-ch Y Y Y SOP/LSSOP/DIP SOP/SKDIP SOP/LQFP
STC12LE5604AD 3.6-2.2 4K 768 Y 4 Y Y Y 2/4-ch 10-bit Y Y Y SOP/LSSOP/DIP SOP/SKDIP SOP/LQFP
STC12LE5612 3.6-2.2 12K 768 Y 4 Y Y Y 2/4-ch Y Y Y Application program can be modified in
STC12LE5612AD 3.6-2.2 12K 768 Y 4 Y Y Y 2/4-ch 10-bit Y Y Y application program area (AP area)

STC12LE5628 3.6-2.2 28K 768 Y 4 Y Y IAP 2/4-ch Y Y Y
STC12LE5628AD 3.6-2.2 28K 768 Y 4 Y Y IAP 2/4-ch 10-bit Y Y Y
STC12LE5630 3.6-2.2 30K 768 Y 4 Y Y IAP 2/4-ch Y Y Y
STC12LE5630AD 3.6-2.2 30K 768 Y 4 Y Y IAP 2/4-ch 10-bit Y Y Y
STC MCU Limited. websitewww.STCMCU.com 11

1.5 STC12C5620AD series Minimum Application System

When the frequency of crystal oscillator is lower than 20MHz,
it is suggested not to use C1 and R1 replaced by 1K
resistor connect to ground.
But R/C reset circuit is also suggest to reserve.
Vin
1 P2.2 VCC 28 System power/5V/3V
Power On SW1
10F + 2 P2.3 P2.1 27
C1 +
C6 C5
3 RST PWM2/PCA2/P2.0 26
0.1F 10F
10K R14 P3.0/RxD ADC7/SCLK/P1.7 25
C2<33pF
.
5 P3.1/TxD ADC6/MIOS/P1.6 24
ed
6 XTAL2 ADC5/MOSI/P1.5 23
i t
X1
7 XTAL1 ADC4/SS/P1.4 22
C3<33pF 8 P3.2/INT0
9 P3.3/INT1
ADC3/P1.3 21
ADC2/P1.2 20
Li m
U
10 P3.4/T0/ECI CLKOUT1/ADC1/P1.1 19
M C
11 P3.5/T1/PCA1/PWM1 CLKOUT0/ADC0/P1.0 18
12 P2.4/PCA3/PWM3 PWM0/PCA0/P3.7 17
C
13 P2.5 P2.7 16
S T
14 Gnd P2.6 15
About crystals circuit:

If using internal R/C oscillator clock (4MHz ~ 8MHz, manufacturing error), XTAL1 and XTAL2 pin should
be floated.
If External clock frequency is higher than 33MHz, it is recommended to directly use external active crystals
which clock are input from XTAL1 pin and XTAL2 pin must be floated.

1.6 STC12C5620AD series MCU Typical Application Circuit for ISP

MCU should be connected to computer through RS-232 converter to download program
1.6.1 STC12C5620AD series MCU (28 pin) Typical Application Circuit for ISP
Vcc
MAX232,MAX3232,SP232,SP3232 PC COM
10F
1 C1+ Vcc 16 Vcc 2 Download user
+
0.1F
3 procedure to STC
2 V+ Gnd 15 Gnd
MCU by the software
3 C1- T1OUT 14 PC_RxD(COM Pin2) 5
STC-ISP programmer
PC_TxD(COM Pin3)
4 C2+ R1IN 13
.
0.1F
Users are suggested stay this USB +5V
Vin
d
5 C2- R1OUT 12
interface on the system , which System Power
e
USB+5V T1OUT R1IN GND
mit
6 V- T1IN 11 can be convenient download
0.1F the users program online. SW1
7 T2OUT T2IN 10
Li
Reset USB1
8 R2IN R2OUT 9
U1-P1.0 Power On
U1-P1.1
MCU-VCC
CU
When the frequency of crystal oscillator is lower
than 20MHz, it is suggested not to use C1 and U1-P3.0
R1 replaced by 1K resistor connect to ground. U1-P3.1
M
But R/C reset circuit is GND 28 Pin
Vcc
also suggest to reserve.
1K Vcc
1 P2.2 VCC 28
C
1K
T
+ 2 P2.3 P2.1 27
S
10 F C1
3 RST PWM2/PCA2/P2.0 26 0.1F + 10F
10K R1 4 P3.0/RxD ADC7/SCLK/P1.7 25
5 P3.1/TxD ADC6/MISO/P1.6 24
<33pF
<33pF 7 XTAL1 ADC4/SS/P1.4 22
8 P3.2/INT0 ADC3/P1.3 21
9 P3.3/INT1 ADC2/P1.2 20
13 P2.5 P2.7 16
14 Gnd P2.6 15
If using internal R/C oscillator clock
(4MHz ~ 8MHz, manufacturing error),
XTAL1 and XTAL2 pin should be floated.
If External clock frequency is higher

than 33MHz, it is recommended to directly
use external active crystals which clock
are input from XTAL1 pin and XTAL2 pin This circuit has been made as a STC12C5620AD series
must be floated. microcontroller ISP download programming tool

Users in their target system, such as the P3.0/P3.1 through the RS-232 level shifter connected to the computer
after the conversion of ordinary RS-232 serial port to connect the system programming / upgrading client
software. If the user panel recommended no RS-232 level converter, should lead to a socket, with Gnd/P3.1/
P3.0/Vcc four signal lines, so that the user system can be programmed directly. Of course, if the six signal lines
can lead to Gnd/P3.1/P3.0/Vcc/P1.1/P1.0 as well, because you can download the program by P1.0/P1.1 ISP ban.
If you can Gnd/P3.1/P3.0/Vcc/P1.1/P1.0/Reset seven signal lines leads to better, so you can easily use "offline
download board (no computer)" .
ISP programming on the Theory and Application Guide to see "STC12C5620AD Series MCU Development /
Programming Tools Help"section. In addition, we have standardized programming download tool, the user can
then program into the goal in the above systems, you can borrow on top of it RS-232 level shifter connected to
the computer to download the program used to do. Programming a chip roughly be a few seconds, faster than the
ordinary universal programmer much faster, there is no need to buy expensive third-party programmer?.
d .
PC STC-ISP software downloaded from the website www.STCMCU.com
m i t e
Li
C U
M
S T C

Vcc
10F
1 C1+ Vcc 16 Vcc 2 Download user proced-
+
0.1F
3 ure to STC MCU by
2 V+ Gnd 15 Gnd
the software STC-ISP
programmer
PC_TxD(COM Pin3)
4 C2+ R1IN 13
0.1F Users are suggested hold this USB +5V
Vin
5 C2- R1OUT 12
interface on the system , which
USB+5V T1OUT R1IN GND System Power
6 V- T1IN 11 can be convenient to download
7 T2OUT T2IN 10
Reset USB1
.
8 R2IN R2OUT 9
U1-P1.0 Power On
d
U1-P1.1
mit e
MCU-VCC
U1-P3.0
than 20MHz, it is suggested not to use C1 and
Li
U1-P3.1
R1 replaced by 1K resistor connect to ground.
GND
But R/C reset circuit is
also suggest to reserve. Vcc 20 Pin
10K R1
Vcc
U
+
C
C1 1 RST VCC 20
1K 1K
M
2 P3.0/RxD ADC7/SCLK/P1.7 19
0.1F + 10F
C
<33pF
S T <33pF 5 XTAL1
6 P3.2/INT0
7 P3.3/INT1
ADC4/SS/P1.4 16
ADC3/P1.3 15
ADC2/P1.2 14
10 Gnd PWM0/PCA0/P3.7 11

(4MHz ~ 8MHz, manufacturing error), This circuit has been made as a STC12C5620AD series
XTAL1 and XTAL2 pin should be floated. microcontroller ISP download programming tool
are input from XTAL1 pin and XTAL2 pin
must be floated.

.
d
m i t e
Li
C U
M
S T C

Vcc PC/COM
STC3232,STC232,MAX232,SP232
10F
2
Download user proced-
1 C1+ Vcc 16 Vcc
+ 3 ure to STC MCU by
0.1F 2 V+ Gnd 15 Gnd the software STC-ISP
PC_RxD(COM Pin2) 5 programmer
3 C1- T1OUT 14
PC_TxD(COM Pin3)
4 C2+ R1IN 13
Vin
0.1F Users are suggested hold this USB +5V
5 C2- R1OUT 12
USB+5V T1OUT R1IN GND
System Power
6 V- T1IN 11 can be convenient to download
0.1F the users program online.
7 T2OUT T2IN 10
SW1
Reset
8 R2IN R2OUT 9 USB1
U1-P1.0
Power On
U1-P1.1
MCU-VCC
.
U1-P3.0
d
U1-P3.1
mit e
Vcc GND The determinant key scanning circuit.
Adding current limiting resistor n both Vcc
1K
Li
sides of dererminant is suggested
1 P2.2 VCC 32
1K
10F + C1 2 P2.3 P2.1 31
U
3 RST PCA2/PWM2/P2.0 30 0.1F 10F
+
C
1K
M
1K
1K
C
6 P0.0 ADC5/MOSI/P1.5 27
System
T
<33pF 1K
7 XTAL2 P0.3 26
S
Gnd
9 P3.2/INT0 ADC3/P1.3 24
1K
VCC
10K 10K 10K 10K
24C02(I2C bus OC doors 10K 10 P0.1 P0.2 23
open-drain circuits need 10K
11 P3.3/INT1 ADC2/P1.2 22
to add pull-up
resistors) A0
SCL 12 P3.4/T0/ECI CLKOUT1/ADC1/P1.1 21
A1
SDA 13 P3.5/T1/PCA1/PWM1 CLKOUT0/ADC0/P1.0 20
A2 24C02
14 P2.4/PCA3/PWM3 PWM0/PCA0/P3.7 19 CS
DC
SK
15 P2.5 P2.7 18
D/A PWM as D/A output DA ORG
16 Gnd P2.6 17 DO
10K 10K
104 93C46 (SPI bus OC doors open-drain circuits need to add pull-up resistors)
104 Vcc Vcc
3.3K
10K 10K Using A/D to key scan
4.7K
0V
3.3K more than 47pF
4.7K 3.3K
1/2 Vcc
3.3K
2/3 Vcc
I/O dirve NPN Transistor circuit I/O dirve PNP Transistor circuit
3.3K
3/4 Vcc

1.7 Pin Descriptions

Pin Number
MNEMONIC SOP-28/ SOP-20/DIP-20/ Description
LQFP-32 SOP-32
SKDIP-28 TSSOP-20
P0.0 2 6 common I/O port PORT0[0]
P1.0 common I/O port PORT1[0]
Analog to Digital Converter Input
ADC0
P1.0/ADC0/CLKOUT0 16 20 18 12 channel 0
d .
Programmable clock output of Timer/
e
CLKOUT0
t
couter 0
P1.1
m i common I/O port PORT1[1]
Li
ADC1
P1.1/ADC1/CLKOUT1 17 21 19 13 channel 1
CU
rogrammable clock output of Timer/
CLKOUT1
counter 1
M
P1.2/ADC2 18 22 20 14 Analog to Digital Converter Input
C
ADC2
channel 2
S T
P1.3/ADC3 20 24 21 15 Analog to Digital Converter Input
ADC3
channel 3
ADC4
P1.4/ADC4/SS 21 25 22 16 channel 4
slave-select signal of serial peripheral
SS
interface, which is active low.
P1.5/ADC5/MOSI 23 27 23 17 ADC5
channel 5
MOSI Master Out, Slave In signal
P1.6/ADC6/MISO 24 28 24 18 ADC5
channel 6
MISO Master In, Slave Out signal
ADC7
P1.7/ADC7/SCLK 25 29 25 19 channel 7
The clock signal of serial peripheral
SCLK
interface

Pin Number
MNEMONIC SOP-28/ SOP-20/DIP-20/ Description
LQFP-32 SOP-32
SKDIP-28 TSSOP-20
P2.0/PCA2/PWM2 26 30 26 PCA2 PCA module 2 Capture input
PWM2 PWM module 2 output
P2.1 27 31 27 common I/O port PORT2[1]
P2.4/PCA3/PWM3 10 14 12 PCA3 PCA module 3 Capture input
.
ed
mit
Li
P3.0/RxD 32 4 4 2
U
RxD Serial recive port
C
M
P3.1/TxD 1 5 5 3
TxD Serial transmit port
C
P3.2/INT0 5 9 8 6
T
INT0 External interrupt 0
S
P3.3/INT1 7 11 9 7
INT1 External interrupt 1
P3.4/T0/ECI 8 12 10 8 T0 Timer/counter 0 input
ECI PCA count input
T1 Timer/counter 1 input
P3.5/T1/PCA1/PWM1 9 13 11 9
PCA1 PCA module 1 Capture input
P3.7/PCA0/PWM0 15 19 17 11 PCA0 PCA module 0 Capture input
RST 31 3 3 1 Reset input
Input to the inverting oscillator amplifier. Receives
XTAL1 4 8 7 5 the external oscillator signal when an external
oscillator is used.
Output from the inverting amplifier. This pin should
XTAL2 3 7 6 4
be floated when an external oscillator is used.
VCC 28 32 28 20 Power
Gnd 12 16 14 10 circuit ground potential

1.8 Package Dimension Drawings

LQFP-32 OUTLINE PACKAGE
D (9mm)
D1(7mm)
VARIATIONS (ALL DIMENSIONS SHOWN IN MM)

1 SYMBOLS MIN. NOM MAX.
A 1.45 1.55 1.65
.
A1 0.01 - 0.21
ed
A2 1.35 1.40 1.45
t
E1
E
i
A3 - 0.254 -
Li m
D 8.80 9.00 9.20
D1 6.90 7.00 7.10
E 8.80 9.00 9.20
U
E1 6.90 7.00 7.10
C
b e 0.80
M
e 0.80mm
b 0.3 0.35 0.4
A
C
b1 0.31 0.37 0.43
T
c - 0.127 -
S
A2
L 0.43 - 0.71
Y S L1 0.90 1.00 1.10
R 0.1 - 0.25
R1 0.1 - -
R1
0 00 - 100
R
A3
NOTES:
GATE PLANE
1. All dimensions are in mm
A1
0 2. Dim D1 AND E1 does not include plastic

L
flash.
L1 Flash:Plastic residual around body edge after
de junk/singulation
3. Dim b does not include dambar protrusion/
b1 intrusion.
b 4. Plating thickness 0.05~0.015 mm.
WITH PLATING
c
BASE METAL

32-Pin Small Outline Package (SOP-32)

Dimensions in Millimeters
D (20.98mm)
E1
E
ed .
mit
z e
1.27mm
Li
C U COMMON DIMENSIONS
A2
A
M
(UNITS OF MEASURE = MILLMETER)
b
A1
SYMBOL MIN NOM MAX
C
A 2.465 2.515 2.565
S T b1
b
A1
A2
b
0.100
2.100
0.356
0.150
2.300
0.406
0.200
2.500
0.456
WITH PLATING b1 0.366 0.426 0.486
c
c - 0.254 -
D 20.88 20.98 21.08
E 9.980 10.180 10.380
BASE METAL
E1 7.390 7.500 7.600

R e 1.27
R1 L 0.700 0.800 0.900
L1 1.303 1.403 1.503
L2 L L2 - 0.274 -
L1
R - 0.200 -
R1 - 0.300 -
00 - 100
z - 0.745 -


Dimensions in Millimeters
D (17.95mm)
E1
E
d .
z e
i t e
1.27mm
Li m
U
A2
COMMON DIMENSIONS
C
A
M
b
A1
SYMBOL MIN NOM MAX
C
A 2.465 2.515 2.565
T
A1 0.100 0.150 0.200
S
b1
b
A2 2.100 2.300 2.500
b 0.356 0.406 0.456
b1 0.366 0.426 0.486
WITH PLATING
c c - 0.254 -
D 17.750 17.950 18.150
E 10.100 10.300 10.500
BASE METAL E1 7.424 7.500 7.624
e 1.27
L 0.764 0.864 0.964
R
L1 1.303 1.403 1.503
R1
L2 - 0.274 -
R - 0.200 -
L2 L R1 - 0.300 -
L1
00 - 100
z - 0.745 -

28-Pin Plastic Dual-In-line Package (SKDIP-28)

Dimensions in Inches and Millmeters
D (1390mil)
0
eA
E1
E
ed .
A A2
Li mit COMMON DIMENSIONS
CU
(UNITS OF MEASURE = INCH)
L SYMBOL MIN NOM MAX
M
A1
e b A - - 0.210
100mil b1
A1 0.015 - -
S T C A2
b
b1
0.125
-
-
0.130
0.018
0.060
0.135
-
-
D 1.385 1.390 1.40
E - 0.310 -
E1 0.283 0.288 0.293
e - 0.100 -
L 0.115 0.130 0.150
0 0 7 15
eA 0.330 0.350 0.370
UNIT: INCH 1inch = 1000mil


Dimensions in Inches and (Millimeters)
D (12.7mm)
E1
E
ed .
z e
i t
1.27mm
Li m COMMON DIMENSIONS
CU
SYMBOL MIN NOM MAX
A2
A
A 2.465 2.515 2.565
M
b
A1 0.100 0.150 0.200
A1
C
A2 2.100 2.300 2.500
S T
b1 0.366 0.426 0.486
b1
b b 0.356 0.406 0.456
c 0.234 - 0.274
WITH PLATING
c1 0.224 0.254 0.274
c c1
D 12.500 12.700 12.900
E 10.206 10.306 10.406
E1 7.450 7.500 7.550
BASE METAL
e 1.270

L 0.800 0.864 0.900
R1
R
L1 1.303 1.403 1.503
L2 - 0.274 -
L2
R - 0.300 -
L
R1 - 0.200 -
L1
0 0
- 100
z - 0.660 -

20-Pin Plastic Dual Inline Package (DIP-20)

Dimensions in Inches
D (1026mil)
C
0

eA
E1
E
S 0.120
ed .
COMMON DIMENSIONS
mit
A A2
(UNITS OF MEASURE = INCH)
Li
L
SYMBOL MIN NOM MAX
A1
e b A - - 0.175
U
100mil A1 0.015 - -
C
b1
M
A2 0.125 0.13 0.135
b 0.016 0.018 0.020
C
b1 0.058 0.060 0.064
S T C
D
E
0.008
1.012
0.290
0.010
1.026
0.300
0.11
1.040
0.310
E1 0.245 0.250 0.255
e 0.090 0.100 0.110
L 0.120 0.130 0.140
0 0 - 15
eA 0.355 0.355 0.375
S - - 0.075
UNIT: INCH 1 inch = 1000 mil

1.9 STC12C5620AD series MCU naming rules
STC12 xx 56 xx xx -- 35 x - xxxx xx
Pin Number
e.g. 20, 28, 32
Package type
e.g. SOP, LQFP, DIP, SKDIP, TSSOP
Temperature range
I : Industrial, -40-85
C : Commercial, 0-70
ed .
Operating frequency
t
i
35 : Up to 35MHz
Li m
AD : Have ADC function, PWM and internal EEPROM
No words: no ADC function, but have PWM and internal EEPROM
Program space
C U
M
30:30KB 28:28KB 20:20KB 16:16KB 08:8KB 04:4KB
768 Bytes RAM, 4 channels PCA/PWM
S T C Operating Voltage
C : 5.5V~3.3V
LE : 2.2V~3.6V
STC 1T Series 8051 MCU

Speed is 8~12 times the traditional 8051

1.10 Global Unique Identification Number (ID)

STC 1T MCU 12C5620AD series, each MCU has a unique identification number (ID). User can use MOV @Ri
instruction read RAM unit F1~F7 to get the ID number after power on. If users need to the unique identification
number to encrypt their procedures, detecting the procedures not be illegally modified should be done first.
//The following example program written by C language is to read internal ID number

/*----------------------------------------------------------------------------------*/
/* --- STC MCU International Limited -------------------------------------*/
/* --- Mobile: 13922809991 ------------------------------------------------ */
/* --- Fax: 0755-82905966 ------------------------------------------------- */
.
/* --- Tel: 0755-82948409 -------------------------------------------------- */
ed
mit
/* --- Web: www.STCMCU.com --------------------------------------------*/
/* If you want to use the program or the program referenced in the --*/
Li
/* article, please specify in which data and procedures from STC --*/
/*---------------------------------------------------------------------------------*/
#include<reg51.h>
#include<intrins.h>
C U
M
sfr ISP_CONTR = 0xE7;
C
sbit MCU_Start_Led = P1^7;
T
//unsigned char self_command_array[4] = {0x22,0x33,0x44,0x55};
void
S
#define Self_Define_ISP_Download_Command
#define RELOAD_COUNT
serial_port_initial();
0xfb
0x22
//18.432MHz,12T,SMOD=0,9600bps
void send_UART(unsigned char);

void UART_Interrupt_Receive(void);
void soft_reset_to_ISP_Monitor(void);
void delay(void);
void display_MCU_Start_Led(void);
void main(void)
{
unsigned char i = 0;
unsigned char j = 0;
unsigned char idata *idata_point;

serial_port_initial(); //initialize serial port

// display_MCU_Start_Led(); //MCU begin to run when LED is be lighted
// send_UART(0x34);
// send_UART(0xa7);

idata_point = 0xF1;
for(j=0;j<=6; j++)
{
i = *idata_point;
send_UART(i);
idata_point++;
}
t ed .
i
while(1);
m
}
void serial_port_initial()
Li
CU
{
SCON = 0x50; //0101,0000 8-bit variable baud rateNo parity
M
TMOD = 0x21; //0011,0001 Timer1 as 8-bit auto-reload Timer
TH1 = RELOAD_COUNT; //Set the auto-reload parameter
T C
TL1 = RELOAD_COUNT;
S
TR1 = 1;
ES = 1;
EA = 1;
}
void send_UART(unsigned char i)

{
ES = 0;
TI = 0;
SBUF = i;
while(TI ==0);
TI = 0;
ES = 1;
}
void UART_Interrupt_Receive(void) interrupt 4

{
unsigned char k = 0;
if(RI==1)
{
RI = 0;
k = SBUF;

if(k==Self_Define_ISP_Download_Command) //Self-define download command
{
delay(); //just delay 1 second
delay();
soft_reset_to_ISP_Monitor(); //Soft rese to ISP Monitor
}
send_UART(k);
}
else
{
TI = 0;
}
}
ed .
mit
void soft_reset_to_ISP_Monitor(void)
{
Li
ISP_CONTR = 0x60; //0110,0000 Soft rese to ISP Monitor
}
C U
void delay(void)
M
{
unsigned int j = 0;
unsigned int g = 0;
C
for(j=0;j<5;j++)
S T
{
for(g=0;g<60000;g++)
{
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
}
}
}
void display_MCU_Start_Led(void)
{
for(i=0;i<3;i++)
{
MCU_Start_Led = 0;
delay();
MCU_Start_Led = 1;
delay();
MCU_Start_Led = 0;
}
}

Chapter 2. Clock, Power Management and Reset

2.1 Clock
2.1.1 On-Chip R/C Clock and External Crystal/Clcok are Optional in STC-ISP.exe
STC12C5620AD series is STC 1T MCU whose system clock is compatible with traditional 8051 MCU.
There are two clock sources available for STC12C5620AD. One is the clock from crystal oscillator and the
other is from internal simple RC oscillator. The internal built-in RC oscillator can be used to replace the external
crystal oscillator in the application which doesn't need an exact system clock. On-chip R/C clock is selected first
in STC-ISP Writer/Programmer because the manufacturer's selection is on-chip R/C clock for STC12C5604AD,
STC12C5608AD, STC12C5612AD, etc. But for STC12C5616AD, STC12C5620AD, STC12C5624AD,
STC12C5628AD, STC12C5630AD and so on, External crystal/clock is selected first in STC-ISP Writer/
d .
Programmer because the manufacturer's selection is external crystal/clock.
i t e
To enable the built-in oscillator, user should enable the option "On-Chip R/C Clock" by STC-ISP Writer/
m
Programmer for STC12C5616AD, STC12C5620AD, STC12C5624AD, STC12C5628AD, STC12C5630AD
Li
etc. To enable the external crystal oscillator, user should enable the option "External Crystal/Clock" by STC-ISP
Writer/Programmer for STC12C5604AD, STC12C5608AD, STC12C5612AD, etc.
C U
M
S T C
After next-power up/ cold reset
MCU clock can be:
1. On-Chip R/C Clock
2. External Crystal/Clock

2.1.2 Divider for System Clock

A clock divider(CLK_DIV) is designed to slow down the operation speed of STC12C5620AD, to save
the operating power dynamically. User can slow down the MCU by means of writing a non-zero value to the
CLKS[2:0] bits in the CLK_DIV register. This feature is especially useful to save power consumption in idle
mode as long as the user changes the CLKS[2:0] to a non-zero value before entering the idle mode.
CLK_DIV register (Clock Divider)

SFR Name SFR Address bit B7 B6 B5 B4 B3 B2 B1 B0
CLK_DIV C7H name - - - - - CLKS2 CLKS1 CLKS0
B2-B0 (CLKS2-CLKS0) :
000 External crystal/clock or On-Chip R/C clock is not divided (default state)
d .
001 External crystal/clock or On-Chip R/C clock is divided by 2.
mit e
Li
U
C
M
C
Not-divided 000
S T 2
4
001
010
8 011 System Clock

On-Chip R/C Clock
(To CPU and peripherals)
External crystal/clock
16 100
32 101
64 110
128 111
CLKS2,CLKS1,CLKS0
Clock Structure

2.1.3 How to Know Internal RC Oscillator frequency(Internal clock frequency)

STC 1T MCU 12C5620AD series in addition to traditional external clock, but also the option of using the internal
RC oscillator clock source. If select internal RC oscillator, external crystal can be saved. XTAL1 and XTAL2
floating. Relatively large errors due to internal clock, so high requirements on the timing or circumstances have
serial communication is not recommended to use the internal oscillator. User can use MOV @Ri instruction
read RAM unit FC~FF to get the internal oscillator frequency of the factory and read RAM unit F8~FB to get
internal oscillator frequency of last used to download programs within the internal oscillator after power on.
//The following example program written by C language is to read internal R/C clock
frequency
/*----------------------------------------------------------------------------------*/
.
ed
/* --- Mobile: 13922809991 ------------------------------------------------ */
i t
/* --- Fax: 0755-82905966 ------------------------------------------------- */
Li m
/* --- Tel: 0755-82948409 -------------------------------------------------- */
C U
/* article, please specify in which data and procedures from STC --*/
M
/*---------------------------------------------------------------------------------*/
#include<reg51.h>
C
#include<intrins.h>
T
sfr ISP_CONTR = 0xE7;
sbit
S
MCU_Start_Led = P1^7;
//unsigned char self_command_array[4] = {0x22,0x33,0x44,0x55};
#define Self_Define_ISP_Download_Command 0x22
#define RELOAD_COUNT 0xfb //18.432MHz,12T,SMOD=0,9600bps
void serial_port_initial();
void delay(void);
void main(void)
{
unsigned char idata *idata_point;

serial_port_initial(); //initialize serial port

// display_MCU_Start_Led(); //MCU begin to run when LED is be lighted
// send_UART(0x34);
// send_UART(0xa7);

idata_point = 0xFC;
for(j=0;j<=3;j++)
{
i = *idata_point;
send_UART(i);
idata_point++;
}
ed .
mit
while(1);
}
void serial_port_initial()
{
Li
SCON = 0x50;
C U //0101,0000 8-bit variable baud rateNo parity
M
TMOD = 0x21; //0011,0001 Timer1 as 8-bit auto-reload Timer
TH1 = RELOAD_COUNT; //Set the auto-reload parameter
C
TL1 = RELOAD_COUNT;
T
TR1 = 1;
}

ES
S = 1;
EA = 1;

{
ES = 0;
TI = 0;
SBUF = i;
while(TI ==0);
TI = 0;
ES = 1;
}
void UART_Interrupt_Receive(void) interrupt 4

{
if(RI==1)
{
RI = 0;
k = SBUF;

if(k==Self_Define_ISP_Download_Command) //Self-define download command

{
delay(); //just delay 1 second
delay();
soft_reset_to_ISP_Monitor(); //Soft rese to ISP Monitor
}
send_UART(k);
}
else
{
TI = 0;
}
}
t ed .
i
{
Li m
ISP_CONTR = 0x60; //0110,0000 Soft rese to ISP Monitor
}
U
void delay(void)
C
{
M
unsigned int j = 0;
unsigned int g = 0;
C
for(j=0;j<5;j++)
T
{
S
for(g=0;g<60000;g++)
{
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
}
}
}
{
for(i=0;i<3;i++)
{
MCU_Start_Led = 0;
delay();
MCU_Start_Led = 1;
delay();
MCU_Start_Led = 0;
}
}

2.1.4 Programmable Clock Output

STC12C5620AD series MCU have two channel programmable clock outputs, they are Timer 0 programmable
clock output CLKOUT0(P1.0) and Timer 1 programmable clock output CLKOUT1(P1.1).
There are some SFRs about programmable clock output as shown below.
Value after
Symbol Description Address Bit Address and Symbol Power-on or
MSB LSB Reset
AUXR Auxiliary register 8EH T0x12 T1x12 UART_M0x6 EADCI ESPI ELVDI - - 0000 00xxB
CLK_Output PCAWAKEUP RXD_PIN_IE T1_PIN_IE T0_PIN_IE - - T1CLKO T0CLKO
Power down
WAKE_CLKO 8FH 0000 xx00B
Wake-up control
register
The satement (used in C language) of Special function registers AUXR/WAKE_CLKO:
ed .
mit
sfr AUXR = 0x8E; //The address statement of Special function register AUXR
Li
sfr WAKE_CLKO = 0x8F; //The address statement of SFR WAKE_CLKO
The satement (used in Assembly language) of Special function registers AUXR/WAKE_CLKO:
U
AUXR EQU 0x8E ;The address statement of Special function register AUXR
WAKE_CLKO EQU 0x8F
M C ;The address statement of SFR WAKE_CLKO

1. AUXR: Auxiliary register (Non bit-addressable)
C
SFR name Address bit B7 B6 B5 B4 B3 B2 B1 B0
AUXR
S
8EH
T name T0x12 T1x12 UART_M0x6 EADCI
T0x12 : Timer 0 clock source bit.
ESPI
0 : The clock source of Timer 0 is SYSclk/12. It will compatible to the traditional 80C51 MCU
ELVDI
1 : The clock source of Timer 0 is SYSclk/1. It will drive the T0 faster than a traditional 80C51 MCU
- -

UART_M0x6 : Baud rate select bit of UART1 while it is working under Mode-0
0 : The baud-rate of UART in mode 0 is SYSclk/12.
EADCI : Enable/Disable interrupt from A/D converter
0 : (default) Inhibit the ADC functional block to generate interrupt to the MCU
1 : Enable the ADC functional block to generate interrupt to the MCU
ESPI : Enable/Disable interrupt from Serial Peripheral Interface (SPI)
0 : (default)Inhibit the SPI functional block to generate interrupt to the MCU
1 : Enable the SPI functional block to generate interrupt to the MCU
ELVDI : Enable/Disable interrupt from low-voltage sensor
0 : (default)Inhibit the low-voltage sensor functional block to generate interrupt to the MCU
1 : Enable the low-voltage sensor functional block to generate interrupt to the MCU
2. WAKE_CLKO: CLK_Output Power down Wake-up control register (Non bit-Addressable)

WAKE_CLKO 8FH name PCAWAKEUP RXD_PIN_IE T1_PIN_IE T0_PIN_IE - - T1CLKO T0CLKO
PCAWAKEUP: When set and the associated-PCA interrupt control registers is configured correctly, the CEXn pin
of PCA function is enabled to wake up MCU from power-down state.
RXD_PIN_IE: When set and the associated-UART interrupt control registers is configured correctly, the RXD
pin (P3.0) is enabled to wake up MCU from power-down state.
T1_PIN_IE : When set and the associated-Timer1 interrupt control registers is configured correctly, the T1 pin
(P3.5) is enabled to wake up MCU from power-down state.
.
T1CKLO :
t ed
When set, P1.1 is enabled to be the clock output of Timer 1. The clock rate is Timer 1overflow rate
i
m
divided by 2.
Li
T0CKLO : When set, P1.0 is enabled to be the clock output of Timer 0. The clock rate is Timer 0overflow rate
divided by 2.
C U
2.1.4.1 Timer 0 Programmable Clock-out on P1.0
M
SYSclk
S T C
12
AUXR.7/T0x12=0
TF0 Interrupt
1 Toggle
AUXR.7/T0x12=1
C/T=0 TL0
C/T=1 (8 Bits)
CLKOUT0
T0 Pin
control
TR0 P1.0
GATE T0CLKO
TH0
INT0 (8 Bits)
Timer/Counter 0 Mode 2: 8-Bit Auto-Reload
STC12C5620AD is able to generate a programmable clock output on P1.0. When T0CLKO/

WAKE_CLKO.0 bit in WAKE_CLKO SFR is set, T0 timer overflow pulse will toggle P1.0 latch to
generate a 50% duty clock. The frequency of clock-out = T0 overflow rate/2.
If C/T (TMOD.2) = 0, Timer/Counter 0 is set for Timer operation (input from internal system clock), the
Frequency of clock-out is as following :
(SYSclk) / (256 TH0) / 2, when AUXR.7 / T0x12=1
or (SYSclk / 12) / (256 TH0) / 2 , when AUXR.7 / T0x12=0
If C/T (TMOD.2) = 1, Timer/Counter 0 is set for Conter operation (input from external P3.4/T0 pin), the
T0_Pin_CLK / (256-TH0) / 2

2.1.4.2 Timer 1 Programmable Clock-out on P1.1
AUXR.6/T1x12=0
12 TF1 Interrupt
SYSclk
1 Toggle
AUXR.6/T1x12=1 C/T=0 TL1
C/T=1 (8 Bits) CLKOUT1
T1 Pin control
P1.1
TR1
GATE TH1 T1CLKO
(8 Bits)
INT1
ed .
mit
STC12C5620AD is able to generate a programmable clock output on P1.1. When T1CLKO/WAKE_CLKO.1 bit
in WAKE_CLKO SFR is set, T1 timer overflow pulse will toggle P1.1 latch to generate a 50% duty clock. The
Li
frequency of clock-out = T1 overflow rate/2.
U
C
M
S T C
T1_Pin_CLK / (256-TH1) / 2

2.2 Power Management Modes

The STC12C5620AD core has three software programmable power management mode: slow-down, idle
and stop/power-down mode. The power consumption of STC12C5620AD series is about 2.7mA~7mA in
normal operation, while it is lower than 0.1uA in stop/power-down mode and 1.8mA in idle mode.
Slow-down mode is controlled by clock divider register(CLK_DIV). Idle and stop/power-down is managed
by the corresponding bit in Power control (PCON) register which is shown in below.
PCON register (Power Control Register)
PCON 87H name SMOD SMOD0 LVDF POF GF1 GF0 PD IDL
SMOD : Double baud rate of UART interface
0 Keep normal baud rate when the UART is used in mode 1,2 or 3.
d .
1 Double baud rate bit when the UART is used in mode 1,2 or 3.
t e
SMOD0 : SM0/FE bit select for SCON.7; setting this bit will set SCON.7 as Frame Error function. Clearing it to
i
set SCON.7 as one bit of UART mode selection bits.

POF
Li m
LVDF : Pin Low-Voltage Flag. Once low voltage condition is detected (VCC power is lower than LVD
voltage), it is set by hardware (and should be cleared by software).
: Power-On flag. It is set by power-off-on action and can only cleared by software.
C U
Practical application: if it is wanted to know which reset the MCU is used, see the following figure.
M
S T C In initializtion program,
judge whether POF/PCON.4
have been set or not
POF=0, No
POF=1, cold boot

Yes Power-On Reset external manual reset
or WDT reset
or software reset
Clear POF/PCON.4 or others
GF1,GF0: General-purposed flag 1 and 0

PD : Stop Mode/Power-Down Select bit..
Setting this bit will place the STC12C5620AD MCU in Stop/Power-Down mode. Stop/Power-Down
mode can be waked up by external interrupt. Because the MCU s internal oscillator stopped in Stop/
Power-Down mode, CPU, Timers, UARTs and so on stop to run, only external interrupt go on to work.
The following pins can wake up MCU from Stop/Power-Down mode: INT0/P3.2, INT1/P3.3, T0/P3.4,
T1/P3.5, RxD/P3.0, PCA0/PWM0/P3.7, PCA1/PWM1/P3.5, PCA2/PWM2/P2.0, PCA3/PWM3/P2.4.
IDL : Idle mode select bit.

Setting this bit will place the STC12C5620AD in Idle mode. only CPU goes into Idle mode. (Shuts off clock to
CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active.) The following pins
can wake up MCU from Idle mode: INT0/P3.2, INT1/P3.3, T0/P3.4, T1/P3.5, RxD/P3.0. Besides, Timer0 and
Timer1 and UARTs interrupt also can wake up MCU from idle mode

2.2.1 Slow Down Mode

A divider is designed to slow down the clock source prior to route to all logic circuit. The operating frequency of
internal logic circuit can therefore be slowed down dynamically , and then save the power.
User can slow down the MCU by means of writing a non-zero value to the CLKS[2:0] bits in the CLK_DIV
register. This feature is especially useful to save power consumption in idle mode as long as the user changes the
CLKS[2:0] to a non-zero value before entering the idle mode.
CLK_DIV register (Clock Divider)

CLK_DIV C7H name - - - - - CLKS2 CLKS1 CLKS0
B2-B0 (CLKS2-CLKS0) :
d .
000 External crystal/clock or On-Chip R/C clock is not divided (default state)
mit e
Li
U
C
M
S T C Not-divided 000
2 001
4 010
8 011 System Clock

On-Chip R/C Clock
(To CPU and peripherals)
External crystal/clock
16 100
32 101
64 110
128 111
CLKS2,CLKS1,CLKS0
Clock Structure

2.2.2 Idle Mode

An instruction that sets IDL/PCON.0 causes that to be the last instruction executed before going into the idle
mode, the internal clock is gated off to the CPU but not to the interrupt, timer, PCA, ADC, SPI, WDT and serial
port functions. The PCA can be programmed either to pause or continue operating during Idle. The CPU status is
preserved in its entirety: the RAM, Stack Pointer, Program Counter, Program Status Word, Accumulator, and all
other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was
activated. Idle mode leaves the peripherals running in order to allow them to wake up the CPU when an interrupt
is generated. Timer 0, Timer 1, PWM timer and UART will continue to function during Idle mode.
There are two ways to terminate the idle. Activation of any enabled interrupt will cause IDL/PCON.0 to be
cleared by hardware, terminating the idle mode. The interrupt will be serviced, and following RETI, the next
instruction to be executed will be the one following the instruction that put the device into idle.
.
The flag bits (GF0 and GF1) can be used to give art indication if an interrupt occurred during normal operation
t ed
or during Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is
i
terminated by an interrupt, the interrupt service routine can examine the flag bits.
Li m
The other way to wake-up from idle is to pull RESET high to generate internal hardware reset.Since the clock
oscillator is still running, the hardware reset neeeds to be held active for only two machine cycles(24 oscillator
U
periods) to complete the reset.
M C
S T C

2.2.3 Stop / Power Down (PD) Mode and Demo Program (C and ASM)
An instruction that sets PD/PCON.1 cause that to be the last instruction executed before going into the Power-
Down mode. In the Power-Down mode, the on-chip oscillator and the Flash memory are stopped in order to
minimize power consumption. Only the power-on circuitry will continue to draw power during Power-Down.
The contents of on-chip RAM and SFRs are maintained. The power-down mode can be woken-up by RESET
pin, external interrupt INT0 ~ INT1, RXD pin, T0 pin, T1 pin and PCA input pinsPWM pins and PWM pins.
When it is woken-up by RESET, the program will execute from the address 0x0000. Be carefully to keep RESET
pin active for at least 10ms in order for a stable clock. If it is woken-up from I/O, the CPU will rework through
jumping to related interrupt service routine. Before the CPU rework, the clock is blocked and counted until 32768
in order for denouncing the unstable clock. To use I/O wake-up, interrupt-related registers have to be enabled
and programmed accurately before power-down is entered. Pay attention to have at least one NOP instruction
subsequent to the power-down instruction if I/O wake-up is used. When terminating Power-down by an interrupt,
the wake up period is internally timed. At the negative edge on the interrupt pin, Power-Down is exited, the
.
oscillator is restarted, and an internal timer begins counting. The internal clock will be allowed to propagate and
ed
the CPU will not resume execution until after the timer has reached internal counter full. After the timeout period,
mit
the interrupt service routine will begin. To prevent the interrupt from re-triggering, the interrupt service routine
Li
should disable the interrupt before returning. The interrupt pin should be held low until the device has timed out
and begun executing. The user should not attempt to enter (or re-enter) the power-down mode for a minimum of 4
us until after one of the following conditions has occured: Start of code execution(after any type of reset), or Exit
U
from power-down mode.
M C
The following circuit can timing wake up MCU from power down mode when external interrupt sources do not
exist
I/O
S T C 300 I I
INTx
0.1uF C1 5M
R1
Operation step:
1. I/O ports are first configured to push-pull output(strong pull-up) mode
2. Writen 1s into ports I/O ports
3. the above circuit will charge the capacitor C1
4. Writen 0s into ports I/O ports, MCU will go into power-down mode
5. The above circuit will discharge. When the electricity of capacitor C1 has been discharged less than
0.8V, external interrupt INTx pin will generate a falling edge and wake up MCU from power-down
mode automatically.

The following example C program demostrates that power-down mode be woken-up by external interrupt .
/*--------------------------------------------------------------------------------*/
/* --- STC MCU International Limited -----------------------------------*/
/* --- STC 1T Series MCU wake up Power-Down mode Demo ------*/
/* --- Mobile: (86)13922809991 ------------------------------------------*/
/* --- Fax: 86-755-82905966 ----------------------------------------------*/
/* --- Tel: 86-755-82948412 -----------------------------------------------*/
/* --- Web: www.STCMCU.com -----------------------------------------*/
/* If you want to use the program or the program referenced in the */
/* article, please specify in which data and procedures from STC */
/*-------------------------------------------------------------------------------*/
#include <reg51.h>
#include <intrins.h>
t ed .
i
sbit Begin_LED = P1^2; //Begin-LED indicator indicates system start-up
Li m
unsigned char Is_Power_Down = 0; //Set this bit before go into Power-down mode
sbit Is_Power_Down_LED_INT0 = P1^7; //Power-Down wake-up LED indicator on INT0
sbit Not_Power_Down_LED_INT0 = P1^6; //Not Power-Down wake-up LED indicator on INT0
U
sbit Is_Power_Down_LED_INT1 = P1^5; //Power-Down wake-up LED indicator on INT1
C
sbit Not_Power_Down_LED_INT1 = P1^4; //Not Power-Down wake-up LED indicator on INT1
sbit Power_Down_Wakeup_Pin_INT0
M = P3^2; //Power-Down wake-up pin on INT0
C
sbit Power_Down_Wakeup_Pin_INT1 = P3^3; //Power-Down wake-up pin on INT1
T
sbit Normal_Work_Flashing_LED = P1^3; //Normal work LED indicator
S
void Normal_Work_Flashing (void);
void INT_System_init (void);
void INT0_Routine (void);
void INT1_Routine (void);
void main (void)

{
unsigned char wakeup_counter = 0;
//clear interrupt wakeup counter variable wakeup_counter
Begin_LED = 0; //system start-up LED
INT_System_init ( ); //Interrupt system initialization
while(1)
{
P2 = wakeup_counter;
wakeup_counter++;
for(j=0; j<2; j++)
{
Normal_Work_Flashing( ); //System normal work
}

Is_Power_Down = 1; //Set this bit before go into Power-down mode
PCON = 0x02; //after this instruction, MCU will be in power-down mode
//external clock stop
_nop_( );
_nop_( );
_nop_( );
_nop_( );
}
}
void INT_System_init (void)
{
IT0 = 0; /* External interrupt 0, low electrical level triggered */
.
// IT0 = 1; /* External interrupt 0, negative edge triggered */
ed
EX0 = 1; /* Enable external interrupt 0
mit
IT1 = 0; /* External interrupt 1, low electrical level triggered */
Li
// IT1 = 1; /* External interrupt 1, negative edge triggered */
EX1 = 1; /* Enable external interrupt 1
EA = 1; /* Set Global Enable bit
C U
}
M
void INT0_Routine (void) interrupt 0
{
C
if (Is_Power_Down)
T
{
S
//Is_Power_Down ==1; /* Power-Down wakeup on INT0 */
Is_Power_Down = 0;
Is_Power_Down_LED_INT0 = 0;
/*open external interrupt 0 Power-Down wake-up LED indicator */
while (Power_Down_Wakeup_Pin_INT0 == 0)
{
/* wait higher */
}
/* close external interrupt 0 Power-Down wake-up LED indicator */
}
else
{
Not_Power_Down_LED_INT0 = 0; /* open external interrupt 0 normal work LED */
while (Power_Down_Wakeup_Pin_INT0 ==0)
{
/* wait higher */
}
Not_Power_Down_LED_INT0 = 1; /* close external interrupt 0 normal work LED */
}
}

void INT1_Routine (void) interrupt 2

{
if (Is_Power_Down)
{
//Is_Power_Down ==1; /* Power-Down wakeup on INT1 */
Is_Power_Down = 0;
Is_Power_Down_LED_INT1= 0;
/*open external interrupt 1 Power-Down wake-up LED indicator */
while (Power_Down_Wakeup_Pin_INT1 == 0)
{
/* wait higher */
}
d .
/* close external interrupt 1 Power-Down wake-up LED indicator */
i t e
}
m
else
Li
{
Not_Power_Down_LED_INT1 = 0; /* open external interrupt 1 normal work LED */
U
while (Power_Down_Wakeup_Pin_INT1 ==0)
C
{
M
/* wait higher */
}
C
Not_Power_Down_LED_INT1 = 1; /* close external interrupt 1 normal work LED */
S T
}
}
void delay (void)

{
unsigned int j = 0x00;
unsigned int k = 0x00;
for (k=0; k<2; ++k)
{
for (j=0; j<=30000; ++j)
{
_nop_( );
_nop_( );
_nop_( );
_nop_( );
_nop_( );
_nop_( );
_nop_( );
_nop_( );
}
}
}

void Normal_Work_Flashing (void)

{
Normal_Work_Flashing_LED = 0;
delay ( );
Normal_Work_Flashing_LED = 1;
delay ( );
}
The following program also demostrates that power-down mode or idle mode be woken-up by external
interrupt, but is written in assembly language rather than C languge.
/*--------------------------------------------------------------------------------*/
.
ed
/* --- STC 1T Series MCU wake up Power-Down mode Demo ------*/
mit
/* --- Mobile: (86)13922809991 ------------------------------------------*/
Li
/* --- Fax: 86-755-82905966 ----------------------------------------------*/
/* --- Tel: 86-755-82948412 -----------------------------------------------*/
U
C
M
/*-------------------------------------------------------------------------------*/
;**************************************************************
C
;Wake Up Idle and Wake Up Power Down

S T
;**************************************************************
ORG
AJMP MAIN
ORG
0000H
0003H
int0_interrupt:
CLR P1.7 ;open P1.7 LED indicator
ACALL delay ;delay in order to observe
CLR EA ;clear global enable bit, stop all interrupts
RETI
ORG 0013H
int1_interrupt:
CLR P1.6 ;open P1.6 LED indicator
ACALL delay ;;delay in order to observe
CLR EA ;clear global enable bit, stop all interrupts
RETI
ORG 0100H
delay:
CLR A
MOV R0, A
MOV R1, A
MOV R2, #02

delay_loop:
DJNZ R0, delay_loop
DJNZ R1, delay_loop
DJNZ R2, delay_loop
RET
main:
MOV R3, #0 ;P1 LED increment mode changed
;start to run program
main_loop:
MOV A, R3
CPL A
MOV P1, A
.
ACALL delay
ed
INC R3
MOV A, R3
m i t
Li
SUBB A, #18H
JC main_loop
MOV P1, #0FFH ;close all LED, MCU go into power-down mode
CLR IT0
C U ;low electrical level trigger external interrupt 0
M
; SETB IT0 ;negative edge trigger external interrupt 0
SETB EX0 ;enable external interrupt 0
C
CLR IT1 ;low electrical level trigger external interrupt 1
S T
; SETB IT1 ;negative edge trigger external interrupt 1
SETB EX1 ;enable external interrupt 1
SETB EA ;set the global enable
;if don't so, power-down mode cannot be wake up
;MCU will go into idle mode or power-down mode after the following instructions
MOV PCON, #00000010B ;Set PD bit, power-down mode (PD = PCON.1)
; NOP
; NOP
; NOP
; MOV PCON, #00000001B ;Set IDL bit, idle mode (IDL = PCON.0)
MOV P1, #0DFH ;1101,1111
NOP
NOP
NOP
WAIT1:
SJMP WAIT1 ;dynamically stop
END

2.3 RESET Sources

In STC12C5620AD, there are 5 sources to generate internal reset. They are RST pin reset, software reset, On-
chip power-on-reset(if delay 200mS after power-on reset, the reset mode is On-chip MAX810 POR timing delay
which actully add 200mS delay after power-on reset), internal low-voltage detection reset and Watch-Dog-Timer
reset.
2.3.1 RESET Pin

External RST pin reset accomplishes the MCU reset by forcing a reset pulse to RST pin from external.
Asserting an active-high signal and keeping at least 24 cycles plus 10us on the RST pin generates a
reset. If the signal on RST pin changed active-low level, MCU will end the reset state and start to run
.
from the 0000H of user procedures.
ed
2.3.2 Software RESET
Li mit
Writing an 1 to SWRST bit in ISP_CONTR register will generate a internal reset.
ISP_CONTR: ISP/IAP Control Register
C U
M
ISP_CONTR E7H name ISPEN SWBS SWRST CMD_FAIL - WT2 WT1 WT0
T C
ISPEN : ISP/IAP operation enable.
S
0 : Global disable all ISP/IAP program/erase/read function.
1 : Enable ISP/IAP program/erase/read function.
SWBS: software boot selection control bit
0 : Boot from main-memory after reset.
1 : Boot from ISP memory after reset.
SWRST: software reset trigger control.
0 : No operation
1 : Generate software system reset. It will be cleared by hardware automatically.
CMD_FAIL: Command Fail indication for ISP/IAP operation.
0 : The last ISP/IAP command has finished successfully.
1 : The last ISP/IAP command fails. It could be caused since the access of flash memory was inhibited.
;Software reset from user appliction program area (AP area) and switch to AP area to run program
MOV ISP_CONTR, #00100000B ;SWBS = 0(Select AP area), SWRST = 1(Software reset)
;Software reset from system ISP monitor program area (ISP area) and switch to AP area to run program
MOV ISP_CONTR, #00100000B ;SWBS = 0(Select AP area), SWRST = 1(Software reset)
;Software reset from user appliction program area (AP area) and switch to ISP area to run program
MOV ISP_CONTR, #01100000B ;SWBS = 1(Select ISP area), SWRST = 1(Software reset)
;Software reset from system ISP monitor program area (ISP area) and switch to ISP area to run program
MOV ISP_CONTR, #01100000B ;SWBS = 1(Select ISP area), SWRST = 1(Software reset)
This reset is to reset the whole system, all special function registers and I/O prots will be reset to the initial value

2.3.3 Power-On Reset (POR)

When VCC drops below the detection threshold of POR circuit, all of the logic circuits are reset.
When VCC goes back up again, an internal reset is released automatically after a delay of 32768 clocks. The
nominal POR detection threshold is around 1.9V for 3V device and 3.3V for 5V device.
The Power-On flag, POF/PCON.4, is set by hardware to denote the VCC power has ever been less than the POR
voltage. And, it helps users to check if the start of running of the CPU is from power-on or from hardware reset
(RST-pin reset), software reset or Watchdog Timer reset. The POF bit should be cleared by software.
t ed .
2.3.4 MAX810 power-on-Reset delay
m i
Li
There is another on-chip POR delay circuit s integrated on STC12C5620AD. This circuit is MAX810sepcial
reset circuit and is controlled by configuring STC-ISP Writter/Programmer shown in the next figure. MAX810
U
special reset circuit just add 200mS extra reset-delay-time after power-up reset. So it is another power-on reset.
M C
S T C

2.3.5 Internal Low Voltage Detection Reset

Besides the POR voltage, there is a higher threshold voltage: the Low Voltage Detection (LVD) voltage for
STC12C5620AD series. When the VCC power drops down to the LVD voltage, the Low voltage Flag, LVDF
bit (PCON.5), will be set by hardware. (Note that during power-up, this flag will also be set, and the user should
clear it by software for the following Low Voltage detecting.) This flag can also generate an interrupt if the enable
bit of LVD interrupt is set to 1.
The threshold voltage of STC12C5620AD built-in low voltage detection reset is optional in STC-ISP Writer/
Programmer. The detection voltage of 5V MCU of STC12C5620AD series is optional between 3.7V and 3.3V as
shown in following figure.
ed .
Li mit
C U
M
S T C
The detection voltage of 3V MCU of STC12LE5620AD series is optional between 2.4V and 2.0V as shown in
following figure.

Some SFRs related to Low voltage detection as shown below.

Reset
Mnemonic Add Name B7 B6 B5 B4 B3 B2 B1 B0 Value
PCON 87H Power Control SMOD SMOD0 LVDF POF GF1 GF0 PD IDL 0011,0000
AUXR 8EH Auxiliary Register T0x12 T1x12 UART_M0x6 EADCI ESPI ELVDI - - 0000,00xx
IE A8H Interrupt Enable EA EPCA_LVD EADC_SPI ES ET1 EX1 ET0 EX0 0000,0000
Interrupt Priority
IP B8H
Low
- PPCA_LVD PADC_SPI PS PT1 PX1 PT0 PX0 x000,0000
Interrupt Priority
IPH B7H
High
- PPCA_LVDH PADC_SPIH PSH PT1H PX1H PT0H PX0H x000,0000
PCON register (Power Control Register)

PCON 87H name SMOD SMOD0 LVDF POF GF1
t ed . GF0 PD IDL
i
Li m
CU
AUXR: Auxiliary register (Non bit-addressable)
M
AUXR 8EH name T0x12 T1x12 UART_M0x6 EADCI ESPI ELVDI - -
C
S T

IE: Interrupt Enable Rsgister

IE A8H name EA EPCA_LVD EADC_SPI ES ET1 EX1 ET0 EX0
Enable Bit = 1 enables the interrupt .
Enable Bit = 0 disables it .
EA (IE.7): disables all interrupts. if EA = 0,no interrupt will be acknowledged. if EA = 1, each
interrupt source is individually enabled or disabled by setting or clearing its enable bit.
EPCA_LVD (IE.6): Interrupt controller of Programmable Counter Array (PCA) and Low-Voltage Detector
0 : Disable theinterrupt of Programmable Counter Array (PCA) and Low-Voltage Detector
1 : enable theinterrupt of Programmable Counter Array (PCA) and Low-Voltage Detector
IPH: Interrupt Priority High Register

SFR name Address bit B7 B6 B5 B4
ed . B3 B2 B1 B0
mit
IPH B7H name - PPCA_LVDH PADC_SPIH PSH PT1H PX1H PT0H PX0H
Li
IP: Interrupt Priority Register
U
IE B8H name - PPCA_LVD PADC_SPI PS PT1 PX1 PT0 PX0
M C
PPCA_LVDH, PPCA_LVD : Programmable Counter Array (PCA) and Low voltage detector interrupt priority control bits.
if PPCA_LVDH=0 and PPCA_LVD=0, Programmable Counter Array (PCA) and Low voltage detector
interrupt are assigned lowest priority(priority 0).
C
S T

2.3.6 Watch-Dog-Timer
The watch dog timer in STC12C5620AD consists of an 8-bit pre-scaler timer and an 15-bit timer. The timer is
one-time enabled by setting EN_WDT(WDT_CONTR.5). Clearing EN_WDT can stop WDT counting. When
the WDT is enabled, software should always reset the timer by writing 1 to CLR_WDT bit before the WDT
overflows. If STC12C5620AD series MCU is out of control by any disturbance, that means the CPU can not run
the software normally, then WDT may miss the "writting 1 to CLR_WDT" and overflow will come. An overflow
of Watch-Dog-Timer will generate a internal reset.
1/256
1/128
1/64
1/32
1/16
15-bit timer WDT Reset
.
1/8
d
1/4
i t e
1/2
m
8-bit prescalar
Li
SYSclk/12
IDL/PCON.0
U
WDT_FLAG - EN_WDT CLR_WDT IDLE_WDT PS2 PS1 PS0
C
WDT_CONTR
M WDT Structure
WDT_CONTR 0E1H S T C
WDT_CONTR: Watch-Dog-Timer Control Register
SFR name Address bit
name WDT_FLAG
B7 B6
-
B5 B4
EN_WDT CLR_WDT IDLE_WDT PS2
B3 B2 B1
PS1
B0
PS0
WDT_FLAG : WDT reset flag.
0 : This bit should be cleared by software.
1 : When WDT overflows, this bit is set by hardware to indicate a WDT reset happened.
EN_WDT : Enable WDT bit. When set, WDT is started.
CLR_WDT : WDT clear bit. When set, WDT will recount. Hardware will automatically clear this bit.
IDLE_WDT : WDT IDLE mode bit. When set, WDT is enabled in IDLE mode. When clear, WDT is disabled in
IDLE.
PS2, PS1, PS0 : WDT Pre-scale value set bit.

Pre-scale value of Watchdog timer is shown as the bellowed table :
PS2 PS1 PS0 Pre-scale WDT overflow Time @20MHz
0 0 0 2 39.3 mS
0 0 1 4 78.6 mS
0 1 0 8 157.3 mS
0 1 1 16 314.6 mS
1 0 0 32 629.1 mS
1 0 1 64 1.25 S
1 1 0 128 2.5 S
1 1 1 256 5S

The WDT overflow time is determined by the following equation:
WDT overflow time = (12 Pre-scale 32768) / SYSclk
The SYSclk is 20MHz in the table above.
If SYSclk is 12MHz, The WDT overflow time is :
WDT overflow time = (12 Pre-scale 32768) / 12000000 = Pre-scale 393216 / 12000000
WDT overflow time is shown as the bellowed table when SYSclk is 12MHz:
PS2 PS1 PS0 Pre-scale WDT overflow Time @12MHz
0 0 0 2 65.5 mS
0 0 1 4 131.0 mS
0 1 0 8 262.1 mS
0 1 1 16 524.2 mS
1 0 0 32 1.0485 S
d .
1 0 1 64 2.0971 S
mit e
1 1 0 128 4.1943 S
1 1 1 256 8.3886 S
Li
WDT overflow time is shown as the bellowed table when SYSclk is 11.0592MHz:
U
PS2 PS1 PS0 Pre-scale WDT overflow Time @11.0592MHz
C
0 0 0 2 71.1 mS
M
0 0 1 4 142.2 mS
0 1 0 8 284.4 mS
C
0 1 1 16 568.8 mS
T
1 0 0 32 1.1377 S
1
1
1
0
1
1
S1
0
1
64
128
256
2.2755 S
4.5511 S
9.1022 S
Options related with WDT in STC-ISP Writter/Programmer is shown in the following figure

The following example is a assembly language program that demostrates STC 1T Series MCU WDT.
;/*-------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited ----------------------------------*/
;/* --- STC 1T Series MCU WDT Demo ---------------------------------*/
;/* --- Mobile: (86)13922809991 ------------------------------------------*/
;/* --- Fax: 86-755-82905966 ----------------------------------------------*/
;/* --- Tel: 86-755-82948412 -----------------------------------------------*/
;/* --- Web: www.STCMCU.com -----------------------------------------*/
;/* If you want to use the program or the program referenced in the */
;/* article, please specify in which data and procedures from STC */
;/*-------------------------------------------------------------------------------*/
; WDT overflow time = (12 Pre-scale 32768) / SYSclk
.
WDT_CONTR EQU 0E1H ;WDT address
WDT_TIME_LED EQU P1.5
t ed
;WDT overflow time LED on P1.5
i
m
;The WDT overflow time may be measured by the LED light time
Li
WDT_FLAG_LED EQU P1.7
;WDT overflow reset flag LED indicator on P1.7
U
Last_WDT_Time_LED_Status EQU 00H

M C
;bit variable used to save the last stauts of WDT overflow time LED indicator
C
;WDT reset time , the SYSclk is 18.432MHz
;Pre_scale_Word EQU
;Pre_scale_Word EQU
;Pre_scale_Word EQU
S T 00111100 B
00111101 B
00111110 B
;open WDT, Pre-scale value is 32, WDT overflow time=0.68S
;Pre_scale_Word EQU 00111111 B ;open WDT, Pre-scale value is 256, WDT overflow time=5.44S

ORG 0000H
AJMP MAIN
ORG 0100H
MAIN:
MOV A, WDT_CONTR ;detection if WDT reset
ANL A, #10000000B
JNZ WDT_Reset
;WDT_CONTR.7=1, WDT reset, jump WDT reset subroutine
;WDT_CONTR.7=0, Power-On reset, cold start-up, the content of RAM is random
SETB Last_WDT_Time_LED_Status ;Power-On reset
CLR WDT_TIME_LED ;Power-On reset,open WDT overflow time LED
MOV WDT_CONTR, #Pre_scale_Word ;open WDT

WAIT1:
SJMP WAIT1 ;wait WDT overflow reset
;WDT_CONTR.7=1, WDT reset, hot strart-up, the content of RAM is constant and just like before reset
WDT_Reset:
CLR WDT_FLAG_LED
;WDT reset,open WDT overflow reset flag LED indicator
JB Last_WDT_Time_LED_Status, Power_Off_WDT_TIME_LED
;when set Last_WDT_Time_LED_Status, close the corresponding LED indicator
;clear, open the corresponding LED indicator
;set WDT_TIME_LED according to the last status of WDT overflow time LED indicator
CLR WDT_TIME_LED ;close the WDT overflow time LED indicator
CPL Last_WDT_Time_LED_Statu
ed .
mit
;reverse the last status of WDT overflow time LED indicator
Li
WAIT2:
Power_Off_WDT_TIME_LED:
SETB WDT_TIME_LED
C U ;close the WDT overflow time LED indicator
M
CPL Last_WDT_Time_LED_Status
;reverse the last status of WDT overflow time LED indicator
WAIT3:
C

S
END

2.3.7 Warm Boot and Cold Boot Reset
Reset type Reset source Result

WatchDog System will reset to AP address 0000H
Reset Pin and begin running user application
Warm boot program
20H ISP_CONTR
60H ISP_CONTR System will reset to ISP address 0000H
and begin running ISP monitor program,
if not detected legitimate ISP command,
Cold boot Power-on system will software reset to the user
d .
program area automatically.
t e
m i
Li
C U
M
S T C

Chapter 3. Memory Organization

The STC12C5620AD series MCU has separate address space for Program Memory and Data Memory. The
logical separation of program and data memory allows the data memory to be accessed by 8-bit addresses, which
can be quickly stored and manipulated by the CPU.
Program memory (ROM) can only be read, not written to. In the STC12C5620AD series, all the program memory
are on-chip Flash memory, and without the capability of accessing external program memory because of no Ex-
ternal Access Enable (/EA) and Program Store Enable (/PSEN) signals designed.
Data memory occupies a separate address space from program memory. In the 12C5A60S2 series, there are 256
bytes internal scratch-pad RAM and 512 bytes of on-chip expanded RAM(XRAM). The high 128 bytes of 256
bytes internal scrach-pad RAM seemingly overlap with SFRs in address. Actually, they are distinguished by
different addressing way. Similarly, STC12C5620AD series also have no the capability of accessing external
d .
data memory because of no the bus that access external data memory.
mit e
Li
3.1 Program Memory
Program memory is the memory which stores the program codes for the CPU to execute. There is 4/8/12/16/20/2
U
4/28/30K-bytes of flash memory embedded for program and data storage. The design allows users to configure it
C
as like there are three individual partition banks inside. They are called AP(application program) region, IAP (In-
M
Application-Program) region and ISP (In-System-Program) boot region. AP region is the space that user program
is resided. IAP(In-Application-Program) region is the nonvolatile data storage space that may be used to save
C
important parameters by AP program. In other words, the IAP capability of STC12C5620AD provides the user to
S T
read/write the user-defined on-chip data flash region to save the needing in use of external EEPROM device. ISP
boot region is the space that allows a specific program we calls ISP program is resided. Inside the ISP region,
the user can also enable read/write access to a small memory space to store parameters for specific purposes.
Generally, the purpose of ISP program is to fulfill AP program upgrade without the need to remove the device
from system. STC12C5620AD hardware catches the configuration information since power-up duration and
performs out-of-space hardware-protection depending on pre-determined criteria. The criteria is AP region can
be accessed by ISP program only, IAP region can be accessed by ISP program and AP program, and ISP region
is prohibited access from AP program and ISP program itself. But if the ISP data flash is enabled, ISP program
can read/write this space. When wrong settings on ISP-IAP SFRs are done, The out-of-space happens and
STC12C5620AD follows the criteria above, ignore the trigger command.
After reset, the CPU begins execution from the location 0000H of Program Memory, where should be the starting
of the users application code. To service the interrupts, the interrupt service locations (called interrupt vectors)
should be located in the program memory. Each interrupt is assigned a fixed location in the program memory. The
interrupt causes the CPU to jump to that location, where it commences execution of the service routine. External
Interrupt 0, for example, is assigned to location 0003H. If External Interrupt 0 is going to be used, its service
routine must begin at location 0003H. If the interrupt is not going to be used, its service location is available as
general purpose program memory.
The interrupt service locations are spaced at an interval of 8 bytes: 0003H for External Interrupt 0, 000BH for
Timer 0, 0013H for External Interrupt 1, 001BH for Timer 1, etc. If an interrupt service routine is short enough (as
is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines
can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use.

4FFFH Type Program Memory

STC12C/LE5604AD 0000H~0FFFH (4K)
20K STC12C/LE5608AD 0000H~1FFFH (8K)
Program Flash STC12C/LE5612AD 0000H~2FFFH (12K)
Memory STC12C/LE5616AD 0000H~3FFFH (16K)
(4~30K) STC12C/LE5620AD 0000H~4FFFH (20K)
STC12C/LE5624AD 0000H~5FFFH (24K)
0000H STC12C/LE5628AD 0000H~6FFFH (28K)
STC12C/LE5630AD 0000H~77FFH (30K)
STC12C5620AD MCU Program Memory
.
3.2 Data Memory(SRAM)
3.2.1 On-chip Scratch-Pad RAM
i t ed
Li m
Just the same as the conventional 8051 micro-controller, there are 256 bytes of SRAM data memory plus 128
bytes of SFR space available on the STC12C5620AD. The lower 128 bytes of data memory may be accessed
U
through both direct and indirect addressing. The upper 128 bytes of data memory and the 128 bytes of SFR
C
space share the same address space. The upper 128 bytes of data memory may only be accessed using indirect
M
addressing. The 128 bytes of SFR can only be accessed through direct addressing. The lowest 32 bytes of data
memory are grouped into 4 banks of 8 registers each. Program instructions call out these registers as R0 through
C
R7. The RS0 and RS1 bits in PSW register select which register bank is in use. Instructions using register
T
addressing will only access the currently specified bank. This allows more efficient use of code space, since
S
register instructions are shorter than instructions that use direct addressing. The next 16 bytes (20H~2FH) above
the register banks form a block of bit-addressable memory space. The 80C51 instruction set includes a wide
selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions.
The bit addresses in this area are 00H through 7FH.
All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing while the Upper 128
can only be accessed by indirect addressing. SFRs include the Port latches, timers, peripheral controls, etc.
These registers can only be accessed by direct addressing. Sixteen addresses in SFR space are both byte- and bit-
addressable. The bit-addressable SFRs are those whose address ends in 0H or 8H.
FF
7FH
Special Function
High 128 Bytes Registers (SFRs)
Internal RAM
30H
80 2FH
7F bit Addressable
Low 128 Bytes 20H
Internal RAM 1FH
Bank 3
18H
17H
00 Bank 2
10H
On-chip Scratch-Pad RAM 0FH
Bank 1
08H
07H
Bank 0
00H
Lower 128 Bytes of internal SRAM

PSW register
PSW D0H name CY AC F0 RS1 RS0 OV F1 P
CY : Carry flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtrac-tion). It is cleared to logic 0 by all other arithmetic operations.
AC : Auxilliary Carry Flag.(For BCD operations)
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations
F0 : Flag 0.(Available to the user for general purposes)
.
RS1: Register bank select control bit 1.
d
mit e
[RS1 RS0] select which register bank is used during register accesses
Li
RS1 RS0 Working Register Bank(R0~R7) and Address
0 0 Bank 0(00H~07H)
0 1 Bank 1(08H~0FH)
1 0
C U
Bank 2(10H~17H)
M
1 1 Bank 3(18H~1FH)
OV : Overflow flag.
C
This bit is set to 1 under the following circumstances:
S T
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
F1 : Flag 1. User-defined flag.
P : Parity flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.
SP : Stack Pointer.
The Stsek Pointer Register is 8 bits wide. It is incremented before data is stored during PUSH and CALL
executions. The stack may reside anywhere in on-chip RAM.On reset, the Stack Pointer is initialized to
07H causing the stack to begin at location 08H, which is also the first register (R0) of register bank
1. Thus, if more than one register bank is to be used, the SP should be initialized to a location in
the data memory not being used for data storage. The stack depth can extend up to 256 bytes.

;Demo Program of internal common 256 bytes RAM
;/*-----------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited --------------------------------------*/
;/* --- STC 1T Series MCU internal common 256 bytes RAM Demo ---*/
;/* --- Mobile: (86)13922809991 ----------------------------------------------*/
;/* --- Fax: 86-755-82905966 --------------------------------------------------*/
;/* --- Tel: 86-755-82948412 ---------------------------------------------------*/
;/* --- Web: www.STCMCU.com ----------------------------------------------*/
;/* If you want to use the program or the program referenced in the ----*/
;/* article, please specify in which data and procedures from STC ----*/
;/*-----------------------------------------------------------------------------------*/
TEST_CONST EQU 5AH
;TEST_RAM EQU 03H
d .
ORG 0000H
t e
LJMP INITIAL
m i
Li
ORG 0050H
INITIAL:
U
MOV R0, #253
C
MOV R1, #3H
M
TEST_ALL_RAM:
MOV R2, #0FFH
C
TEST_ONE_RAM:

MOV A,
MOV @R1,
CLR A
MOV A,
S T R2
A
@R1
CJNE A, 2H, ERROR_DISPLAY
DJNZ R2, TEST_ONE_RAM
INC R1
DJNZ R0, TEST_ALL_RAM
OK_DISPLAY:
MOV P1, #11111110B
Wait1:
SJMP Wait1
ERROR_DISPLAY:
MOV A, R1
MOV P1, A
Wait2:
SJMP Wait2

END

3.2.2 Auxiliary RAM

There are 512 bytes of additional data RAM available on STC12C5620AD. They may be accessed by the
instructions MOVX @Ri or MOVX @DPTR. The auxiliary RAM is the default target for the address range from
0x0000 to 0x01FF and can be indirectly accessed by move external instruction, MOVX @Ri and MOVX @
DPTR.
For KEIL-C51 compiler, to assign the variables to be located at Auxiliary RAM, the pdata or xdata definition
should be used. After being compiled, the variables declared by pdata and xdata will become the memories
accessed by MOVX @Ri and MOVX @DPTR, respectively. Thus the STC12C5620AD hardware can access
them correctly.
01FFH
ed .
mit
512 Bytes
expanded RAM
Li
0000H
U
Auxiliary RAM
M C
An example program for internal expanded RAM demo of STC12C5620AD :
C
;/*--------------------------------------------------------------------------------*/
S T
;/* --- STC MCU International Limited -----------------------------------*/
;/* --- STC 1T Series MCU internal expanded RAM Demo -----------*/
;/* --- Mobile: (86)13922809991 ------------------------------------------*/
;/* --- Fax: 86-755-82905966 ----------------------------------------------*/
;/* --- Tel: 86-755-82948412 -----------------------------------------------*/
;/* --- Web: www.STCMCU.com ------------------------------------------*/
;/*-------------------------------------------------------------------------------*/
#include <reg52.h>
#include <intrins.h> /* use _nop_() function */
sfr AUXR = 0x8e;

sfr IPH = 0xb7;
sfr WDT_CONTR = 0xe1;
sfr ISP_DATA = 0xe2;
sfr ISP_ADDRH = 0xe3;
sfr ISP_ADDRL = 0xe4;
sfr ISP_CMD = 0xe5;
sfr ISP_TRIG = 0xe6;
sfr ISP_CONTR = 0xe7;

sbit ERROR_LED = P1^5;

sbit OK_LED = P1^7;
void main()
{
unsigned int array_point = 0;
/* Test_array_one[256],Test_array_two[256]*/
unsigned char xdata Test_array_one[256] =
{
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
d .
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
i t e
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
Li m
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
U
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
C
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
M
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,

T C
0x58, 0x59, 0x5a, 0x5b, 0x5c,
S
0x60, 0x61, 0x62, 0x63, 0x64,
0x68, 0x69, 0x6a, 0x6b, 0x6c,
0x70, 0x71, 0x72, 0x73, 0x74,
0x5d, 0x5e, 0x5f,
0x65, 0x66, 0x67,
0x6d, 0x6e, 0x6f,
0x75, 0x76, 0x77,
0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
};

unsigned char xdata Test_array_two[256] =
{
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
.
0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
ed
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
mit
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
Li
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
U
0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
C
0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
M
0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
C
0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
T
0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
S
0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,
};
ERROR_LED = 1;
OK_LED = 1;
for(array_point=0; array_point<256; array_point++)
{
if(Test_array_one[array_point]!=Test_array_two [array_point])
{
ERROR_LED = 0;
OK_LED = 1;
break;
}

else
{
OK_LED = 0;
ERROR_LED = 1;
}
}
while(1);
}
t ed .
m i
Li
C U
M
S T C

3.3 Special Function Registers

3.3.1 Special Function Registers Address Map
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
0F8H CH CCAP0H CCAP1H CCAP2H CCAP3H 0FFH
0000,0000 0000,0000 0000,0000 0000,0000 0000,0000
0F0H B PCA_PWM0 PCA_PWM1 PCA_PWM2 PCA_PWM3 0F7H
0000,0000 xxxx,xx00 xxxx,xx00 xxxx,xx00 xxxx,xx00
0E8H CL CCAP0L CCAP1L CCAP2L CCAP3L 0EFH
0000,0000 0000,0000 0000,0000 0000,0000 0000,0000
0E0H ACC WDT_CONR ISP_DATA ISP_ADDRH ISP_ADDRL ISP_CMD ISP_TRIG ISP_CONTR 0E7H
.
0000,0000 0x00,0000 1111,1111 0000,0000 0000,0000 xxxx,xx00 xxxx,xxxx 0000,1000
d
0D8H CCON 0DFH
e
CMOD CCAPM0 CCAPM1 CCAPM2 CCAPM3
mit
00xx,0000 0xxx,x000 x000,0000 x000,0000 x000,0000 x000,0000
Li
0D0H PSW 0D7H
0000,0000
0C8H 0CFH
0C0H
C U ADC_CONTR ADC_DATA CLK_DIV 0C7H
M
0000,0000 0000,0000 xxxx,x000
0B8H IP SADEN ADC_LOW2 0BFH
C
x000,0000 0000,0000
T
0B0H P3 P3M0 P3M1 IPH 0B7H
S
1x11,1111 0000,0000 0000,0000 x000,0000
0A8H IE SADDR 0AFH
0000,0000
0A0H P2 0A7H
Don't use
1111,1111
098H SCON SBUF 09FH
0000,0000 xxxx,xxxx
090H P1 P1M0 P1M1 P0M0 P0M1 P2M0 P2M1 097H
1111,1111 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000
088H TCON TMOD TL0 TL1 TH0 TH1 AUXR WAKE_CLKO 08FH
0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,00xx 0000,xx00
080H P0 SP DPL DPH SPSTAT SPCTL SPDAT PCON 087H
1111,1111 0000,0111 0000,0000 0000,0000 00xx,xxxx 0000,0100 0000,0000 0011,0000
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
Non Bit Addressable

Bit Addressable

3.3.2 Special Function Registers Bits Description

Value after
MSB LSB Reset
P0 Port 0 80H P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 1111 1111B
SP Stack Pointer 81H 0000 0111B
DPL Data Pointer Low 82H 0000 0000B
DPTR
DPH Data Pointer High 83H 0000 0000B
SPSTAT SPI Status register 84H SPIF WCOL - - - - - - 00xx xxxxB
SPCTL SPI control register 85H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 0000 0100B
SPDAT SPI Data register 86H 0000 0000B
d .
PCON Power Control 87H SMOD SMOD0 LVDF POF GF1 GF0 PD IDL 0011 0000B
TCON Timer Control 88H TF1 TR1 TF0 TR0
m i t e
IE1 IT1 IE0 IT0 0000 0000B
Li
TMOD Timer Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 0000 0000B
TL0 Timer Low 0 8AH 0000 0000B
TL1 Timer Low 1 8BH 0000 0000B
C U
TH0 Timer High 0 8CH 0000 0000B
M
TH1 Timer High 1 8DH 0000 0000B
C
CLK_Output
T
PCAWAKEUP RXD_PIN_IE T1_PIN_IE T0_PIN_IE - - T1CLKO T0CLKO
Power down
S
Wake-up control
register
P1 Port 1 90H P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 1111 1111B
P1M0 P1 configuration 0 91H 0000 0000B
SCON Serial Control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 0000 0000B
SBUF Serial Buffer 99H xxxx xxxxB
P2 Port 2 A0H P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 1111 1111B
IE Interrupt Enable A8H EA EPCA_LVD EADC_SPI ES ET1 EX1 ET0 EX0 0000 0000B
SADDR Slave Address A9H 0000 0000B
P3 Port 3 B0H P3.7 - P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 1x11 1111B
P3M0 P2 configuration 0 B1H 0000 0000B
P3M1 P3 configuration 1 B2H 0000 0000B
Interrupt Priority - PPCA_LVDH PADC_SPIH PSH PT1H PX1H PT0H PX0H
IPH B7H x000 0000B
High
Interrupt Priority - PPCA_LVD PADC_SPI PS PT1 PX1 PT0 PX0
IP B8H x000 0000B
Low

Value after
MSB LSB Reset
SADEN Slave Address Mask B9H 0000 0000B
ADC_CONTR ADC Control C5H ADC_POWER SPEED1 SPEED0 ADC_FLAG ADC_START CHS2 CHS1 CHIS0
0000 0000B
ADC_DATA ADC Result High C6H 0000 0000B
ADC_LOW2 ADC Result Low BEH 0000 0000B
CLK_DIV Clock Divder C7h - - - - - CLKS2 CLKS1 CLKS0 xxxx x000B
Program Status CY AC F0 RS1 RS0 OV F1 P
PSW D0H 0000 0000B
Word
PCA Control CF CR - - CCF3 CCF2 CCF1 CCF0
CCON D8H 00xx 0000B
Register
.
CMOD PCA Mode Register D9H 00xx 0000B
d
CIDL - - - - CPS1 CPS0 ECF
mit e
PCA Module 0 - ECOM0 CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0
CCAPM0 DAH x000 0000B
Mode Register
Li
PCA Module 1 - ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1
CCAPM1 DBH x000 0000B
Mode Register
U
PCA Module 2
CCAPM2 DCH - ECOM2 CAPP2 CAPN2 MAT2 TOG2 PWM2 ECCF2 x000 0000B
C
Mode Register
M
PCA Module 3
CCAPM3 DDH - ECOM3 CAPP3 CAPN3 MAT3 TOG3 PWM3 ECCF3 x000 0000B
Mode Register
C
ACC Accumulator E0H 0000 0000B
S T
Watch-Dog-Timer WDT_FLAG - EN_WDT CLR_WDT IDLE_WDT PS2 PS1 PS0
WDT_CONTR E1H xx00 0000B
Control Register
ISP/IAP Flash Data
ISP_DATA E2H 1111 1111B
Register
ISP/IAP Flash
ISP_ADDRH E3H 0000 0000B
Address High
ISP/IAP Flash
ISP_ADDRL E4H 0000 0000B
Address Low
ISP/IAP Flash - - - - - - MS1 MS0
ISP_CMD E5H xxxx x000B
Command Register
ISP/IAP Flash
ISP_TRIG E6H xxxx xxxxB
Command Trigger
ISP/IAP Control IAPEN SWBS SWRST CMD_FAIL - WT2 WT1 WT0
ISP_CONTR E7H 0000 x000B
Register
PCA Base Timer
CL E9H 0000 0000B
Low
PCA module 0
CCAP0L EAH 0000 0000B
capture register low
PCA module 1
CCAP1L EBH 0000 0000B
capture register low
PCA Module-2
CCAP2L ECH 0000 0000B
capture register Low

Value after
MSB LSB Reset
PCA Module-3
CCAP3L EDH 0000 0000B
capture register Low
B B Register F0H 0000 0000B
PCA PWM mode - - - - - - EPC0H EPC0L
PCA_PWM0 F2H xxxx xx00B
auxiliary register 1
PCA PWM mode - - - - - - EPC1H EPC1L
PCA_PWM1 F3H xxxx xx00B
auxiliary register 1
PCA PWM Mode
PCA_PWM2 F4H - - - - - - EPC2H EPC2L xxxx xx00B
Auxiliary Register 2
PCA_PWM3
PCA PWM Mode
F5H - - - - -
t ed
-
. EPC3H EPC3L xxxx xx00B
i
Auxiliary Register 3
Li m
PCA Base Timer
CH F9H 0000 0000B
High
PCA module 0
CCAP0H FAH 0000 0000B
CU
capture register high
PCA module 1
CCAP1H FBH 0000 0000B
M
capture register high
PCA Module-2 C
C
CCAP2H FCH 0000 0000B
capture register High
CCAP3H
S T
PCA Module-3
capture register High
FDH 0000 0000B

Some common SFRs of standard 8051 are shown as below.
Accumulator
ACC is the Accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the
accumulator simply as A.
B-Register
The B register is used during multiply and divide operations. For other instructions it can be treated as another
scratch pad register.
ed .
mit
Stack Pointer
Li
The Stack Pointer register is 8 bits wide. It is incrementde before data is stored during PUSH and CALL
executions. While the stack may reside anywhee in on-chip RAM, the Stack Pointer is initialized to 07H after a
reset. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first
U
register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be
C
initialized to a location in the data memory not being used for data storage. The stack depth can extend
M
up to 256 bytes.
S T C
Data Pointer Register (DPTR)
The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a
16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers.
Program Status Word(PSW)

The program status word(PSW) contains several status bits that reflect the current state of the CPU. The PSW,
shown below, resides in the SFR space. It contains the Carry bit, the Auxiliary Carry(for BCD operation), the two
register bank select bits, the Overflow flag, a Parity bit and two user-definable status flags.
The Carry bit, other than serving the function of a Carry bit in arithmetic operations, also serves as the
Accumulator for a number of Boolean operations.
The bits RS0 and RS1 are used to select one of the four register banks shown in the previous page. A number of
instructions refer to these RAM locations as R0 through R7.
The Parity bit reflects the number of 1s in the Accumulator. P=1 if the Accumulator contains an odd number of 1s
and otherwise P=0.

PSW register
PSW D0H name CY AC F0 RS1 RS0 OV F1 P
CY : Carry flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtrac-tion). It is cleared to logic 0 by all other arithmetic operations.
AC : Auxilliary Carry Flag.(For BCD operations)
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic operations
F0 : Flag 0.(Available to the user for general purposes)
.
ed
i t
[RS1 RS0] select which register bank is used during register accesses
Li m
RS1 RS0 Working Register Bank(R0~R7) and Address
0 0 Bank 0(00H~07H)
0 1 Bank 1(08H~0FH)
1 0
C U
Bank 2(10H~17H)
M
1 1 Bank 3(18H~1FH)
OV : Overflow flag.
S T C
This bit is set to 1 under the following circumstances:
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
F1 : Flag 1. User-defined flag.
P : Parity flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.

Chapter 4. Configurable I/O Ports of STC12C5620AD series

4.1 I/O Ports Configurations
All I/O ports of STC12C5620AD may be independently configured to one of four modes by setting the
corresponding bit in two mode registers PxMn (x= 0 ~ 3, n = 0, 1).The four modes are quasi-bidirectional (standard
8051 port output), push-pull output, input-only or open-drain output. All port pins default to quasi-bidirectional
after reset. Each one has a Schmitt-triggered input for improved input noise rejection. Any port can drive 20mA
current, but the whole chip had better drive lower than 90mA current.
Configure I/O ports mode

P3 Configure <P3.7, P3.6, P3.5, P3.4, P3.3, P3.2, P3.1, P3.0 port> (P3
addressB0H)
d .
P3M0[7 : 0] P3M1 [7 : 0] I/O ports Mode
mit e
quasi_bidirectional(standard 8051 I/O port output ,
0 0 Sink Current up to 20mA , pull-up Current is 230A ,
Li
Because of manufactured error, the actual pull-up current is 250uA ~ 150uA
push-pull output(strong pull-up outputcurrent can be up to 20mA, resistors
0 1
need to be added to restrict current
1 0
C U
input-only (high-impedance )
M
Open Draininternal pull-up resistors should be disabled and external
1 1
pull-up resistors need to join.
C
Example: MOV P3M0, #10100000B
S T
MOV P3M1, #10010000B
;P3.7 in Open Drain mode, P3.5 in high-impedance input, P3.4 in strong push-pull output, P3.3/P3.2/P3.1/P3.0
in quasi_bidirectional
/weak pull-up
addressA0H)
0 1
1 0 input-only (high-impedance )
1 1
MOV P2M1, #11000000B
;P2.7 in Open Drain mode, P2.6 in strong push-pull output, P2.5 in high-impedance input, P2.4/P2.3/P2.2/
P2.1/P2.0 in quasi_bidirectional
/weak pull-up

address90H)
0 1
1 1
MOV P1M1, #11000000B
.
t ed
/weak pull-up
m i
Li
address80H)
U
quasi_bidirectional (standard 8051 I/O port output ,
C
M
0 1
C
T
1
S 1

MOV P0M1, #00001100B

;P0.3 in Open Drain mode, P0.2 in strong push-pull output, P0.1 in high-impedance input, P0.0 in
quasi_bidirectional
/weak pull-up
Some SFRs related with I/O ports are listed below.

P3 register (bit addressable)
P3 B0H name P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
P3 register could be bit-addressable and set/cleared by CPU. And P3.7~P3.0 coulde be set/cleared by CPU.
P3M0 register (non bit addressable)

P3M0 B1H name P3M0.7 P3M0.6 P3M0.5 P3M0.4 P3M0.3 P3M0.2 P3M0.1 P3M0.0

P3M1 B2H name P3M1.7 P3M1.6 P3M1.5 P3M1.4 P3M1.3 P3M1.2 P3M1.1 P3M1.0


P2 A0H name P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0

P2M0 95H name P2M0.7 P2M0.6 P2M0.5 P2M0.4 P2M0.3 P2M0.2 P2M0.1 P2M0.0

.
ed
Li mit
U
P1 90H name P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
C

M
C
P1M0
S
91H
T name P1M0.7 P1M0.6 P1M0.5 P1M0.4 P1M0.3 P1M0.2 P1M0.1 P1M0.0


P0 80H name P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
P0 register could be bit-addressable. And P0.3~P0.0 coulde be set/cleared by CPU.



4.2 I/O ports Modes

4.2.1 Quasi-bidirectional I/O
Port pins in quasi-bidirectional output mode function similar to the standard 8051 port pins. A quasi-bidirectional
port can be used as an input and output without the need to reconfigure the port. This is possible because when
the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin
outputs low, it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-
bidirectional output that serve different purposes.
One of these pull-ups, called the very weak pull-up, is turned on whenever the port register for the pin contains
a logic 1. This very weak pull-up sources a very small current that will pull the pin high if it is left floating.
A second pull-up, called the weak pull-up, is turned on when the port register for the pin contains a logic
d .
1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-
t e
i
bidirectional pin that is outputting a 1. If this pin is pulled low by the external device, this weak pull-up turns off,
m
and only the very weak pull-up remains on. In order to pull the pin low under these conditions, the external device
Li
has to sink enough current to over-power the weak pull-up and pull the port pin below its input threshold voltage.
The third pull-up is referred to as the strong pull-up. This pull-up is used to speed up low-to-high transitions on
C U
a quasi-bidirectional port pin when the port register changes from a logic 0 to a logic 1. When this occurs, the
M
strong pull-up turns on for two CPU clocks, quickly pulling the port pin high.
C
Vcc Vcc Vcc
T
2 clock
S
delay Weak
Strong Very weak
PORT
PORT PIN
LATCH DATA
INPUT
DATA
Quasi-bidirectional output

4.2.2 Push-pull Output

The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-
bidirectional output modes, but provides a continuous strong pull-up when the port register conatins a logic 1.
The push-pull mode may be used when more source current is needed from a port output. In addition, input path
of the port pin in this configuration is also the same as quasi-bidirectional mode.
Vcc
PORT
LATCH DATA PORT
PIN
INPUT
ed .
mit
DATA
Li
Push-pull output
4.2.3 Input-only (High-Impedance)Mode
C U
The input-only configuration is a Schmitt-triggered input without any pull-up resistors on the pin.
INPUT
M PORT
C
DATA PIN
S T Input-only Mode
4.2.4 Open-drain Output

The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor
of the port pin when the port register contains a logic 0. To use this configuration in application, a
port pin must have an external pull-up, typically tied to VCC. The input path of the port pin in this
configuration is the same as quasi-bidirection mode.
PORT
PORT PIN
LATCH DATA
INPUT
DATA
Open-drain output

4.3 I/O port application notes

Traditional 8051 access I/O (signal transition or read status) timing is 12 clocks, STC12C5620AD series MCU is
4 clocks. When you need to read an external signal, if internal output a rising edge signal, for the traditional 8051,
this process is 12 clocks, you can read at once, but for STC12C5620AD series MCU, this process is 4 clocks,
when internal instructions is complete but external signal is not ready, so you must delay 1~2 nop operation.
When MCU is connected to a SPI or I2C or other open-drain peripherals circuit, you need add a 10K pull-up
resistor.
Some IO port connected to a PNP transistor, but no pul-up resistor. The correct access method is IO port pull-up
resistor and transistor base resistor should be consistent, or IO port is set to a strongly push-pull output mode.
d .
Using IO port drive LED directly or matrix key scan, needs add a 470ohm to 1Kohm resistor to limit current.
m i t e
Li
4.4 Typical transistor control circuit
Vcc Vcc
C U
M
R1
R3
10K(3.3K~10K)
T C
common I/O port
S
R2
15K(3.3K~15K)
If I/O is configed as weak pull-up, you should add a external pull-up resistor R1(3.3K~10K ohm). If no pull-up
resistor R1, proposal to add a 15K ohm series resistor R2 at least or config I/O as push-pull mode.
4.5 Typical diode control circuit

1K
I/O Vcc
For weak pull-up / quasi-bidirectional I/O, use sink current drive LED, current limiting resistor as greater than 1K
ohm, minimum not less than 470 ohm.
1K
I/O
For push-pull / strong pull-up I/O, use drive current drive LED.

4.6 3V/5V hybrid system

When STC12C5620AD series 5V MCU connect to 3.3V peripherals. To prevent the 3.3V device can not afford to
5V voltage, the 5V MCU corresponding I/O should first add a 330 ohm current limiting resistor to 3.3 device I/O
ports. And in intialization of procedures the 5V MCU corresponding I/O is set to open drain mode, disconnect the
internal pull-up resistor, the corresponding 3.3V device I/O port add 10K ohm external pull-up resistor to the 3.3V
device VCC, so high level to 3.3V and low to 0V, which can proper functioning
3.3V
10K
330
5V MCU I/O port 3.3V device I/O port
ed .
mit
When STC12LE5620AD series 3V MCU connect to 5V peripherals. To prevent the 3V MCU can not afford to 5V
Li
voltage, if the corresponding I/O port as input port, the port may be in an isolation diode in series, isolated high-
voltage part. When the external signal is higher than MCU operating voltage, the diode cut-off, I/O have been
pulled high by the internal pull-up resistor; when the external signal is low, the diode conduction, I/O port voltage
C U
is limited to 0.7V, its low signal to MCU.
M
MCU common I/O external input signal
C
When STC12LE5620AD series 3V MCU connect to 5V peripherals. To prevent the 3V MCU can not afford to
S T
5V voltage, if the corresponding I/O port as output port, the port may be connect a NPN transistor to isolate high-
voltage part. The circuit is shown as below.
5V
10K
1
common I/O port
0
1
0
5V device I/O port
2K

4.7 How to make I/O port low after MCU reset

Traditional 8051 MCU power-on reset, the general IO port are weak pull-high output, while many practical
applications require IO port remain low level after power-on reset, otherwise the system malfunction would be
generated. For STC12C5620AD series MCU, IO port can add a pull-down resistor (1K/2K/3K), so that when
power-on reset, although a weak internal pull-up to make MCU output high, but because of the limited capacity
of the internal pull-up, it can not pull-high the pad, so this IO port is low level after power-on reset. If the I/O port
need to drive high, you can set the IO model as the push-pull output mode, while the push-pull mode the drive
current can be up to 20mA, so it can drive this I/O high.
More then 470ohm

I/O
d .
1K/2K/3K
m i t e
Li
C U
M
T C
4.8 I/O status while PWM outputing
S
When I/O is used as PWM port, its status as bellow:
Before PWM output While PWM outputing
Quasi-bidirectional Push-Pull (Strong pull-high need 1K~10K limiting resistor)
Push-Pull Push-Pull (Strong pull-high need 1K~10K limiting resistor)
Input ony (Floating) PWM Invalid
Open-drain Open-drain
current limiting resistor between 10K and 1K

common I/O port
To load

4.9 I/O drive LED application circuit
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P2.2 I/O
1 32 VCC
P2.3 2 31 P2.1
RST 3 30 P2.0/PCA2/PWM2
R1 R2 R3 R4 R5 R6 R7 R8 470ohm*8
RxD/P3.0 4 29 P1.7/SCLK/ADC7 a b c d e f g dp
TxD/P3.1 5 28 P1.6/MISO/ADC6
.
P0.0 6 27 P1.5/MOSI/ADC5
d
SOP-32
e
XTAL2 7 26 P0.3
mit
XTAL1 8 25 P1.4/SS/ADC4
INT0/P3.2 9 24 P1.3/ADC3
Li
COM1 COM2 COM3 COM4
P0.1 10 23 P0.2
R1 R2 R3 R4
INT1/P3.3 11 22 P1.2/ADC2 471 471 471 471
ECI/T0/P3.4 12 21 P1.1/ADC1/CLKOUT1
CU
PWM1/PCA1/T1/P3.5 13 20 P1.0/ADC0/CLKOUT0 I/O I/O I/O I/O
PWM3/PCA3/P2.4 14 19 P3.7/PCA0/PWM0
P2.5 15 18 P2.7
I/O dynamic scan driver 4 groups of
M
Gnd 16 17 P2.6
digital tube Cathode circuit
S T C LED1 R1
LED2 R2
4K7
4K7
VCC
LED3 R3 4K7
LED4 R4 4K7
LED1
I/O COM1 COM2 COM3 COM4
LED2
I/O
LED3
I/O
LED4
I/O
a b c d e f g dp
I/O dynamic scan driver 4 groups of
R5 a
digital tube anode circuit I/O
R6 b
I/O
R7 c
I/O
R8 d
I/O
R9 e
I/O
R10 f
I/O
R11 g
I/O
R12 dp
I/O
1Kohm*8

4.10 I/O immediately drive LCD application circuit

VCC
R1 R2 R3 R4
100K 100K 100K 100K
SEG1 COM1
SEG1
SEG2 COM2
SEG2 COM3
SEG3 COM4
SEG3
SEG4 R5 R6 R7 R8
SEG4
I/O
SEG1 100K 100K 100K 100K
SEG5
SEG5 I/O
SEG2
SEG6 SEG3
SEG6 I/O
SEG4
SEG7 I/O
SEG7 SEG5
I/O
SEG8
.
SEG8 I/O
SEG6
d
COM1 SEG7
e
COM1 I/O
t
SEG8
i
COM2 I/O
COM2 COM1
m
I/O
Li
COM3 COM2
COM3 I/O
I/O
COM3
COM4 COM4 COM4
I/O
U
LCD4X8 1/2 BIAS
How to light on the LCD pixels:
M C
When the pixels corresponding COM-side and SEG-side voltage difference is greater than 1/2VCC, this
C
pixel is lit, otherwise off
S T
Contrl SEG-side (Segment) :
I/O direct drive Segment lines, control Segment output high-level (VCC) or low-level (0V).
Contrl COM-side (Common) :
I/O port and two 100K dividing resistors jointly controlled Common line, when the IO output "0", the
Common-line is low level (0V), when the IO push-pull output "1", the Common line is high level (VCC),
when IO as high-impedance input, the Common line is 1/2VCC. VCC
R1 R2 R3 R4
100K 100K 100K 100K
SEG1 COM1
SEG1
SEG2 COM2
SEG2 COM3
SEG3 COM4
SEG3
SEG4 R5 R6 R7 R8
SEG4
I/O
SEG1 100K 100K 100K 100K
SEG5
SEG5 I/O
SEG2
SEG6 SEG3
SEG6 I/O
SEG4
SEG7 I/O
I/O control
SEG7 SEG5
I/O
SEG8 SEG6
SEG8 I/O
COM1 I/O
SEG7 Before MCU enter Power_Down
COM1
I/O
SEG8 mode, the I/O output high level,
COM2 COM1
COM2 I/O then Common side will have no
COM3 COM2
COM3 I/O
COM3
leakage current
COM4 I/O
COM4 COM4
I/O
LCD4X8 1/2 BIAS

4.11 Using A/D Conversion to scan key application circuit
P2.2 1 28 Vcc
+5V
P2.3 2 27 P2.1
RST 3 26 P2.0 R1
ADCx 10K
RxD/P3.0 4 25 P1.7/ADC7
TxD/P3.1 5 SOP-28/SKDIP-28 24 P1.6/ADC6
47pF
XTAL2 6 23 P1.5/ADC5 R2 R3 R4 R5 R6
520 1.8K 3.3K 5.4K 8.2K
XTAL1 7 22 P1.4/ADC4
INT0/P3.2 8 21 P1.3/ADC3 sw1 sw2 sw3 sw4 sw5 sw6
INT1/P3.3 9 20 P1.2/ADC2
.
ECI/T0/P3.4 10 19 P1.1/ADC1/CLKOUT1 0 0`0.5 0.5`1 1`1.5 1.5`2.0 2.0`2.5
d
PWM1/PCA1/T1/P3.5 18 P1.0/ADC0/CLKOUT0
e
11
mit
P2.4 12 17 P3.7/PCA0/PWM0
P2.5 13 16 P2.7
This circuit can achieve a signle key
Li
Gnd 14 15 P2.6
or combin key scan, resistance need to
configure the actual needs
C U
M
This circuit use 10 keys spaced partial pressure, for each key, range
of allowed error is +/-0.25V, it can effectively avoid failure of key
T C
detection because of resistance or temperature drift. If the requested
S
+5V
key detection more stable and reliable, can reduce the number of
R0 buttons, to relax the voltage range of each key
ADCx 10K
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10
47pF 520 1.2K 1.6K 1.8K 3K 4K 6.5 10K 30K 100K
sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw8 sw9 sw10 sw11

Chapter 5. Instruction System

5.1 Addressing Modes
Addressing modes are an integral part of each computer's instruction set. They allow specifyng the source or
destination of data in different ways, depending on the programming situation. There are five modes available:
Immediate
Direct
Indirect
Register
Indexed
Immediate Constant(IMM)
.
The value of a constant can follow the opcode in the program memory. For example,
ed
MOV A, #70H
i t
loads the Accumulator with the hex digits 70. The same number could be specified in decimal number as 112.
m
Li
Direct Addressing(DIR)
In direct addressing the operand is specified by an 8-bit address field in the instruction. Only 128 lowest bytes of
U
internal data RAM and SFRs can be direct addressed.
Indirect Addressing(IND)
M C
In indirect addressing the instruction specified a register which contains the address of the operand. Both internal
T C
and external RAM can be indirectly addressed.
S
The address register for 8-bit addresses can be R0 or R1 of the selected bank, or the Stack Pointer.
The address register for 16-bit addresses can only be the 16-bit data pointer register DPTR.
Register Instruction(REG)
The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3-bit
register specification within the opcode of the instruction. Instructions that access the registers this way are code
efficient because this mode eliminates the need of an extra address byte. When such instruction is executed, one
of the eight registers in the selected bank is accessed.
Register-Specific Instruction
Some instructions are specific to a certain register. For example, some instructions always operate on the
accumulator or data pointer,etc. No address byte is needed for such instructions. The opcode itself does it.
Index Addressing
Only program memory can be accessed with indexed addressing and it can only be read. This addressing mode is
intended for reading look-up tables in program memory. A 16-bit base register(either DPTR or PC) points to the
base of the table, and the accumulator is set up with the table entry number. Another type of indexed
addressing is used in the conditional jump instruction.
In conditional jump, the destination address is computed as the sum of the base pointer and the
accumulator.

5.2 Instruction Set Summary

The STC MCU instructions are fully compatible with the standard 8051's,which are divided among five functional
groups:
Arithmetic
Logical
Data transfer
Boolean variable
Program branching
The following tables provides a quick reference chart showing all the 8051 and STC 1T MCU instructions. Once
you are familiar with the instruction set, this chart should prove a handy and quick source of reference.
Execution Clocks of Execution Clocks of

Conventional 12T 8051 STC12C5620AD series
ed .
Li mit
Execution clocks Execution clocks Efficiency
Mnemonic Description Byte of 12T MCU of STC 1T MCU improved
ARITHMETIC OPERATIONS
CU
ADD A, Rn Add register to Accumulator 1 12 2 6x
ADD A, direct Add ditect byte to Accumulator 2 12 3 4x
M
ADD A, @Ri Add indirect RAM to Accumulator 1 12 3 4x
ADD A, #data Add immediate data to Accumulator 2 12 2 6x
T C
ADDC A, Rn Add register to Accumulator with Carry 1 12 2 6x
S
ADDC A, direct Add direct byte to Accumulator with Carry 2 12 3 4x
ADDC A, @Ri Add indirect RAM to Accumulator with Carry 1 12 3 4x
ADDC A, #data Add immediate data to Acc with Carry 2 12 2 6x
SUBB A, Rn Subtract Register from Acc wih borrow 1 12 2 6x
SUBB A, direct Subtract direct byte from Acc with borrow 2 12 3 4x
SUBB A, @Ri Subtract indirect RAM from ACC with borrow 1 12 3 4x
SUBB A, #data Substract immediate data from ACC with borrow 2 12 2 6x
INC A Increment Accumulator 1 12 2 6x
INC Rn Increment register 1 12 3 4x
INC direct Increment direct byte 2 12 4 3x
INC @Ri Increment direct RAM 1 12 4 3x
DEC A Decrement Accumulator 1 12 2 6x
DEC Rn Decrement Register 1 12 3 4x
DEC direct Decrement direct byte 2 12 4 3x
DEC @Ri Decrement indirect RAM 1 12 4 3x
INC DPTR Increment Data Pointer 1 24 1 24x
MUL AB Multiply A & B 1 48 4 12x
DIV AB Divde A by B 1 48 5 9.6x
DA A Decimal Adjust Accumulator 1 12 4 3x


LOGICAL OPERATIONS
ANL A, Rn AND Register to Accumulator 1 12 2 6x
ANL A, direct AND direct btye to Accumulator 2 12 3 4x
ANL A, @Ri AND indirect RAM to Accumulator 1 12 3 4x
ANL A, #data AND immediate data to Accumulator 2 12 2 6x
ANL direct, A AND Accumulator to direct byte 2 12 4 3x
ANL direct, #data AND immediate data to direct byte 3 24 4 6x
ORL A, Rn OR register to Accumulator 1 12 2 6x
ORL A,direct OR direct byte to Accumulator 2 12 3 4x
.
ORL A,@Ri OR indirect RAM to Accumulator 1 12 3 4x
ed
ORL A, #data OR immediate data to Accumulator 2 12 2 6x
ORL direct, A OR Accumulator to direct byte 2
i m i
12
t 4 3x
L
ORL direct,#data OR immediate data to direct byte 3 24 4 6x
XRL A, Rn Exclusive-OR register to Accumulator 1 12 2 6x
CU
XRL A, direct Exclusive-OR direct byte to Accumulator 2 12 3 4x
M
XRL A, @Ri Exclusive-OR indirect RAM to 1 12 3 4x
Accumulator
XRL A, #data Exclusive-OR immediate data to 2 12 2 6x
T C
Accumulator
S
XRL direct, A Exclusive-OR Accumulator to direct byte 2 12 4 3x
XRL direct,#data Exclusive-OR immediate data to direct 3 24 4 6x
byte
CLR A Clear Accumulator 1 12 1 12x
CPL A Complement Accumulator 1 12 2 6x
RL A Rotate Accumulator Left 1 12 1 12x
RLC A Rotate Accumulator Left through the Carry 1 12 1 12x
RR A Rotate Accumulator Right 1 12 1 12x
RRC A Rotate Accumulator Right through the 1 12 1 12x
Carry
SWAP A Swap nibbles within the Accumulator 1 12 1 12x


DATA TRANSFER
MOV A, Rn Move register to Accumulator 1 12 1 12x
MOV A, direct Move direct byte to Accumulator 2 12 2 6x
MOV A,@Ri Move indirect RAM to 1 12 2 6x
MOV A, #data Move immediate data to Accumulator 2 12 2 6x
MOV Rn, A Move Accumulator to register 1 12 2 6x
MOV Rn, direct Move direct byte to register 2 24 4 6x
MOV Rn, #data Move immediate data to register 2 12 2 6x
MOV direct, A Move Accumulator to direct byte 2 12 3 4x
MOV direct, Rn Move register to direct byte 2 24 3 8x
MOV direct,direct Move direct byte to direct 3 24 4 6x
d .
MOV direct, @Ri Move indirect RAM to direct byte 2 24 4 6x
mit e
MOV direct, #data Move immediate data to direct byte 3 24 3 8x
MOV @Ri, A Move Accumulator to indirect RAM 1 12 3 4x
Li
MOV @Ri, direct Move direct byte to indirect RAM 2 24 4 6x
MOV @Ri, #data Move immediate data to indirect RAM 2 12 3 4x
MOV DPTR, #data16 Move immdiate data to indirect RAM 2 24 3 8x
C U
MOVC A, @A+DPTR Move Code byte relative to DPTR to Acc 1 24 4 6x
M
MOVC A, @A+PC Move Code byte relative to PC to Acc 1 24 4 6x
MOVX A, @Ri Move External RAM(8-bit addr) to Acc 1 24 3 8x
MOVX @Ri, A Move Acc to External RAM(8-bit addr) 1 24 4 6x
T C
MOVX A, @DPTR Move External RAM(16-bit addr) to Acc 1 24 3 8x
S
MOVX @DPTR, A Move Acc to External RAM (16-bit addr) 1 24 3 8x
PUSH direct Push direct byte onto stack 2 24 4 6x
POP direct POP direct byte from stack 2 24 3 8x
XCH A, Rn Exchange register with Accumulator 1 12 3 4x
XCH A, direct Exchange direct byte with Accumulator 2 12 4 3x
XCH A, @Ri Exchange indirect RAM with Accumulator 1 12 4 3x
XCHD A, @Ri Exchange low-order Digit indirect RAM 1 12 4 3x
with Acc


BOOLEAN VARIABLE MANIPULATION
CLR C Clear Carry 1 12 1 12x
CLR bit Clear direct bit 2 12 4 3x
SETB C Set Carry 1 12 1 12x
SETB bit Set direct bit 2 12 4 3x
CPL C Complement Carry 1 12 1 12x
CPL bit Complement direct bit 2 12 4 3x
ANL C, bit AND direct bit to Carry 2 24 3 8x
ANL C, /bit AND complement of direct bit to Carry 2 24 3 8x
ORL C, bit OR direct bit to Carry 2 24 3 8x
ORL C, /bit OR complement of direct bit to Carry 2 24 3 8x
.
MOV C, bit Move direct bit to Carry 2 12 3 4x
ed
MOV bit, C Move Carry to direct bit 2 24 4 6x
i t
JC rel Jump if Carry is set 2 24 3 8x
Li m
JNC rel Jump if Carry not set 2 24 3 8x
JB bit, rel Jump if direct bit is set 3 24 4 6x
JNB bit,rel Jump if direct bit is not set 3 24 4 6x
U
JBC bit, rel Jump if direct bit is set & clear bit 3 24 5 4.8x
C
PROGRAM BRANCHING
M
ACALL addr11 Absolute Subroutine Call 2 24 6 4x
LCALL addr16 Long Subroutine Call 3 24 6 4x
T C
RET Return from Subroutine 1 24 4 6x
S
RETI Return from interrupt 1 24 4 6x
AJMP addr11 Absolute Jump 2 24 3 8x
LJMP addr16 Long Jump 3 24 4 6x
SJMP rel Short Jump (relative addr) 2 24 3 8x
JMP @A+DPTR Jump indirect relative to the DPTR 1 24 3 8x
JZ rel Jump if Accumulator is Zero 2 24 3 8x
JNZ rel Jump if Accumulator is not Zero 2 24 3 8x
CJNE A,direct,rel Compare direct byte to Acc and jump if 3 24 5 4.8x
not equal
CJNE A,#data,rel Compare immediate to Acc and Jump if 3 24 4 6x
not equal
CJNE Rn,#data,rel Compare immediate to register and Jump 3 24 4 6x
if not equal
CJNE @Ri,#data,rel Compare immediate to indirect and jump 3 24 5 4.8x
if not equal
DJNZ Rn, rel Decrement register and jump if not Zero 2 24 4 6x
DJNZ direct, rel Decrement direct byte and Jump if not 3 24 5 4.8x
Zero
NOP No Operation 1 12 1 12x

Instruction execution speed boost summary:

24 times faster execution speed 1
9.6 times faster execution speed 1
4.8 times faster execution speed 4
Based on the analysis of frequency of use order statistics, STC 1T series MCU instruction execution speed is
faster than the traditional 8051 MCU 8 ~ 12 times in the same working environment.
Instruction execution clock count:
ed .
mit
1 clock instruction 12
Li
U
C
M
S T C

5.3 Instruction Definitions

ACALL addr 11
Function: Absolute Call
Description: ACALL unconditionally calls a subroutine located at the indicated address.The instruction
increments the PC twice to obtain the address of the following instruction, then pushes the
16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice.
The destination address is obtained by suceesively concatenating the five high-order bits of
the incremented PC opcode bits 7-5,and the second byte of the instruction. The subroutine
called must therefore start within the same 2K block of the program memory as the first
byte of the instruction following ACALL. No flags are affected.
Example: Initially SP equals 07H. The label SUBRTN is at program memory location 0345H. After
executingthe instruction,
d .
ACALL SUBRTN
i t e
at location 0123H, SP will contain 09H, internal RAM locations 08H and 09H will contain
m
Li
25H and 01H, respectively, and the PC will contain 0345H.
Bytes: 2
Cycles: 2
Encoding: a10 a9 a8 1
C
0 0 1 0
U a7 a6 a5 a4 a3 a2 a1 a0
M
Operation: ACALL
(PC)

(PC)+ 2
T C
(SP)

(SP) +
1
S
((sP))

(PC7-0)
(SP)

(SP) +
1
((SP))

(PC15-8)
(PC10-0)

page
address
ADD A,<src-byte>
Function: Add
Description: ADD adds the byte variable indicated to the Accumulator, leaving the result in the
Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-
out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag
indicates an overflow occured.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit
6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number
produced as the sum of two positive operands, or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register,direct register-indirect, or
immediate.
Example: The Accumulator holds 0C3H(11000011B) and register 0 holds 0AAH (10101010B). The
instruction,
ADD A,R0
will leave 6DH (01101101B) in the Accumulator with the AC flag cleared and both the carry
flag and OV set to 1.

ADD A,Rn
Bytes: 1
Cycles: 1
Encoding: 0 0 1 0 1 r r r
Operation: ADD
(A)

(A)
+
(Rn)
ADD A,direct
Bytes: 2
Cycles: 1
Encoding: 0 0 1 0 0 1 0 1 direct address
.
Operation: ADD
ed
(A)

(A)
+
(direct)
mit
ADD A,@Ri
Li
Bytes: 1
Cycles: 1
U
Encoding: 0 0 1 0 0 1 1 i
Operation: ADD
(A)

(A)
+
((Ri))
M C
C
ADD A,#data
S T
Bytes: 2
Cycles: 1
Encoding: 0 0 1 0 0 1 0 0 immediate data
Operation: ADD
(A)

(A)
+
#data
ADDC A,<src-byte>
Function: Add with Carry
Description: ADDC simultaneously adds the byte variable indicated, the Carry flag and the Accumulator,
leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively,
if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned
integers, the carry flag indicates an overflow occured.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not
out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative
number produced as the sum of two positive operands or a positive sum from two negative
operands.
Four source operand addressing modes are allowed: register, direct, register-indirect, or
immediate.
Example: The Accumulator holds 0C3H(11000011B) and register 0 holds 0AAH (10101010B) with the
Carry. The instruction,
ADDC A,R0
will leave 6EH (01101101B) in the Accumulator with the AC flag cleared and both the carry
flag and OV set to 1.

ADDC A,Rn
Bytes: 1
Cycles: 1
Operation: ADDC
(A)

(A)
+
(C)
+
(Rn)
ADDC A,direct
Bytes: 2
Cycles: 1
d .
Operation: ADDC
t e
(A)

(A)
+
(C)
+
(direct)
m i
Li
ADDC A,@Ri
Bytes: 1
Cycles: 1
Encoding: 0 0 1 1
C
0 1 1 i
U
M
Operation: ADDC
(A)

(A)
+
(C)
+
((Ri))
ADDC A,#data
Bytes:
Cycles:
S
2
1 T C
Operation: ADDC
(A)

(A)
+
(C)
+
#data
AJMP addr 11
Function: Absolute Jump
Description: AJMP transfers program execution to the indicated address, which is formed at run-time by
concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode
bits 7-5, and the second byte of the instruction. The destination must therefore be within the
same 2K block of program memory as the first byte of the instruction following AJMP.
Example: The label JMPADR is at program memory location 0123H. The instruction,
AJMP JMPADR
is at location 0345H and will load the PC with 0123H.
Bytes: 2
Cycles: 2
Encoding: a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0
Operation: AJMP
(PC)

(PC)+ 2
(PC10-0)

page
address

ANL <dest-byte> , <src-byte>
Function: Logical-AND for byte variables
Description: ANL performs the bitwise logical-AND operation between the variables indicated and stores
the results in the destination variable. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the
Accumulator, the source can use register, direct, register-indirect, or immediate addressing;
when the destination is a direct address, the source can be the Accumulator or immediate
data.
Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch not the input pins.
Example: If the Accumulator holds 0C3H(11000011B) and register 0 holds 55H (01010101B) then the
.
instruction,
ed
ANL A,R0
mit
will leave 41H (01000001B) in the Accumulator.
Li
When the destination is a directly addressed byte, this instruction will clear combinations of
bits in any RAM location or hardware register. The mask byte determining the pattern of bits
to be cleared would either be a constant contained in the instruction or a value computed in
C U
the Accumulator at run-time. The instruction,
M
ANL Pl, #01110011B
will clear bits 7, 3, and 2 of output port 1.
ANL A,Rn
Bytes:
Cycles:
S
1
1T C
Operation: ANL
(A)

(A) (Rn)
ANL A,direct
Bytes: 2
Cycles: 1
Operation: ANL
(A)

(A) (direct)
ANL A,@Ri
Bytes: 1
Cycles: 1
Encoding: 0 1 0 1 0 1 1 i
Operation: ANL
(A)

(A) ((Ri))

ANL A,#data
Bytes: 2
Cycles: 1
Operation: ANL
(A)

(A) #data
ANL direct,A
Bytes: 2
Cycles: 1
d .
Operation: ANL
i t e
(direct)

(direct) (A)
Li m
ANL direct,#data
Bytes: 3
CU
Cycles: 2
Encoding: 0 1 0 1 0 0 1 1 direct address immediate data
Operation: ANL
M
C
(direct)

(direct) #data
ANL C , <src-bit>
Function:
Description: S T
Logical-AND for bit variables
If the Boolean value of the source bit is a logical 0 then clear the carry flag; otherwise
leave the carry flag in its current state. A slash ( / ) preceding the operand in the assembly
language indicates that the logical complement of the addressed bit is used as the source
value, but the source bit itself is not affceted. No other flsgs are affected.
Only direct addressing is allowed for the source operand.

Example: Set the carry flag if, and only if, P1.0 = 1, ACC. 7 = 1, and OV = 0:
MOV C, P1.0 ;LOAD CARRY WITH INPUT PIN STATE
ANL C, ACC.7 ;AND CARRY WITH ACCUM. BIT.7
ANL C, /OV ;AND WITH INVERSE OF OVERFLOW FLAG

ANL C,bit
Bytes: 2
Cycles: 2
Encoding: 1 0 0 0 0 0 1 0 bit address
Operation: ANL
(C)

(C) (bit)

ANL C, /bit
Bytes: 2
Cycles: 2
Operation: ADD
(C) (bit)
(C)

CJNE <dest-byte>, <src-byte>, rel

Function: Compare and Jump if Not Equal
Description: CJNE compares the magnitudes of the first two operands, and branches if their values are not
equal. The branch destination is computed by adding the signed relative-displacement in the
last instruction byte to the PC, after incrementing the PC to the start of the next instruction.
d .
The carry flag is set if the unsigned integer value of <dest-byte> is less than the unsigned
mit e
integer value of <src-byte>; otherwise, the carry is cleared. Neither operand is affected.
Li
The first two operands allow four addressing mode combinations: the Accumulator may
be compared with any directly addressed byte or immediate data, and any indirect RAM
location or working register can be compared with an immediate constant.
U
Example: The Accumulator contains 34H. Register 7 contains 56H. The first instruction in the sequence
;
NOT_EQ:
CJNE
...
JC
M C R7,#60H, NOT-EQ
......
REQ_LOW
; R7 = 60H.
; IF R7 < 60H.
C
; ... ..... ; R7 > 60H.
S T
sets the carry flag and branches to the instruction at label NOT-EQ. By testing the carry flag,
this instruction determines whether R7 is greater or less than 60H.
If the data being presented to Port 1 is also 34H, then the instruction,
WAIT: CJNE A,P1,WAIT
clears the carry flag and continues with the next instruction in sequence, since the
Accumulator does equal the data read from P1. (If some other value was being input on Pl,
the program will loop at this point until the P1 data changes to 34H.)
CJNE A,direct,rel
Bytes: 3
Cycles: 2
Encoding: 1 0 1 1 0 1 0 1 direct address rel. address
Operation: (PC)

(PC)
+ 3
IF (A) < > (direct)
THEN
(PC)

+ relative offset
(PC)
IF (A) < (direct)
THEN
(C)
1
ELSE
(C)
0

CJNE A,#data,rel
Bytes: 3
Cycles: 2
Encoding: 1 0 1 1 0 1 0 1 immediata data rel. address
Operation: (PC)

(PC)
+ 3
IF (A) < > (data)
THEN
(PC)

+ relative offset
(PC)
IF (A) < (data)
THEN
(C)
1
ELSE
d .
(C)
0
i t e
CJNE Rn,#data,rel
Li m
Bytes: 3
Cycles: 2
U
Encoding: 1 0 1 1 1 r r r immediata data rel. address
Operation: (PC)

(PC)
+ 3
IF (Rn) < > (data)
THEN
M C
S T C (PC)

IF (Rn) < (data)
THEN
(C)
1
+ relative offset
(PC)
ELSE
(C)
0
CJNE @Ri,#data,rel
Bytes: 3
Cycles: 2
Encoding: 1 0 1 1 0 1 1 i immediate data rel. address
Operation: (PC)

(PC)
+ 3
IF ((Ri)) < > (data)
THEN
(PC)

+ relative offset
(PC)
IF ((Ri)) < (data)
THEN
(C)
1
ELSE
(C)
0

CLR A
Function: Clear Accumulator
Description: The Aecunmlator is cleared (all bits set on zero). No flags are affected.
Example: The Accumulator contains 5CH (01011100B). The instruction,
CLR A
will leave the Accumulator set to 00H (00000000B).
Bytes: 1
Cycles: 1
Encoding: 1 1 1 0 0 1 0 0
Operation: CLR
.
(A)
0
ed
mit
CLR bit
Function: Clear bit
Li
Description: The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on
the carry flag or any directly addressable bit.
U
Example: Port 1 has previously been written with 5DH (01011101B). The instruction,
CLR P1.2
M C
will leave the port set to 59H (01011001B).
C
CLR C
T
Bytes: 1
Cycles:
Encoding:
Operation:
S1
CLR
1 1 0 0 0 0 1 1
(C)
0
CLR bit
Bytes: 2
Cycles: 1
Operation: CLR
(bit)
0

CPL A
Function: Complement Accumulator
Description: Each bit of the Accumulator is logically complemented (ones complement). Bits which
previously contained a one are changed to a zero and vice-versa. No flags are affected.
Example: The Accumulator contains 5CH(01011100B). The instruction,
CPL A
will leave the Accumulator set to 0A3H (101000011B).

Bytes: 1
Cycles: 1
Encoding: 1 1 1 1 0 1 0 0
Operation: CPL
t ed .
i
(A)
(A)
Li m
CPL bit
Function: Complement bit
U
Description: The bit variable specified is complemented. A bit which had been a one is changed to zero
C
and vice-versa. No other flags are affected. CLR can operate on the carry or any directly
M
addressable bit.
C
Note:When this instruction is used to modify an output pin, the value used as the original
T
data will be read from the output data latch, not the input pin.
S
Example: Port 1 has previously been written with 5DH (01011101B). The instruction,
CLR P1.1
CLR P1.2
will leave the port set to 59H (01011001B).

CPL C
Bytes: 1
Cycles: 1
Encoding: 1 0 1 1 0 0 1 1
Operation: CPL
(C)
(C)
CPL bit
Bytes: 2
Cycles: 1
Operation: CPL
(bit)
(bit)

DA A
Function: Decimal-adjust Accumulator for Addition
Description: DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of
two variables (each in packed-BCD format), producing two four-bit digits.Any ADD or
ADDC instruction may have been used to perform the addition.
If Accumulator bits 3-0 are greater than nine (xxxx1010-xxxx1111), or if the AC flag is one,
six is added to the Accumulator producing the proper BCD digit in the low-order nibble.
This internal addition would set the carry flag if a carry-out of the low-order four-bit field
propagated through all high-order bits, but it would not clear the carry flag otherwise.
If the carry flag is now set or if the four high-order bits now exceed nine(1010xxxx-
111xxxx), these high-order bits are incremented by six, producing the proper BCD digit
in the high-order nibble. Again, this would set the carry flag if there was a carry-out of the
d .
high-order bits, but wouldnt clear the carry. The carry flag thus indicates if the sum of
mit e
the original two BCD variables is greater than 100, allowing multiple precision decimal
addition. OV is not affected.
Li
All of this occurs during the one instruction cycle. Essentially, this instruction performs the
decimal conversion by adding 00H, 06H, 60H, or 66H to the Accumulator, depending on
U
initial Accumulator and PSW conditions.
M C
Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD
notation, nor does DA A apply to decimal subtraction.
C
Example: The Accumulator holds the value 56H(01010110B) representing the packed BCD digits of
T
the decimal number 56. Register 3 contains the value 67H (01100111B) representing the
S
packed BCD digits of the decimal number 67.The carry flag is set. The instruction sequence.
ADDC A,R3
DA A
will first perform a standard twos-complement binary addition, resulting in the value 0BEH
(10111110) in the Accumulator. The carry and auxiliary carry flags will be cleared.
The Decimal Adjust instruction will then alter the Accumulator to the value 24H
(00100100B), indicating the packed BCD digits of the decimal number 24, the low-order
two digits of the decimal sum of 56,67, and the carry-in. The carry flag will be set by the
Decimal Adjust instruction, indicating that a decimal overflow occurred. The true sum 56,
67, and 1 is 124.
BCD variables can be incremented or decremented by adding 01H or 99H. If the Accumula-
tor initially holds 30H (representing the digits of 30 decimal), then the instruction sequence,
ADD A,#99H
DA A
will leave the carry set and 29H in the Accumulator, since 30+99=129. The low-order byte
of the sum can be interpreted to mean 30 1 = 29.

Bytes: 1
Cycles: 1
Encoding: 1 1 0 1 0 1 0 0
Operation: DA
-contents of Accumulator are BCD
IF [[(A3-0) > 9] V [(AC) = 1]]
THEN(A3-0)

(A3-0) + 6
AND
IF [[(A7-4) > 9] V [(C) = 1]]
THEN (A7-4)

(A7-4) + 6
DEC byte
.
Function: Decrement
ed
Description: The variable indicated is decremented by 1. An original value of 00H will underflow to
i t
0FFH.
Li m
No flags are affected. Four operand addressing modes are allowed: accumulator, register,
direct, or register-indirect.
U
port data will be read from the output data latch, not the input pins.
Example:
C
Register 0 contains 7FH (01111111B). Internal RAM locations 7EH and 7FH contain 00H
M
and 40H, respectively. The instruction sequence,
C
DEC @R0
S T
DEC
DEC
R0
@R0
will leave register 0 set to 7EH and internal RAM locations 7EH and 7FH set to 0FFH and
3FH.
DEC A
Bytes: 1
Cycles: 1
Encoding: 0 0 0 1 0 1 0 0
Operation: DEC
(A)

(A) -1
DEC Rn
Bytes: 1
Cycles: 1
Operation: DEC
(Rn)

(Rn) - 1

DEC direct
Bytes: 2
Cycles: 1
Operation: DEC
(direct)

(direct) -1
DEC @Ri
Bytes: 1
Cycles: 1
Encoding: 0 0 0 1 0 1 1 i
.
Operation:
d
DEC
mit e
((Ri))

((Ri)) - 1
Li
DIV AB
Function: Divide
Description: DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit
C U
integer in register B. The Accumulator receives the integer part of the quotient; register B
receives the integer remainder. The carry and OV flags will be cleared.
M
Exception: if B had originally contained 00H, the values returned in the Accumulator and
C
B-register will be undefined and the overflow flag will be set. The carry flag is cleared in any
T
case.
Example:
SThe Accumulator contains 251(OFBH or 11111011B) and B contains 18(12H or 00010010B).
The instruction,
DIV AB
will leave 13 in the Accumulator (0DH or 00001101B) and the value 17 (11H or 00010010B)
in B, since 251 = (1318) + 17. Carry and OV will both be cleared.
Bytes: 1
Cycles: 4
Encoding: 1 0 0 0 0 1 0 0
Operation: DIV
(A)15-8
(A)/(B)
(B)7-0

DJNZ <byte>, <rel-addr>

Function: Decrement and Jump if Not Zero
Description: DJNZ decrements the location indicated by 1, and branches to the address indicated by the
second operand if the resulting value is not zero. An original value of 00H will underflow to
0FFH. No flags are afected. The branch destination would be computed by adding the signed
relative-displacement value in the last instruction byte to the PC, after incrementing the PC
to the first byte of the following instruction.
The location decremented may be a register or directly addressed byte.
Example: Internal RAM locations 40H, 50H, and 60H contain the values 01H, 70H, and 15H,
respectively. The instruction sequence,
DJNZ 40H, LABEL_1
t ed .
i
DJNZ 50H, LABEL_2
Li m
DJNZ 60H, LABEL_3
will cause a jump to the instruction at label LABEL_2 with the values 00H, 6FH, and 15H in
the three RAM locations. The first jump was not taken because the result was zero.
U
This instruction provides a simple way of executing a program loop a given number of times,
M C
or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction
The instruction sequence,
C
MOV R2,#8
T
TOOOLE: CPL P1.7
S
DJNZ R2, TOOGLE
will toggle P1.7 eight times, causing four output pulses to appear at bit 7 of output Port 1.
Each pulse will last three machine cycles; two for DJNZ and one to alter the pin.
DJNZ Rn,rel
Bytes: 2
Cycles: 2
Encoding: 1 1 0 1 1 r r r rel. address
Operation: DJNZ
(PC)

(PC)
+ 2
(Rn)

(Rn) 1
IF (Rn) > 0 or (Rn) < 0
THEN
(PC)

(PC)+
rel
DJNZ direct, rel
Bytes: 3
Cycles: 2
Encoding: 1 1 0 1 0 1 0 1 direct address rel. address

Operation: DJNZ
(PC)

(PC)
+ 2
(direct)

(direct) 1
IF (direct) > 0 or (direct) < 0
THEN
(PC)

(PC) +
rel
INC <byte>
Function: Increment
Description: INC increments the indicated variable by 1. An original value of 0FFH will overflow to
00H.No flags are affected. Three addressing modes are allowed: register, direct, or register-
indirect.
.
ed
mit
Example: Register 0 contains 7EH (011111110B). Internal RAM locations 7EH and 7FH contain 0FFH
Li
and 40H, respectively. The instruction sequence,
INC @R0
U
INC R0
C
INC @R0
M
will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding
C
(respectively) 00H and 41H.
S T
INC A
Bytes: 1
Cycles: 1
Encoding: 0 0 0 0 0 1 0 0
Operation: INC
(A)

(A)+1
INC Rn
Bytes: 1
Cycles: 1
Operation: INC
(Rn)

(Rn)+1
INC direct
Bytes: 2
Cycles: 1
Operation: INC
(direct)

(direct) + 1

INC @Ri
Bytes: 1
Cycles: 1
Encoding: 0 0 0 0 0 1 1 i
Operation: INC
((Ri))

((Ri))
+ 1
INC DPTR
Function: Increment Data Pointer
Description: Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 216) is performed; an
overflow of the low-order byte of the data pointer (DPL) from 0FFH to 00H will increment
.
the high-order-byte (DPH). No flags are affected.
d
This is the only 16-bit register which can be incremented.
Example:
i t e
Register DPH and DPL contains 12H and 0FEH,respectively. The instruction sequence,
m
Li
INC DPTR
INC DPTR
INC DPTR
U
will change DPH and DPL to 13H and 01H.
Bytes:
Cycles:
1
2
M C
C
Encoding:
T
1 0 1 0 0 0 1 1
S
Operation: INC
(DPTR)

(DPTR)+1
JB bit, rel
Function: Jump if Bit set
Description: If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement
in the third instruction byte to the PC, after incrementing the PC to the first byte of the next
instruction. The bit tested is not modified. No flags are affected.
Example: The data present at input port 1 is 11001010B. The Accumulator holds 56 (01010110B). The
instruction sequence,
JB P1.2, LABEL1
JB ACC.2, LABEL2
will cause program execution to branch to the instruction at label LABEL2.
Bytes: 3
Cycles: 2
Encoding: 0 0 1 0 0 0 0 0 bit address rel. address
Operation: JB
(PC)

(PC)+ 3
IF (bit) = 1
THEN
(PC)

(PC)
+
rel

JBC bit, rel

Function: Jump if Bit is set and Clear bit
Description: If the indicated bit is one,branch to the address indicated;otherwise proceed with the next
instruction.The bit wili not be cleared if it is already a zero. The branch destination is
computed by adding the signed relative-displacement in the third instruction byte to the PC,
after incrementing the PC to the first byte of the next instruction. No flags are affected.
Note: When this instruction is used to test an output pin, the value used as the original data
will be read from the output data latch, not the input pin.
Example: The Accumulator holds 56H (01010110B). The instruction sequence,
JBC ACC.3, LABEL1
JBC ACC.2, LABEL2
will cause program execution to continue at the instruction identified by the label LABEL2,
d .
with the Accumulator modified to 52H (01010010B).
mit e
Bytes: 3
Li
Cycles: 2
U
Operation: JBC
C
(PC)

(PC)+ 3
M
IF (bit) = 1
THEN
(bit)
0
T C
(PC)

(PC)
+
rel
S
JC rel
Function: Jump if Carry is set
Description: If the carry flag is set, branch to the address indicated; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in
the second instruction byte to the PC, after incrementing the PC twice.No flags are affected.
Example: The carry flag is cleared. The instruction sequence,
JC LABEL1
CPL C
JC LABEL2s
will set the carry and cause program execution to continue at the instruction identified by the
label LABEL2.
Bytes: 2
Cycles: 2
Encoding: 0 1 0 0 0 0 0 0 rel. address
Operation: JC
(PC)

(PC)+ 2
IF (C) = 1
THEN
(PC)

(PC)
+
rel

JMP @A+DPTR
Function: Jump indirect
Description: Add the eight-bit unsigned contents of the Accumulator with the sixteen-bit data pointer,
and load the resulting sum to the program counter. This will be the address for subsequent
instruction fetches. Sixteen-bit addition is performed (modulo 216): a carry-out from the low-
order eight bits propagates through the higher-order bits. Neither the Accumulator nor the
Data Pointer is altered. No flags are affected.
Example: An even number from 0 to 6 is in the Accumulator. The following sequence of instructions
will branch to one of four AJMP instructions in a jump table starting at JMP_TBL:
MOV DPTR, #JMP_TBL
JMP @A+DPTR
JMP-TBL: AJMP LABEL0
.
AJMP LABEL1
ed
AJMP LABEL2
i t
AJMP LABEL3
Li m
If the Accumulator equals 04H when starting this sequence, execution will jump to label
LABEL2. Remember that AJMP is a two-byte instruction, so the jump instructions start at
every other address.
C U
Bytes: 1
M
Cycles: 2
Encoding: 0 1 1 1 0 0 1 1
Operation:
JNB bit, rel T

JMP
S C
(PC)

(A)
+
(DPTR)
Function: Jump if Bit is not set

Description: If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next
in the third instruction byte to the PC, after incrementing the PC to the first byte of the next
instruction. The bit tested is not modified. No flags are affected.
Example: The data present at input port 1 is 11001010B. The Accumulator holds 56H (01010110B).
The instruction sequence,
JNB P1.3, LABEL1
JNB ACC.3, LABEL2
will cause program execution to continue at the instruction at label LABEL2
Bytes: 3
Cycles: 2
Operation: JNB
(PC)

(PC)+ 3
IF (bit) = 0
THEN (PC)

(PC)
+
rel

JNC rel
Function: Jump if Carry not set
Description: If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next
in the second instruction byte to the PC, after incrementing the PC twice to point to the next
instruction. The carry flag is not modified
Example: The carry flag is set. The instruction sequence,
JNC LABEL1
CPL C
JNC LABEL2
will clear the carry and cause program execution to continue at the instruction identified by
d .
the label LABEL2.
Bytes: 2
mit e
Li
Cycles: 2
U
Operation: JNC
C
(PC)

(PC)+ 2
M
IF (C) = 0
THEN (PC)

(PC)
+
rel
C
JNZ rel
Function:
Description:
S T
Jump if Accumulator Not Zero
If any bit of the Accumulator is a one, branch to the indicated address; otherwise proceed
with the next instruction. The branch destination is computed by adding the signed relative-
displacement in the second instruction byte to the PC, after incrementing the PC twice. The
Accumulator is not modified. No flags are affected.
Example: The Accumulator originally holds 00H. The instruction sequence,
JNZ LABEL1
INC A
JNZ LAEEL2
will set the Accumulator to 01H and continue at label LABEL2.

Bytes: 2
Cycles: 2
Operation: JNZ
(PC)

(PC)+ 2
IF (A) 0
THEN (PC)

(PC)
+
rel

JZ rel
Function: Jump if Accumulator Zero
Description: If all bits of the Accumulator are zero, branch to the address indicated; otherwise proceed
with the next instruction. The branch destination is computed by adding the signed relative-
displacement in the second instruction byte to the PC, after incrementing the PC twice. The
Accumulator is not modified. No flags are affected.
Example: The Accumulator originally contains 01H. The instruction sequence,
JZ LABEL1
DEC A
JZ LAEEL2
will change the Accumulator to 00H and cause program execution to continue at the
instruction identified by the label LABEL2.
.
Bytes: 2
ed
Cycles: 2
m i t
Li
Operation: JZ
(PC)

(PC)+ 2
U
IF (A) = 0
C
THEN (PC)

(PC)
+
rel
LCALL addr16
M
C
Function: Long call
T
Description: LCALL calls a subroutine loated at the indicated address. The instruction adds three to the
S
program counter to generate the address of the next instruction and then pushes the 16-bit
result onto the stack (low byte first), incrementing the Stack Pointer by two. The high-order
and low-order bytes of the PC are then loaded, respectively, with the second and third bytes
of the LCALL instruction. Program execution continues with the instruction at this address.
The subroutine may therefore begin anywhere in the full 64K-byte program memory address
space. No flags are affected.
Example: Initially the Stack Pointer equals 07H. The label SUBRTN is assigned to program memory
location 1234H. After executing the instruction,
LCALL SUBRTN
at location 0123H, the Stack Pointer will contain 09H, internal RAM locations 08H and 09H
will contain 26H and 01H, and the PC will contain 1234H.
Bytes: 3
Cycles: 2
Encoding: 0 0 0 1 0 0 1 0 addr15-addr8 addr7-addr0
Operation: LCALL
(PC)

(PC)
+ 3
(SP)

(SP)
+ 1
((SP))

(PC7-0)
(SP)

(SP)
+ 1
((SP))

(PC15-8)
(PC)

addr15-0

LJMP addr16
Function: Long Jump
Description: LJMP causes an unconditional branch to the indicated address, by loading the high-order
and low-order bytes of the PC (respectively) with the second and third instruction bytes. The
destination may therefore be anywhere in the full 64K program memory address space. No
flags are affected.
Example: The label JMPADR is assigned to the instruction at program memory location 1234H. The
instruction,
LJMP JMPADR
at location 0123H will load the program counter with 1234H.
.
Bytes: 3
ed
mit
Cycles: 2
Encoding: 0 0 0 0 0 0 1 0 addr15-addr8 addr7-addr0
Li
Operation: LJMP
(PC)

addr15-0
MOV <dest-byte> , <src-byte>
C U
M
Function: Move byte variable
Description: The byte variable indicated by the second operand is copied into the location specified by the
C
first operand. The source byte is not affected. No other register or flag is affected.
Example:
S T
This is by far the most flexible operation. Fifteen combinations of source and destination
addressing modes are allowed.
Internal RAM location 30H holds 40H. The value of RAM location 40H is 10H. The data
present at input port 1 is 11001010B (0CAH).
MOV R0, #30H ;R0< = 30H

MOV A, @R0 ;A < = 40H
MOV R1, A ;R1 < = 40H
MOV B, @Rl ;B < = 10H
MOV @Rl, Pl ;RAM (40H) < = 0CAH
MOV P2, P1 ;P2 #0CAH
leaves the value 30H in register 0,40H in both the Accumulator and register 1,10H in register
B, and 0CAH(11001010B) both in RAM location 40H and output on port 2.
MOV A,Rn
Bytes: 1
Cycles: 1
Operation: MOV
(A)

(Rn)

*MOV A,direct
Bytes: 2
Cycles: 1
Operation: MOV
(A)

(direct)
*MOV A, ACC is not a valid instruction
MOV A,@Ri
Bytes: 1
Cycles: 1
.
Encoding: 1 1 1 0 0 1 1 i
t ed
Operation: MOV
i
(A)

((Ri))
MOV A,#data
Bytes: 2
Li m
CU
Cycles: 1
Encoding:
M
0 1 1 1 0 1 0 0 immediate data
Operation: MOV
C
(A)

#data
MOV Rn, A
Bytes:
Cycles: S
1
1
T
Operation: MOV
(Rn)

(A)
MOV Rn,direct
Bytes: 2
Cycles: 2
Encoding: 1 0 1 0 1 r r r direct addr.
Operation: MOV
(Rn)

(direct)
MOV Rn,#data
Bytes: 2
Cycles: 1
Encoding: 0 1 1 1 1 r r r immediate data
Operation: MOV
(Rn)

#data

MOV direct, A
Bytes: 2
Cycles: 1
Operation: MOV
(direct)

(A)
MOV direct, Rn
Bytes: 2
Cycles: 2
Encoding: 1 0 0 0 1 r r r direct address
d .
Operation: MOV
mit e
(direct)

(Rn)
MOV direct, direct
Li
Bytes: 3
Cycles: 2
Encoding: 1 0 0 0
C
0 1 0 1
U dir.addr. (src)
M
Operation: MOV
(direct)

(direct)
C
MOV direct, @Ri
Bytes:
Cycles:
Encoding:
S
2
2T 1 0 0 0 0 1 1 i direct addr.
Operation: MOV
(direct)

((Ri))
MOV direct,#data
Bytes: 3
Cycles: 2
Operation: MOV
(direct)

#data
MOV @Ri, A
Bytes: 1
Cycles: 1
Encoding: 1 1 1 1 0 1 1 i
Operation: MOV
((Ri))
(A)


MOV @Ri, direct

Bytes: 2
Cycles: 2
Encoding: 1 0 1 0 0 1 1 i direct addr.
Operation:
MOV
((Ri))
(direct)

MOV @Ri, #data
Bytes: 2
Cycles: 1
Encoding: 0 1 1 1 0 1 1 i immediate data
d .
Operation: MOV
t e
((Ri))

#data
m i
Li
MOV <dest-bit> , <src-bit>
Function: Move bit data
U
Description: The Boolean variable indicated by the second operand is copied into the location specified by
C
the first operand. One of the operands must be the carry flag; the other may be any directly
M
addressable bit. No other register or flag is affected.
Example: The carry flag is originally set. The data present at input Port 3 is 11000101B. The data
T C
previously written to output Port 1 is 35H (00110101B).
S
MOV
MOV
MOV
P1.3, C
C, P3.3
P1.2, C
will leave the carry cleared and change Port 1 to 39H (00111001B).
MOV C,bit
Bytes: 2
Cycles: 1
Operation: MOV
(C)

(bit)
MOV bit,C
Bytes: 2
Cycles: 2
Operation: MOV
(bit)

(C)


MOV DPTR , #data 16

Function: Load Data Pointer with a 16-bit constant
Description: The Data Pointer is loaded with the 16-bit constant indicated.The 16-bit constant is loaded
into the second and third bytes of the instruction. The second byte (DPH) is the high-order
byte, while the third byte (DPL) holds the low-order byte. No flags are affected.
This is the only instruction which moves 16 bits of data at once.
Example: The instruction,
MOV DPTR, #1234H
will load the value 1234H into the Data Pointer: DPH will hold 12H and DPL will hold 34H.
Bytes: 3
Cycles: 2
Encoding: 1 0 0 1 0 0 0 0 immediate data 15-8
Operation: MOV
ed .
mit
(DPTR)

#data15-0
Li
DPH DPL

#data15-8 #data7-0
MOVC A , @A+ <base-reg>
U
Function: Move Code byte
C
Description: The MOVC instructions load the Accumulator with a code byte, or constant from program
M
memory. The address of the byte fetched is the sum of the original unsigned eight-bit.
Accumulator contents and the contents of a sixteen-bit base register, which may be either
C
the Data Pointer or the PC. In the latter case, the PC is incremented to the address of the
T
following instruction before being added with the Accumulator; otherwise the base register
S
is not altered. Sixteen-bit addition is performed so a carry-out from the low-order eight bits
may propagate through higher-order bits. No flags are affected.
Example: A value between 0 and 3 is in the Accumulator. The following instructions will translate the
value in the Accumulator to one of four values defimed by the DB (define byte) directive.
REL-PC: INC A
MOVC A, @A+PC
RET
DB 66H
DB 77H
DB 88H
DB 99H
If the subroutine is called with the Accumulator equal to 01H, it will return with 77H in the
Accumulator. The INC A before the MOVC instruction is needed to get around the RET
instruction above the table. If several bytes of code separated the MOVC from the table, the
corresponding number would be added to the Accumulator instead.
MOVC A,@A+DPTR
Bytes: 1
Cycles: 2
Encoding: 1 0 0 1 0 0 1 1
Operation: MOVC
(A)

((A)+(DPTR))

MOVC A,@A+PC
Bytes: 1
Cycles: 2
Encoding: 1 0 0 0 0 0 1 1
Operation: MOVC
(PC)

(PC)+1
(A)

((A)+(PC))
MOVX <dest-byte> , <src-byte>
Function: Move External
Description: The MOVX instructions transfer data between the Accumulator and a byte of external data
memory, hence the X appended to MOV. There are two types of instructions, differing in
d .
whether they provide an eight-bit or sixteen-bit indirect address to the external data RAM.
t e
i
In the first type, the contents of R0 or R1 in the current register bank provide an eight-bit
Li m
address multiplexed with data on P0. Eight bits are sufficient for external I/O expansion
decoding or for a relatively small RAM array. For somewhat larger arrays, any output port
pins can be used to output higher-order address bits. These pins would be controlled by an
U
output instruction preceding the MOVX.
M C
In the second type of MOVX instruction, the Data Pointer generates a sixteen-bit address.
P2 outputs the high-order eight address bits (the contents of DPH) while P0 multiplexes the
C
low-order eight bits (DPL) with data. The P2 Special Function Register retains its previous
T
contents while the P2 output buffers are emitting the contents of DPH. This form is faster and
S
more efficient when accessing very large data arrays (up to 64K bytes), since no additional
instructions are needed to set up the output ports.
It is possible in some situations to mix the two MOVX types. A large RAM array with its
high-order address lines driven by P2 can be addressed via the Data Pointer, or with code to
output high-order address bits to P2 followed by a MOVX instruction using R0 or R1.
Example: An external 256 byte RAM using multiplexed address/data lines (e.g., an Intel 8155 RAM/
I/O/Timer) is connected to the 8051 Port 0. Port 3 provides control lines for the external
RAM. Ports 1 and 2 are used for normal I/O. Registers 0 and 1 contain 12H and 34H.
Location 34H of the external RAM holds the value 56H. The instruction sequence,
MOVX A, @R1
MOVX @R0, A
copies the value 56H into both the Accumulator and external RAM location 12H.
MOVX A,@Ri
Bytes: 1
Cycles: 2
Encoding: 1 1 1 0 0 0 1 i
Operation: MOVX
(A)

((Ri))

MOVX A,@DPTR
Bytes: 1
Cycles: 2
Encoding: 1 1 1 0 0 0 0 0
Operation: MOVX
(A)

((DPTR))
MOVX @Ri, A
Bytes: 1
Cycles: 2
Encoding: 1 1 1 1 0 0 1 i
d .
Operation: MOVX
mit e
((Ri))

(A)

Li
MOVX @DPTR, A
Bytes: 1
Cycles: 2
Encoding: 1 1 1 1
C
0 0 0 0
U
Operation: MOVX
(DPTR)

(A)
M
MUL AB
Function:
Description: S T C
Multiply
MUL AB multiplies the unsigned eight-bit integers in the Accumulator and register B. The
low-order byte of the sixteen-bit product is left in the Accumulator, and the high-order byte
in B. If the product is greater than 255 (0FFH) the overflow flag is set; otherwise it is cleared.
The carry flag is always cleared
Example: Originally the Accumulator holds the value 80 (50H). Register B holds the value 160
(0A0H). The instruction,
MUL AB
will give the product 12,800 (3200H), so B is changed to 32H (00110010B) and the
Accumulator is cleared. The overflow flag is set, carry is cleared.
Bytes: 1
Cycles: 4
Encoding: 1 0 1 0 0 1 0 0
Operation: MUL
(A)7-0
(A)(B)
(B)15-8

NOP
Function: No Operation
Description: Execution continues at the following instruction. Other than the PC, no registers or flags are
affected.
Example: It is desired to produce a low-going output pulse on bit 7 of Port 2 lasting exactly 5 cycles. A
simple SETB/CLR sequence would generate a one-cycle pulse, so four additional cycles
must be inserted. This may be done (assuming no interrupts are enabled) with the instruction
sequence.
CLR P2.7
NOP
NOP
NOP
d .
NOP
t e
SETB P2.7
m i
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Bytes: 1
Cycles: 1
Encoding: 0 0 0 0 0 0 0 0
Operation: NOP
C U
M
(PC)
(PC)+1
ORL <dest-byte> , <src-byte>
Function:
Description:
S T C
Logical-OR for byte variables
ORL performs the bitwise logical-OR operation between the indicated variables, storing the
results in the destination byte. No flags are affected.
The two operands allow six addressing mode combinations. When the destination is the
when the destination is a direct address, the source can be the Accumulator or immediate
data.
Example: If the Accumulator holds 0C3H (11000011B) and R0 holds 55H (01010101B) then the
instruction,
ORL A, R0
will leave the Accumulator holding the value 0D7H (11010111B).
When the destination is a directly addressed byte, the instruction can set combinations of bits
in any RAM location or hardware register. The pattern of bits to be set is determined by a
mask byte, which may be either a constant data value in the instruction or a variable
computed in the Accumulator at run-time.The instruction,
ORL P1, #00110010B
will set bits 5,4, and 1of output Port 1.

ORL A,Rn
Bytes: 1
Cycles: 1
Operation: ORL
(A)

(A)(Rn)
ORL A,direct
Bytes: 2
Cycles: 1
.
Operation: ORL
ed
mit
(A)

(A)(direct)
ORL A,@Ri
Li
Bytes: 1
Cycles: 1
U
Encoding:
C
0 1 0 0 0 1 1 i
M
Operation: ORL
(A)

(A)((Ri))
C
ORL A,#data
Bytes:
Cycles:
Encoding:
S
2
1T 0 1 0 0 0 1 0 0 immediate data
Operation: ORL
(A)

(A) #data
ORL direct, A
Bytes: 2
Cycles: 1
Operation: ORL
(direct)

(direct)(A)
ORL direct, #data
Bytes: 3
Cycles: 2
Operation: ORL
(direct)

(direct)#data

ORL C, <src-bit>
Function: Logical-OR for bit variables
Description: Set the carry flag if the Boolean value is a logical 1; leave the carry in its current state
otherwise. A slash ( / ) preceding the operand in the assembly language indicates that the
logical complement of the addressed bit is used as the source value, but the source bit itself is
not affected. No other flags are affected.
Example: Set the carry flag if and only if P1.0 = 1, ACC. 7 = 1, or OV = 0:
MOV C, P1.0 ;LOAD CARRY WITH INPUT PIN P10
ORL C, ACC.7 ;OR CARRY WITH THE ACC.BIT 7
ORL C, /OV ;OR CARRY WITH THE INVERSE OF OV
ORL C, bit
Bytes: 2
d .
Cycles: 2
m i t e
Li
Operation: ORL
(C)

(C)(bit)
ORL C, /bit
Bytes: 2
C U
M
Cycles: 2
Encoding:
C
1 0 1 0 0 0 0 0 bit address
T
Operation: ORL
POP direct
Function:
S
(C)

(C)(bit)
Pop from stack

Description: The contents of the internal RAM location addressed by the Stack Pointer is read, and the
Stack Pointer is decremented by one. The value read is then transferred to the directly
addressed byte indicated. No flags are affected.
Example: The Stack Pointer originally contains the value 32H, and internal RAM locations 30H
through 32H contain the values 20H, 23H, and 01H, respectively. The instruction sequence,
POP DPH
POP DPL
will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H. At this
point the instruction,
POP SP
will leave the Stack Pointer set to 20H. Note that in this special case the Stack Pointer was
decremented to 2FH before being loaded with the value popped (20H).
Bytes: 2
Cycles: 2
Operation: POP
(diect)
((SP))
(SP)

(SP) - 1

PUSH direct
Function: Push onto stack
Description: The Stack Pointer is incremented by one. The contents of the indicated variableis then copied
into the internal RAM location addressed by the Stack Pointer. Otherwise no flags are
affected.
Example: On entering interrupt routine the Stack Pointer contains 09H. The Data Pointer holds the
value 0123H. The instruction sequence,
PUSH DPL
PUSH DPH
will leave the Stack Pointer set to 0BH and store 23H and 01H in internal RAM locations
0AH and 0BH, respectively.
Bytes: 2
ed .
mit
Cycles: 2
Li
Operation: PUSH
U
(SP)

(SP)
+ 1
C
((SP))

(direct)
M
RET
Function: Return from subroutine
Description:
S T C
RET pops the high-and low-order bytes of the PC successively from the stack, decrementing
the Stack Pointer by two. Program execution continues at the resulting address, generally the
instruction immediately following an ACALL or LCALL. No flags are affected.
Example: The Stack Pointer originally contains the value 0BH. Internal RAM locations 0AH and 0BH
contain the values 23H and 01H, respectively. The instruction,
RET
will leave the Stack Pointer equal to the value 09H. Program execution will continue at
location 0123H.
Bytes: 1
Cycles: 2
Encoding: 0 0 1 0 0 0 1 0
Operation: RET
(PC15-8)

((SP))
(SP)

(SP) -1
(PC7-0)

((SP))
(SP)

(SP) -1

RETI
Function: Return from interrupt
Description: RETI pops the high- and low-order bytes of the PC successively from the stack, and restores
the interrupt logic to accept additional interrupts at the same priority level as the one just
processed. The Stack Pointer is left decremented by two. No other registers are affected; the
PSW is not automatically restored to its pre-interrupt status. Program execution continues at
the resulting address, which is generally the instruction immediately after the point at which
the interrupt request was detected. If a lower- or same-level interrupt had been pending when
the RETI instruction is executed, that one instruction will be executed before the pending
interrupt is processed.
Example: The Stack Pointer originally contains the value 0BH. An interrupt was detected during the
instruction ending at location 0122H. Internal RAM locations 0AH and 0BH contain the
values 23H and 01H, respectively. The instruction,
RETI
t ed .
m i
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will leave the Stack Pointer equal to 09H and return program execution to location 0123H.
Bytes: 1
U
Cycles: 2
C
Encoding: 0 0 1 1 0 0 1 0
M
Operation: RETI
(PC15-8)

((SP))
T C
(SP)

(SP) -1
S
(PC7-0)

((SP))
(SP)

(SP) -1
RL A
Function: Rotate Accumulator Left
Description: The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0
position. No flags are affected.
Example: The Accumulator holds the value 0C5H (11000101B). The instruction,
RL A
leaves the Accumulator holding the value 8BH (10001011B) with the carry unaffected.
Bytes: 1
Cycles: 1
Encoding: 0 0 1 0 0 0 1 1
Operation: RL
(An+1)

(An) n = 0-6
(A0)
(A
7)

RLC A
Function: Rotate Accumulator Left through the Carry flag
Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit
7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position.
No other flags are affected.
Example: The Accumulator holds the value 0C5H (11000101B), and the carry is zero. The instruction,
RLC A
leaves the Accumulator holding the value 8BH (10001011B) with the carry set.
Bytes: 1
Cycles: 1
Encoding: 0 0 1 1 0 0 1 1
Operation: RLC
(An+1)

(An) n = 0-6
ed .
mit
(A0)

(C)
(C)

(A7)
Li
RR A
Function: Rotate Accumulator Right
U
Description:
C
The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7
position. No flags are affected.
Example:
M
The Accumulator holds the value 0C5H (11000101B). The instruction,
RR A
T C
leaves the Accumulator holding the value 0E2H (11100010B) with the carry unaffected.
S
Bytes: 1
Cycles: 1
Encoding: 0 0 0 0 0 0 1 1
Operation: RR
(An)

(An+1) n=0-6
(A7)

(A0)
RRC A
Function: Rotate Accumulator Right through the Carry flag
Description: The eight bits in the Accumulator and the carry flag are together rotated one bit to the right.
Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7
position.No other flags are affected.
Example: The Accumulator holds the value 0C5H (11000101B), and the carry is zero. The instruction,
RRC A
leaves the Accumulator holding the value 62H (01100010B) with the carry set.
Bytes: 1
Cycles: 1
Encoding: 0 0 0 1 0 0 1 1
Operation: RRC
(An+1)

(An) n = 0-6
(A7)

(C)
(C)

(A0)
SETB <bit>
Function: Set bit
Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly
addressable bit. No other flags are affected
Example: The carry flag is cleared. Output Port 1 has been written with the value 34H (00110100B).
The instructions,
SETB C
SETB P1.0
will leave the carry flag set to 1 and change the data output on Port 1 to 35H (00110101B).
SETB C
Bytes: 1
Cycles: 1
Encoding: 1 1 0 1 0 0 1 1
t ed .
i
Operation: SETB
Lim
(C)
1
SETB bit
U
Bytes: 2
C
Cycles: 1
Encoding: 1 1 0 1 0
M
0 1 0 bit address
C
Operation: SETB
T
(bit)
1
SJMP rel
Function:
Description:
S
Short Jump
Program control branches unconditionally to the address indicated. The branch destination is
computed by adding the signed displacement in the second instruction byte to the PC, after
incrementing the PC twice. Therefore, the range of destinations allowed is from 128bytes
preceding this instruction to 127 bytes following it.
Example: The label RELADR is assigned to an instruction at program memory location 0123H. The
instruction,
SJMP RELADR
will assemble into location 0100H. After the instruction is executed, the PC will contain the
value 0123H.
(Note: Under the above conditions the instruction following SJMP will be at 102H.Therefore,
the displacement byte of the instruction will be the relative offset (0123H - 0102H) = 21H.
Put another way, an SJMP with a displacement of 0FEH would be an one-instruction infinite
loop).
Bytes: 2
Cycles: 2
Operation: SJMP
(PC)

(PC)+2
(PC)

(PC)+rel

SUBB A, <src-byte>
Function: Subtract with borrow
Description: SUBB subtracts the indicated variable and the carry flag together from the Accumulator,
leaving the result in the Accumulator. SUBB sets the carry (borrow)flag if a borrow is needed
for bit 7, and clears C otherwise.(If C was set before executing a SUBB instruction, this
indicates that a borrow was needed for the previous step in a multiple precision subtraction,
so the carry is subtracted from the Accumulator along with the source operand).AC is set if a
borrow is needed for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6,
but not into bit 7, or into bit 7, but not bit 6.
When subtracting signed integers OV indicates a negative number produced when a negative
value is subtracted from a positive value, or a positive result when a positive number is
subtracted from a negative number.
.
The source operand allows four addressing modes: register, direct, register-indirect, or
ed
immediate.
mit
Example: The Accumulator holds 0C9H (11001001B), register 2 holds 54H (01010100B), and the
Li
carry flag is set. The instruction,
SUBB A, R2
C U
will leave the value 74H (01110100B) in the accumulator, with the carry flag and AC cleared
M
but OV set.
Notice that 0C9H minus 54H is 75H. The difference between this and the above result is due
C
to the carry (borrow) flag being set before the operation. If the state of the carry is not known
T
before starting a single or multiple-precision subtraction, it should be explicitly cleared by a
S
CLR C instruction.
SUBB A, Rn
Bytes: 1
Cycles: 1
Operation: SUBB
(A)

(A) - (C) - (Rn)
SUBB A, direct
Bytes: 2
Cycles: 1
Operation: SUBB
(A)

(A) - (C) - (direct)
SUBB A, @Ri
Bytes: 1
Cycles: 1
Encoding: 1 0 0 1 0 1 1 i
Operation: SUBB
(A)

(A) - (C) - ((Ri))

SUBB A, #data
Bytes: 2
Cycles: 1
Operation: SUBB
(A)

(A) - (C) -
#data
SWAP A
Function: Swap nibbles within the Accumulator
Description: SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the Accumulator
(bits 3-0 and bits 7-4). The operation can also be thought of as a four-bit rotate instruction.
No flags are affected.
.
Example: The Accumulator holds the value 0C5H (11000101B). The instruction,
ed
SWAP A
leaves the Accumulator holding the value 5CH (01011100B).
m i t
Li
Bytes: 1
Cycles: 1
U
Encoding: 1 1 0 0 0 1 0 0
C
Operation: SWAP
M
(A3-0) (A7-4)
C
XCH A, <byte>
S T
Function: Exchange Accumulator with byte variable
Description: XCH loads the Accumulator with the contents of the indicated variable, at the same time
writing the original Accumulator contents to the indicated variable. The source/destination
operand can use register, direct, or register-indirect addressing.
Example: R0 contains the address 20H. The Accumulator holds the value 3FH (00111111B). Internal
RAM location 20H holds the value 75H (01110101B). The instruction,
XCH A, @R0
will leave RAM location 20H holding the values 3FH (00111111B) and 75H (01110101B) in
the accumulator.
XCH A, Rn
Bytes: 1
Cycles: 1
Operation: XCH
(A) (Rn)
XCH A, direct
Bytes: 2
Cycles: 1
Operation: XCH
(A) (direct)

XCH A, @Ri
Bytes: 1
Cycles: 1
Encoding: 1 1 0 0 0 1 1 i
Operation: XCH
(A) ((Ri))
XCHD A, @Ri
Function: Exchange Digit
Description: XCHD exchanges the low-order nibble of the Accumulator (bits 3-0), generally representing
a hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by
the specified register. The high-order nibbles (bits 7-4) of each register are not affected. No
.
flags are affected.
ed
Example:
mit
R0 contains the address 20H. The Accumulator holds the value 36H (00110110B). Internal
RAM location 20H holds the value 75H (01110101B). The instruction,
Li
XCHD A, @R0
will leave RAM location 20H holding the value 76H (01110110B) and 35H (00110101B) in
U
the accumulator.
C
Bytes: 1
M
Cycles: 1
Encoding: 1 1 0 1 0 1 1 i
Operation:
S T C
XCHD
(A3-0)
XRL <dest-byte>, <src-byte>
(Ri3-0)
Function: Logical Exclusive-OR for byte variables

Description: XRL performs the bitwise logical Exclusive-OR operation between the indicated variables,
storing the results in the destination. No flags are affected.
The two operands allow six addressing mode combinations.When the destination is the
when the destination is a direct address,the source can be the Accumulator or immediate data.
(Note: When this instruction is used to modify an output port, the value used as the original
port data will be read from the output data latch, not the input pins.)
Example: If the Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH (10101010B) then
the instruction,
XRL A, R0
will leave the Accumulator holding the vatue 69H (01101001B).
When the destination is a directly addressed byte, this instruction can complement combinna-
tion of bits in any RAM location or hardware register. The pattern of bits to be complemented
is then determined by a mask byte, either a constant contained in the instruction or a variable
computed in the Accumulator at run-time. The instruction,
XRL P1, #00110001B
will complement bits 5,4 and 0 of outpue Port 1.

XRL A, Rn
Bytes: 1
Cycles: 1
Operation: XRL
(A)

(A) (Rn)
XRL A, direct
Bytes: 2
Cycles: 1
Operation: XRL
d .
(A)

(A) (direct)
XRL A, @Ri
m i t e
Li
Bytes: 1
Cycles: 1
U
Encoding: 0 1 1 0 0 1 1 i
Operation: XRL
(A)

(A) ((Ri))
M C
C
XRL A, #data
S T
Bytes: 2
Cycles: 1
Operation: XRL
(A)

(A) #data
XRL direct, A
Bytes: 2
Cycles: 1
Operation: XRL
(direct)

(direct) (A)
XRL direct, #dataw
Bytes: 3
Cycles: 2
Operation: XRL
(direct)

(direct) # data

Chapter 6. Interrupt System

STC12C5620AD series support 9 interrupt sources with four priority levels. The 9 interrupt sources are external
interrupt 0(INT0), Timer 0 interrrupt, external interrupt 1(INT1), Timer 1 interrrupt, serial port 1(UART)
interrupt, ADC and SPI interrupt, low voltage detector (LVD) and PCA interrupt. Each interrupt source has one
or more associated interrupt-request flag(s) in SFRs. Associating with each interrupt vector, the interrupt sources
can be individually enabled or disabled by setting or clearing a bit (interrupt enalbe control bit) in the SFRs IE,
CCON. However, interrupts must first be globally enabled by setting the EA bit (IE.7) to logic 1 be-
fore the individual interrupt enables are recognized. Setting the EA bit to logic 0 disables all interrupt
sources regardless of the individual interrupt-enable settings.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-request
flag is set. As soon as execution of the current instruction is complete, the CPU generates an LCALL
d .
to a predetermined address to begin execution of an interrupt service routine (ISR). Each ISR must
e
mit
end with an RETI instruction, which returns program execution to the next instruction that would have
Li
been executed if the interrupt request had not occurred. If interrupts are not enabled, the interrupt-
pending flag is ignored by the hardware and program execution continues as normal. (The interrupt-
pending flag is set to logic 1 regardless of the interrupts enable/disable state.)
C U
M
Each interrupt source has two corresponding bits to represent its priority. One is located in SFR named IPH and
other in IP register. Higher-priority interrupt will be not interrupted by lower-priority interrupt request. If two
interrupt requests of different priority levels are received simultaneously, the request of higher priority is serviced.
C
If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determine
S T
which request is serviced. The following table shows the internal polling sequence in the same priority level and
the interrupt vector address.
Interrupt Sources, vector address, priority and polling sequence Table

Interrupt Priority
Interrupt Interrupt Priority Priority 0 Priority Priority Priority 3 Interrupt Enable
Vector within Interrupt Request
Source setting(IPH, IP) (lowest) 1 2 (highest) Control Bit
address level
External
interrupt 0 0003H 0(highest) PX0H,PX0 0,0 0,1 1,0 1,1 IE0 EX0/EA
(INT0)
Timer 0 000BH 1 PT0H,PT0 0,0 0,1 1,0 1,1 TF0 ET0/EA
External
interrupt 1 0013H 2 PX1H,PX1 0,0 0,1 1,0 1,1 IE1 EX1/EA
(INT1)
Timer1 001BH 3 PT1H, PT1 0, 0 0, 1 1, 0 1, 1 TF1 ET1/EA
UART 0023H 4 PSH, PS 0, 0 0, 1 1, 0 1, 1 RI+TI ES/EA
PADC_SPIH, (EADCI+ESPI) /
ADC/SPI 002BH 5 0, 0 0, 1 1, 0 1, 1 ADC_FLAG+SPIF
PADC_SPI EADC_SPI / EA
(ECF+ECCF0+E
PCA/ PPCA_LVDH, CF+CCF0+CCF1+ CCF1+ECCF2+
0033H 6 (lowest) 0, 0 0, 1 1, 0 1, 1
LVD PPCA_LVD CCF2+CCF3+LVDF ECCF3+ELVD)/
EPCA_LVD/EA

In C language program. the interrupt polling sequence number is equal to interrupt number, for example,
void Int0_Routine(void) interrupt 0;
void Timer0_Rountine(void) interrupt 1;
void UART_Routine(void) interrupt 4;
void ADC_SPI_Routine(void) interrupt 5;
void PCA_LVD_Routine(void) interrupt 6;
t ed .
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M
S T C

6.1 Interrupt Structure

The interrupt structure of STC12C5620AD series is shown as below.
Interrupt Enable Interrupt Priority lowest Priority

Conterol Registers Conterol Registers Level Interrupt
Highest Priority
IP, IPH Registers Level Interrupt
IE Register
TCON.0/IT0=0 EA PX0H, PX0 0,0

EX0 0,1
1,0
INT0 IE0 1,1
TCON.0/IT0=1
high
.
PT0H, PT0 0,0
d
ET0 0,1
e
1,0
mit
Timer0 / TF0 1,1
PX1H, PX1
Li
TCON.2/IT1=0 0,0
EX1 0,1
1,0
INT1 IE1 1,1
TCON.2/IT1=1
PT1H, PT1
U
0,0
ET1 0,1
1,0
C
Timer1 / TF1 1,1
M
PSH, PS 0,0
0,1
RI ES 1,0

UART TI 1,1

T C Interrupt
EADCI PADC_SPIH, PADC_SPI 0,0
S
ADC_FLAG EADC_SPI 0,1
1,0 Polling
ESPI 1,1
SPIF Sequence
CF
ECF
CCF0
ECCF0
PPCA_LVDH, PPCA_LVD 0,0
CCF1 EPCA_LVD 0,1
1,0
ECCF1 1,1
CCF2
ECCF2
CCF3
ECCF3
LVDF
ELVDI low
EA
Global Enable
EA
Figure STC12C5620AD series Interrupt Structure diagram

The External Interrupts INT0 and INT1 can each be either level-activated or transition-activated, depending
on bits IT0 and IT1 in Register TCON. The flags that actually generate these interrupts are bits IE0 and IE1
in TCON. When an external interrupt is generated, the flag that generated it is cleared by the hardware when
the service routine is vectored to if and only if the interrupt was transition activated, otherwise the external
requesting source is what controls the request flag, rather than the on-chip hardware.
The Timer 0 and Timer1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective
Timer/Counter registers in most cases. When a timer interrupt is generated, the flag that generated it is cleared by
the on-chip hardware when the service routine is vectored to.
The Serial Port Interrupt is generated by the logical OR of RI and TI. Neither of these flags is cleared by
hardware when the service routine is vectored to. In fact, the service routine will normally have to determine
.
whether it was RI and TI that generated the interrupt, and the bit will have to be cleared by software.
i t ed
The 2BH interrupt is shared by the logical 1 of SPI interrupt and ADC interrupt.Neither of these flags is cleared
Li m
by hardware when the service routine is vectored to. The service routine should poll them to determine which one
to request service and it will be cleared by software.
U
The 33H interrupt is shared by the logical 1 of PCA interrupt and LVD ( Low-Voltage Detector ) interrupt.
C
Neither of these flags is cleared by hardware when the service routine is vectored to. The service routine should
M
poll them to determine which one to request service and it will be cleared by software.
C
All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had
S T
been set or cleared by hardware. In other words, interrupts can be generated or pending interrupts can be canceled
in software.

6.2 Interrupt Register

Value after
MSB LSB Reset
Interrupt Priority
IP B8H - PPCA_LVD PADC_SPI PS PT1 PX1 PT0 PX0 x000 0000B
Low
Interrupt Priority
IPH B7H - PPCA_LVDH PADC_SPIH PSH PT1H PX1H PT0H PX0H x000 0000B
High
TCON Timer Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 0000 0000B
.
ed
mit
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ADC_CONTR ADC Control C5H ADC_POWER SPEED1 SPEED0 ADC_FLAG ADC_START CHS2 CHS1 CHS0 0000 0000B
PCA Control Regis-
CU
CCON D8H CF CR - - CCF3 CCF2 CCF1 CCF0 00xx 0000B
ter
CMOD PCA Mode Register D9H CIDL - - - - CPS1 CPS0 ECF 00xx 0000B
M
PCA Module 0
CCAPM0 DAH - ECOM0 CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0 x000 0000B
Mode Register
C
PCA Module 1
T
CCAPM1 DBH - ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1 x000 0000B
S
Mode Register
PCA Module 2
CCAPM2 DCH - ECOM2 CAPP2 CAPN2 MAT2 TOG2 PWM2 ECCF2 x000 0000B
Mode Register
PCA Module 3
CCAPM3 DDH - ECOM3 CAPP3 CAPN3 MAT3 TOG3 PWM3 ECCF3 x000 0000B
Mode Register
SPSTAT SPI Status register 84H SPIF WCOL - - - - - -

1. Interrupt Enable control Register IE and AUXR

IE: Interrupt Enable Rsgister (Bit-addressable)
Enable Bit = 1 enables the interrupt .
Enable Bit = 0 disables it .
EA (IE.7): disables all interrupts. If EA = 0,no interrupt will be acknowledged. If EA = 1, each interrupt source is
individually enabled or disabled by setting or clearing its enable bit.
EPCA_LVD (IE.6): Interrupt controller of Programmable Counter Array (PCA) and Low-Voltage Detector.
0: Disable the interrupt of Programmable Counter Array (PCA) and Low-Voltage Detector
1: Enable the interrupt of Programmable Counter Array (PCA) and Low-Voltage Detector
.
EADC_SPI (IE.5): Interrupt controller of Serial Peripheral Interface (SPI) and A/D Converter (ADC).
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0: Disable the interrupt of Serial Peripheral Interface (SPI) and A/D Converter (ADC).
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1: Enable the interrupt of Serial Peripheral Interface (SPI) and A/D Converter (ADC).
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ES (IE.4): Serial Port 1 (UART1) interrupt enable bit. If ES = 0, UART1 interrupt will be diabled. If ES = 1, UART1
interrupt is enabled.
ET1 (IE.3): Timer 1 interrupt enable bit. If ET1 = 0, Timer 1 interrupt will be diabled. If ET1 = 1, Timer 1 interrupt is
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enabled.
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EX1 (IE.2): External interrupt 1 enable bit. If EX1 = 0, external interrupt 1 will be diabled. If EX1 = 1, external
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interrupt 1 is enabled.
ET0 (IE.1): Timer 0 interrupt enable bit. If ET0 = 0, Timer 0 interrupt will be diabled. If ET0 = 1, Timer 0 interrupt is
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enabled.
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EX0 (IE.0): External interrupt 0 enable bit. If EX0 = 0, external interrupt 0 will be diabled. If EX0 = 1, external
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interrupt 0 is enabled.



.
2. Interrupt Priority control Registers IP and IPH
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Each interrupt source of STC12C5620AD all can be individually programmed to one of four priority levels
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by setting or clearing the bits in Special Function Registers IP and IPH. A low-priority interrupt can itself be
interrupted by a high-pority interrupt, but not by another low-priority interrupt. A high-priority interrupt cant be
interrupted by any other interrupt source.
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IPH: Interrupt Priority High Register (Non bit-addressable)
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SFR name Address

IP S
B8H T C
IP: Interrupt Priority Register (Bit-addressable)
bit
name
B7
-
B6
PPCA_LVD PADC_SPI
B5 B4
PS
B3
PT1
B2
PX1
B1
PT0
B0
PX0
PPCA_LVDH, PPCA_LVD: Programmable Counter Array (PCA) and Low voltage detector interrupt priority control bits.
if PPCA_LVDH=1 and PPCA_LVD=1, Programmable Counter Array (PCA) and Low voltage .detector
PADC_SPIH, PADC_SPI : Serial Peripheral Interface (SPI) and A/D Converter (ADC) interrupt priority control bits.
if PADC_SPIH=0 and PADC_SPI=0, Serial Peripheral Interface (SPI) and A/D Converter (ADC)

PSH, PS: Serial Port 1 (UART1) interrupt priority control bits.

if PSH=0 and PS=0, UART1 interrupt is assigned lowest priority (priority 0).
if PSH=0 and PS=1, UART1 interrupt is assigned lower priority (priority 1).
if PSH=1 and PS=0, UART1 interrupt is assigned higher priority (priority 2).
if PSH=1 and PS=1, UART1 interrupt is assigned highest priority (priority 3).
PT1H, PT1: Timer 1 interrupt priority control bits.

if PT1H=0 and PT1=0, Timer 1 interrupt is assigned lowest priority (priority 0).
if PT1H=0 and PT1=1, Timer 1 interrupt is assigned lower priority (priority 1).
if PT1H=1 and PT1=0, Timer 1 interrupt is assigned higher priority (priority 2).
if PT1H=1 and PT1=1, Timer 1 interrupt is assigned highest priority (priority 3).
.
PX1H, PX1: External interrupt 1 priority control bits.
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if PX1H=0 and PX1=0, External interrupt 1 is assigned lowest priority (priority 0).
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if PX1H=0 and PX1=1, External interrupt 1 is assigned lower priority (priority 1).
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if PX1H=1 and PX1=0, External interrupt 1 is assigned higher priority (priority 2).
if PX1H=1 and PX1=1, External interrupt 1 is assigned highest priority (priority 3).
PT0H, PT0: Timer 0 interrupt priority control bits.
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if PT0H=0 and PT0=0, Timer 0 interrupt is assigned lowest priority (priority 0).

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if PT0H=0 and PT0=1, Timer 0 interrupt is assigned lower priority (priority 1).
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if PT0H=1 and PT0=0, Timer 0 interrupt is assigned higher priority (priority 2).
if PT0H=1 and PT0=1, Timer 0 interrupt is assigned highest priority (priority 3).
PX0H, PX0:

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External interrupt 0 priority control bits.
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if PX0H=0 and PX0=0, External interrupt 0 is assigned lowest priority (priority 0).
if PX0H=0 and PX0=1, External interrupt 0 is assigned lower priority (priority 1).
if PX0H=1 and PX0=0, External interrupt 0 is assigned higher priority (priority 2).
if PX0H=1 and PX0=1, External interrupt 0 is assigned highest priority (priority 3).

3. TCON register: Timer/Counter Control Register (Bit-Addressable)

TCON 88H name TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TF1: Timer/Counter 1 Overflow Flag. Set by hardware on Timer/Counter 1 overflow. The flag can be cleared by
software but is automatically cleared by hardware when processor vectors to the Timer 1 interrupt routine.
If TF1 = 0, No Timer 1 overflow detected.
If TF1 = 1, Timer 1 has overflowed.
TR1: Timer/Counter 1 Run Control bit. Set/cleared by software to turn Timer/Counter on/off.
If TR1 = 0, Timer 1 disabled.
If TR1 = 1, Timer 1 enabled.
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IE1: External Interrupt 1 Edge flag. Set by hardware when external interrupt edge/level defined by IT1 is
detected. The flag can be cleared by software but is automatically cleared when the external interrupt 1
service routine has been processed.
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IT1: External Intenupt 1 Type Select bit. Set/cleared by software to specify falling edge/low level triggered ex-
ternal interrupt 1.
If IT1 = 0, INT1 is low level triggered.
If IT1 = 1, INT1 is edge triggered.
ternal interrupt 0.

4. SCON register: Serial Port 1 (UART1) Control Register (Bit-Addressable)

SCON 98H name SM0/FE SM1 SM2 REN TB8 RB8 TI RI
FE: Framing Error bit. The SMOD0 bit must be set to enable access to the FE bit
0: The FE bit is not cleared by valid frames but should be cleared by software.
1: This bit set by the receiver when an invalid stop bit id detected.
SM0,SM1 : Serial Port Mode Bit 0/1.
SM0 SM1 Description Baud rate
0 0 8-bit shift register SYSclk/12
0 1 8-bit UART variable
1 0 9-bit UART SYSclk/64 or SYSclk/32(SMOD=1)
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SM2 : Enable the automatic address recognition feature in mode 2 and 3. If SM2=1, RI will not be
set unless the received 9th data bit is 1, indicating an address, and the received byte is a
Given or Broadcast address. In mode1, if SM2=1 then RI will not be set unless a valid stop
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Bit was received, and the received byte is a Given or Broadcast address. In mode 0, SM2 should be 0.
REN : When set enables serial reception.
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TB8 : The 9th data bit which will be transmitted in mode 2 and 3.
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RB8 : In mode 2 and 3, the received 9th data bit will go into this bit.
S T
TI : Transmit interrupt flag. Set by hardware when a byte of data has been transmitted by UART0 (after the 8th
bit in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0 in-
terrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine. This bit
must be cleared manually by software.
RI : Receive interrupt flag. Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sam-pling time). When the UART0 interrupt is enabled, setting this bit to 1 causes the CPU to
vector to the UART0 interrupt service routine. This bit must be cleared manually by software.

5. Register related with LVD interrupt: Power Control register PCON (Non bit-Addressable)
SMOD: double Baud rate control bit.
0 : Disable double Baud rate of the UART.
1 : Enable double Baud rate of the UART in mode 1,2,or 3.
SMOD0: Frame Error select.
0 : SCON.7 is SM0 function.
1 : SCON.7 is FE function. Note that FE will be set after a frame error regardless of the state of SMOD0.
POF : Power-On flag. It is set by power-off-on action and can only cleared by software.
.
GF1 : General-purposed flag 1
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GF0 : General-purposed flag 0
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PD : Power-Down bit.
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IDL : Idle mode bit.
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EA : disables all interrupts.
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If EA = 0,no interrupt will be acknowledged.
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If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit.
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EPCA_LVD : Interrupt controller of Programmable Counter Array (PCA) and Low-Voltage Detector.
If EPCA_LVD = 0, Disable the interrupt of Programmable Counter Array (PCA) and Low-Voltage Detector.
If EPCA_LVD = 1, Enable the interrupt of Programmable Counter Array (PCA) and Low-Voltage Detector

6. ADC_CONTR: AD Control register (Non bit-Addressable)

ADC_CONTR C5H name ADC_POWER SPEED1 SPEED0 ADC_FLAG ADC_START CHS2 CHS1 CHS0
ADC_POWER : When clear, shut down the power of ADC bolck. When set, turn on the power of ADC block.
ADC_FLAG : ADC interrupt flag.It will be set by the device after the device has finished a conversion, and
should be cleared by the user's software.
ADC_STRAT : ADC start bit, which enable ADC conversion.It will automatically cleared by the device after the
device has finished the conversion

IE A8H name EA EPCA_LVD EADC_SPI ES
t ed .ET1 EX1 ET0 EX0
i
Lim
EADC_SPI : Interrupt controller of Serial Peripheral Interface (SPI) and A/D Converter (ADC).

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If EADC_SPI = 0, Disable the interrupt of Serial Peripheral Interface (SPI) and A/D Converter (ADC).
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If EADC_SPI = 1, Enable the interrupt of Serial Peripheral Interface (SPI) and A/D Converter (ADC).
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7. Register related with PCA interrupt
CCON: PCA Control Register (bit-Addressable)
CCON D8H name CF CR - - CCF3 CCF2 CCF1 CCF0
CF : PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF
in CMOD is set. CF may be set by either hardware or software but can only be cleared by software.
CR : PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to
turn the PCA counter off.
CCF3: PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by
software.
software.
software.
software.

CMOD: PCA Mode Register (Non bit-Addressable)
CMOD D9H name CIDL - - - - CPS1 CPS0 ECF
CIDL : Counter Idle control. CIDL=0 programs the PCA Counter to continue functioning during idle mode.
CIDL=1 programs it to be gated off during idle.
CPS1~ CPS0 : PCA Counter Pulse Select bits.
0 0 Internal clock, fosc/12
0 1 Internal clock, fosc/2
0 0 Timer 0 overflow
0 1 External clock at ECI/P3.4 pin
.
ECF : PCA Enable Counter Overflow interrupt. ECF=1 enables CF bit in CCON to generate an interrupt.
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CCAPMn register (Non bit-Addressable)
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CCAPM0 DAH name - ECOM0 CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0
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CCAPM1 DBH name - ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1
CCAPM2 DCH name - ECOM2 CAPP2 CAPN2 MAT2 TOG2 PWM2 ECCF2
CCAPM3 DDH name -
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ECOM3 CAPP3 CAPN3 MAT3 TOG3 PWM3 ECCF3
C
ECOMn : Enable Comparator. ECOMn=1 enables the comparator function.
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CAPPn : Capture Positive, CAPPn=1 enables positive edge capture.
CAPNn : Capture Negative, CAPNn=1 enables negative edge capture.
MATn : Match. When MATn=1, a match of the PCA counter with this modules compare/capture register
causes the CCFn bit in CCON to be set.
TOGn : Toggle. When TOGn=1, a match of the PCA counter with this modules compare/capture register causes
the CEXn pin to toggle.
PWMn : Pulse Width Modulation. PWMn=1 enables the CEXn pin to be used as a pulse width modulated output.
ECCFn : Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate

EPCA_LVD : Interrupt controller of Programmable Counter Array (PCA) and Low-Voltage Detector.
If EPCA_LVD = 0, Disable the interrupt of Programmable Counter Array (PCA) and Low-Voltage Detector.
If EPCA_LVD = 1, Enable the interrupt of Programmable Counter Array (PCA) and Low-Voltage Detector

8. Register related with SPI interrupt : SPSTAT

SPI State register: SPSTAT (Non bit-addressable)
SPSTAT CDH name SPIF WCOL - - - - - -
SPIF : SPI transfer completion flag.
When a serial transfer finishes, the SPIF bit is set and an interrupt is generated if all the EADC_SPI (IE.6)
bit, ESPI bit (AUXR.3) and the EA (IE.7) bit are set. If SS is an input and is driven low when SPI is in
master mode with SSIG = 0, SPIF will also be set to signal the mode change.The SPIF is cleared in
software by writing 1 to this bit.
WCOL: SPI write collision flag.
The WCOL bit is set if the SPI data register, SPDAT, is written during a data transfer. The WCOL flag is
.
cleared in software by writing 1 to this bit.
i t ed
SFR name Address
IE A8H
bit
name
B7
EA
B6
EPCA_LVD EADC_SPI
B5
Li
B4
ES m B3
ET1
B2
EX1
B1
ET0
B0
EX0
U
C
M
C
T
S

9. Interrupt register related with Power down wake-up: WAKE_CLKO (Non bit-Addressable)
WAKE_CLKO 8FH name PCAWAKEUP RXD_PIN_IE T1_PIN_IE T0_PIN_IE - - T1CKLO T0CKLO
divided by 2.
divided by 2.

6.3 Interrupt Priorities

Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing the
bits in Special Function Registers IP and IPH. A low-priority interrupt can itself be interrupted by a high-pority
interrupt, but not by another low-priority interrupt. A high-priority interrupt cant be interrupted by any other
interrupt source.
If two requests of different priority levels are received simultaneously, the request of higher priority level
is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority structure
determined by the polling sequence,as follows:
Source Priority Within Level
0. INT0 (highest)
d .
1. Timer 0
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2. INT1
3. Timer 1
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4. UART1
5. ADC_SPI
6. PCA_LVD (lowest)
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Note that the priority within level structure is only used to resolve simultaneous requests of the same prionty
level.
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In C language program. the interrupt polling sequence number is equal to interrupt number, for example,
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void UART_Rountine(void) interrupt 4;
void ADC_SPI_Routine(void) interrupt 5;
void PCA_LVD_Routine(void) interrupt 6;

6.4 How Interrupts Are Handled

External interrupt pins and other interrupt sources are sampled at the rising edge of each instruction OPcode
fetch cycle. The samples are polled during the next instruction OPcode fetch cycle. If one of the flags was in a set
condition of the first cycle, the second cycle of polling cycles will find it and the interrupt system will generate an
hardware LCALL to the appropriate service routine as long as it is not blocked by any of the following conditions.
Block conditions :
An interrupt of equal or higher priority level is already in progress.
The current cycle(polling cycle) is not the final cycle in the execution of the instruction in progress.
The instruction in progress is RETI or any write to the IE, IP and IPH registers.
The ISP/IAP activity is in progress.
.
Any of these four conditions will block the generation of the hardware LCALL to the interrupt service routine.
ed
Condition 2 ensures that the instruction in progress will be completed before vectoring into any service routine.
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Condition 3 ensures that if the instruction in progress is RETI or any access to IE, IP or IPH, then at least one or
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more instruction will be executed before any interrupt is vectored to.
The polling cycle is repeated with the last clock cycle of each instruction cycle. Note that if an interrupt flag is
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active but not being responded to for one of the above conditions, if the flag is not still active when the blocking
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condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag
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was once active but not being responded to for one of the above conditions, if the flag is not still active when the
blocking condition is removed, the denied interrupt will not be serviced. The interrupt flag was once active but
C
not serviced is not kept in memory. Every polling cycle is new.
S T
Note that if an interrupt of higher priority level goes active prior to the rising edge of the third machine cycle,
then in accordance with the above rules it will be vectored to during fifth and sixth machine cycle, without any
instruction of the lower priority routine having been executed.
Thus the processor acknowledges an interrupt request by executing a hardware-generated LCALL to the
appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, and in other cases
it doesnt. It never clears the Serial Port flags. This has to be done in the users software. It clears an external
interrupt flag (IE0 or IE1) only if it was transition-activated. The hardware-generated LCALL pushes the contents
of the Program Counter onto the stack (but it does not save the PSW) and reloads the PC with an address that
depends on the source of the interrupt being vectored to, as shown be low.

Source Vector Address

External Interrupt 0 0003H
Timer 0 000BH
External Interrupt 1 0013H
Timer 1 001BH
UART 0023H
ADC/SPI 002BH
PCA/LVD 0033H
Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs
the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and
reloads the Program Counter. Execution of the interrupted program continues from where it left off.
ed .
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Note that a simple RET instruction would also have returned execution to the interrupted program, but it would
have left the interrupt control system thinking an interrupt was still in progress.
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6.5 External Interrupts
The external sources can be programmed to be level-activated or transition-activated by clearing or setting bit IT1
or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INTx pin. If ITx=1,
external interrupt x is edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle
and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then requests the interrupt.
Since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at
least 12 system clocks to ensure sampling. If the external interrupt is transition-activated, the external source has
to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle to
ensure that the transition is seen so that interrupt request flag IEx will be set. IEx will be automatically cleared by
the CPU when the service routine is called.
If the external interrupt is level-activated, the external source has to hold the request active until the requested
interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is
completed, or else another interrupt will be generated.

Example: Design an intrusion warning system using interrupts that sounds a 400Hz tone for 1 second (using a
loudspeaker connected to P1.7) whenever a door sensor connected to INT0 makes a high-to-low transition.
Assembly Language Solution
ORG 0
LJMP MAIN ;3-byte instruction
LJMP INT0INT ;EXT 0 vector address
ORG 000BH ;Timer 0 vector
LJMP T0INT
ORG 001BH ;Timer 1 vector
LJMP T1INT
ORG 0030H
MAIN:
.
SETB IT0 ;negative edge activated
d
MOV TMOD, #11H ;16-bit timer mode
i t e
MOV IE, #81H ;enable EXT 0 only
m
SJMP $ ;now relax
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;
INT0INT:
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MOV R7, #20 ;20 ' 5000 us = 1 second
C
SETB TF0 ;force timer 0 interrupt
M
SETB TF1 ;force timer 1 interrupt
SETB ET0 ;begin tone for 1 second
C
SETB ET1 ;enable timer interrupts
T
RETI
S
;
T0INT:
CLR TR0 ;stop timer
DJNZ R7, SKIP ;if not 20th time, exit
CLR ET0 ;if 20th, disable tone
CLR ET1 ;disable itself
LJMP EXIT
SKIP:
MOV TH0, #HIGH (-50000) ;0.05sec. delay
MOV TL0, #LOW (-5000)
SETB TR0
EXIT:
RETI
;
T1INT:
CLR TR1
MOV TH1, #HIGH (-1250) ;count for 400Hz
MOV TL1, #LOW (-1250)
CPL P1.7 ;music maestro!
SETB TR1
RETI
END

C Language Solution
#include <REG51.H> /* SFR declarations */
sbit outbit = P1^7; /* use variable outbit to refer to P1.7 */
unsigned char R7; /* use 8-bit variable to represent R7 */
main( )
{
IT0 = 1; /* negative edge activated */
TMOD = 0x11; /* 16-bit timer mode */
IE = 0x81; /* enable EXT 0 only */
while(1);
}
void INT0INT(void) interrupt 0
{
d .
R7 = 20; /* 20 x 5000us = 1 second */
mit e
TF0 = 1; /* force timer 0 interrupt */
TF1 = 1; /* force timer 1 interrupt */
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ET0 = 1; /* begin tone for 1 second */
ET1 = 1; /* enable timer 1 interrupts */
/* timer interrupts will do the work */
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}
void T0INT(void) interrupt 1

{
TR0 = 0;
M /* stop timer */
C
R7 = R7-1; /* decrement R7 */
S T
if (R7 == 0) /* if 20th time, */
{
ET0 = 0; /* disable itself */
ET1 = 0;
}
else
{
TH0 = 0x3C; /* 0.05 sec. delay */
TL0 = 0xB0;
}
}
void T1INT (void) interrupt 3
{
TR0 = 0;
TH1 = 0xFB; /* count for 400Hz */
TL1 = 0x1E;
outbit = !outbit; /* music maestro! */
TR1 = 1;
}

In the above assembly language solution, five distinct sections are the interrupt vector loactions, the main
program, and the three interrupt service routines. All vector loacations contain LJMP instructions to the respective
routines. The main program, starting at code address 0030H, contains only four instructions. SETB IT0 configures
the door sensing interrupt input as negative-edge triggered. MOV TMOD, #11H configures both timers for mode 1,
16-bit timer mode. Only the external 0 interrupt is enabled initially (MOV IE,#81H), so a "door-open" condition
is needed before any interrupt is accepted. Finally, SJMP $ puts the main program in a do-nothing loop.
When a door-open condition is sensed (by a high-to-low transition of INT0), an external 0 interrupt is
generated, INT0INT begins by putting the constant 20 in R7, then sets the overflow flags for both timers to force
timer interrupts to occur.
Timer interrupt will only occur, however, if the respective bits are enabled in the IE register. The next two
instructions (SETB ET0 and SETB ET1) enable timer interrupts. Finally, INT0INT terminates with a RETI to the
main program.
Timer 0 creates the 1 second timeout, and Timer 1 creates the 400Hz tone. After INT0INT returns to the main
.
program, timer interrupt are immediately generated (and accepted after one excution of SJMP $). Because of the
d
fixed polling sequence, the Timer 0 interrupt is serviced first. A 1 second timeout is created by programming 20
i t e
repetitions of a 50,000 us timeout. R7 serves as the counter. Nineteen times out of 20, T0INT operates as follows.
m
First, Timer 0 is turned off and R7 is decremented. Then, TH0/TL is reload with -50,000, the timer is turned back
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on, and the interrupt is terminated. On the 20th Timer 0 interrupt, R7 is decremented to 0 (1 second has elapsed).
Both timer interrupts are disabled(CLR ET0, CLR ET1)and the interrupt is terminated. No further timer interrupts
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will be generated until the next "door-open" condition is sensed.
C
The 400Hz tone is programmed using Timer 1 interrupts, 400Hz requires a period of 1/400 = 2,500 us or
M
1,250 high-time and 1,250 us low-time. Each timer 1 ISR simply puts -1250 in TH1/TL1, complements the port
bit driving the loudspeaker, then terminates.
S T C

6.6 Response Time
The INT0 and INT1 levels are inverted and latched into the interrupt flags IE0 and IE1 at rising edge of every
syetem clock cycle.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set after which the timers overflow. The values are then polled
by the circuitry at rising edge of the next system clock cycle.
If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the
requested service routine will be the next instruction to be executed. The call itself takes six system clock cycles.
Thus, a minimum of seven complete system clock cycles elapse between activation of an external interrupt
request and the beginning of execution of the first instruction of the service routine.
ed .
A longer response time would result if the request is blocked by one of the four previously listed conditions. If an
mit
interrupt of equal or higher priority level is already in progress, the additional wait time obviously depends on the
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nature of the other interrupts service routine. If the instruction in progress is not in its final cycle, the additional
wait time cannot be more than 3 cycles, since the longest instructions (LCALL) are only 6 cycles long, and if the
instruction in progress is RETI or an access to IE or IP, the additional wait time cannot be more than 5 cycles (a
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maximum of one more cycle to complete the instruction in progress, plus 6 cycles to complete the next instruction
C
if the instruction is LCALL).
M
Thus, in a single-interrupt system, the response time is always more than 7 cycles and less than 12 cycles.
S T C

6.7 Demo Programs about Interrupts (C and ASM)
6.7.1 External Interrupt 0 (INT0) Demo Programs (C and ASM)

1. Demostrate External Interrupt 0 triggered by Falling Edge
C program
/*-------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ----------------------------------*/
/* --- STC 1T Series MCU Ext0 (Falling edge) Demo -----------------*/
/* --- Mobile: (86)13922809991 ------------------------------------------*/
.
/* --- Fax: 86-755-82905966 ----------------------------------------------*/
ed
/* --- Tel: 86-755-82948412 -----------------------------------------------*/
i t
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/*-------------------------------------------------------------------------------*/
#include "reg51.h"
C U
//External interrupt0 service routine
M
T C
void exint0() interrupt 0 //INT0, interrupt 0 (location at 0003H)
S
{
}
void main()
{
IT0 = 1; //set INT0 interrupt type (1:Falling 0:Low level)
EX0 = 1; //enable INT0 interrupt
EA = 1; //open global interrupt switch
while (1);
}

Assembly program
;/*-------------------------------------------------------------------------------*/
;/* --- STC 1T Series MCU Ext0(Falling edge) Demo -----------------*/
;/* --- Mobile: (86)13922809991 ------------------------------------------*/
;/* --- Fax: 86-755-82905966 ----------------------------------------------*/
;/* --- Tel: 86-755-82948412 -----------------------------------------------*/
;/*-------------------------------------------------------------------------------*/
;-----------------------------------------
.
;interrupt vector table
ed
mit
ORG 0000H
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LJMP MAIN
ORG 0003H ;INT0, interrupt 0 (location at 0003H)
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LJMP EXINT0
;-----------------------------------------
M C
C
ORG 0100H
T
MAIN:
S
MOV SP, #7FH ;initial SP
SETB IT0 ;set INT0 interrupt type (1:Falling 0:Low level)
SETB EX0 ;enable INT0 interrupt
SETB EA ;open global interrupt switch
SJMP $
;-----------------------------------------
;External interrupt0 service routine
EXINT0:
RETI
;-----------------------------------------
END

2. Demostrate the Power-Down Mode waked up by Falling Edge of External Interrupt 0

C program
/*------------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ---------------------------------------*/
/* --- STC 1T Series MCU Power-Down wakeup by INT0 Demo -------*/
/* --- Mobile: (86)13922809991 -----------------------------------------------*/
/* --- Fax: 86-755-82905966 ---------------------------------------------------*/
/* --- Tel: 86-755-82948412 ----------------------------------------------------*/
/* --- Web: www.STCMCU.com -----------------------------------------------*/
/* If you want to use the program or the program referenced in the ------*/
/* article, please specify in which data and procedures from STC -------*/
/*-------------------------------------------------------------------------------------*/
#include "reg51.h"
t ed .
i
#include "intrins.h"

void exint0( ) interrupt 0
Li m
//INT0, interrupt 0 (location at 0003H)
U
{
C
}
void main()
M
C
{
T
S
while (1)
{
INT0 = 1; //ready read INT0 port
while (!INT0); //check INT0
_nop_();
_nop_();
PCON = 0x02; //MCU power down
_nop_();
_nop_();
P1++;
}
}

Assembly program
/*------------------------------------------------------------------------------------*/
/* --- Mobile: (86)13922809991 -----------------------------------------------*/
/* --- Fax: 86-755-82905966 ---------------------------------------------------*/
/* --- Tel: 86-755-82948412 ----------------------------------------------------*/
/*-------------------------------------------------------------------------------------*/
;-----------------------------------------
.
ed
mit
ORG 0000H
LJMP MAIN
Li
LJMP EXINT0
C U
;-----------------------------------------
M
ORG 0100H
MAIN:
C
T
S
LOOP:
SETB INT0 ;ready read INT0 port
JNB INT0, $ ;check INT0
NOP
NOP
MOV PCON, #02H ;MCU power down
NOP
NOP
CPL P1.0
SJMP LOOP
;-----------------------------------------
EXINT0:
RETI
;-----------------------------------------
END

6.7.2 External Interrupt 1 (INT1) Demo Programs (C and ASM)

1. Demostrate External Interrupt 1 triggered by Falling Edge
C program
/*-------------------------------------------------------------------------------*/
/* --- STC 1T Series MCU Ext1(Falling edge) Demo -----------------*/
/* --- Mobile: (86)13922809991 ------------------------------------------*/
/* --- Fax: 86-755-82905966 ----------------------------------------------*/
/* --- Tel: 86-755-82948412 -----------------------------------------------*/
.
ed
/*-------------------------------------------------------------------------------*/
m i t
Li
#include "reg51.h"
U
C
void exint1() interrupt 2 //INT1, interrupt 2 (location at 0013H)
M
{
}
void main()
{
IT1 = 1;
S T C //set INT1 interrupt type (1:Falling only 0:Low level)
while (1);
}

Assembly program
;/*-------------------------------------------------------------------------------*/
;/* --- STC 1T Series MCU Ext1(Falling edge) Demo -----------------*/
;/* --- Mobile: (86)13922809991 ------------------------------------------*/
;/* --- Fax: 86-755-82905966 ----------------------------------------------*/
;/* --- Tel: 86-755-82948412 -----------------------------------------------*/
;/*-------------------------------------------------------------------------------*/
;-----------------------------------------
d .
ORG 0000H
mit e
Li
LJMP MAIN
U
LJMP EXINT1
;-----------------------------------------
M C
C
ORG 0100H
T
MAIN:

S
MOV SP,
SETB IT1
SETB EX1
SETB EA
#7FH

;initial SP
;set INT1 interrupt type (1:Falling 0:Low level)
;enable INT1 interrupt
;open global interrupt switch
SJMP $
;-----------------------------------------
EXINT1:
RETI
;-----------------------------------------
END

2. Demostrate the Power-Down Mode waked up by Falling Edge of External Interrupt 1

C program
/*------------------------------------------------------------------------------------*/
/* --- Mobile: (86)13922809991 -----------------------------------------------*/
/* --- Fax: 86-755-82905966 ---------------------------------------------------*/
/* --- Tel: 86-755-82948412 ----------------------------------------------------*/
/* article, please specify in which data and procedures from STC ------*/
/*-------------------------------------------------------------------------------------*/
#include "reg51.h"
t ed .
i

void exint1( ) interrupt 2
Li m
//INT1, interrupt 2 (location at 0013H)
U
{
C
}
void main()
M
C
{
T
S
while (1)
{
INT1 = 1; //ready read INT1 port
while (!INT1); //check INT1
_nop_();
_nop_();
_nop_();
_nop_();
P1++;
}
}

Assembly program
/*------------------------------------------------------------------------------------*/
/* --- Mobile: (86)13922809991 -----------------------------------------------*/
/* --- Fax: 86-755-82905966 ---------------------------------------------------*/
/* --- Tel: 86-755-82948412 ----------------------------------------------------*/
/*-------------------------------------------------------------------------------------*/
;-----------------------------------------
.
ed
mit
ORG 0000H
LJMP MAIN
Li

LJMP EXINT1
U
;-----------------------------------------

MAIN:
ORG 0100H
M C
C
MOV SP,#7FH ;initial SP
T
S
LOOP:
SETB INT1 ;ready read INT1 port
JNB INT1,$ ;check INT1
NOP
NOP
MOV PCON,#02H ;MCU power down
NOP
NOP
CPL P1.0
SJMP LOOP
;-----------------------------------------
EXINT1:
RETI
;-----------------------------------------
END

6.7.3 Programs of P3.4/T0 Interrupt(falling edge) used to wake up PD mode

1. C program
/*-----------------------------------------------------------------------------------------------------------------------------*/
/* --- STC MCU International Limited --------------------------------------------------------------------------------*/
/* --- STC 1T Series MCU Power-Down wakeup by T0 Demo ----------------------------------------------------*/
/* ---This Interrupt will borrow Timer 0 interrupt request bit TF0 and Timer 0 interrupt vector address ----*/
/* ---So Timer 0 function should be disabled when this Interrupt is enabled -------------------------------------*/
/* ---The enable bit of this Interrupt is T0_PIN_IE / WAKE_CLKO.4 in WAKE_CLKO register -----------*/
/* --- Mobile: (86)13922809991 ----------------------------------------------------------------------------------------*/
/* --- Fax: 86-755-82905966 --------------------------------------------------------------------------------------------*/
/* --- Tel: 86-755-82948412 ---------------------------------------------------------------------------------------------*/
d .
/* --- Web: www.STCMCU.com ---------------------------------------------------------------------------------------*/
i t e
/* If you want to use the program or the program referenced in the ----------------------------------------------*/
m
/* article, please specify in which data and procedures from STC ----------------------------------------------*/
Li
/*-----------------------------------------------------------------------------------------------------------------------------*/
#include "reg51.h"
C U
M
sfr WAKE_CLKO = 0x8f;
C
T
void t0int( ) interrupt 1 //T0 interrupt, interrupt 1 (location at 000BH)
{
}
void main()
S
{
WAKE_CLKO = 0x10; //enable P3.4/T0/INT
falling edge wakeup MCU
//from power-down mode
//T0_PIN_IE (WAKE_CLKO.4) = 1
//ET0 = 1; //enable T0 interrupt
while (1)
{
T0 = 1; //ready read T0 port
while (!T0); //check T0
_nop_();
_nop_();
_nop_();
_nop_();
P1++;
}
}

2. Assembly program
/* --- Mobile: (86)13922809991 ----------------------------------------------------------------------------------------*/
/* --- Fax: 86-755-82905966 --------------------------------------------------------------------------------------------*/
/* --- Tel: 86-755-82948412 ---------------------------------------------------------------------------------------------*/
d .
/*-----------------------------------------------------------------------------------------------------------------------------*/
mit e
WAKE_CLKO EQU 8FH
;-----------------------------------------
Li
ORG 0000H
U
LJMP MAIN
M
ORG 000BH ;T0 interrupt, interrupt 1 (location at 000BH)
LJMP T0INT
;-----------------------------------------
T C
ORG 0100H
S
MAIN:
MOV SP,#7FH ;initial SP
MOV WAKE_CLKO, #10H ;enable P3.4/T0/INT
;from power-down mode
;T0_PIN_IE (WAKE_CLKO.4) = 1
;SETB ET0 ;enable T0 interrupt
LOOP:
SETB T0 ;ready read T0 port
JNB T0 ,$ ;check T0
NOP
NOP
NOP
NOP
CPL P1.0
SJMP LOOP
;-----------------------------------------
;T0 interrupt service routine
T0INT:
RETI
;-----------------------------------------
END
6.7.4 Programs of P3.5/T1 Interrupt(falling edge) used to wake up PD mode

1. C program
/*-----------------------------------------------------------------------------------------------------------------------------*/
/* --- Mobile: (86)13922809991 ----------------------------------------------------------------------------------------*/
/* --- Fax: 86-755-82905966 --------------------------------------------------------------------------------------------*/
/* --- Tel: 86-755-82948412 ---------------------------------------------------------------------------------------------*/
d .
i t e
m
Li
/*-----------------------------------------------------------------------------------------------------------------------------*/
#include "reg51.h"
C U
M
sfr WAKE_CLKO = 0x8f;
C
T
void t1int() interrupt 3 //T1 interrupt, interrupt 3 (location at 001BH)
S
{
}
void main()
{
WAKE_CLKO = 0x20; //enable P3.5/T1/INT
//T1_PIN_IE / WAKE_CLKO.5 = 1
//ET1 = 1; //enable T1 interrupt
while (1)
{
T1 = 1; //ready read T1 port
while (!T1); //check T1
_nop_();
_nop_();
_nop_();
_nop_();
P1++;
}
}

2. Assembly program
/* --- Mobile: (86)13922809991 ----------------------------------------------------------------------------------------*/
/* --- Fax: 86-755-82905966 --------------------------------------------------------------------------------------------*/
/* --- Tel: 86-755-82948412 ---------------------------------------------------------------------------------------------*/
.
/*-----------------------------------------------------------------------------------------------------------------------------*/
ed
mit
WAKE_CLKO EQU 8FH
Li
;-----------------------------------------
ORG 0000H
U
LJMP MAIN
M
ORG 001BH ;T1 interrupt, interrupt 3 (location at 001BH)
LJMP T1INT
C
;-----------------------------------------
T
ORG 0100H
S
MAIN:
MOV WAKE_CLKO, #20H ;enable P3.5/T1/INT
;T1_PIN_IE / WAKE_CLKO.5 = 1
;SETB ET1 ;enable T1 interrupt
LOOP:
SETB T1 ;ready read T1 port
JNB T1, $ ;check T1
NOP
NOP
NOP
NOP
CPL P1.0
SJMP LOOP
;-----------------------------------------
T1INT:
RETI
;-----------------------------------------
END
6.7.5 Program of P3.0/RxD Interrupt(falling edge) used to wake up PD mode

1. C program
/*-----------------------------------------------------------------------------------------------------------------------------*/
/* --- STC 1T Series MCU Power-Down wakeup by RxD Demo -------------------------------------------------*/
/* ---This Interrupt will borrow RxD interrupt request bit RI and its interrupt vector address ----------------*/
/* ---So UART function should be disabled when this Interrupt is enabled --------------------------------------*/
/* ---The enable bit of this Interrupt is RXD_PIN_IE / WAKE_CLKO.6 in WAKE_CLKO register --------*/
/* --- Mobile: (86)13922809991 ----------------------------------------------------------------------------------------*/
/* --- Fax: 86-755-82905966 --------------------------------------------------------------------------------------------*/
/* --- Tel: 86-755-82948412 ---------------------------------------------------------------------------------------------*/
.
t ed
i
Li m
/*-----------------------------------------------------------------------------------------------------------------------------*/
U
#include "reg51.h"
C
typedef unsigned char BYTE;

M
C
typedef unsigned int WORD;
S T
/*Declare SFR associated with the RxD */
sfr WAKE_CLKO = 0x8F;
void uart_isr() interrupt 4 using 1

{
if (RI)
{
RI = 0;
}
}
void main()
{
WAKE_CLKO = 0x40; //enable P3.0/RxD/INT falling edge wakeup MCU
//RxD_PIN_IE (WAKE_CLKO.6) = 1
ES = 1;
EA = 1;

while (1)
{
RXD = 1; //ready read RXD port
while (!RXD); //check RXD
_nop_();
_nop_();
_nop_();
_nop_();
P2++;
}
}
ed .
2. Assembly program
Li mit
/*-----------------------------------------------------------------------------------------------------------------------------*/
U
C
/* --- STC 1T Series MCU Power-Down wakeup by RxD Demo -------------------------------------------------*/
M
/* ---This Interrupt will borrow RxD interrupt request bit RI and its interrupt vector address ----------------*/
/* ---So UART function should be disabled when this Interrupt is enabled --------------------------------------*/
C
/* ---The enable bit of this Interrupt is RXD_PIN_IE / WAKE_CLKO.6 in WAKE_CLKO register --------*/
S T
/* --- Mobile: (86)13922809991 ----------------------------------------------------------------------------------------*/
/* --- Fax: 86-755-82905966 --------------------------------------------------------------------------------------------*/
/* --- Tel: 86-755-82948412 ---------------------------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------------------------------------------------------*/
;/*Declare SFR associated with the RxD */

WAKE_CLKO EQU 8FH
;-----------------------------------------
ORG 0000H
LJMP MAIN
ORG 0023H
UART_ISR:
JBC RI, EXIT ;clear RI flag
EXIT:
RETI
;-----------------------------------------

ORG 0100H
MAIN:
MOV WAKE_CLKO, #40H ;enable P3.0/RxD falling edge wakeup MCU
;RxD_PIN_IE (WAKE_CLKO.6) = 1
SETB ES
SETB EA
LOOP:
SETB RXD ;ready read RXD port
JNB RXD, $ ;check RXD
NOP
.
NOP
d
i t e
NOP
m
NOP
Li
CPL P1.0
SJMP LOOP
;-----------------------------------------
C U
END
M
S T C

6.7.6 Program of PCA Interrupt used to wake up Power Down mode

1. C program
/*--------------------------------------------------------------------------------------------*/
/* --- STC MCU International Limited -----------------------------------------------*/
/* --- STC 1T Series MCU Power-Down wakeup by PCA Demo ----------------*/
/* --- Mobile: (86)13922809991 -------------------------------------------------------*/
/* --- Fax: 86-755-82905966 -----------------------------------------------------------*/
/* --- Tel: 86-755-82948412 ------------------------------------------------------------*/
/* --- Web: www.STCMCU.com ------------------------------------------------------*/
/* If you want to use the program or the program referenced in the -------------*/
/* article, please specify in which data and procedures from STC -------------*/
/*--------------------------------------------------------------------------------------------*/
ed .
mit
#include "reg51.h"
Li
/*Declare SFR associated with the PCA */
C U
M
C
sfr CCON = 0xD8; //PCA control register
S T
sbit CCF0 = CCON^0; //PCA module-0 interrupt flag
sbit CR = CCON^6; //PCA timer run control bit
sbit CF = CCON^7; //PCA timer overflow flag
sfr CMOD = 0xD9; //PCA mode register
sfr CL = 0xE9; //PCA base timer LOW
sfr CH = 0xF9; //PCA base timer HIGH
sfr CCAPM0= 0xDA; //PCA module-0 mode register
sfr CCAP0L = 0xEA; //PCA module-0 capture register LOW
sfr CCAP0H = 0xFA; //PCA module-0 capture register HIGH
sfr CCAPM1= 0xDB; //PCA module-1 mode register
sfr CCAP1L = 0xEB; //PCA module-1 capture register LOW
sfr CCAP1H = 0xFB; //PCA module-1 capture register HIGH
sfr CCAPM2= 0xDC; //PCA module-2 mode register
sfr CCAP2L = 0xEC; //PCA module-2 capture register LOW
sfr CCAP2H = 0xFC; //PCA module-2 capture register HIGH
sfr CCAPM3= 0xDD; //PCA module-3 mode register
sfr CCAP3L = 0xED; //PCA module-3 capture register LOW
sfr CCAP3H = 0xFD; //PCA module-3 capture register HIGH
sfr PCAPWM0 = 0xF2;
sfr PCAPWM1 = 0xF3;
sfr PCAPWM2 = 0xF4;
sfr PCAPWM3 = 0xF5;

sbit PCA_LED = P1^0; //PCA test LED

sbit CCP0 = P3^7;
void PCA_isr() interrupt 7 using 1

{
CCF0 = 0; //Clear interrupt flag
PCA_LED = !PCA_LED; //toggle the test pin while CCP0(P3.7) have a falling edge
}
void main()
{
CCON = 0; //Initial PCA control register
d .
//PCA timer stop running
t e
//Clear CF flag

m i
//Clear all module interrupt flag
Li
CL = 0; //Reset PCA base timer
CH = 0;
U
CMOD = 0x00; //Set PCA timer clock source as Fosc/12
C
//Disable PCA timer overflow interrupt
M
CCAPM0 = 0x11; //PCA module-0 capture by a negative tigger on CCP0(P3.7)
//and enable PCA interrupt
C
// CCAPM0 = 0x21; //PCA module-0 capture by a rising edge on CCP0(P3.7) and

//
S
CCAPM0 = 0x31;
T //enable PCA interrupt
//PCA module-0 capture by a transition (falling/rising edge)
//on CCP0(P3.7) and enable PCA interrupt
WAKE_CLKO = 0x80; //enable PCA falling/raising edge wakeup MCU

CR = 1; //PCA timer start run
EA = 1;
while (1)
{
CCP0 = 1; //ready read CCP0 port
while (!CCP0); //check CCP0
_nop_();
_nop_();
_nop_();
_nop_();
P2++;
}
}

2 Assembly program
/*--------------------------------------------------------------------------------------------*/
/* --- STC 1T Series MCU Power-Down wakeup by PCA Demo ----------------*/
/* --- Mobile: (86)13922809991 -------------------------------------------------------*/
/* --- Fax: 86-755-82905966 -----------------------------------------------------------*/
/* --- Tel: 86-755-82948412 ------------------------------------------------------------*/
/* --- Web: www.STCMCU.com ------------------------------------------------------*/
/* If you want to use the program or the program referenced in the -------------*/
/* article, please specify in which data and procedures from STC -------------*/
/*--------------------------------------------------------------------------------------------*/
d .
;/*Declare SFR associated with the PCA */
mit e
WAKE_CLKO EQU 8FH
Li
CCON EQU 0D8H ;PCA control register
CCF0 BIT CCON.0 ;PCA module-0 interrupt flag
U
C
CR BIT CCON.6 ;PCA timer run control bit
M
CF BIT CCON.7 ;PCA timer overflow flag
CMOD EQU 0D9H ;PCA mode register
C
CL EQU 0E9H ;PCA base timer LOW
CH
CCAPM0
CCAP0L
CCAP0H
EQU

S T
0F9H
EQU
EQU
EQU

0DAH
0EAH
0FAH

;PCA base timer HIGH
;PCA module-0 mode register
;PCA module-0 capture register LOW
;PCA module-0 capture register HIGH
CCAPM1 EQU 0DBH ;PCA module-1 mode register
CCAP1L EQU 0EBH ;PCA module-1 capture register LOW
CCAP1H EQU 0FBH ;PCA module-1 capture register HIGH
CCAPM2 EQU 0DCH ;PCA module-2 mode register
CCAP2L EQU 0ECH ;PCA module-2 capture register LOW
CCAP2H EQU 0FCH ;PCA module-2 capture register HIGH
CCAPM3 EQU 0DDH ;PCA module-3 mode register
CCAP3L EQU 0EDH ;PCA module-3 capture register LOW
CCAP3H EQU 0FDH ;PCA module-3 capture register HIGH
PCA_LED BIT P1.1 ;PCA test LED

CCP0 BIT P1.3

;-----------------------------------------
ORG 0000H
LJMP MAIN
ORG 003BH
PCA_ISR:
CLR CCF0 ;Clear interrupt flag
CPL PCA_LED ;toggle the test pin while CCP0(P3.7) have a falling edge
RETI
;-----------------------------------------
ORG 0100H
MAIN:
MOV CCON, #0 ;Initial PCA control register
d .
;PCA timer stop running
t e
;Clear CF flag

m i
;Clear all module interrupt flag
Li
CLR A ;
MOV CL, A ;Reset PCA base timer
U
MOV CH, A ;
C
MOV CMOD, #00H ;Set PCA timer clock source as Fosc/12
M
;Disable PCA timer overflow interrupt
MOV CCAPM0, #11H ;PCA module-0 capture by a falling edge on CCP0(P1.3)
T C
;and enable PCA interrupt
S
; MOV CCAPM0, #21H ;PCA module-0 capture by a rising edge on CCP0(P1.3)
; MOV CCAPM0, #31H ;PCA module-0 capture by a transition (falling/rising edge)
;on CCP0(P1.3) and enable PCA interrupt
;-------------------------------
MOV WAKE_CLKO, #80H ;enable PCA falling/raising edge wakeup MCU from
;power-down mode
SETB CR ;PCA timer start run
SETB EA
LOOP:
SETB CCP0 ;ready read CCP0 port
JNB CCP0, $ ;check CCP0
NOP
NOP
NOP
NOP
CPL P1.0
SJMP LOOP
;-----------------------------------------
END

Chapter 7. Timer/Counter 0/1

Timer 0 and timer 1 are like the ones in the conventional 8051, both of them can be individually configured as
timers or event counters.
In the Timer function, the register is incremented every 12 system clocks or every system clock depending on
AUXR.7(T0x12) bit and AUXR.6(T1x12). In the default state, it is fully the same as the conventional 8051. In
the x12 mode, the count rate equals to the system clock.
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding
external input pin, T0 or T1. In this function, the external input is sampled once at the positive edge of every clock
cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new
count value appears in the register during at the end of the cycle following the one in which the transition was
.
detected. Since it takes 2 machine cycles (24 system clocks) to recognize a l-to-0 transition, the maximum count
ed
rate is 1/24 of the system clock. There are no restrictions on the duty cycle of the external input signal, but to
mit
ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine
Li
cycle.
In addition to the Timer or Counter selection, Timer 0 and Timer 1 have four operating modes from which
U
to select. The Timer or Counter function is selected by control bits C/T in the Special Function Register
C
TMOD. These two Timer/Counter have four operating modes, which are selected by bit-pairs (M1, M0) in
M
TMOD. Modes 0, 1, and 2 are the same for both Timer/Counters. Mode 3 is different.The four operating modes
are described in the following text.
S T C
7.1 Special Function Registers about Timer/Counter
Value after
MSB LSB Reset
TCON Timer Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 0000 0000B
TMOD Timer Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 0000 0000B
TL0 Timer Low 0 8AH 0000 0000B
TL1 Timer Low 1 8BH 0000 0000B
TH0 Timer High 0 8CH 0000 0000B
TH1 Timer High 1 8DH 0000 0000B
Power down
Wake-up control
register

1. TCON register: Timer/Counter Control Register (Bit-Addressable)

TCON 88H name TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
d .
i t e
m
Li
U
M C
C
S T
ternal interrupt 1.
ternal interrupt 0.

2. TMOD register: Timer/Counter Mode Register

TMOD address: 89H (Non bit-addressable)
(MSB) (LSB)
GATE C/T M1 M0 GATE C/T M1 M0

} Timer 1
GATR/TMOD.7: Timer/Counter Gate Control.

Timer 0
If GATE/TMOD.7=0,Timer/Counter 1 enabled when TR1 is set irrespective of INT1 logic level;

If GATE/TMOD.7=1, Timer/Counter 1 enabled only when TR1 is set AND INT1 pin is high.
C/T /TMOD.6: Timer/Counter 1 Select bit.
If C/T /TMOD.6=0,Timer/Counter 1 is set for Timer operation (input from internal system clock);
If C/T /TMOD.6=0,Timer/Counter 1 is set for Counter operation (input from external T1 pin).
M1/TMOD.5 ~ M0/TMOD.4: Timer 1 Mode Select bits.
ed .
mit
M1 M0 Operating Mode
Li
0 0 Mode 0: 13-bit Timer/Counter for Timer 1
0 1 Mode 1: 16-bit Timer/Counter. TH1and TL1 are cascaded; there is no prescaler.
Mode 2: 8-bit auto-reload Timer/Counter. TH1 holds a value which is to be reloaded into TL1
U
1 0
each time it overflows.
Timer/Counter 1 stopped
C
1 1
GATR/TMOD.3: Timer/Counter Gate Control.

M
C
If GATE/TMOD.3=0,Timer/Counter 0 enabled when TR0 is set irrespective of INT0 logic level;
T
If GATE/TMOD.3=1, Timer/Counter 0 enabled only when TR0 is set AND INT0 pin is high.

S
C/T /TMOD.2: Timer/Counter 0 Select bit.
If C/T /TMOD.2=0,Timer/Counter 0 is set for Timer operation (input from internal system clock);
If C/T /TMOD.2=0,Timer/Counter 0 is set for Counter operation (input from external T0 pin).
M1/TMOD.1 ~ M0/TMOD.0: Timer 0 Mode Select bits.
M1 M0 Operating Mode
0 0 Mode 0: 13-bit Timer/Counter for Timer 0
0 1 Mode 1: 16-bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.
Mode 2: 8-bit auto-reload Timer/Counter. TH0 holds a value which is to be reloaded
1 0
into TL0 each time it overflows.
Mode3: TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits
1 1
TH0 is an 8-bit timer only controlled by Timer 1 control bits.


d .
i t e
m
Li
U
C
M
S T C
divided by 2.
divided by 2.

7.2 Timer/Counter 0 Mode of Operation (Compatible with traditional 8051 MCU)

Timer/Counter 0 can be configured for four modes by setting M1(TMOD.1) and M0(TMOD.0) in sepcial function
register TMOD.
7.2.1 Mode 0 (13-bit Timer/Counter)

Mode 0
In this mode, the timer 0 is configured as a 13-bit timer/counter. As the count rolls over from all 1s to all 0s, it sets
the timer interrupt flag TF0. The counted input is enabled to the timer when TR0 = 1 and either GATE=0 or INT0
= 1.(Setting GATE = 1 allows the Timer to be controlled by external input INT0 , to facilitate pulse width mea-
surements.) TR0 is a control bit in the Special Function Register TCON. GATE is in TMOD.
.
The 13-Bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are
ed
indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers.
Li mit
There are two different GATE bits. one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
U
AUXR.7/T0x12=0
12
SYSclk
1
M C
AUXR.7/T0x12=1
C/T=0 TL0 TH0
C
TF0 Interrupt
(5 Bits) (8 bits)
T
T0 Pin C/T=1
S
control
TR0
GATE
INT0
Timer/Counter 0 Mode 0: 13-Bit Timer/Counter

7.2.2 Mode 1 (16-bit Timer/Counter) and Demo Programs (C and ASM)

In this mode, the timer register is configured as a 16-bit register. As the count rolls over from all 1s to all 0s, it
sets the timer interrupt flag TF0. The counted input is enabled to the timer when TR0 = 1 and either GATE=0 or
INT0 = 1.(Setting GATE = 1 allows the Timer to be controlled by external input INT0 , to facilitate pulse width
measurements.) TR0 is a control bit in the Special Function Register TCON. GATE is in TMOD.
The 16-Bit register consists of all 8 bits of TH0 and the lower 8 bits of TL0. Setting the run flag (TR0) does not
clear the registers.
Mode 1 is the same as Mode 0, except that the timer register is being run with all 16 bits.
AUXR.7/T0x12=0
.
12
ed
SYSclk
i t
1
m
AUXR.7/T0x12=1
Li
C/T=0 TL0 TH0
TF0 Interrupt
C/T=1 (8 Bits) (8 bits)
T0 Pin
control
TR0
U
GATE
M C
INT0
Timer/Counter 0 Mode 1 : 16-Bit Timer/Counter
S T C
There are two simple programs that demostrates Timer 0 as 16-bit Timer/Counter, one written in C language
while other in Assembly language.
C Program:
/*-------------------------------------------------------------------------------*/
/* --- STC 1T Series 16-bit Timer Demo --------------------------------*/
/* --- Mobile: (86)13922809991 ------------------------------------------*/
/* --- Fax: 86-755-82905966 ----------------------------------------------*/
/* --- Tel: 86-755-82948412 -----------------------------------------------*/
/* --- Web: www.STCMCU.com ------------------------------------------*/
/*-------------------------------------------------------------------------------*/
#include "reg51.h"

//-----------------------------------------------
/* define constants */
#define FOSC 18432000L
#define MODE 1T //Timer clock mode, comment this line is 12T mode, uncomment is 1T mode

#ifdef MODE1T
#define T1MS (65536-FOSC/1000) //1ms timer calculation method in 1T mode
#else
#define T1MS (65536-FOSC/12/1000) //1ms timer calculation method in 12T mode
#endif
/* define SFR */
sfr AUXR = 0x8e; //Auxiliary register
sbit TEST_LED = P0^0; //work LED, flash once per second
/* define variables */
WORD count; //1000 times counter
.
//-----------------------------------------------
ed
mit
/* Timer0 interrupt routine */
Li
void tm0_isr() interrupt 1 using 1
{
TL0 = T1MS; //reload timer0 low byte
U
TH0 = T1MS >> 8; //reload timer0 high byte
C
if (count-- == 0) //1ms * 1000 -> 1s
M
{
count = 1000; //reset counter
TEST_LED = ! TEST_LED; //work LED flash
T C
}
S
}
//-----------------------------------------------
/* main program */
void main()
{
#ifdef MODE1T
AUXR = 0x80; //timer0 work in 1T mode
#endif
TMOD = 0x01; //set timer0 as mode1 (16-bit)
TL0 = T1MS; //initial timer0 low byte
TH0 = T1MS >> 8; //initial timer0 high byte
TR0 = 1; //timer0 start running
ET0 = 1; //enable timer0 interrupt
count = 0; //initial counter
while (1); //loop

}

Assembly Program:
;/*-------------------------------------------------------------------------------*/
;/* --- STC 1T Series 16-bit Timer Demo --------------------------------*/
;/* --- Mobile: (86)13922809991 -------------- ---------------------------*/
;/* --- Fax: 86-755-82905966 ----------------------------------------------*/
;/* --- Tel: 86-755-82948412 -----------------------------------------------*/
;/*------------------------------------------------------------------------------*/
;/* define constants */
#define MODE1T ;Timer clock mode, comment this line is 12T mode, uncomment is 1T mode
#ifdef MODE1T
t ed .
i
T1MS EQU 0B800H ;1ms timer calculation method in 1T mode is (65536-18432000/1000)
Li m
#else
T1MS EQU 0FA00H ;1ms timer calculation method in 12T mode is (65536-18432000/12/1000)
#endif
CU
;/* define SFR */
AUXR DATA 8EH ;Auxiliary register
M
TEST_LED BIT P1.0 ;work LED, flash once per second
T C
;/* define variables */
S
COUNT DATA 20H ;1000 times counter (2 bytes)
;-----------------------------------------------
ORG 0000H
LJMP MAIN
ORG 000BH
LJMP TM0_ISR
;-----------------------------------------------
;/* main program */
MAIN:
#ifdef MODE1T
MOV AUXR, #80H ;timer0 work in 1T mode
#endif
MOV TMOD, #01H ;set timer0 as mode1 (16-bit)
MOV TL0, #LOW T1MS ;initial timer0 low byte
MOV TH0, #HIGH T1MS ;initial timer0 high byte
SETB TR0 ;timer0 start running
SETB ET0 ;enable timer0 interrupt
CLR A
MOV COUNT, A
MOV COUNT+1, A ;initial counter
SJMP $

;-----------------------------------------------
;/* Timer0 interrupt routine */
TM0_ISR:
PUSH ACC
PUSH PSW
MOV TL0, #LOW T1MS ;reload timer0 low byte
MOV TH0, #HIGH T1MS ;reload timer0 high byte
MOV A, COUNT
ORL A, COUNT+1 ;check whether count(2byte) is equal to 0
JNZ SKIP
MOV COUNT, #LOW 1000 ;1ms * 1000 -> 1s
MOV COUNT+1,#HIGH 1000
CPL TEST_LED ;work LED flash
SKIP:
CLR C
ed .
mit
MOV A, COUNT ;count--
SUBB A, #1
Li
MOV COUNT, A
MOV A, COUNT+1
SUBB A, #0
MOV COUNT+1,A
C U
M
POP PSW
POP ACC
RETI
S T C
;-----------------------------------------------
END

7.2.3 Mode 2 (8-bit Auto-Reload Mode) and Demo Programs (C and ASM)
Mode 2 configures the timer register as an 8-bit counter(TL0) with automatic reload. Overflow from TL0 not
only set TF0, but also reload TL0 with the content of TH0, which is preset by software. The reload leaves TH0
unchanged.
AUXR.7/T0x12=0
12 TF0 Interrupt
SYSclk
1 Toggle
AUXR.7/T0x12=1
C/T=0 TL0
C/T=1 (8 Bits)
CLKOUT0
T0 Pin
control
TR0 P1.0
d .
GATE
e
T0CLKO
t
TH0
i
INT0 (8 Bits)
Li
m
U
C
M
S T C
(SYSclk) / (256 TH0) / 2,
or (SYSclk / 12) / (256 TH0) / 2 ,
when AUXR.7 / T0x12=1
when AUXR.7 / T0x12=0
T0_Pin_CLK / (256-TH0) / 2

;T0 Interrupt (falling edge) Demo programs, where T0 operated in Mode 2 (8-bit auto-relaod mode)
; The Timer Interrupt can not wake up MCU from Power-Down mode in the following programs
1. C program
/*----------------------------------------------------------------------------------*/
/* --- STC 1T Series MCU T0 (Falling edge) Demo ---------------------*/
/* --- Mobile: (86)13922809991 --------------------------------------------*/
/* --- Fax: 86-755-82905966 ------------------------------------------------*/
/* --- Tel: 86-755-82948412 -------------------------------------------------*/
/* --- Web: www.STCMCU.com -------------------------------------------*/
/* article, please specify in which data and procedures from STC ---*/
d .
/*---------------------------------------------------------------------------------*/
#include "reg51.h"
mit e
sfr AUXR = 0x8e;
Li
//Auxiliary register
//T0 interrupt service routine
C U
M
void t0int( ) interrupt 1 //T0 interrupt (location at 000BH)
{
C
}
void main()
{
AUXR = 0x80;
S T //timer0 work in 1T mode
TMOD = 0x06; //set timer0 as counter mode2 (8-bit auto-reload)
TL0 = TH0 = 0xff; //fill with 0xff to count one time
TR0 = 1; //timer0 start run
ET0 = 1; //enable T0 interrupt
while (1);
}

2. Assembly program
/*-------------------------------------------------------------------------------*/
/* --- STC 1T Series MCU T0(Falling edge) Demo -------------------*/
/* --- Mobile: (86)13922809991 ------------------------------------------*/
/* --- Fax: 86-755-82905966 ----------------------------------------------*/
/* --- Tel: 86-755-82948412 -----------------------------------------------*/
/*------------------------------------------------------------------------------*/
.
;-----------------------------------------
i t ed
m
Li
ORG 0000H
LJMP MAIN
C U
ORG 000BH ;T0 interrupt (location at 000BH)
M
LJMP T0INT
;-----------------------------------------

MAIN:

ORG
MOV SP,
MOV AUXR,
T C
0100H
S #7FH
#80H

;initial SP
;timer0 work in 1T mode
MOV TMOD, #06H ;set timer0 as counter mode2 (8-bit auto-reload)
MOV A, #0FFH
MOV TL0, A ;fill with 0xff to count one time
MOV TH0, A
SETB TR0 ;timer0 start run
SETB ET0 ;enable T0 interrupt
SJMP $
;-----------------------------------------
T0INT:
RETI
;-----------------------------------------
END

7.2.4 Mode 3 (Two 8-bit Timers/Couters)

Timer 1 in Mode 3 simply holds its count, the effect is the same as setting TR1 = 0. Timer 0 in Mode 3 established
TL0 and TH0 as two separate 8-bit counters. TL0 use the Timer 0 control bits: C/T,GATE,TR0, INT0 and TF0.
TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 from Tmer 1. Thus,
TH0 now controls the Timer 1 interrupt.
Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When Timer 0 is in Mode 3, Timer 1
can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a
baud rate generator, or in fact, in any application not requiring an interrupt.
AUXR.7/T0x12=0
12
.
SYSclk
ed
mit
1
TF0 Interrupt
C/T=1 (8 bit)
Li
T0 Pin control
TR0
GATE
C U
INT0
M
AUXR.7/T0x12=0
12
SYSclk TH0 TF1
C
(8 Bits) Interrupt
1
T
AUXR.7/T0x12=0 control
S
TR1
Timer/Counter 0 Mode 3: Two 8-Bit Timers/Counters

7.3 Timer/Counter 1 Mode of Operation

Timer/Counter 1 can be configured for three modes by setting M1(TMOD.5) and M0(TMOD.4) in sepcial
function register TMOD.
7.3.1 Mode 0 (13-bit Timer/Counter)

INT1= 1.(Setting GATE = 1 allows the Timer to be controlled by external input INT1, to facilitate pulse width
measurements.) TR0 is a control bit in the Special Function Register TCON. GATE is in TMOD.
The 13-Bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are
d .
indeterminate and should be ignored. Setting the run flag (TR1) does not clear the registers.
m i t e
Li
AUXR.6/T1x12=0
12
SYSclk
CU
1
AUXR.6/T1x12=1 C/T=0 TL1 TH1
M
(5 Bits) (8 bits) TF1 Interrupt
C/T=1
T1 Pin control
C
TR1
T
GATE
S
INT1
Timer/Counter 1 Mode 0: 13-Bit Timer/Counter

7.3.2 Mode 1 (16-bit Timer/Counter) and Demo Programs (C and ASM)

INT1 = 1.(Setting GATE = 1 allows the Timer to be controlled by external input INT1, to facilitate pulse width
measurements.) TRl is a control bit in the Special Function Register TCON. GATE is in TMOD.
The 16-Bit register consists of all 8 bits of THl and the lower 8 bits of TL1. Setting the run flag (TR1) does not
clear the registers.
Mode 1 is the same as Mode 0, except that the timer register is being run with all 16 bits.
AUXR.6/T1x12=0
12
d .
SYSclk
mit e
1
AUXR.6/T1x12=1 C/T=0 TL1 TH1
TF1 Interrupt
Li
C/T=1 (8 Bits) (8 bits)
T1 Pin
control
TR1
U
GATE
C
INT1
M
Timer/Counter 1 Mode 1 : 16-Bit Timer/Counter
S T C
There are another two simple programs that demostrates Timer 1 as 16-bit Timer/Counter, one written in C
language while other in Assembly language.
1. C Program
/*-------------------------------------------------------------------------------*/
/* --- STC 1T Series 16-bit Timer Demo --------------------------------*/
/* --- Mobile: (86)13922809991 ------------------------------------------*/
/* --- Fax: 86-755-82905966 ----------------------------------------------*/
/* --- Tel: 86-755-82948412 -----------------------------------------------*/
/*-------------------------------------------------------------------------------*/
#include "reg51.h"


//-----------------------------------------------
#define MODE1T //Timer clock mode, comment this line is 12T mode, uncomment is 1T mode
#ifdef MODE1T
#define T1MS (65536-FOSC/1000) //1ms timer calculation method in 1T mode
#else
#define T1MS (65536-FOSC/12/1000) //1ms timer calculation method in 12T mode
#endif
/* define SFR */
.
sbit TEST_LED = P0^0; //work LED, flash once per second
/* define variables */
i t ed
Li m
WORD count; //1000 times counter
//-----------------------------------------------
U
/* Timer0 interrupt routine */
C
void tm1_isr() interrupt 3 using 1
M
{
TL1 = T1MS; //reload timer1 low byte
C
TH1 = T1MS >> 8; //reload timer1 high byte
S T
if (count-- == 0) //1ms * 1000 -> 1s
{
count = 1000; //reset counter
TEST_LED = ! TEST_LED; //work LED flash
}
}
//-----------------------------------------------
/* main program */
void main()
{
#ifdef MODE1T
#endif
TMOD = 0x10; //set timer1 as mode1 (16-bit)
TL1 = T1MS; //initial timer1 low byte
TH1 = T1MS >> 8; //initial timer1 high byte
ET1 = 1; //enable timer1 interrupt
count = 0; //initial counter
while (1); //loop

}

2. Assembly Program
;/*---------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited ------------------------------------*/
;/* --- STC 1T Series 16-bit Timer Demo ----------------------------------*/
;/* --- Mobile: (86)13922809991 -------------------------------------------*/
;/* --- Fax: 86-755-82905966 -----------------------------------------------*/
;/* --- Tel: 86-755-82948412 -----------------------------------------------*/
;/*------------------------------------------------------------------------------*/
#define MODE1T ;Timer clock mode, comment this line is 12T mode, uncomment is 1T mode
#ifdef MODE1T
ed .
mit
T1MS EQU 0B800H ;1ms timer calculation method in 1T mode is (65536-18432000/1000)
#else
Li
T1MS EQU 0FA00H ;1ms timer calculation method in 12T mode is (65536-18432000/12/1000)
#endif
CU
;/* define SFR */
M
TEST_LED BIT P1.0 ;work LED, flash once per second
C
;/* define variables */
COUNT DATA
S T 20H
;-----------------------------------------------
ORG 0000H
;1000 times counter (2 bytes)
LJMP MAIN
ORG 001BH
LJMP TM1_ISR
;-----------------------------------------------
;/* main program */
MAIN:
#ifdef MODE1T
#endif
MOV TMOD, #10H ;set timer1 as mode1 (16-bit)
MOV TL1, #LOW T1MS ;initial timer1 low byte
MOV TH1, #HIGH T1MS ;initial timer1 high byte
SETB TR1 ;timer1 start running
SETB ET1 ;enable timer1 interrupt
CLR A
MOV COUNT, A
MOV COUNT+1,A ;initial counter
SJMP $
;-----------------------------------------------
;/* Timer1 interrupt routine */

TM1_ISR:
PUSH ACC
PUSH PSW
MOV TL1, #LOW T1MS ;reload timer1 low byte
MOV TH1, #HIGH T1MS ;reload timer1 high byte
MOV A, COUNT
ORL A, COUNT+1 ;check whether count(2byte) is equal to 0
JNZ SKIP
MOV COUNT, #LOW 1000 ;1ms * 1000 -> 1s
.
MOV COUNT+1,#HIGH 1000
ed
CPL TEST_LED ;work LED flash
i t
SKIP:
Li m
CLR C
MOV A, COUNT ;count--
SUBB A, #1
C U
MOV COUNT, A
M
MOV A, COUNT+1
SUBB A, #0
C
MOV COUNT+1,A
T
POP PSW

POP ACC
RETI
S
;-----------------------------------------------
END

7.3.3 Mode 2 (8-bit Auto-Reload Mode) and Demo Programs (C and ASM)
Mode 2 configures the timer register as an 8-bit counter(TL1) with automatic reload. Overflow from TL1 not
only set TFx, but also reload TL1 with the content of TH1, which is preset by software. The reload leaves TH1
unchanged.
AUXR.6/T1x12=0
12 TF1 Interrupt
SYSclk
1 Toggle
T1 Pin control
P1.1
TR1
GATE TH1 T1CLKO
.
(8 Bits)
d
INT1
mit e
Li
U
M C
C
S T
T1_Pin_CLK / (256-TH1) / 2

;T1 Interrupt (falling edge) Demo programs, where T1 operated in Mode 2 (8-bit auto-relaod mode)
; The Timer Interrupt can not wake up MCU from Power-Down mode in the following programs
1. C program
/*-------------------------------------------------------------------------------*/
/* --- Mobile: (86)13922809991 ------------------------------------------*/
/* --- Fax: 86-755-82905966 ----------------------------------------------*/
/* --- Tel: 86-755-82948412 -----------------------------------------------*/
.
ed
/*------------------------------------------------------------------------------*/
m i t
Li
#include "reg51.h"
C U
M
//T1 interrupt service routine
void t1int( ) interrupt 3 //T1 interrupt (location at 001BH)
C
{
T
}
void main()
{
AUXR = 0x40;
S //timer1 work in 1T mode
TMOD = 0x60; //set timer1 as counter mode2 (8-bit auto-reload)
TL1 = TH1 = 0xff; //fill with 0xff to count one time
TR1 = 1; //timer1 start run
ET1 = 1; //enable T1 interrupt
while (1);
}

2. Assembly program
/*-------------------------------------------------------------------------------*/
/* --- Mobile: (86)13922809991 ------------------------------------------*/
/* --- Fax: 86-755-82905966 ----------------------------------------------*/
/* --- Tel: 86-755-82948412 -----------------------------------------------*/
/*------------------------------------------------------------------------------*/

;-----------------------------------------
ed .
mit
Li
ORG 0000H
LJMP MAIN
ORG 001BH
C U ;T1 interrupt (location at 001BH)
M
LJMP T1INT
;-----------------------------------------
T C
ORG 0100H
S
MAIN:
MOV TMOD, #60H ;set timer1 as counter mode2 (8-bit auto-reload)
MOV A, #0FFH
MOV TL1, A ;fill with 0xff to count one time
MOV TH1, A
SETB TR1 ;timer1 start run
SETB ET1 ;enable T1 interrupt
SJMP $
;-----------------------------------------
T1INT:
RETI
;-----------------------------------------
END

7.4 Programmable Clock Output and Demo Programs (C and ASM)

STC12C5620AD series MCU have two channel programmable clock outputs, they are Timer 0 programmable
clock output CLKOUT0(P1.0) and Timer 1 programmable clock output CLKOUT1(P1.1).
There are some SFRs about programmable clock output as shown below.
Value after
MSB LSB Reset
Power down
Wake-up control
.
register
The satement (used in C language) of Special function registers AUXR/WAKE_CLKO:
sfr AUXR = 0x8E;
i t ed
//The address statement of Special function register AUXR
Li m
//The address statement of SFR WAKE_CLKO
The satement (used in Assembly language) of Special function registers AUXR/WAKE_CLKO:

AUXR EQU 0x8E
C U ;The address statement of Special function register AUXR
M
WAKE_CLKO EQU 0x8F ;The address statement of SFR WAKE_CLKO
SFR name
AUXR
Address
8EH
S T C bit B7 B6 B5 B4
name T0x12 T1x12 UART_M0x6 EADCI
B3
ESPI
B2
ELVDI
B1
-
B0
-


.
ed
mit
LVD_WAKE: When set and the associated-LVD interrupt control registers is configured correctly, the CMPIN
pin is enabled to wake up MCU from power-down state.
Li
divided by 2.
U
C
divided by 2.
M
S T C

7.4.1 Timer 0 Programmable Clock-out on P1.0 and Demo Program(C and ASM)
AUXR.7/T0x12=0
12 TF0 Interrupt
SYSclk
1 Toggle
AUXR.7/T0x12=1
C/T=0 TL0
C/T=1 (8 Bits)
CLKOUT0
T0 Pin
control
TR0 P1.0
GATE T0CLKO
TH0
INT0 (8 Bits)
.
i t ed
m
Li
U
C
M
T C
S
T0_Pin_CLK / (256-TH0) / 2
The following programs demostrate Program Clock Output on P1.0 pin when Timer 0 operates as 8-bit auto-
reload Timer/Counter.
1. C Program:
/*--------------------------------------------------------------------------------*/
/* --- STC 1T Series Programmable Clock Output Demo -------------*/
/* --- Mobile: (86)13922809991 -------------- ----------------------------*/
/* --- Fax: 86-755-82905966 ----------------------------------------------*/
/* --- Tel: 86-755-82948412 -----------------------------------------------*/
/*-------------------------------------------------------------------------------*/
#include "reg51.h"
//-----------------------------------------------
//#define MODE 1T //Timer clock mode, comment this line is 12T mode, uncomment is 1T mode

#ifdef MODE 1T
#define F38_4KHz (256-FOSC/2/38400) //38.4KHz frequency calculation method of 1T mode
#else
#define F38_4KHz (256-FOSC/2/12/38400) //38.4KHz frequency calculation method of 12T mode
#endif
/* define SFR */
sfr WAKE_CLKO = 0x8f; //wakeup and clock output control register
sbit T0CLKO = P1^0; //timer0 clock output pin
//-----------------------------------------------
d .
/* main program */
mit e
void main()
{
Li
#ifdef MODE1T
U
#endif
C
TMOD = 0x02; //set timer0 as mode2 (8-bit auto-reload)
M
TL0 = F38_4KHz; //initial timer0
TH0 = F38_4KHz; //initial timer0
C
S T
WAKE_CLKO = 0x01; //enable timer0 clock output
while (1); //loop

}
2. Assembly Program:
;/*--------------------------------------------------------------------------------*/
;/* --- STC 1T Series Programmable Clock Output Demo -------------*/
;/* --- Mobile: (86)13922809991 -------------- ----------------------------*/
;/* --- Fax: 86-755-82905966 -----------------------------------------------*/
;/* --- Tel: 86-755-82948412 -----------------------------------------------*/
;/*-------------------------------------------------------------------------------*/

#define MODE 1T ;Timer clock mode, comment this line is 12T mode, uncomment is 1T mode

#ifdef MODE 1T
F38_4KHz EQU 010H ;38.4KHz frequency calculation method of 1T mode is (256-18432000/2/38400)
#else
F38_4KHz EQU 0ECH ;38.4KHz frequency calculation method of 12T mode (256-18432000/2/12/38400)
#endif
;/* define SFR */

WAKE_CLKO DATA 08FH ;wakeup and clock output control register
T0CLKO BIT P1.0 ;timer0 clock output pin
;-----------------------------------------------
ORG 0000H
t ed .
i
LJMP MAIN
m
;-----------------------------------------------
;/* main program */

Li
CU
MAIN:
#ifdef MODE1T
M
#endif
C
MOV TMOD, #02H ;set timer0 as mode2 (8-bit auto-reload)
T
MOV TL0, #F38_4KHz ;initial timer0
S
MOV TH0, #F38_4KHz ;initial timer0
SETB TR0
MOV WAKE_CLKO, #01H ;enable timer0 clock output
SJMP $
;-----------------------------------------------
END

7.4.2 Timer 1 Programmable Clock-out on P1.1 and Demo Program(C and ASM)
AUXR.6/T1x12=0
12 TF1 Interrupt
SYSclk
1 Toggle
T1 Pin control
P1.1
TR1
GATE TH1 T1CLKO
(8 Bits)
INT1
ed .
mit
Li
U
C
M

S T C
T1_Pin_CLK / (256-TH1) / 2
The following programs demostrate Program Clock Output on Timer 1 pin when Timer 1 operates as 8-bit auto-
reload Timer/Counter.
1. C Program:
/*-------------------------------------------------------------------------------*/
/* --- STC 1T Series Programmable Clock Output Demo ------------*/
/* --- Mobile: (86)13922809991 -------------- ---------------------------*/
/* --- Fax: 86-755-82905966 ----------------------------------------------*/
/* --- Tel: 86-755-82948412 -----------------------------------------------*/
/*-------------------------------------------------------------------------------*/
#include "reg51.h"
//-----------------------------------------------

//#define MODE 1T //Timer clock mode, comment this line is 12T mode, uncomment is 1T mode
#ifdef MODE 1T
#define F38_4KHz (256-FOSC/2/38400) //38.4KHz frequency calculation method of 1T mode
#else
#define F38_4KHz (256-FOSC/2/12/38400) //38.4KHz frequency calculation method of 12T mode
#endif
/* define SFR */
sfr WAKE_CLKO = 0x8f; //wakeup and clock output control register
sbit T1CLKO = P1^1; //timer1 clock output pin
d .
//-----------------------------------------------
/* main program */
m i t e
Li
void main()
{
#ifdef MODE1T
C U
#endif

TMOD =
TL1 =
0x20;
F38_4KHz;
M

//set timer1 as mode2 (8-bit auto-reload)
//initial timer1
T C
TH1 = F38_4KHz; //initial timer1
S
WAKE_CLKO = 0x02; //enable timer1 clock output

while (1); //loop
}

2. Assembly Program:
;/*---------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited ------------------------------------*/
;/* --- STC 1T Series Programmable Clock Output Demo --------------*/
;/* --- Mobile: (86)13922809991 -------------------------------------------*/
;/* --- Fax: 86-755-82905966 -----------------------------------------------*/
;/* --- Tel: 86-755-82948412 ------------------------------------------------*/
;/*-------------------------------------------------------------------------------*/

#define MODE 1T
d .
;Timer clock mode, comment this line is 12T mode, uncomment is 1T mode
e
Li mit
#ifdef MODE 1T
F38_4KHz EQU 010H ;38.4KHz frequency calculation method of 1T mode is (256-18432000/2/38400)
#else
U
F38_4KHz EQU 0ECH ;38.4KHz frequency calculation method of 12T mode (256-18432000/2/12/38400)
C
#endif
;/* define SFR */

M
C
T
WAKE_CLKO DATA 08FH ;wakeup and clock output control register
T1CLKO
S
BIT P1.1
;-----------------------------------------------
ORG 0000H
;timer1 clock output pin
LJMP MAIN
;-----------------------------------------------
;/* main program */
MAIN:
#ifdef MODE1T
#endif
MOV TMOD, #20H ;set timer1 as mode2 (8-bit auto-reload)
MOV TL1, #F38_4KHz ;initial timer1
MOV TH1, #F38_4KHz ;initial timer1
SETB TR1
MOV WAKE_CLKO, #02H ;enable timer1 clock output
SJMP $
;-----------------------------------------------
END

7.5 Application note for Timer in practice

(1) Real-time Timer
Timer/Counter start running, When the Timer/Counter is overflow, the interrupt request generated, this
action handle by the hardware automatically, however, the process which from propose interrupt request to
respond interrupt request requires a certain amount of time, and that the delay interrupt request on-site with
the environment varies, it normally takes three machine cycles of delay, which will bring real-time processing
bias. In most occasions, this error can be ignored, but for some real-time processing applications, which
require compensation.
Such as the interrupt response delay, for timer mode 0 and mode 1, there are two meanings: the first,
because of the interrupt response time delay of real-time processing error; the second, if you require multiple
consecutive timing, due to interruption response delay, resulting in the interrupt service program once again
sets the count value is delayed by several count cycle.
ed .
If you choose to use Timer/Counter mode 1 to set the system clock, these reasons will produce real-time
t
i
error for this situation, you should use dynamic compensation approach to reducing error in the system clock,
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compensation method can refer to the following example program.

CLR EA ;disable interrupt
U
MOV A, TLx ;read TLx
C
ADD A, #LOW ;LOW is low byte of compensation value
M
MOV TLx, A ;update TLx
MOV A, THx ;read THx
C
ADDC A, #HIGH ;HIGH is high byte of compensation value
S T
MOV THx, A ;update THx
SETB EA ;enable interrupt

(2) Dynamic read counts

When dynamic read running timer count value, if you do not pay attention to could be wrong, this is because it
is not possible at the same time read the value of the TLx and THx. For example the first reading TLx then THx,
because the timer is running, after reading TLx, TLx carry on the THx produced, resulting in error; Similarly,
after the first reading of THx then TLx, also have the same problems.
A kind of way avoid reading wrong is first reading THx then TLx and read THx once more, if the THx twice
to read the same value, then the read value is correct, otherwise repeat the above process. Realization method
reference to the following example code.

RDTM: MOV A, THx ;save THx to ACC
MOV R0, TLx ;save TLx to R0
CJNE A, THx, RDTM ;read THx again and compare with the previous value
MOV R1, A ;save THx to R1


Chapter 8. UART with Enhanced Function

The serial port is full duplex,meaning it can transmit and receive simultaneously. It is also receive-buffered,
meaning it can commence reception of a second byte before a previously received byte has been read from the
reeeive register. (However,if the first byte still hasnt been read by the time reception of the second byte is
complete, one of the bytes will be lost). The serial port receive and transmit share the same SFR SBUF, but
actually there is two SBUF in the chip, one is for transmit and the other is for receive.
The serial port(UART) can be operated in 4 different modes: Mode 0 provides synchronous communication
while Modes 1, 2, and 3 provide asynchronous communication. The asynchronous communication operates
as a full-duplex Universal Asynchronous Receiver and Transmitter (UART), which can transmit and receive
simultaneously and at different baud rates.
Serial communiction involves the transimission of bits of data through only one communication line. The data are
d .
transimitted bit by bit in either synchronous or asynchronous format. Synchronous serial communication transmits
mit e
ont whole block of characters in syschronization with a reference clock while asynchronous serial communication
randomly transmits one character at any time, independent of any clock.
8.1 Special Function Registers about UART

Li
CU
Value after
M
MSB LSB Reset
C
AUXR Auxiliary register 8EH - 0000 00xxB
T
T0x12 T1x12 UART_M0x6 EADCI ESPI ELVDI -
S
SBUF Serial Buffer 99H xxxx xxxxB
IP Interrupt Priority Low B8H - PPCA_LVD PADC_LVD PS PT1 PX1 PT0 PX0 x000 0000B
IPH Interrupt Priority High B7H - PPCA_LVDH PADC_LVDH PSH PT1H PX1H PT0H PX0H x000 0000B
SADEN Slave Address Mask B9H 0000 0000B
SADDR Slave Address A9H 0000 0000B
CLK_Output Power down PCAWAKEUP RxD_PIN_IE T1_PIN_IE T0_PIN_IE - - T1CLKO T0CLKO
Wake-up control register

1. Serial Port 1 (UART1) Control Register: SCON and PCON
Serial port 1 of STC12C5620AD series has two control registers: Serial port control register (SCON) and
PCON which used to select Baud-Rate
SCON: Serial port Control Register (Bit-Addressable)
SCON 98H name SM0/FE SM1 SM2 REN TB8 RB8 TI RI
FE: Framing Error bit. The SMOD0 bit must be set to enable access to the FE bit
0: The FE bit is not cleared by valid frames but should be cleared by software.
1: This bit set by the receiver when an invalid stop bit id detected.
SM0,SM1 : Serial Port Mode Bit 0/1.
SM0 SM1 Description Baud rate
d .
0 0 8-bit shift register SYSclk/12
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1 0 9-bit UART
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SYSclk/64 or SYSclk/32(SMOD=1)
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U
SM2 : Enable the automatic address recognition feature in mode 2 and 3. If SM2=1, RI will not be
C
set unless the received 9th data bit is 1, indicating an address, and the received byte is a
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Given or Broadcast address. In mode1, if SM2=1 then RI will not be set unless a valid stop
Bit was received, and the received byte is a Given or Broadcast address. In mode 0, SM2 should be 0.
S T C
REN : When set enables serial reception.
TB8 : The 9th data bit which will be transmitted in mode 2 and 3.
RB8 : In mode 2 and 3, the received 9th data bit will go into this bit.
TI : Transmit interrupt flag. Set by hardware when a byte of data has been transmitted by UART0 (after the 8th
bit in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART0 in-
terrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine. This bit
must be cleared manually by software.
RI : Receive interrupt flag. Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sam-pling time). When the UART0 interrupt is enabled, setting this bit to 1 causes the CPU to
vector to the UART0 interrupt service routine. This bit must be cleared manually by software.
SMOD/PCON.7 in PCON register can be used to set whether the baud rates of mode 1, mode2 and mode 3
are doubled or not.
PCON: Power Control register (Non bit-addressable)
SMOD: double Baud rate control bit.
0 : Disable double Baud rate of the UART.
1 : Enable double Baud rate of the UART in mode 1,2,or 3.
SMOD0: Frame Error select.
0 : SCON.7 is SM0 function.
1 : SCON.7 is FE function. Note that FE will be set after a frame error regardless of the state of SMOD0.

2. SBUF: Serial port 1 Data Buffer register (Non bit-addressable)

SBUF 99H name
It is used as the buffer register in transmission and reception.The serial port buffer register (SBUF) is really two
buffers. Writing to SBUF loads data to be transmitted, and reading SBUF accesses received data. These are two
separate and distinct registers, the transimit write-only register, and the receive read-only register.

.
ed
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M
S T C

4. Slave Address Control registers SADEN and SADDR

SADEN: Slave Address Mask register
SADDR: Slave Address register
SADDR register is combined with SADEN register to form Given/Broadcast Address for automatic address
recognition. In fact, SADEN function as the "mask" register for SADDR register. The following is the example
for it.
SADDR = 1100 0000
SADEN = 1111 1101
Given = 1100 00x0 The Given slave address will be checked except bit 1 is
treated as "don't care".
The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zero in this
result is considered as "don't care" and a Broad cast Address of all " don't care". This disables the automatic
.
address detection feature.
i t ed
5. Power down wake-up register: WAKE_CLKO (Non bit-Addressable)
SFR name Address bit B7 B6 B5
LiB4 m B3 B2 B1 B0
U
8FH name
C
WAKE_CLKO PCAWAKEUP RXD_PIN_IE T1_PIN_IE T0_PIN_IE - - T1CKLO T0CKLO
M
C
T1_PIN_IE :
S T
When set and the associated-Timer1 interrupt control registers is configured correctly, the T1 pin
divided by 2.
divided by 2.

6. Registers related with UART1 interrupt : IE, IP and IPH

ES : Serial port 1(UART1) interrupt enable bit.
If ES = 0, Serial port (UART) interrupt will be diabled.
If ES = 1, Serial port (UART) interrupt is enabled.0
.
i
B4
t ed
B3 B2 B1 B0
m
L i B4 B3 B2 B1 B0
IP B8H name -
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PPCA_LVD PADC_SPI PS PT1 PX1 PT0 PX0
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PSH, PS: Serial Port (UART) interrupt priority control bits.
if PSH=0 and PS=0, UART interrupt is assigned lowest priority (priority 0).
C
if PSH=0 and PS=1, UART interrupt is assigned lower priority (priority 1).
T
if PSH=1 and PS=0, UART interrupt is assigned higher priority (priority 2).
S
if PSH=1 and PS=1, UART interrupt is assigned highest priority (priority 3).

8.2 UART1 Operation Modes

The serial port 1 (UART) can be operated in 4 different modes which are configured by setting SM0 and SM1
in SFR SCON. Mode 1, Mode 2 and Mode 3 are asynchronous communication. In Mode 0, UART1 is used as a
simple shift register.
8.2.1 Mode 0: 8-Bit Shift Register

Mode 0, selected by writing 0s into bits SM1 and SM0 of SCON, puts the serial port into 8-bit shift register mode.
Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted/received
with the least-significant (LSB) first. The baud rate is fixed at 1/12 the System clock cycle in the default state. If
AUXR.5(UART_M0x6) is set, the baud rate is 1/2 System clock cycle.
.
Transmission is initiated by any instruction that uses SBUF as a destination register. The write to SBUF signal
ed
also loads a 1 into the 9th position of the transmit shift register and tells the TX Control block to commence a
i t
transmission. The internal timing is such that one full system clock cycle will elapse between "write to SBUF,"
m
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and activation of SEND.
SEND transfers the output of the shift register to the alternate output function line of P3.0, and also transfers Shift
U
Clock to the alternate output function line of P3.1. At the falling edge of the Shift Clock, the contents of the shift
C
register are shifted one position to the right.
M
As data bits shift out to the right, 0 come in from the left. When the MSB of the data byte is at the output
C
position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the
S T
MSB, and all positions to the left of that contains zeroes. This condition flags the TX Control block to do one last
shift and then deactivate SEND and set TI. Both of these actions occur after "write to SBUF".
Reception is initiated by the condition REN=1 and RI=0. After that, the RX Control unit writes the bits 11111110
to the receive shift register, and in the next clock phase activates RECEIVE. RECEIVE enables SHIFT CLOCK
to the alternate output function line of P3.1.At RECEIVE is active, the contents of the receive shift register are
shifted to the left one position. The value that comes in from the right is the value that was sampled at the P3.0
pin the rising edge of Shift clock.
As data bits come in from the right, 1s shift out to the left. When the 0 that was initially loaded into the right-
most position arrives at the left-most position in the shift register, it flags the RX Control block to do one last shift
and load SBUF. Then RECEIVE is cleared and RI is set.

INTERNAL BUS
WRITE
TO
SBUF DS Q SBUF
RXD/P3.0
OUTPUT FUNCTION
CL
SHIFT
ZERO DETECTOR
START SHIFT
SYSclk/12 0 TX CONTROL
TX CLOCK TI SEND
1 SERIAL
SYSclk/2 PORT
INTERRUPT SHIFT TXD/P3.1
.
CLOCK OUTPUT FUNCTION
d
RX CLOCK RI RECEIVE
e
AUXR.5(UART_M0x6)
mit
RX CONTROL SHIFT
REN START 1 1 1 1 1 1 1 0
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RI
INPUT SHIFT REG. RXD/P3.0

INPUT FUNCTION
U
LOAD
C
SBUF SHIFT
M SBUF
C
READ
T
SBUF
S INTERNAL BUS
WRITE TO SBUF
SEND
SHIFT
TRANSMIT
RXD(DATA OUT) D0 D1 D2 D3 D4 D5 D6 D7
TXD(SHIFT CLOCK)
TI
WRITE TO SCON(CLEAR RI)
RI
RECEIVE
SHIFT RECEIVE
D0 D1 D2 D3 D4 D5 D6 D7
RXD(DATA IN)
TXD(SHIFT CLOCK)
Serial Port Mode 0

8.2.2 Mode 1: 8-Bit UART with Variable Baud Rate

10 bits are transmitted through TXD or received through RXD. The frame data includes a start bit(0), 8 data bits
and a stop bit(1). One receive, the stop bit goes into RB8 in SFR SCON. The baud rate is determined by the
Timer 1 or BRT overflow rate.
Baud rate in mode 1 = (2SMOD /32 ) x Timer 1 overflow rate

When T1x12=0, Timer 1 overflow rate = SYSclk/12/(256-TH1);
When T1x12=1, Timer 1 overflow rate = SYSclk / (256-TH1);
Transmission is initiated by any instruction that uses SBUF as a destination register. The write to SBUF
signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX Control unit that a
transmission is requested. Transmission actually happens at the next rollover of divided-by-16 counter. Thus the
bit times are synchronized to the divided-by-16 counter, not to the write to SBUF signal.
d .
The transmission begins with activation of SEND , which puts the start bit at TXD. One bit time later, DATA is
t e
i
activated, which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit
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time after that.
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As data bits shift out to the right, zeroes are clocked in from the left. When the MSB of the data byte is at the
output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the
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MSB, and all positions to the left of that contain zeroes. This condition flags the TX Control unit to do one last
shift and then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after write to SBUF.
M
Reception is initiated by a 1-to-0 transition detected at RXD. For this purpose, RXD is sampled at a rate of 16
C
times the established baud rate. When a transition is detected, the divided-by-16 counter is immediately reset,
S T
and 1FFH is written into the input shift register. Resetting the divided-by-16 counter aligns its roll-overs with the
boundaries of the incoming bit times.
The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th and 9th counter states of each bit time,
the bit detector samples the value of RXD. The value accepted is the value that was seen in at least 2 of the 3
samples. This is done to reject noise. In order to reject false bits, if the value accepted during the first bit time is
not a 0, the receive circuits are reset and the unit continues looking for another 1-to-0 transition. This is to provide
rejection of false start bits. If the start bit is valid, it is shifted into the input shift register, and reception of the rest
of the frame proceeds.
As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the left most position
in the shift register,(which is a 9-bit register in Mode 1), it flags the RX Control block to do one last shift, load
SBUF and RB8, and set RI. The signal to load SBUF and RB8 and to set RI is generated if, and only if, the
following conditions are met at the time the final shift pulse is generated.
1) RI=0 and
2) Either SM2=0, or the received stop bit = 1
If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the
stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At this time, whether or not the above
conditions are met, the unit continues looking for a 1-to-0 transition in RXD.

INTERNAL BUS
TB8
Timer 1 WRITE
Overflow TO
DS Q SBUF
SBUF TXD
CL
2 ZERO DETECTOR
SMOD SMOD
=0 =1
START SHIFT DATA
TX CONTROL
16 TX CLOCK TI SEND
SERIAL
PORT
d .
INTERRUPT
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16
SAMPLE
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1-TO-0 RX CLOCK RI LOAD
TRANSITION START SBUF
DETECTOR
RX CONTROL SHIFT
1FFH
C U BIT
M
DETECTOR
INPUT SHIFT REG.
RXD (9 BITS)
T C LOAD SHIFT
S
SBUF
SBUF
READ
SBUF
INTERNAL BUS
TX
CLOCK
WRITE TO SBUF
SEND
DATA TRANSMIT
SHIFT
TXD D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT
TI START BIT
RX CLOCK
RXD D1 D2 D3 D4 D5 D6 D7
START BIT D0 STOP BIT
RECEIVE BIT DETECTOR SAMPLE TIMES
SHIFT
RI
Serial Port Mode 1

8.2.3 Mode 2: 9-Bit UART with Fixed Baud Rate

11 bits are transmitted through TXD or received through RXD. The frame data includes a start bit(0), 8 data
bits, a programmable 9th data bit and a stop bit(1). On transmit, the 9th data bit comes from TB8 in SCON. On
receive, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 the System
clock cycle.
Baud rate in mode 2 = (2SMOD/64) x SYSclk
Transmission is initiated by any instruction that uses SBUF as a destination register. The write to SBUF
signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a
transmission is requested. Transmission actually happens at the next rollover of divided-by-16 counter. Thus the
bit times are synchronized to the divided-by-16 counter, not to the write to SBUF signal.
.
The transmission begins when /SEND is activated, which puts the start bit at TXD. One bit time later, DATA is
ed
activated, which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit
i t
time after that. The first shift clocks a 1(the stop bit) into the 9th bit position on the shift register. Thereafter,
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only 0s are clocked in. As data bits shift out to the right, 0s are clocked in from the left. When TB8 of the data
byte is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the
left of that contains 0s. This condition flags the TX Control unit to do one last shift, then deactivate /SEND and
U
set TI. This occurs at the 11th divided-by-16 rollover after write to SBUF.
M C
Reception is initiated by a 1-to-0 transition detected at RXD. For this purpose, RXD is sampled at a rate of
16 times whatever baud rate has been estabished. When a transition is detected, the divided-by-16 counter is
C
immediately reset, and 1FFH is written into the input shift register.
S T
At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RXD. The value accepted
is the value that was seen in at least 2 of the 3 samples. This is done to reject noise. In order to reject false bits, if
the value accepted during the first bit time is not a 0, the receive circuits are reset and the unit continues looking
for another 1-to-0 transition. If the start bit is valid, it is shifted into the input shift register, and reception of the
rest of the frame proceeds.
As data bits come in from the right, 1s shift out to the left. When the start bit arrives at the leftmost position
in the shift register,(which is a 9-bit register in Mode-2 and 3), it flags the RX Control block to do one last shift,
load SBUF and RB8, and set RI. The signal to load SBUF and RB8 and to set RI is generated if, and only if, the
following conditions are met at the time the final shift pulse is generated.:
1) RI=0 and
2) Either SM2=0, or the received 9th data bit = 1
If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met,
the stop bit goes into RB8, the first 8 data bits go into SBUF, and RI is activated. At this time, whether or not the
above conditions are met, the unit continues looking for a 1-to-0 transition at the RXD input.
Note that the value of received stop bit is irrelevant to SBUF, RB8 or RI.

INTERNAL BUS
TB8
WRITE
TO
SBUF DS Q SBUF TXD
CL
ZERO DETECTOR
SYSclk/2
STOP BIT SHIFT DATA
START GEN.
MODE 2 TX CONTROL
16 TX CLOCK TI SEND
SMOD=1 SERIAL
PORT
2 INTERRUPT
d .
SMOD=0
16
mit e
(SMOD IS PCON.7) SAMPLE
RX RI
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1-TO-0 LOAD
CLOCK SBUF
TRANSITION START
DETECTOR RX CONTROL SHIFT
1FFH
C U BIT
DETECTOR
M
INPUT SHIFT REG.
RXD (9 BITS)
C
SHIFT
T
LOAD
S
SBUF
SBUF
READ
SBUF
INTERNAL BUS
TX
CLOCK
WRITE TO SBUF
SEND
DATA TRANSMIT
SHIFT
TXD D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT
TI START BIT
STOP BIT GEN
RX CLOCK
RXD D1 D2 D3 D4 D5 D6 RB8
START BIT D0 D7 STOP BIT
RECEIVE
BIT DETECTOR SAMPLE TIMES
SHIFT
RI
Serial Port Mode 2

8.2.4 Mode 3: 9-Bit UART with Variable Baud Rate

Mode 3 is the same as mode 2 except the baud rate is variable.
Baud rate in mode 3 = (2SMOD /32 ) x Timer 1 overflow rate
When T1x12=0, Timer 1 overflow rate = SYSclk/12/(256-TH1);
When T1x12=1, Timer 1 overflow rate = SYSclk / (256-TH1);
In all four modes, transmission is initiated by any instruction that use SBUF as a destination register. Reception
is initiated in mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the
incoming start bit with 1-to-0 transition if REN=1.
t ed .
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S T C

INTERNAL BUS
TB8
TIMER 1 WRITE
OVERFLOW TO
DS Q SBUF
SBUF TXD
CL
2 ZERO DETECTOR
SMOD SMOD
=0 =1
START SHIFT DATA
TX CONTROL
16 TX CLOCK TI SEND
SERIAL
PORT
.
INTERRUPT
d
16
mit e
SAMPLE
RX CLOCK RI
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1-TO-0 LOAD
TRANSITION START SBUF
DETECTOR RX CONTROL SHIFT
1FFH
C U BIT
DETECTOR
M
INPUT SHIFT REG.
RXD (9 BITS)
C
SHIFT
T
LOAD
S
SBUF
SBUF
READ
SBUF
INTERNAL BUS
TX
CLOCK
WRITE TO SBUF
SEND
DATA TRANSMIT
SHIFT
TXD D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT
TI START BIT
STOP BIT GEN

RX CLOCK 16 RESET
RXD D1 D2 D3 D4 D5 D6 RB8
START BIT D0 D7 STOP BIT
RECEIVE
BIT DETECTOR SAMPLE TIMES
SHIFT
RI
Serial Port Mode 3
8.3 Frame Error Detection

When used for frame error detect, the UART looks for missing stop bits in the communication. A missing bit will
set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is
determined by PCON.6(SMOD0). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0
when SMOD0 is cleared.When used as FE,SCON.7 can only be cleared by software.Refer to the following figure.
9-bit data
D0 D1 D2 D3 D4 D5 D6 D7 D8 STOP BIT
START BIT
SET FE bit if STOP=0
SM0 to UART mode control
PCON.SMOD0
d .
SCON SM0/FE SM1 SM2 REN TB8 RB8 TI RI
UART Frame Error Detection
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8.4 Multiprocessor Communications
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Modes 2 and 3 have a special provision for multiproceasor communications. In these modes 9 data bits are
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received.The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop
bit is received,the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit
C
SM2 in SCON. A way to use this feature in multiprocessor systems is as follows.
S T
When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address
byte which identifies the target slave.An address byte differs from a data byte in that the 9th bit is 1 in an address
byte and 0 in a data byte.With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however,will
interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed.The addressed
slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that werent be-
ing addressed leave their SM2s set and go on about their business, ignoring the coming data bytes.
SM2 has no effect in Mode 0,and in Mode 1 can be used to check the validity of the stop bit. In a Mode 1 recep-
tion, if SM2 = 1, the receive interrupt will not be activated unless a vatid stop bit is received.

8.5 Automatic Address Recognition

Automatic Address Recognition is a future which allows the UART to recognize certain addresses in the serial
bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by
eliminating the need for the software to examine every serial address which passes by the serial port. This feature
is enabled by setting the SM2 bit in SCON. In the 9-bit UART modes, Mode 2 and Mode 3, the Receive interrupt
flag(RI) will be automatically set when the received byte contains either the Given address or the Broadcast
address. The 9-bit mode requires that the 9th information bit is a 1 to indicate that the received information is an
address and not data.
The 8-bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information
received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast
address.
Mode 0 is the Shift Register mode and SM2 is ignored.
d .
Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more
e
mit
slaves by invoking the given slave address or addresses. All of the slaves may be contacted by using the broadcast
address. Two special function registers are used to define the slaves address, SADDR, and the address mask,
Li
SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are dont care. The
SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will
U
use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized which
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excluding others. The following examples will help to show the versatility of this scheme :
Slave 0 SADDR = 1100 0000

SADEN = 1111 1101
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T C
GIVEN = 1100 00x0
Slave 1
SSADDR = 1100 0000
SADEN = 1111 1110
GIVEN = 1100 000x
In the previous example SADDR is the same and the SADEN data is used to differentiate between the two slaves.
Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique
address for slave 0 would be 11000010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would
be 11000001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address
which has bit 0=0 (for slave 0) and bit 1 =0 (for salve 1). Thus, both could be addressed with 11000000.
In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:
SADEN = 1111 1001
GIVEN = 1100 0xx0

SADEN = 1111 1010
GIVEN = 1110 0x0x

SADEN = 1111 1100
GIVEN = 1110 00xx

In the above example the differentiation among the 3 slaves is in the lower 3 address bits.Slave 0 requires that
bit0 = 0 and it can be uniquely addressed by 11100110. Slave 1 requires that bit 1=0 and it can be uniquely
addressed by 11100101. Slave 2 requires that bit 2=0 and its unique address is 11100011. To select Salve 0 and 1
and exclude Slave 2, use address 11100100, since it is necessary to make bit2=1 to exclude Slave 2.
The Broadcast Address for each slave is created by taking the logic OR of SADDR and SADEN. Zeros in this
result are trended as dont cares. In most cares, interpreting the dont cares as ones, the broadcast address will be
FF hexadecimal.
Upon reset SADDR and SADEN are loaded with 0s. This produces a given address of all dont cares as well
as a Broadcast address of all dont cares. This effectively disables the Automatic Addressing mode and allows
the microcontroller to use standard 80C51-type UART drivers which do not make use of this feature.
.
Example: write an program that continually transmits characters from a transmit buffer. If incoming characters
t ed
are detected on the serial port, store them in the receive buffer starting at internal RAM location 50H. Assume that
i
the STC12C5620AD series MCU serial port has already been initialized in mode 1.
Li m
Solution:
ORG 0030H
MOV R0, #30H ;pointer for tx buffer
C U
MOV R1, #50H ;pointer for rx buffer
LOOP: JB RI, RECEIVE ;character received?
M
;yes: process it
JB TI, TX ;previous character transmitted ?
T C
;yes: process it
S
SJMP LOOP ;no: continue checking
TX: MOV A, @R0 ;get character from tx buffer
MOV C, P ;put parity bit in C
CPL C ;change to odd parity
MOV ACC.7, C ;add to character code
CLR TI ;clear transmit flag
MOV SBUF, A ;send character
CLR ACC.7 ;strip off parity bit
INC R0 ;point to next character in buffer
CJNE R0, #50H, LOOP ;end of buffer?
;no: continue
MOV R0, #30H ;yes: recycle
SJMP LOOP ;continue checking
RX: CLR RI ;clear receive flag
MOV A, SBUF ;read character into A
MOV C, P ;for odd parity in A, P should be set
CPL C ;complementing correctly indicates "error"
CLR ACC.7 ;strip off parity
MOV @R1, A ;store received character in buffer
INC R1 ;point to next location in buffer
SJMP LOOP ;continue checking
END


8.6 Buad Rates

The baud rate in Mode 0 is fixed:
SYSclk
Mode 0 Baud Rate = when AUXR.5/UART_M0x6 =0
12
SYSclk
or = when AUXR.5/UART_M0x6 =1
2
The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON. If SMOD =0
(which is the value on reset), the baud rate 1/64 the System clock cycle. If SMOD = 1, the baud rate is 1/32 the
System clock cycle .
2SMOD
Mode 2 Baud Rate = (SYSclk)

64
d .
In the STC12C5620AD, the baud rates in Modes 1 and 3 are determined by Timer 1 overflow rate.
e
mit
The baud rate in Mode 1 and 3 are fixed:
Mode 1,3 Baud rate = (2SMOD /32 ) x timer 1 overflow rate
Timer 1 overflow rate = (SYSclk/12)/(256 - TH1);

Li
C U
M
When Timer 1 is used as the baud rate generator, the Timer 1 interrupt should be disabled in this application.
The Timer itself can be configured for either timer or cormter operation, and in any of its 3 running modes.
C
In the most typcial applications, it is configured for timer operation, in the auto-reload mode (high nibble of
T
TMOD = 0010B).
S
One can achieve very low baud rate with Timer 1 by leaving the Timer 1 interrupt enabled, and configuring the
Timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1 interrupt to do a l6-bit
software reload.
The following figure lists various commonly used baud rates and how they can be obtained from Timer 1.
Timer 1
Baud Rate fOSC SMOD Reload
C/T Mode
Value
Mode 0 MAX:1MHZ 12MHZ X X X X
Mode 2 MAX:375K 12MHZ 1 X X X
Mode 1,3:62.5K 12MHZ 1 0 2 FFH
19.2K 11.059MHZ 1 0 2 FDH
9.6K 11.059MHZ 0 0 2 FDH
4.8K 11.059MHZ 0 0 2 FAH
2.4K 11.059MHZ 0 0 2 F4H
1.2K 11.059MHZ 0 0 2 E8H
137.5 11.986MHZ 0 0 2 1DH
110 6MHZ 0 0 2 72H
110 12MHZ 0 0 1 FEEBH
Timer 1 Generated Commonly Used Baud Rates

8.7 Demo Programs about UART (C and ASM)

1. C program:
/*-------------------------------------------------------------------------------*/
/* --- STC12C5Axx Series MCU UART (8-bit/9-bit)Demo ----------*/
/* --- Mobile: (86)13922809991 ------------------------------------------*/
/* --- Fax: 86-755-82905966 ----------------------------------------------*/
/* --- Tel: 86-755-82948412 -----------------------------------------------*/
.
/*-------------------------------------------------------------------------------*/
#include "reg51.h"
i t ed
m
Li
CU
#define FOSC 18432000L //System frequency
M
#define BAUD 9600 //UART baudrate
C
/*Define UART parity mode*/
T
#define NONE_PARITY 0 //None parity
#define ODD_PARITY 1
#define EVEN_PARITY 2
#define MARK_PARITY 3
S
#define SPACE_PARITY 4

//Odd parity
//Even parity
//Mark parity
//Space parity
#define PARITYBIT EVEN_PARITY //Testing even parity
sbit bit9 = P2^2; //P2.2 show UART data bit9

bit busy;
void SendData(BYTE dat);

void SendString(char *s);
void main()
{
#if (PARITYBIT == NONE_PARITY)
SCON = 0x50; //8-bit variable UART
#elif (PARITYBIT == ODD_PARITY) || (PARITYBIT == EVEN_PARITY) || (PARITYBIT == MARK_PARITY)
SCON = 0xda; //9-bit variable UART, parity bit initial to 1
#elif (PARITYBIT == SPACE_PARITY)
SCON = 0xd2; //9-bit variable UART, parity bit initial to 0
#endif

TMOD = 0x20; //Set Timer1 as 8-bit auto reload mode

TH1 = TL1 = -(FOSC/12/32/BAUD); //Set auto-reload vaule
TR1 = 1; //Timer1 start run
ES = 1; //Enable UART interrupt
EA = 1; //Open master interrupt switch
SendString("STC12C5620AD\r\nUart Test !\r\n");

while(1);
}
/*----------------------------
UART interrupt service routine
.
----------------------------*/
ed
void Uart_Isr() interrupt 4 using 1
mit
{
Li
if (RI)
{
RI = 0; //Clear receive interrupt flag
C U
P0 = SBUF; //P0 show UART data
M
bit9 = RB8; //P2.2 show parity bit
}
if (TI)

} S T C TI = 0;
busy = 0;

//Clear transmit interrupt flag
//Clear transmit busy flag
}
/*----------------------------
Send a byte data to UART
Input: dat (data to be sent)
Output:None
----------------------------*/
void SendData(BYTE dat)
{
while (busy); //Wait for the completion of the previous data is sent
ACC = dat; //Calculate the even parity bit P (PSW.0)
if (P) //Set the parity bit according to P
{
#if (PARITYBIT == ODD_PARITY)
TB8 = 0; //Set parity bit to 0
#elif (PARITYBIT == EVEN_PARITY)
#endif
}

else
{
#endif
}
busy = 1;
SBUF = ACC; //Send data to UART buffer
}
/*----------------------------
d .
Send a string to UART
i t e
Input: s (address of string)
m
Output:None
Li
----------------------------*/
void SendString(char *s)
CU
{
while (*s) //Check the end of the string
M
{
SendData(*s++); //Send current char and increment string ptr
T C
}
S
}

2. Assembly program:
/*-------------------------------------------------------------------------------*/
/* --- STC12C5Axx Series MCU UART (8-bit/9-bit)Demo ----------*/
/* --- Mobile: (86)13922809991 ------------------------------------------*/
/* --- Fax: 86-755-82905966 ----------------------------------------------*/
/* --- Tel: 86-755-82948412 -----------------------------------------------*/
/*-------------------------------------------------------------------------------*/
.
;/*Define UART parity mode*/
ed
#define NONE_PARITY 0 //None parity
mit
#define ODD_PARITY 1 //Odd parity
Li
#define EVEN_PARITY 2 //Even parity
#define MARK_PARITY 3 //Mark parity
#define SPACE_PARITY 4 //Space parity
#define PARITYBIT
M
EVEN_PARITY
;----------------------------------------- CU //Testing even parity
C
BUSY BIT 20H.0 ;transmit busy flag
T
;-----------------------------------------
S
ORG 0000H
LJMP MAIN
ORG 0023H
LJMP UART_ISR
;-----------------------------------------
ORG 0100H
MAIN:
CLR BUSY
CLR EA
MOV SP, #3FH
#if (PARITYBIT == NONE_PARITY)
MOV SCON, #50H ;8-bit variable UART
#elif (PARITYBIT == ODD_PARITY) || (PARITYBIT == EVEN_PARITY) || (PARITYBIT == MARK_PARITY)
MOV SCON, #0DAH ;9-bit variable UART, parity bit initial to 1
#elif (PARITYBIT == SPACE_PARITY)
MOV SCON, #0D2H ;9-bit variable UART, parity bit initial to 0
#endif
;-------------------------------

MOV TMOD, #20H ;Set Timer1 as 8-bit auto reload mode
MOV A, #0FBH ;256-18432000/12/32/9600
MOV TH1, A ;Set auto-reload vaule
MOV TL1, A
SETB TR1 ;Timer1 start run
SETB ES ;Enable UART interrupt
SETB EA ;Open master interrupt switch
;-------------------------------
MOV DPTR, #TESTSTR ;Load string address to DPTR
LCALL SENDSTRING ;Send string
;-------------------------------
SJMP $
.
;-----------------------------------------
t ed
TESTSTR: ;Test string
i
DB "STC12C5620AD Uart Test !", 0DH,0AH,0
;/*----------------------------
;UART2 interrupt service routine
Li m
U
;----------------------------*/
C
UART_ISR:
M
PUSH ACC
PUSH PSW

JNB RI,
CLR RI
S
MOV P0,
MOV C,
T C CHECKTI
SBUF
RB8

;Check RI bit
;Clear RI bit
;P0 show UART data
MOV P2.2, C ;P2.2 show parity bit

CHECKTI:
JNB TI, ISR_EXIT ;Check S2TI bit
CLR TI ;Clear S2TI bit
CLR BUSY ;Clear transmit busy flag
ISR_EXIT:
POP PSW
POP ACC
RETI
;/*----------------------------
;Send a byte data to UART
;Input: ACC (data to be sent)
;Output:None
;----------------------------*/
SENDDATA:
JB BUSY, $ ;Wait for the completion of the previous data is sent
MOV ACC, A ;Calculate the even parity bit P (PSW.0)
JNB P, EVEN1INACC ;Set the parity bit according to P

ODD1INACC:
CLR TB8 ;Set parity bit to 0
SETB TB8 ;Set parity bit to 1
#endif
SJMP PARITYBITOK
EVEN1INACC:
SETB TB8 ;Set parity bit to 1
CLR TB8 ;Set parity bit to 0
d .
#endif
mit e
PARITYBITOK: ;Parity bit set completed
SETB BUSY
Li
MOV SBUF, A ;Send data to UART buffer
RET
;/*----------------------------
C U
M
;Send a string to UART
;Input: DPTR (address of string)
C
;Output:None
S T
;----------------------------*/
SENDSTRING:
CLR A
MOVC A, @A+DPTR ;Get current char
JZ STRINGEND ;Check the end of the string
INC DPTR ;increment string ptr
LCALL SENDDATA ;Send current char
SJMP SENDSTRING ;Check next
STRINGEND:
RET
;-----------------------------------------
END

Chapter 9. Analog to Digital Converter

9.1 A/D Converter Structure
STC12C5620AD series MCU with A/D conversion function have 8-channel and 10-bit high-speed A/D converter
whose speed is up to 100KHz (100 thousand times per second). the 8-channel ADC, which are on P1 port
(P1.0-P1.7) , can be used as temperature detection, battery voltage detection, key scan, spectrum detection, etc.
After power on reset, P1 ports are in weak pull-up mode. Users can set any one of 8 channels as A/D conversion
through software. And those I/O ports not as ADC function can continue to be used as I/O ports.
STC12C5620AD series MCU ADC (A/D converter) structure is shown below.
.
ADC_CONTR Register
t ed
ADC_POWER SPEED1 SPEED0 ADC_FLAG ADC_START CHS2 CHS1 CHS0
m i
Analog input Signal channel
Select switch CHS2/CHS1/CHS0
Li ADC result Register :
U
ADC_ DATA and ADC_LOW2
C
ADC7/P1.7
M
ADC6/P1.6
ADC5/P1.5
ADC4/P1.4
ADC3/P1.3
ADC2/P1.2 S T C +
-
Successive
Approximation
Register
ADC1/P1.1 Comparator
ADC0/P1.0
10-bit DAC
ADC_DATA[7:0]
ADC_B9 ADC_B8 ADC_B7 ADC_B6 ADC_B5 ADC_B4 ADC_B3 ADC_B2
- - - - - - ADC_B1 ADC_B0 ADC_LOW2[1:0]
The ADC on STC12C5620AD is an 8-bit resolution, successive-approximation approach, medium-speed A/D

converter. VREFP/VREFM is the positive/negative reference voltage input for internal voltage-scaling DAC use, the
typical sink current on it is 600uA ~ 1mA. For STC12C5620AD, these two references are internally tied to VCC
and GND separately.

Conversion is invoked since ADC_STRAT(ADC_CONTR.3) bit is set. Before invoking conversion,
ADC_POWER/ADC_CONTR.7 bit should be set first in order to turn on the power of analog front-end in
ADC circuitry. Prior to ADC conversion, the desired I/O ports for analog inputs should be configured as input-
only or open-drain mode first. The converter takes around a fourth cycles to sample analog input data and other
three fourths cycles in successive-approximation steps. Total conversion time is controlled by two register bits
SPEED1 and SPEED0. Eight analog channels are available on P1 and only one of them is connected to to the
comparator depending on the selection bits {CHS2,CHS1,CHS0}. When conversion is completed, the result will
be saved onto ADC_DATA and ADC_LOW2 registerS. After the result are completed and saved, ADC_FLAG is
also set. ADC_FLAG should be cleared in software. The ADC interrupt service routine vectors to 2Bh . When the
chip enters idle mode or power-down mode, the power of ADC is gated off by hardware.
If user need 10-bit conversion result, calculating the result according to the following formula:
ed . Vin
mit
10-bit A/D Conversion Result:(ADC_DATA[7:0], ADC_LOW2[1:0]) = 1024 x Vcc
Li
C U Vin
M
8-bit A/D Conversion Result:(ADC_DATA[7:0]) = 256 x
Vcc
C
In the above formula, Vin stand for analog input channel voltage, Vcc stand for actual operation voltage
S T

9.2 Registers for ADC

bit address and Symbol
Mnemonic Description Address Reset value
MSB LSB
P1M0 P1 Configuration 0 91H 0000 0000B
P1M1 P1 Configuration 1 92H 0000 0000B
ADC_CONTR ADC Control Register C5H ADC_POWER SPEED1 SPEED0 ADC_FLAG ADC_START CHS2 CHS1 CHS0 0000 0000B
ADC_DATA ADC Result high C6H 0000 0000B
ADC_LOW2 ADC Result low BEH
Interrupt Priority
IP B8H - PPCA_LVD PADC_SPI PS PT1 PX1 PT0 PX0 x000 0000B
Low
d .
Interrupt Priority
e
IPH B7H x000 0000B
t
- PPCA_LVDH PADC_SPIH PSH PT1H PX1H PT0H PX0H
i
High
m
AUXR Auxiliary register A2H 0000 00xxB
Li
T0x12 T1x12 UART_M0x12 EADCI ESPI ELVDI - -
1. P1 Analog Function Configure register: P1M0 and P1M1
C U
Those P1 ports which need to be used as A/D converter should be first set in open-drain or high-impedance
M
(input-only) mode through registers P1M0 and P1M1.
C
address90H)
0 S T
P1M0[7 : 0] P1M1 [7 : 0]
0
I/O ports Mode
Sink Current up to 20mA , pull-up Current is 230A ,
0 1
input-only (high-impedance ).
1 0 If any P1 port need to be used as ADC, its mode is optional between input-
only (high-impedance ) and open-drain mode.
1 1
If any P1 port need to be used as ADC, its mode is optional between input-
only (high-impedance ) and open-drain mode.

MOV P1M1, #11000000B
/weak pull-up

2. ADC control register: ADC_CONTR (Non bit-addressable)
ADC_CONTR C5H name ADC_POWER SPEED1 SPEED0 ADC_FLAG ADC_START CHS2 CHS1 CHS0
When operating to ADC_CONTR register, "MOV" should be used, while "AND" and "OR" don not be
recommended to use
ADC_POWER : When clear shut down the power of ADC block. When set turn on the power of ADC block.
SPEED1, SPEED0 : Conversion speed selection.
SPEED1 SPEED0 Times needed by an A/D Coversion
0 0 1080 clock cycles are needed for a conversion.
ed .
270 clock cycles are needed for a conversion. When the CPU operation
mit
1 1
frequency is 27MHz, the speed of ADC is about 100KHz.
Li
The clock source used by ADC block of STC12C5620AD series MCU is On-chip R/C clock which is not divided
by Clock divider register CLK_DIV.
U
ADC_FLAG : ADC interrupt flag.It will be set by the device after the device has finished a conversion, and
C
should be cleared by the user's software.

M
ADC_STRAT : ADC start bit, which enable ADC conversion.It will automatically cleared by the device after the
device has finished the conversion.
0 0 S0T C
CHS2 ~ CHS0 : Used to select one analog input source from 8 channels.
CHS2 CHS1 CHS0 Source
P1.0 (default) as the A/D channel input
0 0 1 P1.1 as the A/D channel input
Note : The corresponding bits in P1ASF should be configured correctly before starting A/D conversion. The
sepecific P1ASF bits should be set corresponding with the desired channels.
Because it will by delayed 4 CPU clocks after the instruction which set ADC_CONTR register has been executed,
Four "NOP" instructions should be added after setting ADC_CONTR register. See the following code:
MOV ADC_CONTR, #DATA
NOP
NOP
NOP
NOP
MOV A, ADC_CONTR
;Only delayed 4 clocks, can the ADC_CONTR be read correctly.

3. ADC result register: ADC_DATA and ADC_LOW2

ADC_DATA and ADC_LOW2 are used to save the ADC result, their format as shown below:
Mnemonic Add Name B7 B6 B5 B4 B3 B2 B1 B0
ADC result
ADC_DATA C6h
register high
ADC result
ADC_LOW2 BEh x x x x x x
register low
Vin
10-bit A/D Conversion Result:(ADC_DATA[7:0], ADC_LOW2[1:0]) = 1024 x Vcc
t ed .
i
Li
8-bit A/D Conversion Result:(ADC_DATA[7:0]) = 256 xm Vin
Vcc
C U
M
In the above formula, Vin stand for analog input channel voltage, Vcc stand for actual operation voltage
S T C
4. Registers related with UART1 interrupt : IE, AUXR, IP and IPH



IP B8H name - PPCA_LVD PADC_SPI PS PT1 PX1 PT0 PX0
d .
mit e
Li
C U
M
S T C
9.3 Application Circuit of A/D Converter
P2.2 1 28 Vcc
P2.3 2 27 P2.1
RST 3 26 P2.0/PCA2/PWM2
more than 47pF 1K
RxD/P3.0 4 25 P1.7/ADC7 Signal source
SOP-28/SKDIP-28
TxD/P3.1 5 24 P1.6/ADC6
INT0/P3.2 8 21 P1.3/ADC3
INT1/P3.3 9 20 P1.2/ADC2
PWM1/PCA1/T1/P3.5 11 18 P1.0/ADC0/CLKOUT0
P2.5 13 16 P2.7
Gnd 14 15 P2.6
ADC function in P1 port, P1.0 - P1.7 in all 8 channels

9.4 ADC Application Circuit for Key Scan
P2.2 1 28 Vcc Vcc

P2.3 2 27 P2.1
RST 3 26 P2.0/PCA2/PWM2 10K
more than 47pF 1K
RxD/P3.0 4 25 P1.7/ADC7 0V
SOP-28/SKDIP-28
TxD/P3.1 5 24 P1.6/ADC6 10K
XTAL2 6 23 P1.5/ADC5 1/2 Vcc
XTAL1 7 22 P1.4/ADC4 10K
INT0/P3.2 8 21 P1.3/ADC3 2/3 Vcc
INT1/P3.3 9 20 P1.2/ADC2 10K
ECI/T0/P3.4 10 19 P1.1/ADC1/CLKOUT1 3/4 Vcc
PWM1/PCA1/T1/P3.5 11 18 P1.0/ADC0/CLKOUT0 10K
.
PWM3/PCA3/P2.4 12 17 P3.7/PCA0/PWM0 4/5 Vcc
ed
P2.5 13 16 P2.7
i t
Gnd 14 15 P2.6
Li m
ADC function in P1 port, P1.0 - P1.7 in all 8 channels
M CU
P2.2 1 28 Vcc +5V
P2.3 2 27 P2.1
R1
RST 3 26 P2.0/PCA2/PWM2 10K
C
ADCx
T
RxD/P3.0 4 25 P1.7/ADC7
SOP-28/SKDIP-28
S
TxD/P3.1 5 24 P1.6/ADC6 47pF R2 R3 R4 R5 R6
XTAL2 6 23 P1.5/ADC5 520 1.8K 3.3K 5.4K 8.2K
INT0/P3.2 8 21 P1.3/ADC3 sw1 sw2 sw3 sw4 sw5 sw6
INT1/P3.3 9 20 P1.2/ADC2
0 0`0.5 0.5`1 1`1.5 1.5`2.0 2.0`2.5
PWM1/PCA1/T1/P3.5 11 18 P1.0/ADC0/CLKOUT0
This curcuit can realize the single key scan
P2.5 13 16 P2.7
and assembling key scan detection function,
Gnd 14 15 P2.6
but the value of resistors should be adjusted
according to the actual demand.
+5V
10 keys are used to divide the voltage in the below curcuit, what the error of each
key float between -0.25V and +0.25V can effectively avoid that resistance error or
R0
ADCx 10K
temprature difit lead to disable key detection.
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10
47pF 520 1.2K 1.6K 1.8K 3K 4K 6.5 10K 30K 100K
sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw8 sw9 sw10 sw11

9.5 A/D reference voltage source

STC12C5620AD series ADC reference voltage is from MCU power supply voltage directly, so it can work
without an external reference voltage source. If the required precision is relatively high, then you maybe using
a stable reference voltage source, in order to calculate the operating voltage VCC, then calculate the ADC exact
value. For example, you can connect a 1.25V(or 1.00V, ect. ) to ADC channel 7, according to the conversion
result, you can get the actual VCC voltage, thus you can calculate other 7 channels ADC results. (Vcc is constant
in short time)
ed .
Li mit
C U
M
S T C

9.6 Program using interrupts to demostrate A/D Conversion

There are two example procedures using interrupts to demostrate A/D conversion, one written in C langugage and
the other in assembly language.
1. C language code listing:

/*---------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ------------------------------------*/
/* --- STC 1T Series MCU A/D Conversion Demo ----------------------*/
/* --- Mobile: (86)13922809991 --------------------------------------------*/
/* --- Fax: 86-755-82905966 ------------------------------------------------*/
/* --- Tel: 86-755-82948412 -------------------------------------------------*/
.
ed
i t
/*---------------------------------------------------------------------------------*/
Li m

#include "reg51.h"
C U
M
#define BAUD 9600

typedef unsigned int
sfr AUXR S T C WORD;
/*Declare SFR associated with the ADC */

= 0x8e;
sfr ADC_CONTR = 0xC5; //ADC control register
sfr ADC_DATA = 0xC6; //ADC high 8-bit result register
sfr ADC_LOW2 = 0xBE; //ADC low 2-bit result register
sfr P1M0 = 0x91; //P1 mode control register0
/*Define ADC operation const for ADC_CONTR*/

#define ADC_POWER 0x80 //ADC power control bit
#define ADC_FLAG 0x10 //ADC complete flag
#define ADC_START 0x08 //ADC start control bit
#define ADC_SPEEDLL 0x00 //1080 clocks
#define ADC_SPEEDL 0x20 //810 clocks
#define ADC_SPEEDH 0x40 //540 clocks
#define ADC_SPEEDHH 0x60 //270 clocks
void InitUart();
void Delay(WORD n);
void InitADC();

BYTE ch = 0; //ADC channel NO.
void main()
{
InitUart(); //Init UART, use to show ADC result
InitADC(); //Init ADC sfr
AUXR |= 0x10; //set EADCI
IE = 0xa0; //Enable ADC interrupt and Open master interrupt switch
//Start A/D conversion
while (1);
}
.
/*----------------------------
ed
mit
ADC interrupt service routine
----------------------------*/
Li
void adc_isr() interrupt 5 using 1
{
CU
ADC_CONTR &= !ADC_FLAG; //Clear ADC interrupt flag
M
SendData(ch); //Show Channel NO.
SendData(ADC_DATA); //Get ADC high 8-bit result and Send to UART
S T C
//if you want show 10-bit result, uncomment next line
// SendData(ADC_LOW2); //Show ADC low 2-bit result
if (++ch > 7) ch = 0; //switch to next channel

ADC_CONTR = ADC_POWER | ADC_SPEEDLL | ADC_START | ch;
}
/*----------------------------
Initial ADC sfr
----------------------------*/
void InitADC()
{
P1 = P1M0 = P1M1 = 0xff; //Set all P1 as Open-Drain mode
ADC_DATA = 0; //Clear previous result
ADC_CONTR = ADC_POWER | ADC_SPEEDLL | ADC_START | ch;
Delay(2); //ADC power-on delay and Start A/D conversion
}
/*----------------------------
Initial UART
----------------------------*/

void InitUart()
{
SCON = 0x5a; //8 bit data ,no parity bit
TMOD = 0x20; //T1 as 8-bit auto reload
TH1 = TL1 = -(FOSC/12/32/BAUD); //Set Uart baudrate
TR1 = 1; //T1 start running
}
/*----------------------------
Send one byte data to PC
Input: dat (UART data)
Output:-
----------------------------*/
.
d
{
i t e
while (!TI); //Wait for the previous data is sent
m
TI = 0; //Clear TI flag
Li
SBUF = dat; //Send current data
}
/*----------------------------
C U
M
Software delay function
----------------------------*/
C
void Delay(WORD n)
T
{
S
WORD x;
while (n--)
{
x = 5000;
while (x--);
}
}

2. Assembly language code listing:
;/*----------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited -------------------------------------*/
;/* --- STC 1T Series MCU A/D Conversion Demo -----------------------*/
;/* --- Mobile: (86)13922809991 ---------------------------------------------*/
;/* --- Fax: 86-755-82905966 -------------------------------------------------*/
;/* --- Tel: 86-755-82948412 --------------------------------------------------*/
;/* --- Web: www.STCMCU.com ---------------------------------------------*/
;/*-----------------------------------------------------------------------------------*/
;/*Declare SFR associated with the ADC */
.
AUXR EQU 8EH
ed
ADC_CONTR EQU 0C5H ;ADC control register
mit
ADC_DATA EQU 0C6H ;ADC high 8-bit result register
Li
ADC_LOW2 EQU 0BEH ;ADC low 2-bit result register
P1M0 EQU 091H ;P1 mode control register0
;/*Define ADC operation const for ADC_CONTR*/
C U
M
ADC_POWER EQU 80H ;ADC power control bit
ADC_FLAG EQU 10H ;ADC complete flag
C
ADC_START EQU 08H ;ADC start control bit
S T
ADC_SPEEDLL EQU 00H ;1080 clocks
ADC_SPEEDL EQU 20H ;810 clocks
ADC_SPEEDH EQU 40H ;540 clocks
ADC_SPEEDHH EQU 60H ;270 clocks
ADCCH DATA 20H ;ADC channel NO.
;-----------------------------------------
ORG 0000H
LJMP MAIN
ORG 002BH
LJMP ADC_ISR
;-----------------------------------------
ORG 0100H
MAIN:
MOV SP, #3FH
MOV ADCCH, #0
LCALL INIT_UART ;Init UART, use to show ADC result
LCALL INIT_ADC ;Init ADC sfr
ORL AUXR, #10H ;set EADCI
MOV IE, #0A0H ;Enable ADC interrupt and Open master interrupt switch
SJMP $

;/*----------------------------
;ADC interrupt service routine
;----------------------------*/
ADC_ISR:
PUSH ACC
PUSH PSW
ANL ADC_CONTR, #NOT ADC_FLAG ;Clear ADC interrupt flag

MOV A, ADCCH
LCALL SEND_DATA ;Send channel NO.
MOV A, ADC_DATA ;Get ADC high 8-bit result
LCALL SEND_DATA ;Send to UART
;//if you want show 10-bit result, uncomment next 2 lines
t ed .
i
; MOV A, ADC_LOW2 ;Get ADC low 2-bit result
Li m
; LCALL SEND_DATA ;Send to UART
INC ADCCH
C U
MOV A, ADCCH
M
ANL A, #07H
MOV ADCCH, A
C
ORL A, #ADC_POWER | ADC_SPEEDLL | ADC_START
T
MOV ADC_CONTR,A ;ADC power-on delay and re-start A/D conversion

POP
POP
RETI
S
PSW
ACC
;/*----------------------------
;Initial ADC sfr
;----------------------------*/
INIT_ADC:
MOV A, #0FFH
MOV P1, A
MOV P1M0, A
MOV P1M1, A ;Set all P1 as Open-Drain mode
MOV ADC_DATA, #0 ;Clear previous result
MOV A, ADCCH
MOV ADC_CONTR, A ;ADC power-on delay and Start A/D conversion
MOV A,#2
LCALL DELAY
RET

;/*----------------------------
;Initial UART
;----------------------------*/
INIT_UART:
MOV SCON, #5AH ;8 bit data ,no parity bit
MOV TMOD, #20H ;T1 as 8-bit auto reload
MOV A, #-5 ;Set Uart baudrate -(18432000/12/32/9600)
MOV TH1, A ;Set T1 reload value
MOV TL1, A
SETB TR1 ;T1 start running
RET
;/*----------------------------
.
;Send one byte data to PC
ed
;Input: ACC (UART data)
mit
;Output:-
Li
;----------------------------*/
SEND_DATA:
JNB TI, $ ;Wait for the previous data is sent
U
CLR TI ;Clear TI flag
C
MOV SBUF, A ;Send current data
M
RET
C
;/*----------------------------
T
;Software delay function
S
;----------------------------*/
DELAY:
MOV R2, A
CLR A
MOV R0, A
MOV R1, A
DELAY1:
DJNZ R0, DELAY1
DJNZ R1, DELAY1
DJNZ R2, DELAY1
RET
END

9.7 Program using polling to demostrate A/D Conversion

There are two example procedures using inquiry to demostrate A/D conversion, one written in C langugage and
the other in assembly language.
1. C language code listing:

/*--------------------------------------------------------------------------------*/
/* --- STC 1T Series MCU A/D Conversion Demo ---------------------*/
/* --- Mobile: (86)13922809991 ------------------------------------------*/
/* --- Fax: 86-755-82905966 ----------------------------------------------*/
/* --- Tel: 86-755-82948412 -----------------------------------------------*/
.
ed
/*------------------------------------------------------------------------------*/
m i t
Li
#include "reg51.h"
U
#define BAUD 9600

M C
C
sfr
sfr ADC_DATA
S T
/*Declare SFR associated with the ADC */
ADC_CONTR = 0xC5;
= 0xC6;

//ADC control register
//ADC high 8-bit result register
sfr ADC_LOW2 = 0xBE; //ADC low 2-bit result register
/*Define ADC operation const for ADC_CONTR*/

#define ADC_POWER 0x80 //ADC power control bit
#define ADC_FLAG 0x10 //ADC complete flag
#define ADC_START 0x08 //ADC start control bit
#define ADC_SPEEDLL 0x00 //1080 clocks
#define ADC_SPEEDL 0x20 //810 clocks
#define ADC_SPEEDH 0x40 //540 clocks
#define ADC_SPEEDHH 0x60 //270 clocks
void InitUart();
void InitADC();
BYTE GetADCResult(BYTE ch);
void Delay(WORD n);
void ShowResult(BYTE ch);

void main()
{
InitUart(); //Init UART, use to show ADC result
InitADC(); //Init ADC sfr
while (1)
{
ShowResult(0); //Show Channel0
.
ed
mit
}
Li
}
/*----------------------------
U
Send ADC result to UART
C
----------------------------*/
M
void ShowResult(BYTE ch)
{
C
SendData(ch); //Show Channel NO.
S T
SendData(GetADCResult(ch)); //Show ADC high 8-bit result
//if you want show 10-bit result, uncomment next line

// SendData(ADC_LOW2); //Show ADC low 2-bit result
}
/*----------------------------
Get ADC result
----------------------------*/
BYTE GetADCResult(BYTE ch)
{
ADC_CONTR = ADC_POWER | ADC_SPEEDLL | ch | ADC_START;
_nop_(); //Must wait before inquiry
_nop_();
_nop_();
_nop_();
while (!(ADC_CONTR & ADC_FLAG)); //Wait complete flag
ADC_CONTR &= ~ADC_FLAG; //Close ADC
return ADC_DATA; //Return ADC result

}

/*----------------------------
Initial UART
----------------------------*/
void InitUart()
{
SCON = 0x5a; //8 bit data ,no parity bit
TMOD = 0x20; //T1 as 8-bit auto reload
TH1 = TL1 = -(FOSC/12/32/BAUD); //Set Uart baudrate
TR1 = 1; //T1 start running
}
/*----------------------------
Initial ADC sfr
.
----------------------------*/
ed
void InitADC()
{
m i t
Li
P1 = P1M0 = P1M1 = 0xff; //Set all P1 as Open-Drain mode
ADC_DATA = 0; //Clear previous result
ADC_CONTR = ADC_POWER | ADC_SPEEDLL;
Delay(2);
C U
//ADC power-on and delay
M
}
/*----------------------------
T C
Send one byte data to PC
S
Input: dat (UART data)
Output:-
----------------------------*/
{
while (!TI); //Wait for the previous data is sent
SBUF = dat; //Send current data
}
/*----------------------------
----------------------------*/
void Delay(WORD n)
{
WORD x;
while (n--)
{
x = 5000;
while (x--);
}
}
2. Assembly language code listing:

;/*-------------------------------------------------------------------------------*/
;/* --- STC 1T Series MCU A/D Conversion Demo --------------------*/
;/* --- Mobile: (86)13922809991 ------------------------------------------*/
;/* --- Fax: 86-755-82905966 ----------------------------------------------*/
;/* --- Tel: 86-755-82948412 -----------------------------------------------*/
;/*------------------------------------------------------------------------------*/
.
ed
ADC_CONTR EQU 0C5H ;ADC control register
mit
ADC_DATA EQU 0C6H ;ADC high 8-bit result register
Li
ADC_LOW2 EQU 0BEH ;ADC low 2-bit result register
;/*Define ADC operation const for ADC_CONTR*/
C U
M
ADC_POWER EQU 80H ;ADC power control bit
ADC_FLAG EQU 10H ;ADC complete flag
C
ADC_START EQU 08H ;ADC start control bit
S
ADC_SPEEDL EQU 20H
ADC_SPEEDH EQU 40H
T
ADC_SPEEDLL EQU 00H
ADC_SPEEDHH EQU 60H

;1080 clocks
;810 clocks
;540 clocks
;270 clocks
;-----------------------------------------
ORG 0000H
LJMP MAIN
;-----------------------------------------
ORG 0100H
MAIN:
LCALL INIT_UART ;Init UART, use to show ADC result
LCALL INIT_ADC ;Init ADC sfr
;-------------------------------
NEXT:
MOV A, #0
LCALL SHOW_RESULT ;Show channel0 result
MOV A, #1
MOV A, #2

MOV A, #3
MOV A, #4
MOV A, #5
MOV A, #6
MOV A, #7
SJMP NEXT
.
;/*----------------------------
t ed
;Send ADC result to UART
i
;Input: ACC (ADC channel NO.)
Li m
;Output:-
;----------------------------*/
SHOW_RESULT:
LCALL SEND_DATA
C U ;Show Channel NO.
M
LCALL GET_ADC_RESULT ;Get high 8-bit ADC result
LCALL SEND_DATA ;Show result
;
;

MOV A,
S T C
;//if you want show 10-bit result, uncomment next 2 lines
LCALL SEND_DATA
RET
ADC_LOW2

;Get low 2-bit ADC result
;Show result
;/*----------------------------
;Read ADC conversion result
;Input: ACC (ADC channel NO.)
;Output:ACC (ADC result)
;----------------------------*/
GET_ADC_RESULT:
MOV ADC_CONTR, A ;Start A/D conversion
NOP ;Must wait before inquiry
NOP
NOP
NOP
WAIT:
MOV A, ADC_CONTR ;Wait complete flag
JNB ACC.4, WAIT ;ADC_FLAG(ADC_CONTR.4)
ANL ADC_CONTR ,#NOT ADC_FLAG ;Clear ADC_FLAG
MOV A, ADC_DATA ;Return ADC result
RET

;/*----------------------------
;Initial ADC sfr
;----------------------------*/
INIT_ADC:
MOV A, #0FFH
MOV P1, A
MOV P1M0, A
MOV P1M1, A ;Set all P1 as Open-Drain mode
MOV ADC_DATA,#0 ;Clear previous result
MOV ADC_CONTR, #ADC_POWER | ADC_SPEEDLL
MOV A, #2 ;ADC power-on and delay
LCALL DELAY
RET
;/*----------------------------
.
;Initial UART
ed
mit
;----------------------------*/
INIT_UART:
Li
MOV SCON, #5AH ;8 bit data ,no parity bit
MOV TMOD, #20H ;T1 as 8-bit auto reload
MOV A, #-5 ;Set Uart baudrate -(18432000/12/32/9600)
U
MOV TH1, A ;Set T1 reload value
C
MOV TL1, A
M
SETB TR1 ;T1 start running
RET
T C
;/*----------------------------
S
;Send one byte data to PC
;Input: ACC (UART data)
;Output:-
;----------------------------*/
SEND_DATA:
JNB TI,$ ;Wait for the previous data is sent
CLR TI ;Clear TI flag
MOV SBUF, A ;Send current data
RET
;/*----------------------------
;----------------------------*/
DELAY:
MOV R2, A
CLR A
MOV R0, A
MOV R1, A
DELAY1:
DJNZ R0, DELAY1
DJNZ R1, DELAY1
DJNZ R2, DELAY1
RET
END
Chapter 10. Programmable Counter Array(PCA)

The Programmable Counter Array is a special 16-bit Timer that has four 16-bit capture/compare modules
associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling
edge capture (calculator of duty length for high/low pulse), software timer, high-speed output, or pulse width
modulator. Module 0 is connected to pin P3.7, module 1 to pin P3.5, module 2 to pin P2.0, module 3 to pin P2.4
in STC12C5620AD series.
The PCA timer is a common time base for all four modules and can be programmed to run at 1/12 the system
clock, 1/2 the system clock, the Timer 0 overflow or the input on ECI pin(P3.4). The timer count source is
determined from CPS1 and CPS0 bits in the CMOD SFR.
10.1 SFRs related with PCA
t ed .
i
PCA/PWM SFRs table
Mnemonic Description Add

B7 B6 B5
Li B4 m
Bit address and Symbol
B3 B2 B1 B0
Reset
Value
CU
CCON PCA Control Register D8H CF CR - - CCF3 CCF2 CCF1 CCF0 00xx,0000
CMOD PCA Mode Register D9H CIDL - - - - CPS1 CPS0 ECF 0xxx,x000
CCAPM0 PCA Module 0 Mode Register DAH
M - ECOM0 CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0 x000,0000
C
CCAPM1 PCA Module 1 Mode Register DBH - ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1 x000,0000
S T
CCAPM2 PCA Module 2 Mode Register DCH - ECOM2 CAPP2 CAPN2 MAT2 TOG2 PWM2 ECCF2 x000,0000
CCAPM3 PCA Module 3 Mode Register DDH - ECOM3 CAPP3 CAPN3 MAT3 TOG3 PWM3 ECCF3 x000,0000
CL PCA Base Timer Low E9H 0000,0000
CH PCA Base Timer High F9H 0000,0000
PCA Module-0 Capture
CCAP0L EAH 0000,0000
Register Low
CCAP0H FAH 0000,0000
Register High
CCAP1L EBH 0000,0000
Register Low
CCAP1H FBH 0000,0000
Register High
CCAP2L ECH 0000,0000
Register Low
CCAP2H FCH 0000,0000
Register High
CCAP3L EDH 0000,0000
Register Low
CCAP3H FDH 0000,0000
Register High

Bit address and Symbol Reset

Mnemonic Description Add
B7 B6 B5 B4 B3 B2 B1 B0 Value
PCA PWM Mode Auxiliary
PCA_PWM0 F2H - - - - - - EPC0H EPC0L xxxx,xx00
Register 0
Register 1
Register 2
Register 3
ed .
mit
1. PCA operation mode register: CMOD (Non bit-addressable)
Li
CMOD D9H name CIDL - - - - CPS1 CPS0 ECF
C
CIDL : PCA Counter control bit in Idle mode.
U
M
If CIDL=0, the PCA counter will continue functioning during idle mode.
If CIDL=1, the PCA counter will be gated off during idle mode.
C
CPS1, CPS0 : PCA Counter Pulse source Select bits.
0
0
1
S T
CPS1 CPS0 Select PCA/PWM clock source
0 0, System clock/12, SYSclk/12
1, System clock/2, SYSclk/2
2, Timer 0 overflow. PCA/PWM clock can up to SYSclk because Timer 0 can operate in
1 0 1T mode. Frequency-adjustable PWM output can be achieved by changing the Timer 0
overflow.
1 1 3, Exrenal clock from ECI/P3.4 pin (max speed = SYSclk/2)
For example, If CPS1/CPS0=0/0, PCA/PWM clock source is SYSclk/12.
If users need to select SYSclk/3 as PCA clock source, Timer 0 should be set to operate in 1T mode and generate
an overflow every 3 counting pulse.
ECF : PCA Counter Overflow interrupt Enable bit.

ECF=0 disables CF bit in CCON to generate an interrupt.
ECF=1 enables CF bit in CCON to generate an interrupt.

2. PCA control register : CCON (Non bit-addressable)

CCON D8H name CF CR - - CCF3 CCF2 CCF1 CCF0
CF : PCA Counter overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF
in CMOD is set. CF may be set by either hardware or software but can only be cleared by software.
CR : PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to
turn the PCA counter off.
CCF3 : PCA Module 3 interrupt flag. Set by hardware when a match or capture from module 3 occurs. Must
be cleared by software. A match means the value of the PCA counter equals the value of the Capture/
Compare register in module 3. A capture means a specific edge from PCA3 happens, so the Capture/
.
Compare register latches the value of the PCA counter, and the CCF3 is set.
t ed
i
Li m
U
C
M
T C
S

3. PCA capture/campare register CCAPM0, CCAPM1, CCAPM2 and CCAPM3

Each module in the PCA has a special function register associated with it. These registers are CCAPMn, n=0
~3. CCAPM0 for module 0, CCAPM1 for module 1, CCAPM2 for module 2 and CCAPM3 for module 3. The
register contains the bits that control the mode in which each module will operate. The ECCFn bit enables the
CCFn flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module.
PWMn enables the pulse width modulation mode. The TOGn bit when set causes the CCPn output associated
with the module to toggle when there is a match between the PCA counter and the modules capture/compare
register. The match bit(MATn) when set will cause the CCFn bit in the CCON register to be set when there is a
match between the PCA counter and the modules capture/compare register.
The next two bits CAPNn and CAPPn determine the edge that a capture input will be active on. The CAPNn bit
enables the negative edge, and the CAPPn bit enables the positive edge. If both bits are set, both edges will be
enabled and a capture will occur for either transition. The bit ECOMn when set enables the comparator function.
ed .
mit
Capture/Compare register of PCA module 0 : CCAPM0 (Non bit-addressable)
Li
CCAPM0 DAH name - ECOM0 CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0
U
ECOM0 : Comparator Enable bit.
C
ECOM0=0 disables the comparator function;
M
ECOM0=1 enables the comparator function.
CAPP0 : Capture Positive control bit.
C
CAPP0=1 enables positive edge capture.
S T
CAPN0 : Capture Negative control bit.
CAPN0=1 enables negative edge capture.
MAT0 : Match control bit.
When MAT0 = 1, a match of the PCA counter with this modules compare/capture register causes the
CCF0 bit in CCON to be set.
TOG0 : Toggle control bit.
When TOG0=1, a match of the PCA counter with this modules compare/capture register causes the
CCP0 pin to toggle.
(PCA0/PWM0/P3.7)
PWM0 : Pulse Width Modulation.
PWM0=1 enables the CCP0 pin to be used as a pulse width modulated output.
(PCA0/PWM0/P3.7)
ECCF0 : Enable CCF0 interrupt.
Enables compare/capture flag CCF0 in the CCON register to generate an interrupt.

CCAPM1 DBH name - ECOM1 CAPP1 CAPN1 MAT1 TOG1 PWM1 ECCF1
d .
i t e
m
When TOG1=1, a match of the PCA counter with this modules compare/capture register causes the
Li
CCP1 pin to toggle.
(PCA1/PWM1/P3.5)
U
C
PWM1=1 enables the CEX1 pin to be used as a pulse width modulated output.
M
(PCA1/PWM1/P3.5)
C
SFR name Address

CCAPM2 DCH S T
bit
name
B7
-
B6 B5
ECOM2 CAPP2 CAPN2
B4 B3
MAT2
B2
TOG2
B1
PWM2 ECCF2
B0

When TOG2=1, a match of the PCA counter =with this modules compare/capture register causes the
CCP2 pin to toggle.
(PCA2/PWM2/P2.0)
(PCA2/PWM2/P2.0)

CCAPM3 DDH name - ECOM3 CAPP3 CAPN3 MAT3 TOG3 PWM3 ECCF3
.
d
mit e
Li
When TOG3=1, a match of the PCA counter =with this modules compare/capture register causes the
CCP3 pin to toggle.
(PCA3/PWM3/P2.4)
U
C
M
(PCA3/PWM3/P2.4)
C
S T
The operation mode of PCA modules set as shown in the below table.
Setting the operation mode of PCA modulesCCAPMn registern = 0,1,2,3

- ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Function of PCA modules
0 0 0 0 0 0 0 No operation
1 0 0 0 0 1 0 8-bit PWM, no interrupt
8-bit PWM output, interrupt can be generated
1 1 0 0 0 1 1
on rising edge.
1 0 1 0 0 1 1
on falling edge.
1 1 1 0 0 1 1
on both rising and falling edges.
16-bit Capture Mode, caputre triggered by the
X 1 0 0 0 0 X
rising edge on CCPn/PCAn pin
16-bit Capture Mode, capture triggered by the
X 0 1 0 0 0 X
falling edge on CCPn/PCAn pin
X 1 1 0 0 0 X
transition on CCPn/PCAn pin
1 0 0 1 0 0 X 16-bit software timer
1 0 0 1 1 0 X 16-bit high-speed output

4. PCA 16-bit Counter low 8-bit CL and high 8-bit CH
The addresses of CL and CH respectively are E9H and F9H, and their reset value both are 00H. CL and CH are
used to save the PCA load value.
5. PCA Capture/Compare register CCAPnL and CCAPnH

When PCA is used to capture/compare, CCAPnL and CCAPnH are used to save the 16-bit capture value in
corresponding block. When PCA is operated in PWM mode, CCAPnL and CCAPnH are used to control the duty
cycle of PWM output signal. "n=0 or 1 or 2 or 3" respectively stand for module 0, 1, 2 and 3. Reset value of
regsiters CCAPnL and CCAPnH are both 00H. Their addresses respectively are:
CCAP0L EAH, CCAP0H FAH : Capture / Compare register of module 0
CCAP1L EBH, CCAP1H FBH : Capture / Compare register of module 1
CCAP2L ECH, CCAP2H FCH : Capture / Compare register of module 2
.
CCAP3L EDH, CCAP3H FDH : Capture / Compare register of module 3
6. PWM registers of PCA modules : PCA_PWM0 and PCA_PWM1
i t ed
Li m
PCA_PWM0 : PWM register of PCA module 0
U
PCA_PWM0 F2H name - - - - - - EPC0H EPC0L
B7 ~ B2 : Reserved
M C
EPC0H : Associated with CCAP0H, it is used in PCA PWM mode.
EPC0L : Associated with CCAP0L, it is used in PCA PWM mode.
S T C
B7 ~ B2 : Reserved

B7 ~ B2 : Reserved

B7 ~ B2 : Reserved

10.2 PCA/PWM Structure

There are 2 channels Programmable Counter Arrary PCA/PWM in STC12C5620AD series MCU.
Module 0 P3.7/CCP0/PCA0/PWM0
16-bit PCA
Timer/Counter
ed .
mit
Programmable Counter Arrary Structure
Li
Each PCA/PWM module can be operated in 4 modes : rising / falling capture mode, software timer, high-speed
output mode and adjustable pulse output mode.
U
STC12C5620AD series: module 0 connect to P3.7/PCA0/PWM0,
C
module 1 connect to P3.5/PCA1/PWM1.
M
S T C
SYSclk/1
SYSclk/2
To PCA Module
SYSclk/4
SYSclk/6
CH CL
SYSclk/8 16-Bit counter PCA Interrput
SYSclk/12
Timer 0 overflow
External input
ECI(P3.4)
IDLE CMOD CIDL - - - - CPS1 CPS0 ECF
CF CR - - CCF3 CCF2 CCF1 CCF0 CCON
PCA Timer/Counter

In the CMOD SFR, there are two additional bits associated with the PCA. They are CIDL which allows the PCA
to stop during idle mode, and ECF which when set causes an interrupt and the PCA overflow flag CF(in the
CCON SFR) to be set when the PCA timer overflows.
The CCON SFR contains the run control bit for PCA and the flags for the PCA timer and each module. To run
the PCA the CR bit(CCON.6) must be set by software; oppositely clearing bit CR will shut off PCA is shut off
PCA. The CF bit(CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF
(CMOD.0) bit in the CMOD register is set. The CF bit can only be cleared by software. There are two bits named
CCF0 and CCF1 in SFR CCON. The CCF0 and CCF1 are the flags for module 0 and module 1 respectively. They
are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software.
Each module in the PCA has a special function register associated with it, CCAPM0 for module-0, CCAPM1
.
for module-1, CCAPM2 for module-2 and CCAPM3 for module-3. The register contains the bits that control
ed
the mode in which each module will operate. The ECCFn bit controls if to pass the interrupt from CCFn flag
i t
in the CCON SFR to the MCU when a match or compare occurs in the associated module. PWMn enables the
Li m
pulse width modulation mode. The TOGn bit when set causes the pin CCPn output associated with the module to
toggle when there is a match between the PCA counter and the modules Capture/Compare register. The match bit
(MATn) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA
U
counter and the modules Capture/Compare register.
M C
The next two bits CAPNn and CAPPn determine the edge type that a capture input will be active on. The CAPNn
bit enables the negative edge, and the CAPPn bit enables the positive edge. If both bits are set, both edges will be
C
enabled and a capture will occur for either transition. The bit ECOMn when set enables the comparator function.
S T

10.3 PCA Modules Operation Mode

The operation mode of PCA modules set as shown in the below table.
Setting the operation mode of PCA modulesCCAPMn registern = 0,1
- ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Function of PCA modules
0 0 0 0 0 0 0 No operation
1 0 0 0 0 1 0 8-bit PWM, no interrupt
1 1 0 0 0 1 1
on rising edge.
1 0 1 0 0 1 1
on falling edge.
.
d
1 1 1 0 0 1 1
e
on both rising and falling edges.
mit
16-bit Capture Mode, caputre triggered by the
X 1 0 0 0 0 X
Li
rising edge on CCPn/PCAn pin
X 0 1 0 0 0 X
falling edge on CCPn/PCAn pin
U
C
X 1 1 0 0 0 X
transition on CCPn/PCAn pin
M
1 0 0 1 0 0 X 16-bit software timer
1 0 0 1 1 0 X 16-bit high-speed output
S T C
10.3.1 PCA Capture Mode
To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPPn
and CAPNn, for the module must be set. The external CCPn input (CCP0/P3.7, CCP1/P3.5) for the
module is sampled for a transition. When a valid transition occurs, the PCA hardware loads the value
of the PCA counter register(CH and CL) into the modules capture registers(CCAPnH and CCAPnL).
If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then
an interrupt will be generated.
CF CR CCF3 CCF2 CCF1 CCF0 CCON (address:D8H)
PCA interrupt
CH CL
CCPn Capture
CCAPnH CCAPnL
CCAPMn, n=0,1,2,3
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Address: DAh, DBh, DCh, DDh
0 0 0 0
PCA Capture Mode

10.3.2 16-bit Software Timer Mode

The PCA modules can be used as software timers by setting both the ECOMn and MATn bits in the modules
CCAPMn register. The PCA timer will be compared to the modules capture registers and when a match occurs an
interrupt will be generated if the CCFn and ECCFn bits for the module are both set.
write first write late

Write to CCAPnL Write to CCAPnH
CF CR CCF3 CCF2 CCF1 CCF0 CCON
Stop comparing Renew comparing

0 1
CCAPnH CCAPnL
PCA Interrupt
.
(To CCFn)
ed
Enable Match
t
16-Bit comparator
m i
if ECOMn=0, Stop comparing
CH CL
Li
U
if ECOMn=0, renew comparing
M C
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn
0 0 1 0 0
S T C PCA Software Timer Mode

10.3.3 High Speed Output Mode

In this mode the CCPn output (port latch) associated with the PCA module will toggle each time a match occurs
between the PCA counter and the modules capture registers. To activate this mode the TOGn,MATn,and ECOMn
bits in the modules CCAPMn SFR must be set.
write first write late

Write to CCAPnL Write to CCAPnH
CF CR CCF3 CCF2 CCF1 CCF0 CCON
Stop comparing Renew comparing

0 1
CCAPnH CCAPnL
PCA Interrupt
(To CCFn)
d .
Enable Match
e
16-Bit comparator
t
Toggle
i m i CCPn
L
if ECOMn=0, Stop comparing CL
CH
if ECOMn=0, renew comparing
C U
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn
M
0 0 1 1 0
C
PCA High-Speed Output Mode
S T

10.3.4 Pulse Width Modulator Mode (PWM mode)

All of the PCA modules can be used as PWM outputs. The frequency of the output depends on the
source for the PCA timer. All of the modules will have the same frequency of output because they all
share the same PCA timer. The duty cycle of each module is independently variable using the module
s capture register CCAPnL and EPCnL bit in PCAPWMn register. When the value of the PCA CL SFR
is less than the value in the modules {EPCnL,CCAPnL} SFR, the output will be low. When it is equal
to or greater than , the output will be high. When CL overflows from FFH to 00H, {EPCnL,CCAPnL}
is reloaded with the value in {EPCnH,CCAPnH}. That allows updating the PWM without glitches.
The PWMn and ECOMn bits in the modules CCAPMn register must be set to enable the PWM mode.
d .
EPCnH CCAPnH
m i t e
Li
U
EPCnL CCAPnL
M C output 0
S T C
enable 9-BIT
COMPARATOR
(0,CL)<(EPCnL,CCPnL)
(0,CL)>=(EPCnL,CCPnL)
PWMn
CCPn
output 1
0 CL
CL overflow
- ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n=0,1,2,3

1 0 0 0 0 1 0
PCA PWM mode

10.4 Programs for PCA module extended external interrupt (C and ASM)
There are two programs for PCA module extended external interrupt demo, one wrriten in C language and the
other in assembly language.
1. C code listing:
/*-------------------------------------------------------------------------------------*/
/* --- STC MCU International Limited ----------------------------------------*/
/* --- STC 1T Series MCU PCA module Extended external interrupt ----*/
/* --- Mobile: (86)13922809991 -----------------------------------------------*/
/* --- Fax: 86-755-82905966 ---------------------------------------------------*/
/* --- Tel: 86-755-82948412 ----------------------------------------------------*/
d .
mit e
/*------------------------------------------------------------------------------------*/
Li
#include "reg51.h"
C U
M
C
sbit EPCAI = IE^6;
T
sbit
sbit
sbit
sbit
CCF0
CCF1
CR
CF

S = CCON^0;
= CCON^1;
= CCON^6;
= CCON^7;

//PCA module-0 interrupt flag
//PCA timer run control bit
//PCA timer overflow flag
sfr CCAPM0 = 0xDA; //PCA module-0 mode register
sfr CCAPM1 = 0xDB; //PCA module-1 mode register
sfr CCAPM2 = 0xDC; //PCA module-2 mode register
sfr CCAPM3 = 0xDD; //PCA module-3 mode register
sfr PCAPWM0 = 0xF2;
sfr PCAPWM1 = 0xF3;
sfr PCAPWM2 = 0xF4;
sfr PCAPWM3 = 0xF5;


{
PCA_LED = !PCA_LED; //toggle the test pin while CEX0(P1.3) have a falling edge
}
void main()
{
//Clear CF flag
d .
i t e

m

CH = 0;
Li

U
CCAPM0 = 0x11; //PCA module-0 capture by a negative tigger on CEX0(P1.3)
C
M
// CCAPM0 = 0x21; //PCA module-0 capture by a rising edge on CEX0(P1.3)
T C
// CCAPM0 = 0x31; //PCA module-0 capture by a transition (falling/rising edge)
S
//on CEX0(P1.3) and enable PCA interrupt

EPCAI = 1;
EA = 1;
while (1);
}

2. Assembly code listing:

;/*------------------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited ---------------------------------------------*/
;/* --- STC 1T Series MCU PCA module Extended external interrupt ----------*/
;/* --- Mobile: (86)13922809991 -----------------------------------------------------*/
;/* --- Fax: 86-755-82905966 ---------------------------------------------------------*/
;/* --- Tel: 86-755-82948412 ----------------------------------------------------------*/
;/* --- Web: www.STCMCU.com -----------------------------------------------------*/
;/*-------------------------------------------------------------------------------------------*/
.
ed
mit
EPCAI BIT IE.6
Li
U
C
M
C
T
CH EQU 0F9H ;PCA base timer HIGH
CCAPM0
CCAP0L
CCAP0H
CCAPM1

S EQU
EQU
EQU
EQU
0DAH
0EAH
0FAH
0DBH

;-----------------------------------------
ORG 0000H
LJMP MAIN

ORG 0033H
PCA_ISR:
CPL PCA_LED ;toggle the test pin while CEX0(P1.3) have a falling edge
RETI
;-----------------------------------------
ORG 0100H
MAIN:
;Clear CF flag
d .
CLR A ;
i t e
m
MOV CH, A ;
Li
U
MOV CCAPM0,#11H ;PCA module-0 capture by a falling edge on CEX0(P1.3)
C
M
; MOV CCAPM0,#21H ;PCA module-0 capture by a rising edge on CEX0(P1.3)
T C
; MOV CCAPM0,#31H ;PCA module-0 capture by a transition (falling/rising edge)
S
;on CEX0(P1.3) and enable PCA interrupt
;-------------------------------
SETB EPCAI
SETB EA
SJMP $
;-----------------------------------------
END

10.5 Demo Programs for PCA module acted as 16-bit Timer (C and ASM)
There are two programs for PCA module acted as 16-bit Timer demo, one wrriten in C language and the other in
assembly language.
1. C code listing:
;/*------------------------------------------------------------------------------------------*/
;/* --- STC 1T Series MCU PCA module acted as 16-bit Timer Demo ---------*/
;/* --- Mobile: (86)13922809991 -----------------------------------------------------*/
;/* --- Fax: 86-755-82905966 ---------------------------------------------------------*/
;/* --- Tel: 86-755-82948412 ----------------------------------------------------------*/
;/* --- Web: www.STCMCU.com -----------------------------------------------------*/
.
ed
mit
;/*------------------------------------------------------------------------------------------*/
Li
#include "reg51.h"
C U
M
#define T100Hz (FOSC / 12 / 100)
C
sfr
sbit
EPCAI
CCON
CCF0
S

T
sbit

= IE^6;
= 0xD8;
= CCON^0;

//PCA control register


BYTE cnt;
WORD value;

{
CCAP0L = value;
CCAP0H = value >> 8; //Update compare value
value += T100Hz;
if (cnt-- == 0)
{
cnt = 100; //Count 100 times
t ed .
i
PCA_LED = !PCA_LED; //Flash once per second
Li m
}
}
U
void main()
C
{
M

CL = 0;

CH = 0; S T

C

//Clear CF flag
//Reset PCA base timer

value = T100Hz;
CCAP0L = value;
CCAP0H = value >> 8; //Initial PCA module-0
value += T100Hz;
CCAPM0 = 0x49; //PCA module-0 work in 16-bit timer mode

EPCAI = 1;
EA = 1;
cnt = 0;
while (1);
}


;/*------------------------------------------------------------------------------------------*/
;/* --- STC 1T Series MCU PCA module acted as 16-bit Timer Demo ---------*/
;/* --- Mobile: (86)13922809991 -----------------------------------------------------*/
;/* --- Fax: 86-755-82905966 ---------------------------------------------------------*/
;/* --- Tel: 86-755-82948412 ---------------------------------------------------------*/
;/* --- Web: www.STCMCU.com ----------------------------------------------------*/
;/*-----------------------------------------------------------------------------------------*/
.
T100Hz EQU 3C00H ;(18432000 / 12 / 100)
ed
mit
Li
EPCAI BIT IE.6
U
C
M
C
S T
CCAPM0 EQU 0DAH ;PCA module-0 mode register
CCAP0L EQU 0EAH ;PCA module-0 capture register LOW
CCAP0H EQU 0FAH ;PCA module-0 capture register HIGH
CNT EQU 20H

;-----------------------------------------
ORG 0000H
LJMP MAIN

ORG 0033H
LJMP PCA_ISR
;-----------------------------------------
ORG 0100H
MAIN:
MOV SP, #3FH ;Initial stack point
;Clear CF flag
CLR A ;
.
MOV CH, A ;
ed
i t
Li m
;-------------------------------
MOV CCAP0L, #LOW T100Hz ;
MOV CCAP0H,#HIGH T100Hz ;Initial PCA module-0
U
MOV CCAPM0,#49H ;PCA module-0 work in 16-bit timer mode and enable PCA interrupt
C
;-------------------------------
M
SETB EPCAI
T C
SETB EA
S
MOV CNT, #100
SJMP $
;-----------------------------------------
PCA_ISR:
PUSH PSW
PUSH ACC
MOV A, CCAP0L
ADD A, #LOW T100Hz ;Update compare value
MOV CCAP0L, A
MOV A, CCAP0H
ADDC A, #HIGH T100Hz
MOV CCAP0H,A
DJNZ CNT, PCA_ISR_EXIT ;count 100 times
MOV CNT, #100
CPL PCA_LED ;Flash once per second
PCA_ISR_EXIT:
POP ACC
POP PSW
RETI
;-----------------------------------------
END
10.6 Programs for PCA module as 16-bit High Speed Output(C and ASM)
There are two programs for PCA module as 16-bit High Speed Output, one wrriten in C language and the other in
assembly language.
1. C code listing:
;/*--------------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited -----------------------------------------*/
;/* --- STC 1T Series MCU PCA module as 16-bit High Speed Output ----*/
;/* --- Mobile: (86)13922809991 -------------------------------------------------*/
;/* --- Fax: 86-755-82905966 -----------------------------------------------------*/
;/* --- Tel: 86-755-82948412 ------------------------------------------------------*/
.
;/* --- Web: www.STCMCU.com -------------------------------------------------*/
ed
mit
Li
;/*---------------------------------------------------------------------------------------*/
#include "reg51.h"
U
C
M
#define T100KHz (FOSC / 4 / 100000)
T
typedef unsigned int
S C WORD;
sbit EPCAI = IE^6;


BYTE cnt;
WORD value;
void PCA_isr( ) interrupt 7 using 1

{
CCAP0L = value;
CCAP0H = value >> 8; //Update compare value
value += T100KHz;
}
d .
void main()
i t e
{
m
Li
//Clear CF flag
U
C

M

CH = 0;

T C
S
value = T100KHz;
CCAP0L = value; //P1.3 output 100KHz square wave
CCAP0H = value >> 8; //Initial PCA module-0
value += T100KHz;
CCAPM0 = 0x4d; //PCA module-0 work in 16-bit timer mode
//and enable PCA interrupt, toggle the output pin CEX0(P1.3)

EPCAI = 1;
EA = 1;
cnt = 0;
while (1);
}


;/*--------------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited -----------------------------------------*/
;/* --- STC 1T Series MCU PCA module as 16-bit High Speed Output ----*/
;/* --- Mobile: (86)13922809991 -------------------------------------------------*/
;/* --- Fax: 86-755-82905966 -----------------------------------------------------*/
;/* --- Tel: 86-755-82948412 ------------------------------------------------------*/
;/* --- Web: www.STCMCU.com -------------------------------------------------*/
;/*---------------------------------------------------------------------------------------*/
d .
T100KHz EQU 2EH ;(18432000 / 4 / 100000)
mit e
Li
C U
CMOD
CL
EQU 0D9H
EQU 0E9H

M ;PCA mode register
;PCA base timer LOW
C
S T
;-----------------------------------------
ORG 0000H
LJMP MAIN
ORG 0033H
PCA_ISR:
PUSH PSW
PUSH ACC

MOV A, CCAP0L
ADD A, #T100KHz ;Update compare value
MOV CCAP0L, A
CLR A
ADDC A, CCAP0H
MOV CCAP0H,A
PCA_ISR_EXIT:
POP ACC
POP PSW
RETI
;-----------------------------------------
ORG 0100H
.
MAIN:
ed
i t
Li m
;Clear CF flag
CLR A ;
U
C
MOV CH, A ;
M
C
;-------------------------------
T
MOV CCAP0L, #T100KHz ;P1.3 output 100KHz square wave
S
MOV CCAP0H,#0 ;Initial PCA module-0
MOV CCAPM0,#4dH ;PCA module-0 work in 16-bit timer mode
;and enable PCA interrupt, toggle the output pin CEX0(P1.3)
;-------------------------------
SETB EA

SJMP $
;-----------------------------------------
END

10.7 Demo Programs for PCA module as PWM Output (C and ASM)
1. C code listing:
*------------------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited --------------------------------------------*/
;/* --- STC 1T Series MCU PCA module output PWM wave Demo -----------*/
;/* --- Mobile: (86)13922809991 ----------------------------------------------------*/
;/* --- Fax: 86-755-82905966 --------------------------------------------------------*/
;/* --- Tel: 86-755-82948412 ---------------------------------------------------------*/
.
;/*------------------------------------------------------------------------------------------*/
ed
mit
#include "reg51.h"
Li
U
C
M
C
T
S
sfr PCAPWM0 = 0xF2;
sfr PCAPWM1 = 0xF3;
sfr PCAPWM2 = 0xF4;
sfr PCAPWM3 = 0xF5;

void main()
{
//Clear CF flag


CH = 0;

CCAP0H = CCAP0L = 0x80; //PWM0 port output 50% duty cycle square wave
.
CCAPM0 = 0x42; //PCA module-0 work in 8-bit PWM mode
//and no PCA interrupt
i t ed

CCAP1H = CCAP1L = 0xff;
PCAPWM1 = 0x03;

Li m
//PWM1 port output 0% duty cycle square wave
U
CCAPM1 = 0x42; //PCA module-1 work in 8-bit PWM mode
C
//and no PCA interrupt
CR = 1;
M //PCA timer start run
}
while (1);
S T C

*------------------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited --------------------------------------------*/
;/* --- STC 1T Series MCU PCA module output PWM wave Demo -----------*/
;/* --- Mobile: (86)13922809991 ----------------------------------------------------*/
;/* --- Fax: 86-755-82905966 --------------------------------------------------------*/
;/* --- Tel: 86-755-82948412 ---------------------------------------------------------*/
;/*------------------------------------------------------------------------------------------*/
.
ed
mit
Li
U
CL
CH
CCAPM0

EQU 0E9H
EQU 0F9H
EQU 0DAH

M C ;PCA base timer LOW
;PCA base timer HIGH
C
CCAP0H
CCAPM1
CCAP1L
CCAP1H

S T
EQU 0FAH
EQU 0DBH
EQU 0EBH
EQU 0FBH

;-----------------------------------------
ORG 0000H
LJMP MAIN
;-----------------------------------------
ORG 0100H
MAIN:
;Clear CF flag

CLR A ;
MOV CH, A ;
;-------------------------------
MOV A, #080H ;
MOV CCAP0H,A ;PWM0 port output 50% duty cycle square wave
MOV CCAP0L,A ;
MOV CCAPM0,#42H ;PCA module-0 work in 8-bit PWM mode and no PCA interrupt
;-------------------------------
MOV A, #0C0H ;
d .
MOV CCAP1H,A ;PWM1 port output 25% duty cycle square wave
i t e
MOV CCAP1L,A ;
m
MOV CCAPM1,#42H ;PCA module-1 work in 8-bit PWM mode and no PCA interrupt
Li
;-------------------------------
SJMP $
C U
M
;-----------------------------------------
END
S T C

10.8 Demo Program for PCA clock base on Timer 1 overflow rate
;/*-------------------------------------------------------------------------------*/
;/* --- STC 1T Series achieve adjustable frequency PWM output-----*/
;/* --- Mobile: (86)13922809991 ------------------------------------------*/
;/* --- Fax: 86-755-82905966 ----------------------------------------------*/
;/* --- Tel: 86-755-82948412 -----------------------------------------------*/
;/*------------------------------------------------------------------------------*/
ed .
mit
IPH EQU 0B7H ;Interrupt priority control register high byte
Li
U
CF BIT CCON.7
CMOD EQU 0D9H
CL EQU 0E9H
;PCA mode register
;PCA base timer LOW
C
;PCA timer overflow flag
M
T C
S
;/*Define working LED */

LED_MCU_START EQU P1.7
LED_5ms_Flashing EQU P1.6
LED_1S_Flashing EQU P1.5
Channel_5mS_H EQU 01H ;PCA module-1 5ms counter high byte @ 18.432MHz
Channel_5mS_L EQU 00H ;PCA module-1 5ms counter low byte @ 18.432MHz
Timer0_Reload_1 EQU 0F6H ;Timer0 auto reload value (-10)

Timer0_Reload_2 EQU 0ECH ;Timer0 auto reload value (-20)
PWM_WIDTH EQU 0FFH ;low duty
Counter EQU 030H ;counter value

;-----------------------------------------
ORG 0000H
LJMP MAIN
ORG 003BH
LJMP PCA_interrupt
;-----------------------------------------
ORG 0050H
MAIN:
CLR LED_MCU_START ;Turn on MCU working LED
MOV SP,#7FH
MOV Counter,#0 ;initial Counter var
.
ACALL PAC_Initial ;initial PCA
ACALL Timer0_Initial ;Initial Timer0
i t ed
MAIN_Loop:
;-------------------------------
Li m
U
MOV TH0,#Timer0_Reload_1 ;Set Timer0 overload rate 1
C
MOV TL0,#Timer0_Reload_1
M
MOV A,#PWM_WIDTH ;setting duty
MOV CCAP0H,A
C
ACALL delay
S T
ACALL delay
;-------------------------------
MOV A,#PWM_WIDTH
ACALL RL_A ;change duty
ACALL RL_A
MOV CCAP0H,A
ACALL delay
ACALL delay
;-------------------------------
MOV A,#PWM_WIDTH
ACALL RL_A ;change duty

ACALL RL_A
ACALL RL_A
ACALL RL_A
MOV CCAP0H,A
ACALL delay
ACALL delay
;-------------------------------
SJMP MAIN_Loop
;-----------------------------------------
.
RL_A:
ed
mit
CLR C
RRC A
Li
RET
U
;-----------------------------------------
C
Timer0_Initial:
M
MOV TMOD,#02H ;8-bit auto-reload
MOV TH0,#Timer0_Reload_1
C
T
SETB TR0 ;strat run
RET
S
;-----------------------------------------
PCA_Initial:
MOV CMOD,#10000100B ;PCA timer base on Timer0
MOV CCON,#00H ;PCA stop count
MOV CL,#0 ;initial PCA counter
MOV CH,#0
MOV CCAPM0,#42H ;PCA module-0 as 8-bit PWM
MOV PCA_PWM0,#0 ;PWM mode 9th bit
; MOV PCA_PWM0,#03H ;PWM will keep low level
MOV CCAP1L,#Channel_5mS_L ;initial PCA module-1

MOV CCAP1H,#Channel_5mS_H
MOV CCAPM1,#49H ;PCA module-1 as 16-bit timer
SETB EA
SETB CR ;PCA counter start running
RET

;-----------------------------------------
PCA_Interrupt:
PUSH ACC
PUSH PSW
CPL LED_5mS_Flashing ;Flashing once per 5ms
MOV A,#Channel_5mS_L
ADD A,CCAP1L
MOV CCAP1L,A
MOV A,#Channel_5mS_H
ADDC A,CCAP1H
MOV CCAP1H,A
CLR CCF1 ;Clear PCA module-1 flag
t ed .
i
INC Counter
m
MOV A,Counter
Li
CLR C
SUBB A,#100 ;Count 100 times
U
JC PCA_Interrupt_Exit
C
MOV Counter,#0
M
CPL LED_1S,Flash
PCA_Interrupt_Exit:
T C
POP PSW
S
POP ACC
RETI
;-----------------------------------------
delay:
CLR A
MOV R1,A
MOV R2,A
MOV R3,#80H
delay_loop:
NOP
NOP
NOP
DJNZ R1,delay_loop
DJNZ R2,delay_loop
DJNZ R3,delay_loop
RET
;-----------------------------------------
END

10.9 Using PWM achieve D/A Conversion function reference circuit
P2.2 1 32 VDD
P2.3 2 31 P2.1
RST 3 30 P2.0
RxD/P3.0 4 29 P1.7/ADC7
TxD/P3.1 5 28 P1.6/ADC6
P0.0 6 27 P1.5/ADC5
SOP-32
XTAL2 7 26 P0.3
INT0/P3.2 9 24 P1.3/ADC3
P0.1 10 23 P0.2
d .
INT1/P3.3 11 22 P1.2/ADC2/LVD
mit e
PWM1/T1/P3.5 13 20 P1.0/ADC0/CLKOUT0 10K D/A
10K
Li
P2.4 14 19 P3.7/PWM0
P2.5 15 18 P2.7 104
104
VSS 16 17 P2.6
C U
M
S T C

Chapter 11. Serial Peripheral Interface (SPI)

STC12C5620AD provides another high-speed serial communication interface, the SPI interface. SPI
is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master
mode and Slave mode. Up to 3Mbit/s can be supported in either Master or Slave mode under the
SYSclk=12MHz. Two status flags are provided to signal the transfer completion and write-collision
occurrence.
11.1 Special Function Registers related with SPI

SPI Management SFRs
Bit address and Symbol
.
Reset
Mnemonic Description Address
d
Value
e
B7 B6 B5 B4 B3 B2 B1 B0
i t
SPCTL SPI Control Register 85H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 0000,0100
Li m
SPSTAT SPI Status Register 84H SPIF WCOL - - - - - - 00xx,xxxx
SPDAT SPI Data Register 86H 0000,0000
C U
1. SPI Control register: SPCTL (Non bit-addressable)
M
SPCTL 85H name SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0
SSIG :

S T C
Control whether SS pin is ignored or not.
If SSIG=1, MSTR(SPCTL.4) decides whether the device is a master or slave.
If SSIG=0, the SS pin decides whether the device is a master or slave. SS pin can be used as I/O port.
SPEN : SPI enable bit.
If SPEN=0, the SPI interface is disabled and all SPI pins will be general-purpose I/O ports.
If SPEN=1, the SPI is enabled.
DORD : Set the transmitted or received SPI data order.
If DORD=1, The LSB of the data word is transmitted first.
If DORD=0, The MSB of the data word is transmitted first.
MSTR : Master/Slave mode select bit.
If MSTR=0, set the SPI to play as Slave part.
If MSTR=1, set the SPI to play as Master part.
CPOL : SPI clock polarity select bit.
If CPOL=1, SPICLK is high level when in idle mode. The leading edge of SPICLK is the falling edge
and the trailing edge is the rising edge.
If CPOL=0, SPICLK is low when idle. The leading edge of SPICLK is the rising edge and the trailing
edge is the falling edge.
CPHA : SPI clock phase select bit.
If CPHA=1, Data is driven on the leading edge of SPICLK, and is sampled on the trailing edge.
If CPHA=0, Data is driven when SS pin is low (SSIG=0) and changes on the trailing edge of SPICLK.
Data is sampled on the leading edge of SPICLK. (Note : If SSIG=1, CPHA must not be 0,
otherwise the operation is undefined)

SPR1-SPR0 : SPI clock rate select bit (when in master mode)

SPI clock frequency select bit
SPR1 SPR0 SPI clock (SCLK )
0 0 CPU_CLK/4
0 1 CPU_CLK/16
1 0 CPU_CLK/64
1 1 CPU_CLK/128
CPU_CLK is CPU clock.
When CPHA equals 0, SSIG must be 0 and SS pin must be negated and reasserted between each successive serial
byte transfer. If the SPDAT register is written while SS is active(0), a write collision error results and WCOL is
.
set.
ed
mit
When CPHA equals 1, SSIG may be 0 or 1. If SSIG=0, the SS pin may remain active low between successive
Li
transfers(can be tied low at any times). This format is sometimes preferred for use in systems having a signle
fixed master and a single slave configuration.
U
2. SPI State register: SPSTAT (Non bit-addressable)
SFR name Address
SPSTAT CDH
bit
name
B7
SPIF
M C
B6
WCOL
B5
-
B4
-
B3
-
B2
-
B1
-
B0
-
T C
SPIF : SPI transfer completion flag.
S
When a serial transfer finishes, the SPIF bit is set and an interrupt is generated if all the EADC_SPI (IE.6)
bit, ESPI bit (AUXR.3) and the EA (IE.7) bit are set. If SS is an input and is driven low when SPI is in
master mode with SSIG = 0, SPIF will also be set to signal the mode change.The SPIF is cleared in
software by writing 1 to this bit.
WCOL: SPI write collision flag.
The WCOL bit is set if the SPI data register, SPDAT, is written during a data transfer. The WCOL flag is
cleared in software by writing 1 to this bit.
3. SPI Data register : SPDAT (Non bit-addressable)

SPDAT CFH name
The SFR SPDAT holds the data to be transmitted or the data received.

5. Registers related with SPI interrupt : IE, AUXR, IP and IPH


SFR name Address bit B7 B6 B5 B4
t ed
B3
. B2 B1 B0
i
Li m
U
M C
C
S T

IP B8H name - PPCA_LVD PADC_SPI PS PT1 PX1 PT0 PX0

11.2 SPI Structure
S
MISO
M P1.6
CPU clock M
8-bit shift register S MOSI
I/O P1.5
Clock divider read data buffer
4, 16, 64, 128 control
SCLK
P1.7
clock
selection SPI clock(host) S
clock logic SS
.
M
d
P1.4
SPR0
e
SPR1
mit
MSTR
Li
SPEN
MSTR
SPI Control SPEN
MSTR
DORD
CPHA
CPOL
SPEN
WCOL
U SPR1
SPR0
SSIG
SPIF
C
SPI Control Register: SPCTL
M
SPI state register: SPSTAT
C
SPI interrupt request
T
internal data bus
S SPI block diagram

The SPI interface has three pins implementing the SPI functionality: SCLK(P1.7), MISO(P1.6), MOSI(P1.5). An
extra pin SS(P1.4) is designed to configure the SPI to run under Master or Slave mode. SCLK, MOSI and MISO
are typically tied together between two or more SPI devices. Data flows from master to slave on MOSI(Master
Out Slave In) pin and flows from slave to master on MISO(Master In Slave Out) pin. The SCLK signal is output
in the master mode and is input in the slave mode. If the SPI system is disabled, i.e, SPEN(SPCTL.6)=0, these
pins are configured as general-purposed I/O port(P1.4 ~ P1.7).
SS is thel slave select pin. In a typical configuration, an SPI master asserts one of its port pins to select one SPI
device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected. But if SPEN=0
or SSIG(SPCTL.7) bit is 1, the SS pin is ignored. Note that even if the SPI is configured as a master(MSTR/
SPCTL.4=1), it can still be converted to a slave by driving the SS pin low. When the conversion happened, the
SPIF bit(SPSTAT.7) will be set.
Two devices with SPI interface communicate with each other via one synchronous clock signal, one input data
signal, and one output data signal. There are two concerns the user should take care, one of them is latching data
on the negative edge or positive edge of the clock signal which named polarity, the other is keeping the clock
signal low or high while the device idle which named phase. Permuting those states from polarity and phase, there
could be four modes formed, they are SPI-MODE-0, SPI-MODE-1, SPI-MODE-2, SPI-MODE-3. Many device
declares that they meet SPI machanism, but few of them are adaptive to all four modes. The STC12C5A60S2
series are flexible to be configured to communicate to another device with MODE-0, MODE-1, MODE-2 or
MODE-3 SPI, and play part of Master and Slave.

11.3 SPI Data Communication

11.3.1 SPI Configuration
When SPI data communication, SPEN, SSIG, SS(P1.4) and MSTR jointly control the selection of master and
slave.
Table: SPI master and slave selection
SS MISO MOSI SPICLK
SPEN SSIG MSTR Mode Remark
(P1.4) (P1.6) (P1.5) (P1.7)
GPI/O GPI/O GPI/O SPI is disabled. P1.4/P1.5/P1.6/
0 X P1.4 X SPI disable
P1.6 P1.5 P1.7 P1.7 as GPIO.
1 0 0 0 Selected salve output input input Selected as slave
1 0 1 0 Unselected slave Hi-Z input input
t ed .
Not selected.
i
1 0 0 1->0 slave output input input Convert from Master to Slave
Li m
MOSI and SCLK are in high-
impedance state in order to
avoid bus clash when master is
U
high- high-
Master (idle) idle. Whether is SCLK pulled
C
impedance impedance
up or pulled down depends on
M
1 0 1 1 input
CPOL/SPCTL.3. But it do not be
allowed that SCLK is suspended.
1 1 P1.4
S T
0
C Master (active)
slave output
output
input
output
input
MOSI and SCLK is strong push-
pull output.
Slave
1 1 P1.4 1 Master input output output Master

11.3.2 SPI Data Communication Modes

There are 3 SPI data communication modes: single master single slave, dual devices configuration (both can be a
master or slave) and single master multiple slaves.
Master Slave
MISO MISO
8-bit shift register 8-bit shift register
MOSI MOSI
SPICLK SPICLK
SPI clock
generator
Port /SS
d .
SPI single master single slave configuration
mit e
Li
Master/Slave Master/Slave
MISO MISO
CU
MOSI MOSI
M
SPICLK SPICLK
SPI clock SPI clock
generator generator
C
/SS /SS
S T SPI dual device configuration, both can be a master or slave
Master Slave #1
MISO MISO
MOSI MOSI
SPICLK SPICLK
SPI clock
generator
Port /SS
Slave #1
MISO
8-bit shift register
MOSI
SPICLK
Port /SS
SPI single master multiple slaves configuration

In SPI, transfers are always initiated by the master. If the SPI is enabled(SPEN=1) and selected as master, any
instruction that use SPI data register SPDAT as the destination will starts the SPI clock generator and a data
transfer. The data will start to appear on MOSI about one half SPI bit-time to one SPI bit-time after it. Before
starting the transfer, the master may select a slave by driving the SS pin of the corresponding device low. Data
written to the SPDAT register of the master shifted out of MOSI pin of the master to the MOSI pin of the slave.
And at the same time the data in SPDAT register of the selected slave is shifted out of MISO pin to the MISO pin
of the master. During one byte transfer, data in the master and in the slave is interchanged. After shifting one byte,
the transfer completion flag(SPIF) is set and an interrupt will be created if the SPI interrupt is enabled.
If SPEN=1, SSIG=0, SS pin=1 and MSTR=1, the SPI is enabled in master mode. Before the instruction that use
SPDAT as the destination register, the master is in idle state and can be selected as slave device by any other
master drives the idle master SS pin low. Once this happened, MSTR bit of the idle master is cleared by hardware
and changes its state a selected slave. User software should always check the MSTR bit. If this bit is cleared by
.
the mode change of SS pin and the user wants to continue to use the SPI as a master later, the user must set the
t ed
MSTR bit again, otherwise it will always stay in slave mode.
m i
Li
The SPI is single buffered in transmit direction and double buffered in receive direction. New data for
transmission can not be written to the shift register until the previous transaction is complete. The WCOL bit is set
to signal data collision when the data register is written during transaction. In this case, the data currently being
U
transmitted will continue to be transmitted, but the new data which causing the collision will be lost. For receiving
C
data, received data is transferred into a internal parallel read data buffer so that the shift register is free to accept
M
a second byte. However, the received byte must be read from the data register(SPDAT) before the next byte has
been completely transferred. Otherwise the previous byte is lost. WCOL can be cleared in software by writing 1
C
to the bit.
S T

11.3.3 SPI Data Modes

CPHA/SPCTL.2 is SPI clock phase select bit which is used to setting the clock edge of Data sample and change.
CPOL/SPCTL.3 is used to select SPI clock polarity.
The following are some typical timing diagrams which depend on the value of CPHA/SPCTL.2
Clock Cycle 1 2 3 4 5 6 7 8
SCLK(CPOL=0)
SCLK(CPOL=1)
.
MOSI(input)
d
DORD=0 MSB 6 5 4 3 2 1 LSB
mit e
LSB 1 2 3 4 5 6 MSB
DORD=1
Li
MISO(output) DORD=0 MSB
LSB
6
1
5
2
4
3
3
4
2
5
1
6
LSB
MSB
undefined
DORD=1
SS pin(if SSIG bit=0)
C U
SPI slave transfer format with CPHA=0
M
S T C Clock Cycle
SCLK(CPOL=0)
1 2 3 4 5 6 7 8
SCLK(CPOL=1)
MOSI(input) 6 5 4 3 1
DORD=0 MSB 2 LSB
LSB 1 2 3 4 5 6 MSB
DORD=1
MISO(output) DORD=0 MSB 6 5 4 3 2 1 LSB

1) LSB 1 2 3 4 5 6 MSB
DORD=1
SS pin(if SSIG bit=0) 1)undefined
SPI slave transfer format with CPHA=1

Clock Cycle 1 2 3 4 5 6 7 8
SCLK(CPOL=0)
SCLK(CPOL=1)
MOSI(input)
DORD=0 MSB 6 5 4 3 2 1 LSB
DORD=1 LSB 1 2 3 4 5 6 MSB

DORD=1 LSB 1 2 3 4 5 6 MSB
SPI master transfer format with CPHA=0
t ed .
m i
Li
U
1 2 3 4 5 6 7 8
C
Clock Cycle
M
SCLK(CPOL=0)
C
SCLK(CPOL=1)
S T DORD=0
MOSI(input) DORD=1 MSB
LSB
6
1
5
2
4
3
3
4
2
5
1
6
LSB
MSB

DORD=1 LSB 1 2 3 4 5 6 MSB
SPI master transfer format with CPHA=1
*When P4SPI bit in AUXR1 register is set, the function of SPI is redirected from P3[7:4] to P4[7:4]
pin by pin.

11.4 SPI Function Demo Programs (Single Master Single Slave)

11.4.1 SPI Function Demo Programs using Interrupts (C and ASM)
The following program,written in C language and assembly language, tests SPI function and applys to SPI single
master single slave configuration.
1. C code listing:
;/*----------------------------------------------------------------------------------*/
;/* --- STC 1T Series MCU SPI Demo (1 master and 1 slave) -----------*/
;/* --- Mobile: (86)13922809991 ---------------------------------------------*/
;/* --- Fax: 86-755-82905966 -------------------------------------------------*/
;/* --- Tel: 86-755-82948412 --------------------------------------------------*/
.
ed
mit
Li
;/*-----------------------------------------------------------------------------------*/
#include "reg51.h"
U
#define MASTER //define:master undefine:slave
C
M
#define BAUD (256 - FOSC / 32 / 115200)
C
T
sfr
sfr
S
typedef unsigned long
AUXR = 0x8e;
SPSTAT = 0x84;
DWORD;

//SPI status register

#define SPIF 0x80 //SPSTAT.7
#define WCOL 0x40 //SPSTAT.6
sfr SPCTL = 0x85; //SPI control register
#define SSIG 0x80 //SPCTL.7
#define SPEN 0x40 //SPCTL.6
#define DORD 0x20 //SPCTL.5
#define MSTR 0x10 //SPCTL.4
#define CPOL 0x08 //SPCTL.3
#define CPHA 0x04 //SPCTL.2
#define SPDHH 0x00 //CPU_CLK/4
#define SPDH 0x01 //CPU_CLK/16
#define SPDL 0x02 //CPU_CLK/64
#define SPDLL 0x03 //CPU_CLK/128
sfr SPDAT = 0x86; //SPI data register
sbit SPISS = P1^3; //SPI slave select, connect to slave' SS(P1.4) pin
sbit EADC_SPI = IE^5;

#define ESPI 0x08; //AUXR.3

void InitUart();
void InitSPI();
void SendUart(BYTE dat); //send data to PC
BYTE RecvUart(); //receive data from PC
///////////////////////////////////////////////////////////
void main()
{
InitUart(); //initial UART
InitSPI(); //initial SPI
.
AUXR |= ESPI;
d
EADC_SPI = 1;
EA = 1;
m i t e
Li
while (1)
{
U
#ifdef MASTER //for master (receive UART data from PC and send it to slave,

ACC = RecvUart();
M C //in the meantime receive SPI data from slave and send it to PC)
C
SPISS = 0; //pull low slave SS
T
SPDAT = ACC; //trigger SPI send
S
#endif
}
}
///////////////////////////////////////////////////////////
void spi_isr() interrupt 5 using 1 //SPI interrupt routine 5 (002BH)

{
SPSTAT = SPIF | WCOL; //clear SPI status
#ifdef MASTER
SPISS = 1; //push high slave SS
SendUart(SPDAT); //return received SPI data
#else //for salve (receive SPI data from master and
SPDAT = SPDAT; // send previous SPI data to master)
#endif
}
///////////////////////////////////////////////////////////

void InitUart()
{
SCON = 0x5a; //set UART mode as 8-bit variable baudrate
TMOD = 0x20; //timer1 as 8-bit auto reload mode
AUXR = 0x40; //timer1 work at 1T mode
TH1 = TL1 = BAUD; //115200 bps
TR1 = 1;
}
///////////////////////////////////////////////////////////
void InitSPI()
d .
{
mit e
SPDAT = 0; //initial SPI data
Li
#ifdef MASTER
SPCTL = SPEN | MSTR; //master mode
U
#else
C
SPCTL = SPEN; //slave mode
M
#endif
}
S T C
///////////////////////////////////////////////////////////
void SendUart(BYTE dat)

{
while (!TI); //wait pre-data sent
TI = 0; //clear TI flag
SBUF = dat; //send current data
}
///////////////////////////////////////////////////////////
BYTE RecvUart()
{
while (!RI); //wait receive complete
RI = 0; //clear RI flag
return SBUF; //return receive data
}

2. Assemly code listing:

;/*----------------------------------------------------------------------------------*/
;/* --- Mobile: (86)13922809991 ---------------------------------------------*/
;/* --- Fax: 86-755-82905966 -------------------------------------------------*/
;/* --- Tel: 86-755-82948412 --------------------------------------------------*/
;/*-----------------------------------------------------------------------------------*/
//#define MASTER //define:master undefine:slave
t ed .
i
SPSTAT DATA 084H ;SPI status register
Li m
SPIF EQU 080H ;SPSTAT.7
WCOL EQU 040H ;SPSTAT.6
SPCTL DATA 085H ;SPI control register
C U
SSIG EQU 080H ;SPCTL.7
M
SPEN EQU 040H ;SPCTL.6
DORD EQU 020H ;SPCTL.5
C
MSTR EQU 010H ;SPCTL.4
T
CPOL EQU 008H ;SPCTL.3
CPHA EQU
SPDHH EQU
SPDH EQU
SPDL EQU
S
004H
000H
001H
002H

;SPCTL.2
;CPU_CLK/4
;CPU_CLK/16
;CPU_CLK/64
SPDLL EQU 003H ;CPU_CLK/128
SPDAT DATA 086H ;SPI data register
SPISS BIT P1.3 ;SPI slave select, connect to slave' SS(P1.4) pin
EADC_SPI BIT IE.5

ESPI EQU 08H ;AUXR.3
;//////////////////////////////////////////////////////////
ORG 0000H
LJMP RESET
ORG 002BH ;SPI interrupt routine 5(2BH)

SPI_ISR:
PUSH ACC
PUSH PSW
MOV SPSTAT, #SPIF | WCOL ;clear SPI status

#ifdef MASTER
SETB SPISS ;push high slave SS
MOV A, SPDAT ;return received SPI data
LCALL SEND_UART
MOV SPDAT, SPDAT ; send previous SPI data to master)
#endif
POP PSW
POP ACC
RETI
;//////////////////////////////////////////////////////////
ed .
mit
ORG 0100H
RESET:
Li
LCALL INIT_UART ;initial UART
LCALL INIT_SPI ;initial SPI
U
ORL AUXR, #ESPI ;enable SPI interrupt
C
SETB EADC_SPI
M
SETB EA
MAIN:
C
S T
LCALL RECV_UART ; in the meantimereceive SPI data from slave and send it to PC)
CLR SPISS ;pull low slave SS
MOV SPDAT, A ;trigger SPI send
#endif
SJMP MAIN
;//////////////////////////////////////////////////////////
INIT_UART:
MOV SCON, #5AH ;set UART mode as 8-bit variable baudrate
MOV TMOD, #20H ;timer1 as 8-bit auto reload mode
MOV AUXR, #40H ;timer1 work at 1T mode
MOV TL1, #0FBH ;115200 bps(256 - 18432000 / 32 / 115200)
MOV TH1, #0FBH
SETB TR1
RET
;//////////////////////////////////////////////////////////

INIT_SPI:
MOV SPDAT, #0 ;initial SPI data
#ifdef MASTER
MOV SPCTL, #SPEN | MSTR ;master mode
#else
MOV SPCTL, #SPEN ;slave mode
#endif
RET
;//////////////////////////////////////////////////////////
.
SEND_UART:
JNB TI, $
t
;wait pre-data sent
i ed
m
CLR TI ;clear TI flag
Li
MOV SBUF, A ;send current data
RET
;//////////////////////////////////////////////////////////
C U
RECV_UART:
M
C
JNB RI,$ ;wait receive complete

CLR RI
MOV A,
RET
RET
SBUF
S T ;clear RI flag
;return receive data
;//////////////////////////////////////////////////////////
END

11.4.2 SPI Function Demo Programs using Polling (C and ASM)

1. C code listing:
;/*-----------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited --------------------------------------*/
;/* --- STC 1T Series MCU SPI Demo (1 master and 1 slave) ------------*/
;/* --- Mobile: (86)13922809991 ----------------------------------------------*/
;/* --- Fax: 86-755-82905966 --------------------------------------------------*/
;/* --- Tel: 86-755-82948412 ---------------------------------------------------*/
.
;/*----------------------------------------------------------------------------------*/
ed
mit
#include "reg51.h"
Li
#define BAUD (256 - FOSC / 32 / 115200)
C U
M
typedef unsigned long DWORD;
sfr
sfr
#define
S T C
AUXR = 0x8e;
SPSTAT = 0x84;
SPIF 0x80

//SPSTAT.7
#define WCOL 0x40 //SPSTAT.6
void InitUart();
void InitSPI();
BYTE SPISwap(BYTE dat); //swap SPI data between master and slave

///////////////////////////////////////////////////////////
void main()
{
while (1)
{
// in the meantime receive SPI data from slave and send it to PC)
SendUart(SPISwap(RecvUart()));
d .
i t e
ACC = SPISwap(ACC); // send previous SPI data to master)
m
#endif
Li
}
}
///////////////////////////////////////////////////////////
C U
void InitUart()
M
T C
{
S
TH1 = TL1 = BAUD; //115200 bps
TR1 = 1;
}
///////////////////////////////////////////////////////////
void InitSPI()
{
#ifdef MASTER
SPCTL = SPEN | MSTR; //master mode
#else
#endif
}

///////////////////////////////////////////////////////////

{
}
///////////////////////////////////////////////////////////
.
BYTE RecvUart()
d
{
mit e
Li
}
///////////////////////////////////////////////////////////
C U
BYTE SPISwap(BYTE dat)
M
T C
{
S
#ifdef MASTER
#endif
SPDAT = dat; //trigger SPI send
while (!(SPSTAT & SPIF)); //wait send complete
#ifdef MASTER
#endif
return SPDAT; //return received SPI data
}

;/*----------------------------------------------------------------------------------*/
;/* --- Mobile: (86)13922809991 ---------------------------------------------*/
;/* --- Fax: 86-755-82905966 -------------------------------------------------*/
;/* --- Tel: 86-755-82948412 --------------------------------------------------*/
;/*-----------------------------------------------------------------------------------*/
.
i t ed
SPSTAT DATA
SPIF EQU
084H
080H

Li
;SPI status register
;SPSTAT.7
m
U
C
M
C
S T
CPHA EQU 004H ;SPCTL.2
SPDHH EQU 000H ;CPU_CLK/4
SPDH EQU 001H ;CPU_CLK/16
SPDL EQU 002H ;CPU_CLK/64
;//////////////////////////////////////////////////////////
ORG 0000H
LJMP RESET
ORG 0100H
RESET:

MAIN:
#ifdef MASTE //for master (receive UART data from PC and send it to slave, in the meantime
LCALL RECV_UART ; receive SPI data from slave and send it to PC)
LCALL SPI_SWAP
LCALL SEND_UART
LCALL SPI_SWAP ; send previous SPI data to master)
#endif
SJMP MAIN
;//////////////////////////////////////////////////////////
INIT_UART:
.
ed
mit
Li
MOV TL1, #0FBH ;115200 bps(256 - 18432000 / 32 / 115200)
MOV TH1, #0FBH
SETB TR1
RET
C U
M
;//////////////////////////////////////////////////////////
INIT_SPI:

S T
MOV SPDAT, #0 C
MOV SPSTAT, #SPIF | WCOL
;initial SPI data
;clear SPI status
#ifdef MASTER
MOV SPCTL, #SPEN | MSTR ;master mode
#else
#endif
RET
;//////////////////////////////////////////////////////////
SEND_UART:
JNB TI, $ ;wait pre-data sent
RET
;//////////////////////////////////////////////////////////

RECV_UART:
JNB RI, $ ;wait receive complete
CLR RI ;clear RI flag
MOV A, SBUF ;return receive data
RET
RET
;//////////////////////////////////////////////////////////
SPI_SWAP:
#ifdef MASTER
.
#endif
i t ed
m
Li
WAIT:
MOV A, SPSTAT
U
JNB ACC.7, WAIT ;wait send complete
C
M
#ifdef MASTER
C
#endif

MOV
RET
S
A,
T SPDAT
;//////////////////////////////////////////////////////////
;return received SPI data
END

11.5 SPI Function Demo Programs (Each other as the Master-Slave)

11.5.1 SPI Function Demo Programs using Interrupts (C and ASM)
1. C code listing:
/*--------------------------------------------------------------------------------------------*/
/* --- STC12C5Axx Series MCU SPI Demo(Each other as the master-slave) --*/
/* --- Mobile: (86)13922809991 -------------------------------------------------------*/
/* --- Fax: 86-755-82905966 -----------------------------------------------------------*/
/* --- Tel: 86-755-82948412 ------------------------------------------------------------*/
/* --- Web: www.STCMCU.com -------------------------------------------------------*/
/* If you want to use the program or the program referenced in the --------------*/
.
/* article, please specify in which data and procedures from STC --------------*/
d
/*---------------------------------------------------------------------------------------------*/
#include "reg51.h"
mit e
Li
#define BAUD (256 - FOSC / 32 / 115200)
C U
M
C
sfr
#define
#define
SPIF
WCOL S T
SPSTAT = 0x84;
0x80
0x40

//SPSTAT.7
//SPSTAT.6
sbit SPISS = P1^3; //SPI slave select, connect to other MCU's SS(P1.4) pin
sbit EADC_SPI = IE^5;

#define ESPI 0x08; //AUXR.3

void InitUart();
void InitSPI();
bit MSSEL; //1: master 0:slave
///////////////////////////////////////////////////////////
void main()
{
.
AUXR |= ESPI;
ed
EADC_SPI = 1;
i t
EA = 1;
Li m

while (1)
{
CU
if (RI)
{
M
SPCTL = SPEN | MSTR; //set as master
MSSEL = 1;
C
ACC = RecvUart();
S T
SPDAT = ACC; //trigger SPI send
}
}
}
///////////////////////////////////////////////////////////
void spi_isr( ) interrupt 5 using 1 //SPI interrupt routine 5 (002BH)

{
if (MSSEL)
{
SPCTL = SPEN; //reset as slave
MSSEL = 0;
SendUart(SPDAT); //return received SPI data
}
else
{ //for salve (receive SPI data from master and
SPDAT = SPDAT; // send previous SPI data to master)
}
}
///////////////////////////////////////////////////////////

void InitUart()
{
TH1 = TL1 = BAUD; //115200 bps
TR1 = 1;
}
///////////////////////////////////////////////////////////
void InitSPI()
.
{
ed
mit
Li
}
///////////////////////////////////////////////////////////
C U
M
C
{
T
S
}
///////////////////////////////////////////////////////////
BYTE RecvUart()
{
}

/*--------------------------------------------------------------------------------------------*/
/* --- Mobile: (86)13922809991 -------------------------------------------------------*/
/* --- Fax: 86-755-82905966 -----------------------------------------------------------*/
/* --- Tel: 86-755-82948412 ------------------------------------------------------------*/
/*---------------------------------------------------------------------------------------------*/
t ed .
i
Li m
U
C
CPOL EQU 008H
M ;SPCTL.3
C
T
S
SPISS BIT P1.3 ;SPI slave select, connect to other MCU's SS(P1.4) pin
EADC_SPI BIT IE.5

ESPI EQU 08H ;AUXR.3
MSSEL BIT 20H.0 ;1: master 0:slave
;//////////////////////////////////////////////////////////
ORG 0000H
LJMP RESET
ORG 002BH ;SPI interrupt routine

SPI_ISR:
PUSH ACC
PUSH PSW
JBC MSSEL, MASTER_SEND

SLAVE_RECV:
//for salve (receive SPI data from master and
MOV SPDAT, SPDAT ; send previous SPI data to master)
JMP SPI_EXIT
MASTER_SEND:
MOV SPCTL, #SPEN ; ;reset as slave
LCALL SEND_UART
SPI_EXIT:
POP PSW
POP ACC
.
RETI
ed
mit
;//////////////////////////////////////////////////////////
ORG 0100H
Li
U
RESET:
C
MOV SP,#3FH
M
C
ORL AUXR, #ESPI
T
SETB EADC_SPI

MAIN:

SETB EA
JNB RI,
S $
MOV SPCTL, #SPEN | MSTR
;wait UART data
; ;set as master
SETB MSSEL
LCALL RECV_UART ;receive UART data from PC
SJMP MAIN
;//////////////////////////////////////////////////////////
INIT_UART:
MOV AUXR ,#40H ;timer1 work at 1T mode
MOV TL1, #0FBH ;115200 bps(256 - 18432000 / 32 / 115200)
MOV TH1, #0FBH
SETB TR1
RET

;//////////////////////////////////////////////////////////
INIT_SPI:
RET
;//////////////////////////////////////////////////////////
SEND_UART:
t ed .
i
Li m
RET
;//////////////////////////////////////////////////////////
RECV_UART:
C U
M

MOV A,
RET
RET
SBUF
S T C ;return receive data
;//////////////////////////////////////////////////////////
END

11.5.2 SPI Function Demo Programs using Polling

1. C code listing:
/*--------------------------------------------------------------------------------------------*/
/* --- Mobile: (86)13922809991 -------------------------------------------------------*/
/* --- Fax: 86-755-82905966 -----------------------------------------------------------*/
/* --- Tel: 86-755-82948412 ------------------------------------------------------------*/
/*---------------------------------------------------------------------------------------------*/
#include "reg51.h"
ed .
Li mit
#define BAUD (256 - FOSC / 32 / 115200)
U
C
M
sfr
#define
#define
SPSTAT =
SPIF
WCOL S T C

0x84;
0x80
0x40

//SPSTAT.7
//SPSTAT.6

void InitUart();
void InitSPI();
BYTE SPISwap(BYTE dat); //swap SPI data between master

///////////////////////////////////////////////////////////
void main()
{
while (1)
{
if (RI)
{
SPCTL = SPEN | MSTR; //set as master
SendUart(SPISwap(RecvUart()));
t ed .
i
SPCTL = SPEN; //reset as slave
Li m
}
if (SPSTAT & SPIF)
{
U
C
SPDAT = SPDAT; //mov data from receive buffer to send buffer
M
}
}
}
S T C
///////////////////////////////////////////////////////////
void InitUart()
{
TH1 = TL1 = BAUD; //115200 bps
TR1 = 1;
}
///////////////////////////////////////////////////////////
void InitSPI()
{
}

///////////////////////////////////////////////////////////

{
}
///////////////////////////////////////////////////////////
BYTE RecvUart()
d .
{
mit e
Li
}
///////////////////////////////////////////////////////////
C U
BYTE SPISwap(BYTE dat)
M
C
{
S T
SPDAT = dat; //trigger SPI send
while (!(SPSTAT & SPIF)); //wait send complete
return SPDAT; //return received SPI data
}


/*--------------------------------------------------------------------------------------------*/
/* --- Mobile: (86)13922809991 -------------------------------------------------------*/
/* --- Fax: 86-755-82905966 -----------------------------------------------------------*/
/* --- Tel: 86-755-82948412 ------------------------------------------------------------*/
/*---------------------------------------------------------------------------------------------*/
d .
i t e
m
Li
U
C
M
T C
S
;//////////////////////////////////////////////////////////
ORG 0000H
LJMP RESET
ORG 0100H
RESET:
MAIN:
JB RI, MASTER_MODE

SLAVE_MODE:
MOV A, SPSTAT
JNB ACC.7, MAIN
MOV SPDAT, SPDAT ;return received SPI data
SJMP MAIN
MASTER_MODE:
MOV SPCTL, #SPEN | MSTR ;set as master
LCALL RECV_UART ;receive UART data from PC
LCALL SPI_SWAP ;send it to slave, in the meantime, receive SPI data from slave
LCALL SEND_UART ;send SPI data to PC
MOV SPCTL, #SPEN ; ;reset as slave
.
SJMP MAIN
ed
mit
;//////////////////////////////////////////////////////////
INIT_UART:
MOV SCON, #5AH
Li
;set UART mode as 8-bit variable baudrate
MOV TMOD, #20H
C U
;timer1 as 8-bit auto reload mode
M
MOV TL1, #0FBH ;115200 bps(256 - 18432000 / 32 / 115200)
C
MOV TH1, #0FBH
T
SETB TR1
S
RET
;//////////////////////////////////////////////////////////
INIT_SPI:
RET
;//////////////////////////////////////////////////////////
SEND_UART:
RET

;//////////////////////////////////////////////////////////
RECV_UART:
MOV A, SBUF ;return receive data
RET
RET
;//////////////////////////////////////////////////////////
SPI_SWAP:
d .
t e
WAIT:
m i
Li
MOV A, SPSTAT
JNB ACC.7, WAIT ;wait send complete
U
C
M
RET
S T C
;//////////////////////////////////////////////////////////
END

Chapter 12. IAP / EEPROM

The ISP in STC12C5620AD series makes it possible to update the users application program and non-volatile
application data (in IAP-memory) without removing the MCU chip from the actual end product. This useful
capability makes a wide range of field-update applications possible. (Note ISP needs the loader program pre-
programmed in the ISP-memory.) In general, the user neednt know how ISP operates because STC has provided
the standard ISP tool and embedded ISP code in STC shipped samples.But, to develop a good program for ISP
function, the user has to understand the architecture of the embedded flash.
The embedded flash consists of 8~60 pages. Each page contains 512 bytes. Dealing with flash, the user must
erase it in page unit before writing (programming) data into it.Erasing flash means setting the content of that
flash as FFh. Two erase modes are available in this chip. One is mass mode and the other is page mode. The mass
mode gets more performance, but it erases the entire flash. The page mode is something performance less, but it
is flexible since it erases flash in page unit. Unlike RAMs real-time operation, to erase flash or to write (program)
flash often takes long time so to wait finish.
ed .
mit
Furthermore, it is a quite complex timing procedure to erase/program flash. Fortunately, the STC12C5620AD
Li
series carried with convenient mechanism to help the user read/change the flash content. Just filling the target
address and data into several SFR, and triggering the built-in ISP automation, the user can easily erase, read, and
U
program the embedded flash.
M C
The In-Application Program feature is designed for user to Read/Write nonvolatile data flash. It may bring great
help to store parameters those should be independent of power-up and power-done action. In other words, the user
can store data in data flash memory, and after he shutting down the MCU and rebooting the MCU, he can get the
T C
original value, which he had stored in.
S
The user can program the data flash according to the same way as ISP program, so he should get deeper under-
standing related to SFR ISP_DATA, ISP_ADDRL, ISP_ADDRH, ISP_CMD, ISP_TRIG, and ISP_CONTR.

12.1 IAP / EEPROM Special Function Registers

The following special function registers are related to the IAP/ISP/EEPROM operation. All these
registers can be accessed by software in the users application program.
Value after
MSB LSB Reset
ISP/IAP Flash Data
ISP_DATA E2H 1111 1111B
Register
ISP/IAP Flash
ISP_ADDRH E3H 0000 0000B
Address High
.
ISP/IAP Flash
d
ISP_ADDRL E4H 0000 0000B
e
Address Low
i t
ISP/IAP Flash - - - - - - MS1 MS0
m
ISP_CMD E5H xxxx x000B
Li
Command Register
ISP/IAP Flash
ISP_TRIG E6H xxxx xxxxB
Command Trigger
U
ISP/IAP Control ISPEN SWBS SWRST CMD_FAIL - WT2 WT1 WT0
C
ISP_CONTR E7H 0000 1000B
Register
M
S T C
1. ISP/IAP Flash Data Register : ISP_DATA (Address: E2H, Non bit-addressable)
ISP_DATA is the data port register for ISP/IAP operation. The data in ISP_DATA will be written into
the desired address in operating ISP/IAP write and it is the data window of readout in operating ISP/
IAP read.
2. ISP/IAP Flash Address Registers : ISP_ADDRH and ISP_ADDRL

ISP_ADDRH (address:E3H) is the high-byte address port for all ISP/IAP modes.
ISP_ADDRH[7:5] must be cleared to 000, if one bit of ISP_ADDRH[7:5] is set, the IAP/ISP write
function must fail.
ISP_ADDRL (address:E4H) is the low port for all ISP/IAP modes. In page erase operation, it is
ignored.

3. ISP/IAP Flash Command Register : ISP_CMD (Non bit -addressable)
ISP_CMD E5H name - - - - - - MS1 MS0
B7~B2: Reserved.
MS1, MS0 : ISP/IAP operating mode selection. IAP_CMD is used to select the flash mode for
performing numerous ISP/IAP function or used to access protected SFRs.
0, 0 : Standby
0, 1 : Data Flash/EEPROM read.
1, 0 : Data Flash/EEPROM program.
1, 1 : Data Flash/EEPROM page erase.
ed .
4. ISP/IAP Flash Command Trigger Register : ISP_TRIG (Address: E6H, Non bit -addressable)
mit
ISP_TRIG is the command port for triggering ISP/IAP activity and protected SFRs access. If ISP_TRIG is filled
Li
with sequential 0x46h, 0xB9h and if ISPEN(ISP_CONTR.7) = 1, ISP/IAP activity or protected SFRs access will
triggered.
C U
5. ISP/IAP Control Register : ISP_CONTR (Non bit-addressable)
SFR name Address bit B7

M B6 B5 B4 B3 B2 B1 B0
C
ISP_CONTR E7H name ISPEN SWBS SWRST CMD_FAIL - WT2 WT2 WT0
S T
ISPEN : ISP/IAP operation enable.
0 : Global disable all ISP/IAP program/erase/read function.
1 : Enable ISP/IAP program/erase/read function.
SWBS: software boot selection control.
0 : Boot from main-memory after reset.
1 : Boot from ISP memory after reset.
SWRST: software reset trigger control.
0 : No operation
1 : Generate software system reset. It will be cleared by hardware automatically.
CMD_FAIL: Command Fail indication for ISP/IAP operation.
0 : The last ISP/IAP command has finished successfully.
1 : The last ISP/IAP command fails. It could be caused since the access of flash memory was inhibited.
B3: Reserved. Software must write 0 on this bit when ISP_CONTR is written.

WT2~WT0 : Waiting time selection while flash is busy.

Setting wait times CPU wait times
Read
Program Sector Erase Recommended System
WT2 WT1 WT0 (2 System
(=55uS) (=21mS) Clock Frequency (MHz)
clocks)
1 1 1 2 SYSclks 55 SYSclks 21012 SYSclks 1MHz
.
t ed
Note: Software reset actions could reset other SFR,but it never influences bits ISPEN and SWBS.The ISPEN and
i
SWBS. The ISPEN and SWBS only will be reset by power-up action, while not software reset.
Li m
CU
6. When the operation voltage is too low, EEPROM / IAP function should be disabled
M
LVDF

T C
: Pin Low-Voltage Flag. Once low voltage condition is detected (VCC power is lower than LVD
S

12.2 STC12C5620AD series Internal EEPROM Allocation Table

STC12C5620AD series microcontroller's Data Flash (internal available EEPROM) address (and program space
is separate) : if the application area of IAP write Data/erase sector of the action, the statements will be ignore
and continue to the next one. Program in user application area (AP area), only operate IAP/ISP on Data Flash
(EEPROM )
STC12C5612AD / STC12C5628AD / STC12C5630AD and STC12LE5612AD / STC12LE5628AD /

STC12C5630AD are excepted, this several types in the application area can modify the application
STC12C5620AD series MCU internal EEPROM Selection Table

STC12LE5620AD series MCU internal EEPROM Selection Table
EEPROM Sector Begin_Sector End_Sector
Type
.
(Byte) Numbers Begin_Address End_Address
ed
STC12C5604AD/
mit
4K 8 0000h 0FFFh
STC12LE5604AD
Li
STC12C5608AD/
4K 8 0000h 0FFFh
STC12LE5608AD
U
STC12C5616AD/
C
4K 8 0000h 0FFFh
STC12LE5616AD
STC12C5620AD/
STC12LE5620AD
4K
M 8 0000h 0FFFh
T C
The following series are special.
S
User can modify the application the application area, all flash area can be modified as EEPROM
STC12C5612AD/
- 24 0000h 2FFFh
STC12LE5612AD
STC12C5628AD/
- 56 0000h 6FFFh
STC12LE5628AD
STC12C5630AD/
- 60 0000h 77FFh
STC12LE5630AD
STC12C5620AD series MCU address reference table in detail (512 bytes per sector)
STC12LE5620AD series MCU address reference table in detail (512 bytes per sector)
Sector 1 Sector 2 Sector 3 Sector 4 Each sector 512 byte
Start End Start End Start End Start End
0000H 01FFH 0200H 03FFH 0400H 05FFH 0600H 07FFH Suggest the same
Sector 5 Sector 6 Sector7 Sector 8 times modified data
Start End Start End Start End Start End in the same sector,
each times modified
d a t a i n d i ff e r e n t
0800H 09FFH 0A00H 0BFFH 0C00H 0DFFH 0E00H 0FFFH sectors, don't have to
use full, of course, it
was all to use

12.3 IAP/EEPROM Assembly Language Program Introduction

; /*It is decided by the assembler/compiler used by users that whether the SFRs addresses are declared by the
DATA or the EQU directive*/
ISP_DATA DATA 0E2H or ISP_DATA EQU 0E2H
ISP_ADDRH DATA 0E3H or ISP_ADDRH EQU 0E3H
ISP_ADDRL DATA 0E4H or ISP_ADDRL EQU 0E4H
ISP_CMD DATA 0E5H or ISP_CMD EQU 0E5H
ISP_TRIG DATA 0E6H or ISP_TRIG EQU 0E6H
ISP_CONTR DATA 0E7H or ISP_CONTR EQU 0E7H
;/*Define ISP/IAP/EEPROM command and wait time*/

ISP_IAP_BYTE_READ EQU 1 ;Byte-Read
ISP_IAP_BYTE_PROGRAM EQU 2 ;Byte-Program
d .
ISP_IAP_SECTOR_ERASE EQU 3 ;Sector-Erase
t e
WAIT_TIME EQU 0 ;Set wait time
m i
Li
;/*Byte-Read*/
MOV ISP_ADDRH, #BYTE_ADDR_HIGH ;Set ISP/IAP/EEPROM address high
MOV ISP_ADDRL, #BYTE_ADDR_LOW ;Set ISP/IAP/EEPROM address low
C U
MOV ISP_CONTR, #WAIT_TIME ;Set wait time
ORL ISP_CONTR, #10000000B ;Open ISP/IAP function
M
MOV ISP_CMD, #ISP_IAP_BYTE_READ ;Set ISP/IAP Byte-Read command
MOV ISP_TRIG, #46H ;Send trigger command1 (0x46)
T C
MOV ISP_TRIG, #0B9H ;Send trigger command2 (0xB9)
S
NOP ;CPU will hold here until ISP/IAP/EEPROM operation complete
MOV A, ISP_DATA ;Read ISP/IAP/EEPROM data
;/*Disable ISP/IAP/EEPROM function, make MCU in a safe state*/

MOV ISP_CONTR, #00000000B ;Close ISP/IAP/EEPROM function
MOV ISP_CMD, #00000000B ;Clear ISP/IAP/EEPROM command
;MOV ISP_TRIG, #00000000B ;Clear trigger register to prevent mistrigger
;MOV ISP_ADDRH, #0FFH ;Move 00 into address high-byte unit,
;Data ptr point to non-EEPROM area
;MOV ISP_ADDRL, #0FFH ;Move 00 into address low-byte unit,
;prevent misuse
;/*Byte-Program, if the byte is null(0FFH), it can be programmed; else, MCU must operate Sector-Erase firstly,
and then can operate Byte-Program.*/
MOV ISP_DATA, #ONE_DATA ;Write ISP/IAP/EEPROM data
MOV ISP_ADDRH, #BYTE_ADDR_HIGH ;Set ISP/IAP/EEPROM address high
MOV ISP_ADDRL, #BYTE_ADDR_LOW ;Set ISP/IAP/EEPROM address low
MOV ISP_CMD, #ISP_IAP_BYTE_READ ;Set ISP/IAP Byte-Read command
MOV ISP_TRIG, #0B9H ;Send trigger command2 (0xb9)


MOV ISP_CONTR, #00000000B ;Close ISP/IAP/EEPROM function
;MOV ISP_ADDRH, #FFH ;Move 00H into address high-byte unit,
;Data ptr point to non-EEPROM area
;MOV ISP_ADDRL, #0FFH ;Move 00H into address low-byte unit,
;prevent misuse
;/*Erase one sector area, there is only Sector-Erase instead of Byte-Erase, every sector area account for 512
bytes*/
MOV ISP_ADDRH, #SECTOT_FIRST_BYTE_ADDR_HIGH
;Set the sector area starting address high
.
MOV ISP_ADDRL, #SECTOT_FIRST_BYTE_ADDR_LOW
ed
;Set the sector area starting address low
mit
Li
MOV ISP_CMD, #ISP_IAP_SECTOR_ERASE ;Set Sectot-Erase command
U
MOV ISP_TRIG, #0B9H ;Send trigger command2 (0xb9)
C
MOV ISP_CONTR,
M
#00000000B ;Close ISP/IAP/EEPROM function
T C
S
;MOV ISP_ADDRH, #0FFH ;Move 00H into address high-byte unit,
; Data ptr point to non-EEPROM area
;MOV ISP_ADDRL, #0FFH ;Move 00H into address low-byte unit,
;prevent misuse

Little common sense: (STC MCU Data Flash use as EEPROM function)
Three basic commands -- bytes read, byte programming, the sector erased
Byte programming: "1" write "1" or "0", will "0" write "0".Just FFH can byte programming. If the byte not FFH,
you must erase the sector , because only the "sectors erased" to put "0" into "1".
Sector erased: only "sector erased" will also be a "0" erased for "1".
Big proposal:
1. The same times modified data in the same sector, not the same times modified data in other sectors, won't have
to read protection.
.
2. If a sector with only one byte, that's real EEPROM, STC MCU Data Flash faster than external EEPROM, read
ed
a byte/many one byte programming is about 2 clock / 55uS.
i t
3. If in a sector of storing a large amounts of data, a only need to modify one part of a byte, or when the other
m
Li
byte don't need to modify data must first read on STC MCU, then erased RAM the whole sector, again will need
to keep data and need to amend data in bytes written back to this sector section literally only bytes written orders
(without continuous bytes, write command). Then each sector use bytes are using the less the convenient (not
U
need read a lot of maintained data).
M C
S T C
Frequently asked questions:
1. IAP instructions after finishing, address is automatically "add 1" or "minus 1"?
Answer: not
2. Send 46 and B9 after IAP ordered the trigger whether to have sent 46 and B9 trigger?
Answer: yes

12.4 EEPROM Demo Program (C and ASM)

1. C Code Listing
/*-------------------------------------------------------------------------------*/
/* --- STC 1T Series MCU ISP/IAP/EEPROM Demo ----------------*/
/* --- Mobile: (86)13922809991 -----------------------------------------*/
/* --- Fax: 86-755-82905966 ---------------------------------------------*/
/* --- Tel: 86-755-82948412 ----------------------------------------------*/
/*-------------------------------------------------------------------------------*/
#include "reg51.h"
ed .
mit
Li
U
/*Declare SFR associated with the IAP */
C
sfr IAP_DATA = 0xE2; //Flash data register
M
sfr IAP_ADDRH = 0xE3; //Flash address HIGH
sfr IAP_ADDRL = 0xE4; //Flash address LOW
sfr IAP_CMD = 0xE5; //Flash command register
T C
sfr IAP_TRIG = 0xE6; //Flash command trigger
S
sfr IAP_CONTR = 0xE7; //Flash control register
/*Define ISP/IAP/EEPROM command*/

#define CMD_IDLE 0 //Stand-By
#define CMD_READ 1 //Byte-Read
#define CMD_PROGRAM 2 //Byte-Program
#define CMD_ERASE 3 //Sector-Erase
/*Define ISP/IAP/EEPROM operation const for IAP_CONTR*/
//#define ENABLE_IAP 0x80 //if SYSCLK<30MHz
#define ENABLE_IAP 0x82 //if SYSCLK<20MHz
//Start address for STC12C5620AD series EEPROM
#define IAP_ADDRESS 0x0400
void Delay(BYTE n);
void IapIdle();
BYTE IapReadByte(WORD addr);

void IapProgramByte(WORD addr, BYTE dat);
void IapEraseSector(WORD addr);
void main()
{
WORD i;
P1 = 0xfe; //1111,1110 System Reset OK

Delay(10); //Delay
IapEraseSector(IAP_ADDRESS); //Erase current sector
for (i=0; i<512; i++) //Check whether all sector data is FF
{
if (IapReadByte(IAP_ADDRESS+i) != 0xff)
goto Error; //If error, break
}
t ed .
i
P1 = 0xfc; //1111,1100 Erase successful
m
Delay(10); //Delay
Li
for (i=0; i<512; i++) //Program 512 bytes data into data flash
{
IapProgramByte(IAP_ADDRESS+i, (BYTE)i);
}
C U
M
P1 = 0xf8; //1111,1000 Program successful
Delay(10); //Delay
C
for (i=0; i<512; i++) //Verify 512 bytes data
T
{
S
if (IapReadByte(IAP_ADDRESS+i) != (BYTE)i)
goto Error; //If error, break
}
P1 = 0xf0; //1111,0000 Verify successful
while (1);
Error:
P1 &= 0x7f; //0xxx,xxxx IAP operation fail
while (1);
}
/*----------------------------
----------------------------*/
void Delay(BYTE n)
{
WORD x;
while (n--)
{
x = 0;
while (++x);
}
}

/*----------------------------
Disable ISP/IAP/EEPROM function
Make MCU in a safe state
----------------------------*/
void IapIdle()
{
IAP_CONTR = 0; //Close IAP function
IAP_CMD = 0; //Clear command to standby
IAP_TRIG = 0; //Clear trigger register
IAP_ADDRH = 0x80; //Data ptr point to non-EEPROM area
IAP_ADDRL = 0; //Clear IAP address to prevent misuse
}
.
/*----------------------------
ed
Read one byte from ISP/IAP/EEPROM area
mit
Input: addr (ISP/IAP/EEPROM address)
Li
Output:Flash data
----------------------------*/
BYTE IapReadByte(WORD addr)
U
{
C
BYTE dat; //Data buffer

IAP_CONTR = ENABLE_IAP;
M //Open IAP function, and set wait time
C

IAP_CMD = CMD_READ; //Set ISP/IAP/EEPROM READ command
T

IAP_ADDRL = addr; //Set ISP/IAP/EEPROM address low
S

IAP_ADDRH = addr >> 8; //Set ISP/IAP/EEPROM address high
IAP_TRIG = 0x46; //Send trigger command1 (0x46)
IAP_TRIG = 0xb9; //Send trigger command2 (0xb9)
_nop_(); //MCU will hold here until ISP/IAP/EEPROM
//operation complete
dat = IAP_DATA; //Read ISP/IAP/EEPROM data
IapIdle(); //Close ISP/IAP/EEPROM function
return dat; //Return Flash data

}
/*----------------------------
Program one byte to ISP/IAP/EEPROM area
dat (ISP/IAP/EEPROM data)
Output:-
----------------------------*/

void IapProgramByte(WORD addr, BYTE dat)

{
IAP_CONTR = ENABLE_IAP; //Open IAP function, and set wait time
IAP_CMD = CMD_PROGRAM; //Set ISP/IAP/EEPROM PROGRAM command
IAP_DATA = dat; //Write ISP/IAP/EEPROM data
IapIdle();
}
/*----------------------------
t ed .
i
Erase one sector area
Output:-
----------------------------*/
Li m
U
void IapEraseSector(WORD addr)
C
{
M
IAP_CONTR = ENABLE_IAP; //Open IAP function, and set wait time
IAP_CMD = CMD_ERASE; //Set ISP/IAP/EEPROM ERASE command
T C
S
IapIdle();
}

2. Assembly Code Listing

;/*--------------------------------------------------------------------------------*/
;/* --- STC 1T Series MCU ISP/IAP/EEPROM Demo -----------------*/
;/* --- Mobile: (86)13922809991 ------------------------------------------*/
;/* --- Fax: 86-755-82905966 ----------------------------------------------*/
;/* --- Tel: 86-755-82948412 -----------------------------------------------*/
;/*------------------------------------------------------------------------------*/
d .
;/*Declare SFRs associated with the IAP */
mit e
IAP_DATA EQU 0E2H ;Flash data register
IAP_ADDRH EQU 0E3H ;Flash address HIGH
Li
IAP_ADDRL EQU 0E4H ;Flash address LOW
IAP_CMD EQU 0E5H ;Flash command register
IAP_TRIG EQU 0E6H ;Flash command trigger
C U
IAP_CONTR EQU 0E7H ;Flash control register
;/*Define ISP/IAP/EEPROM command*/

CMD_IDLE EQU 0
M ;Stand-By
C
CMD_READ EQU 1 ;Byte-Read
S T
CMD_PROGRAM EQU 2 ;Byte-Program
CMD_ERASE EQU 3 ;Sector-Erase
;/*Define ISP/IAP/EEPROM operation const for IAP_CONTR*/

;ENABLE_IAP EQU 80H ;if SYSCLK<30MHz
ENABLE_IAP EQU 82H ;if SYSCLK<20MHz
;//Start address for STC12C5620AD series EEPROM

IAP_ADDRESS EQU 0000H
;-----------------------------------------
ORG 0000H
LJMP MAIN
;-----------------------------------------
ORG 0100H
MAIN:
MOV P1, #0FEH ;1111,1110 System Reset OK
LCALL DELAY ;Delay

;-------------------------------
MOV DPTR, #IAP_ADDRESS ;Set ISP/IAP/EEPROM address
LCALL IAP_ERASE ;Erase current sector
;-------------------------------
MOV R0, #0 ;Set counter (512)
MOV R1, #2
CHECK1: ;Check whether all sector data is FF
LCALL IAP_READ ;Read Flash
CJNE A, #0FFH, ERROR ;If error, break
INC DPTR ;Inc Flash address
DJNZ R0, CHECK1 ;Check next
;-------------------------------
d .
MOV P1, #0FCH ;1111,1100 Erase successful
i t e
LCALL DELAY ;Delay
m
;-------------------------------
Li
MOV R1, #2
C U
MOV R2, #0 ;Initial test data
NEXT: ;Program 512 bytes data into data flash
M
MOV A, R2 ;Ready IAP data
LCALL IAP_PROGRAM ;Program flash
T C
S
INC R2 ;Modify test data
DJNZ R0, NEXT ;Program next
DJNZ R1, NEXT ;Program next
;-------------------------------
MOV P1, #0F8H ;1111,1000 Program successful
LCALL DELAY ;Delay
;-------------------------------
MOV R1, #2
MOV R2, #0
CHECK2: ;Verify 512 bytes data
LCALL IAP_READ ;Read Flash
CJNE A, 2, ERROR ;If error, break
INC R2 ;Modify verify data
;-------------------------------
MOV P1, #0F0H ;1111,0000 Verify successful
SJMP $
;-------------------------------

ERROR:
MOV P0, R0
MOV P2, R1
MOV P3, R2
CLR P1.7 ;0xxx,xxxx IAP operation fail
SJMP $
;/*----------------------------
;----------------------------*/
DELAY:
CLR A
MOV R0, A
MOV R1, A
d .
MOV R2, #20H
mit e
DELAY1:
DJNZ R0, DELAY1
Li
DJNZ R1, DELAY1
DJNZ R2, DELAY1
RET
;/*----------------------------
C U
M
;Disable ISP/IAP/EEPROM function
;Make MCU in a safe state
C
;----------------------------*/
S T
IAP_IDLE:
MOV IAP_CONTR, #0 ;Close IAP function
MOV IAP_CMD, #0 ;Clear command to standby
MOV IAP_TRIG, #0 ;Clear trigger register
MOV IAP_ADDRH, #80H ;Data ptr point to non-EEPROM area
MOV IAP_ADDRL, #0 ;Clear IAP address to prevent misuse
RET
;/*----------------------------
;Read one byte from ISP/IAP/EEPROM area
;Input: DPTR(ISP/IAP/EEPROM address)
;Output:ACC (Flash data)
;----------------------------*/
IAP_READ:
MOV IAP_CONTR, #ENABLE_IAP ;Open IAP function, and set wait time
MOV IAP_CMD, #CMD_READ ;Set ISP/IAP/EEPROM READ command
MOV IAP_ADDRL, DPL ;Set ISP/IAP/EEPROM address low
MOV IAP_ADDRH, DPH ;Set ISP/IAP/EEPROM address high
MOV IAP_TRIG, #46H ;Send trigger command1 (0x46)
MOV IAP_TRIG, #0B9H ;Send trigger command2 (0xb9)
NOP ;MCU will hold here until ISP/IAP/EEPROM operation complete
MOV A, IAP_DATA ;Read ISP/IAP/EEPROM data
LCALL IAP_IDLE ;Close ISP/IAP/EEPROM function
RET

;/*----------------------------
;Program one byte to ISP/IAP/EEPROM area
;Input: DPAT(ISP/IAP/EEPROM address)
;ACC (ISP/IAP/EEPROM data)
;Output:-
;----------------------------*/
IAP_PROGRAM:
MOV IAP_CMD, #CMD_PROGRAM ;Set ISP/IAP/EEPROM PROGRAM command
MOV IAP_DATA, A ;Write ISP/IAP/EEPROM data
MOV IAP_TRIG, #46H ;Send trigger command1 (0x46)
.
MOV IAP_TRIG, #0B9H ;Send trigger command2 (0xb9)
d
i t e
m
RET
;/*----------------------------
Li
U
;Erase one sector area
C
;Input: DPTR(ISP/IAP/EEPROM address)
M
;Output:-
;----------------------------*/
C
IAP_ERASE:
T
S
MOV IAP_CMD, #CMD_ERASE ;Set ISP/IAP/EEPROM ERASE command
MOV IAP_TRIG,#46H ;Send trigger command1 (0x46)
MOV IAP_TRIG,#0B9H ;Send trigger command2 (0xb9)
RET
END

Chapter 13. STC12 series Development/Programming Tool
13.1 In-System-Programming (ISP) principle

If need download code into STC12C5620AD series, P1.0
and P1.1 pin must be connected to GND
If you chose the "Next program code, P1.0/1.1 need=0/0"
option, then the next time you need to re-download the
program, first of all must be connected P1.0 and P1.1 to
GND
.
Power-on,reset
ed
mit
Must be cold-reset (power-on reset),MCU will
Li
MCU frist running ISP monitor code run from ISP monitor code, for any warm-reset
(include reset-pin, watchdog), MCU will run user
code directly.
NO
C U
Detect whether there ia a
M
legitimate ISP command
Wait ISP command for tens or hundreds
YES
C
milliseconds, if no legitimate command, MCU
T
will reset to AP area.
S
Download user program to AP area.
PC application must send command at

first then power on MCU
Reset to AP area running user code

13.2 STC12C5620AD series Typical Application Circuit for ISP
Vcc
10F
1 C1+ Vcc 16 Vcc 2 Download user
+
0.1F
3 procedure to STC
2 V+ Gnd 15 Gnd
MCU by the software
STC-ISP programmer
PC_TxD(COM Pin3)
4 C2+ R1IN 13
0.1F
Users are suggested stay this USB +5V
Vin
5 C2- R1OUT 12
USB+5V T1OUT R1IN GND System Power
6 V- T1IN 11 can be convenient download
7 T2OUT T2IN 10
.
Reset
d
8 R2IN R2OUT 9 USB1
U1-P1.0 Power On
i t e
U1-P1.1
MCU-VCC
m
Li
than 20MHz, it is suggested not to use C1 and U1-P3.0
R1 replaced by 1K resistor connect to ground. U1-P3.1
But R/C reset circuit is GND 28 Pin
Vcc
also suggest to reserve.
Vcc
CU
1K
1 P2.2 VCC 28
1K
M
+ 2 P2.3 P2.1 27
10 F C1
3 RST PWM2/PCA2/P2.0 26 0.1F +
C
10F
T
S
<33pF
8 P3.2/INT0 ADC3/P1.3 21
9 P3.3/INT1 ADC2/P1.2 20
13 P2.5 P2.7 16
14 Gnd P2.6 15
(4MHz ~ 8MHz, manufacturing error),
XTAL1 and XTAL2 pin should be floated.

are input from XTAL1 pin and XTAL2 pin This circuit has been made as a STC12C5620AD series
must be floated. microcontroller ISP download programming tool

.
ed
Li mit
C U
M
S T C

13.3 PC side application usage
According to
actual situation,
the user selects
.
the appropriate
d
maximum baud
i t e
rate
Li m In practice, if P3.0/
P3.1 already connected
C U
to a RS232/RS485 or
M
other equipment, it
is recommended that
selection P1.0 / P1.1
S T C = 0/0 can download

options
Press this button when

mass production
All new settings

are valid in the
next power-on.
Enable the option in
debugging stage

Step1 : Select MCU type (E.g. STC12C5620AD)

Step2 : Load user program code (*.bin or *.hex)
Setp3 : Select the serial port you are using
Setp4 : Config the hardware option
Step5 : Press ISP programming or Re-Programming button to download user program
NOTE : Must press ISP programming or Re-Programming button first, then power on MCU, otherwise
will cannot download.
About hardware connection

1. MCU RXD (P3.0) ---- RS232 ---- PC COM port TXD (Pin3)
2. MCU TXD (P3.1) ---- RS232 ---- PC COM port RXD (Pin2)
3. MCU GNG-------PC COM port GND (Pin5)
4. RS232 : You can select STC232 / STC3232 / MAX232 / MAX3232 /
Using a demo board as a programmer
ed .
mit
STC-ISP ver3.0A PCB can be welded into three kinds of circuits, respectively, support the STC's 16/20/28/32
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pins MCU, the back plate of the download boards are affixed with labels,users need to pay special attention
to. All the download board is welded 40-pin socket, the sockets 20-pin is ground line, all types of MCU
should be put on the socket according to the way of alignment with the ground. The method of programming
U
user code using download board as follow:
C
1. According to the type of MCU choose supply voltage,
M
A. For 5V MCU, using jumper JP1 to connect MCU-VCC to +5V pin
B. For 3V MCU, using jumper JP1 to connect MCU-VCC to +3.3V pin
C
2. Download cable (Provide by STC)
T
A. Connect DB9 serial connector to the computer's RS-232 serial interface
S
B. Plug the USB interface at the same side into your computer's USB port for power supply
C. Connect the USB interface at the other side into STC download board
3. Other interfaces do not need to connect.
4. In a non-pressed state to SW1, and MCU-VCC power LED off.
5. For SW3
P1.0/P1.1 = 1/1 when SW3 is non-pressed
P1.0/P1.1 = 0/0 when SW3 is pressed
If you have select the Next program code, P1.0/P1.1 Need = 0/0 option, then SW3 must be in a pressed
state
6. Put target MCU into the U1 socket, and locking socket
7. Press the Download button in the PC side application
8. Press SW1 switch in the download board
9. Close the demo board power supply and remove the MCU after download successfully.

13.4 Compiler / Assembler Programmer and Emulator

About Compiler/Assembler
Any traditional compiler / assembler and the popular Keil are suitable for STC MCU. For selection MCU
body, the traditional compiler / assembler, you can choose Intel's 8052 / 87C52 / 87C52 / 87C58 or Philips's
P87C52 / P87C54/P87C58 in the traditional environment, in Keil environment, you can choose the types in
front of the proposed or download the STC chips database file (STC.CDB) from the STC official website.
About Programmer
You can use the STC specific ISP programmer. (Can be purchased from the STC or apply for free sample).
Programmer can be used as demo board
About Emulator
.
We do not provite specific emulator now. If you have a traditional 8051 emulator, you can use it to simulate
t ed
STC MCUs some 8052 basic functions.
m i
Li
13.5 Self-Defined ISP download Demo
U
/*-------------------------------------------------------------------------------------------------------------*/
C
/* --- STC MCU International Limited ----------------------------------------------------------------*/
M
/* --- STC 1T Series MCU using software to custom download code Demo---------------------*/
/* --- Mobile: (86)13922809991 ------------------------------------------------------------------------*/
C
/* --- Fax: 86-755-82905966 ----------------------------------------------------------------------------*/
T
/* --- Tel: 86-755-82948412 -----------------------------------------------------------------------------*/
S
/* --- Web: www.STCMCU.com -----------------------------------------------------------------------*/
/* If you want to use the program or the program referenced in the ------------------------------*/
/* article, please specify in which data and procedures from STC ------------------------------*/
/*-------------------------------------------------------------------------------------------------------------*/
#include <reg51.h>
#include <instrins.h>
sfr IAP_CONTR = 0xe7;

sbit MCU_Start_Led = P1^7;
#define Self_Define_ISP_Download_Command 0x22

#define RELOAD_COUNT 0xfb //18.432MHz,12T,SMOD=0,9600bps
//#define RELOAD_COUNT 0xf6 //18.432MHz,12T,SMOD=0,4800bps
//#define RELOAD_COUNT 0xec //18.432MHz,12T,SMOD=0,2400bps
//#define RELOAD_COUNT 0xd8 //18.432MHz,12T,SMOD=0,1200bps
void serial_port_initial(void);
void delay(void);

void main(void)
{
serial_port_initial(); //Initial UART

display_MCU_Start_Led(); //Turn on the work LED
send_UART(0x34); //Send UART test data
send_UART(0xa7); // Send UART test data
while (1);
}

{
.
ES = 0; //Disable serial interrupt
d
mit e
SBUF = i; //send this data
while (!TI); //wait for the data is sent
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ES = 1; //enable serial interrupt
U
}
{
M C
void UART_Interrupt)Receive(void) interrupt 4 using 1
T C
if (RI)
S
{
RI = 0;
k = SBUF;
if (k == Self_Define_ISP_Command) //check the serial data
{
delay(); //delay 1s
delay(); //delay 1s
soft_reset_to_ISP_Monitor();
}
}
if (TI)
{
TI = 0;
}
}
{
IAP_CONTR = 0x60; //0110,0000 soft reset system to run ISP monitor
}

void delay(void)
{
unsigned int j = 0;
unsigned int g = 0;
for (j=0; j<5; j++)
{
for (g=0; g<60000; g++)
{
_nop_();
_nop_();
_nop_();
_nop_();
.
_nop_();
t ed
}
i
}
}
{
Li m
C U
M
for (i=0; i<3; i++)
{
C
MCU_Start_Led = 0; //Turn on work LED
S T
dejay();
MCU_Start_Led = 1; //Turn off work LED
dejay();
MCU_Start_Led = 0; //Turn on work LED
}
}

In addition, the PC-side application also need to make the following settings
ed .
Li mit
C U
Clicking the "Help" button as show in above figure, we can see the detail explaination as below.
M
S T C

Appendix A: Assembly Language Programming

INTRODUCTION
Assembly language is a computer language lying between the extremes of machine language and high-level
language like Pascal or C use words and statements that are easily understood by humans, although still a long
way from "natural" language.Machine language is the binary language of computers.A machine language program
is a series of binary bytes representing instructions the computer can execute.
Assembly language replaces the binary codes of machine language with easy to remember "mnemonics"that
facilitate programming.For example, an addition instruction in machine language might be represented by the
code "10110011".It might be represented in assembly language by the mnemonic "ADD".Programming with
mnemonics is obviously preferable to programming with binary codes.
Of course, this is not the whole story. Instructions operate on data, and the location of the data is specified by
various "addressing modes" emmbeded in the binary code of the machine language instruction. So, there may be
.
several variations of the ADD instruction, depending on what is added. The rules for specifying these variations
t ed
are central to the theme of assembly language programming.
i
An assembly language program is not executable by a computer. Once written, the program must undergo
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translation to machine language. In the example above, the mnemonic "ADD" must be translated to the binary
code "10110011". Depending on the complexity of the programming environment, this translation may involve
one or more steps before an executable machine language program results. As a minimum, a program called an
U
"assembler" is required to translate the instruction mnemonics to machine language binary codes. Afurther step
C
may require a "linker" to combine portions of program from separate files and to set the address in memory at
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which th program may execute. We begin with a few definitions.
An assembly language program i a program written using labels, mnemonics, and so on, in which each
C
statement corresponds to a machine instruction. Assembly language programs, often called source code or
S T
symbolic code, cannot be executed by a computer.
A machine language program is a program containing binary codes that represent instructions to a computer.
Machine language programs, often called object code, are executable by a computer.
A assembler is a program that translate an assembly language program into a machine language program.
The machine language program (object code) may be in "absolute" form or in "relocatable" form. In the latter
case, "linking" is required to set the absolute address for execution.
A linker is a program that combines relocatable object programs (modules) and produces an absolute object
program that is executable by a computer. A linker is sometimes called a "linker/locator" to reflect its separate
functions of combining relocatable modules (linking) and setting the address for execution (locating).
A segment is a unit of code or data memory. A segment may be relocatable or absolute. A relocatable
segment has a name, type, and other attributes that allow the linker to combine it with other paritial segments,
if required, and to correctly locate the segment. An absolute segment has no name and cannot be combined with
other segments.
A module contains one or more segments or partial segments. A module has a name assigned by the user. The
module definitions determine the scope of local symbols. An object file contains one or more modules. A module
may be thought of as a "file" in many instances.
A program consists of a single absolute module, merging all absolute and relocatable segments from all input
modules. A program contains only the binary codes for instructions (with address and data constants) that are
understood by a computer.

ASSEMBLER OPERATION
There are many assembler programs and other support programs available to facilitate the development of
applications for the 8051 microcontroller. Intel's original MCS-51 family assembler, ASM51, is no longer
available commercially. However, it set the standard to which the others are compared.
ASM51 is a powerful assembler with all the bells and whistles. It is available on Intel development systems
and on the IBM PC family of microcomputers. Since these "host" computers contain a CPU chip other than the
8051, ASM51 is called a cross assembler. An 8051 source program may be written on the host computer (using
any text editor) and may be assembled to an object file and listing file (using ASM51), but the program may not
be executed. Since the host system's CPU chip is not an 8051, it does not understand the binary instruction in the
object file. Execution on the host computer requires either hardware emulation or software simulation of the target
CPU. A third possibility is to download the object program to an 8051-based target system for execution.
ASM51 is invoked from the system prompt by
ASM51 source_file [assembler_controls]
d .
The source file is assembled and any assembler controls specified take effect. The assembler receives a source
e
mit
file as input (e.g., PROGRAM.SRC) and generates an object file (PROGRAM.OBJ) and listing file (PROGRAM.
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LST) as output. This is illustrated in Figure 1.
Since most assemblers scan the source program twice in performing the translation to machine language,
they are described as two-pass assemblers. The assembler uses a location counter as the address of instructions
U
and the values for labels. The action of each pass is described below.
M C PROGRAM.OBJ
C
ASM51
T
PROGRAM.SRC
S Legend
Utility program
User file
PROGRAM.LST
Figure 1 Assembling a source program
Pass one
During the first pass, the source file is scanned line-by-line and a symbol table is built. The location counter
defaults to 0 or is set by the ORG (set origin) directive. As the file is scanned, the location counter is incremented
by the length of each instruction. Define data directives (DBs or DWs) increment the location counter by the
number of bytes defined. Reserve memory directives (DSs) increment the location counter by the number of bytes
reserved.
Each time a label is found at the beginning of a line, it is placed in the symbol table along with the current
value of the location counter. Symbols that are defined using equate directives (EQUs) are placed in the symbol
table along with the "equated" value. The symbol table is saved and then used during pass two.
Pass two
During pass two, the object and listing files are created. Mnemonics are converted to opcodes and placed in
the output files. Operands are evaluated and placed after the instruction opcodes. Where symbols appear in the
operand field, their values are retrieved from the symbol table (created during pass one) and used in calculating
the correct data or addresses for the instructions.
Since two passes are performed, the source program may use "forward references", that is, use a symbol
before it is defined. This would occur, for example, in branching ahead in a program.

The object file, if it is absolute, contains only the binary bytes (00H-0FH) of the machine language program.
A relocatable object file will also contain a sysmbol table and other information required for linking and locating.
The listing file contains ASCII text codes (02H-7EH) for both the source program and the hexadecimal bytes in
the machine language program.
A good demonstration of the distinction between an object file and a listing file is to display each on the
host computer's CRT display (using, for example, the TYPE command on MS-DOS systems). The listing file
clearly displays, with each line of output containing an address, opcode, and perhaps data, followed by the
program statement from the source file. The listing file displays properly because it contains only ASCII text
codes. Displaying the object file is a problem, however. The output will appear as "garbage", since the object file
contains binary codes of an 8051 machine language program, rather than ASCII text codes.
ASSEMBLY LANGUAGE PROGRAM FORMAT

Assembly language programs contain the following:
.
Machine instructions
ed
Assembler directives
Assembler controls
m i t
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Comments
Machine instructions are the familiar mnemonics of executable instructions (e.g., ANL). Assembler directives
are instructions to the assembler program that define program structure, symbols, data, constants, and so on (e.g.,
U
ORG). Assembler controls set assembler modes and direct assembly flow (e.g., $TITLE). Comments enhance the
C
readability of programs by explaining the purpose and operation of instruction sequences.
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Those lines containing machine instructions or assembler directives must be written following specific rules
understood by the assembler. Each line is divided into "fields" separated by space or tab characters. The general
C
format for each line is as follows:
S T
[label:] mnemonic [operand] [, operand] [] [;commernt]
Only the mnemonic field is mandatory. Many assemblers require the label field, if present, to begin on the left in
column 1, and subsequent fields to be separated by space or tab charecters. With ASM51, the label field needn't
begin in column 1 and the mnemonic field needn't be on the same line as the label field. The operand field must,
however, begin on the same line as the mnemonic field. The fields are described below.
Label Field
A label represents the address of the instruction (or data) that follows. When branching to this instruction, this
label is usded in the operand field of the branch or jump instruction (e.g., SJMP SKIP).
Whereas the term "label" always represents an address, the term "symbol" is more general. Labels are
one type of symbol and are identified by the requirement that they must terminate with a colon(:). Symbols
are assigned values or attributes, using directives such as EQU, SEGMENT, BIT, DATA, etc. Symbols may be
addresses, data constants, names of segments, or other constructs conceived by the programmer. Symbols do not
terminate with a colon. In the example below, PAR is a symbol and START is a label (which is a type of symbol).
PAR EQU 500 ;"PAR" IS A SYMBOL WHICH
;REPRESENTS THE VALUE 500
START: MOV A,#0FFH ;"START" IS A LABEL WHICH
;REPRESENTS THE ADDRESS OF
;THE MOV INSTRUCTION
A symbol (or label) must begin with a letter, question mark, or underscore (_); must be followed by letters,
digit, "?", or "_"; and can contain up to 31 characters. Symbols may use upper- or lowercase characters, but they
are treated the same. Reserved words (mnemonics, operators, predefined symbols, and directives) may not be
used.
Mnemonic Field
Intruction mnemonics or assembler directives go into mnemonic field, which follows the label field. Examples of
instruction mnemonics are ADD, MOV, DIV, or INC. Examples of assembler directives are ORG, EQU, or DB.
Operand Field
The operand field follows the mnemonic field. This field contains the address or data used by the instruction. A
label may be used to represent the address of the data, or a symbol may be used to represent a data constant. The
possibilities for the operand field are largely dependent on the operation. Some operations have no operand (e.g.,
the RET instruction), while others allow for multiple operands separated by commas. Indeed, the possibilties for
the operand field are numberous, and we shall elaborate on these at length. But first, the comment field.
Comment Field
Remarks to clarify the program go into comment field at the end of each line. Comments must begin with a
d .
semicolon (;). Each lines may be comment lines by beginning them with a semicolon. Subroutines and large
mit e
sections of a program generally begin with a comment blockserveral lines of comments that explain the general
properties of the section of software that follows.
Special Assembler Symbols

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Special assembler symbols are used for the register-specific addressing modes. These include A, R0 through
C
R7, DPTR, PC, C and AB. In addition, a dollar sign ($) can be used to refer to the current value of the location
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counter. Some examples follow.
SETB C
INC DPTR
T C
JNB TI , $
written as
HERE: JNB
S
The last instruction above makes effective use of ASM51's location counter to avoid using a label. It could also be
TI , HERE
Indirect Address
For certain instructions, the operand field may specify a register that contains the address of the data. The
commercial "at" sign (@) indicates address indirection and may only be used with R0, R1, the DPTR, or the PC,
depending on the instruction. For example,
ADD A , @R0
MOVC A , @A+PC
The first instruction above retrieves a byte of data from internal RAM at the address specified in R0. The second
instruction retrieves a byte of data from external code memory at the address formed by adding the contents of
the accumulator to the program counter. Note that the value of the program counter, when the add takes place, is
the address of the instruction following MOVC. For both instruction above, the value retrieved is placed into the
accumulator.
Immediate Data
Instructions using immediate addressing provide data in the operand field that become part of the instruction.
Immediate data are preceded with a pound sign (#). For example,

CONSTANT EQU 100
MOV A , #0FEH
ORL 40H , #CONSTANT
All immediate data operations (except MOV DPTR,#data) require eight bits of data. The immediate data are
evaluated as a 16-bit constant, and then the low-byte is used. All bits in the high-byte must be the same (00H or
FFH) or the error message "value will not fit in a byte" is generated. For example, the following instructions are
syntactically correct:
MOV A , #0FF00H
MOV A , #00FFH
But the following two instructions generate error messages:

MOV A , #0FE00H
MOV A , #01FFH
t ed .
i
If signed decimal notation is used, constants from -256 to +255 may also be used. For example, the following
m
two instructions are equivalent (and syntactically correct):
Li
MOV A , #-256
MOV A , #0FF00H
C U
Both instructions above put 00H into accumulator A.
Data Address
M
C
Many instructions access memory locations using direct addressing and require an on-chip data memory address
T
(00H to 7FH) or an SFR address (80H to 0FFH) in the operand field. Predefined symbols may be used for the
S
SFR addresses. For example,
MOV A , 45H
MOV A , SBUF ;SAME AS MOV A, 99H
Bit Address
One of the most powerful features of the 8051 is the ability to access individual bits without the need for masking
operations on bytes. Instructions accessing bit-addressable locations must provide a bit address in internal data
memory (00h to 7FH) or a bit address in the SFRs (80H to 0FFH).
There are three ways to specify a bit address in an instruction: (a) explicitly by giving the address, (b) using
the dot operator between the byte address and the bit position, and (c) using a predefined assembler symbol. Some
examples follow.
SETB 0E7H ;EXPLICIT BIT ADDRESS
SETB ACC.7 ;DOT OPERATOR (SAME AS ABOVE)
JNB TI , $ ;"TI" IS A PRE-DEFINED SYMBOL
JNB 99H , $ ;(SAME AS ABOVE)
Code Address
A code address is used in the operand field for jump instructions, including relative jumps (SJMP and conditional
jumps), absolute jumps and calls (ACALL, AJMP), and long jumps and calls (LJMP, LCALL).
The code address is usually given in the form of a label.
ASM51 will determine the correct code address and insert into the instruction the correct 8-bit signed offset,
11-bit page address, or 16-bit long address, as appropriate.

Generic Jumps and Calls
ASM51 allows programmers to use a generic JMP or CALL mnemonic. "JMP" can be used instead of SJMP,
AJMP or LJMP; and "CALL" can be used instead of ACALL or LCALL. The assembler converts the generic
mnemonic to a "real" instruction following a few simple rules. The generic mnemonic converts to the short form
(for JMP only) if no forward references are used and the jump destination is within -128 locations, or to the
absolute form if no forward references are used and the instruction following the JMP or CALL instruction is in
the same 2K block as the destination instruction. If short or absolute forms cannot be used, the conversion is to
the long form.
The conversion is not necessarily the best programming choice. For example, if branching ahead a few
instrucions, the generic JMP will always convert to LJMP even though an SJMP is probably better. Consider the
following assembled instructions sequence using three generic jumps.
LOC OBJ LINE SOURCE
.
1234 1 ORG 1234H
d
1234 04 2 START: INC A
mit e
1235 80FD 3 JMP START ;ASSEMBLES AS SJMP
12FC 4 ORG START + 200
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12FC 4134 5 JMP START ;ASSEMBLES AS AJMP
12FE 021301 6 JMP FINISH ;ASSEMBLES AS LJMP
U
1301 04 7 FINISH: INC A
C
8 END
M
The first jump (line 3) assembles as SJMP because the destination is before the jump ( i.e., no forward reference)
and the offset is less than -128. The ORG directive in line 4 creates a gap of 200 locations between the label
T C
START and the second jump, so the conversion on line 5 is to AJMP because the offset is too great for SJMP.
S
Note also that the address following the second jump (12FEH) and the address of START (1234H) are within the
same 2K page, which, for this instruction sequence, is bounded by 1000H and 17FFH. This criterion must be met
for absolute addressing. The third jump assembles as LJMP because the destination (FINISH) is not yet defined
when the jump is assembled (i.e., a forward reference is used). The reader can verify that the conversion is as
stated by examining the object field for each jump instruction.
ASSEMBLE-TIME EXPRESSION EVALUATION

Values and constants in the operand field may be expressed three ways: (a) explicitly (e.g.,0EFH), (b) with a
predefined symbol (e.g., ACC), or (c) with an expression (e.g.,2 + 3). The use of expressions provides a powerful
technique for making assembly language programs more readable and more flexible. When an expression is used,
the assembler calculates a value and inserts it into the instruction.
All expression calculations are performed using 16-bit arithmetic; however, either 8 or 16 bits are inserted
into the instruction as needed. For example, the following two instructions are the same:
MOV DPTR, #04FFH + 3
MOV DPTR, #0502H ;ENTIRE 16-BIT RESULT USED
If the same expression is used in a "MOV A,#data" instruction, however, the error message "value will not fit in a
byte" is generated by ASM51. An overview of the rules for evaluateing expressions follows.

Number Bases
The base for numeric constants is indicated in the usual way for Intel microprocessors. Constants must be
followed with "B" for binary, "O" or "Q" for octal, "D" or nothing for decimal, or "H" for hexadecimal. For
example, the following instructions are the same:

MOV A , #15H
MOV A , #1111B
MOV A , #0FH
MOV A , #17Q
MOV A , #15D
Note that a digit must be the first character for hexadecimal constants in order to differentiate them from labels (i.e.,
"0A5H" not "A5H").
Charater Strings
t ed .
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Strings using one or two characters may be used as operands in expressions. The ASCII codes are converted to the
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binary equivalent by the assembler. Character constants are enclosed in single quotes ('). Some examples follow.
CJNE A , # 'Q', AGAIN
SUBB A , # '0' ;CONVERT ASCII DIGIT TO BINARY DIGIT
U
MOV DPTR, # 'AB'
C
MOV DPTR, #4142H ;SAME AS ABOVE
Arithmetic Operators
M
T C
The arithmetic operators are
S
+ addition
- subtraction
* multiplication
/ division
MOD modulo (remainder after division)
For example, the following two instructions are same:

MOV A, 10 +10H
MOV A, #1AH
The following two instructions are also the same:

MOV A, #25 MOD 7
MOV A, #4
Since the MOD operator could be confused with a symbol, it must be seperated from its operands by at least one
space or tab character, or the operands must be enclosed in parentheses. The same applies for the other operators
composed of letters.
Logical Operators
The logical operators are
OR logical OR
AND logical AND
XOR logical Exclusive OR
NOT logical NOT (complement)

The operation is applied on the corresponding bits in each operand. The operator must be separated from the
operands by space or tab characters. For example, the following two instructions are the same:
MOV A, # '9' AND 0FH
MOV A, #9
The NOT operator only takes one operand. The following three MOV instructions are the same:
THREE EQU 3
MINUS_THREE EQU -3
MOV A, # (NOT THREE) + 1
MOV A, #MINUS_THREE
MOV A, #11111101B
Special Operators
.
The sepcial operators are
d
SHR shift right
mit e
SHL shift left
HIGH high-byte
Li
LOW low-byte
() evaluate first
C U
For example, the following two instructions are the same:
M
MOV A, #8 SHL 1
MOV A, #10H
T C
The following two instructions are also the same:
S
MOV A, #HIGH 1234H
MOV A, #12H
Relational Operators
When a relational operator is used between two operands, the result is alwalys false (0000H) or true (FFFFH).
The operators are
EQ = equals
NE < > not equals
LT < less than
LE <= less than or equal to
GT > greater than
GE >= greater than or equal to
Note that for each operator, two forms are acceptable (e.g., "EQ" or "="). In the following examples, all relational
tests are "true":
MOV A, #5 = 5
MOV A,#5 NE 4
MOV A,# 'X' LT 'Z'
MOV A,# 'X' >= 'X'
MOV A,#$ > 0
MOV A,#100 GE 50

So, the assembled instructions are equal to
MOV A, #0FFH
Even though expressions evaluate to 16-bit results (i.e., 0FFFFH), in the examples above only the low-order
eight bits are used, since the instruction is a move byte operation. The result is not considered too big in this case,
because as signed numbers the 16-bit value FFFFH and the 8-bit value FFH are the same (-1).
Expression Examples
The following are examples of expressions and the values that result:
Expression Result
'B' - 'A' 0001H
8/3 0002H
155 MOD 2 0001H
4 * 4 0010H
d .
8 AND 7 0000H
i t e
NOT 1 FFFEH
m
'A' SHL 8 4100H
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LOW 65535 00FFH
(8 + 1) * 2 0012H
5 EQ 4 0000H
C U
'A' LT 'B' FFFFH
3 <= 3 FFFFHss
M
A practical example that illustrates a common operation for timer initialization follows: Put -500 into Timer 1
T C
registers TH1 and TL1. In using the HIGH and LOW operators, a good approach is
S
VALUE EQU -500
MOV TH1, #HIGH VALUE
MOV TL1, #LOW VALUE
The assembler converts -500 to the corresponding 16-bit value (FE0CH); then the HIGH and LOW operators
extract the high (FEH) and low (0CH) bytes. as appropriate for each MOV instruction.
Operator Precedence
The precedence of expression operators from highest to lowest is
()
HIGH LOW
* / MOD SHL SHR
+-
EQ NE LT LE GT GE = < > < <= > >=
NOT
AND
OR XOR
When operators of the same precedence are used, they are evaluated left to right.
Examples:
Expression Value
HIGH ( 'A' SHL 8) 0041H
HIGH 'A' SHL 8 0000H
NOT 'A' - 1 FFBFH
'A' OR 'A' SHL 8 4141H

ASSEMBLER DIRECTIVES
Assembler directives are instructions to the assembler program. They are not assembly language instructions
executable by the target microprocessor. However, they are placed in the mnemonic field of the program. With the
exception of DB and DW, they have no direct effect on the contents of memory.
ASM51 provides several catagories of directives:
Assembler state control (ORG, END, USING)
Symbol definition (SEGMENT, EQU, SET, DATA, IDATA, XDATA, BIT, CODE)
Storage initialization/reservation (DS, DBIT, DB, DW)
Program linkage (PUBLIC, EXTRN,NAME)
Segment selection (RSEG, CSEG, DSEG, ISEG, ESEG, XSEG)
Each assembler directive is presented below, ordered by catagory.
Assembler State Control

ORG (Set Origin)
ed .
The format for the ORG (set origin) directive is
mit
ORG expression
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The ORG directive alters the location counter to set a new program origin for statements that follow. A label is
not permitted. Two examples follow.
ORG 100H ;SET LOCATION COUNTER TO 100H
C U
ORG ($ + 1000H) AND 0F00H ;SET TO NEXT 4K BOUNDARY
M
The ORG directive can be used in any segment type. If the current segment is absolute, the value will be an
absolute address in the current segment. If a relocatable segment is active, the value of the ORG expression is
treated as an offset from the base address of the current instance of the segment.

End
END
S T C
The format of the END directive is
END should be the last statement in the source file. No label is permitted and nothing beyond the END statement
is processed by the assembler.
Using The format of the END directive is

USING expression
This directive informs ASM51 of the currently active register bank. Subsequent uses of the predefined symbolic
register addresses AR0 to AR7 will convert to the appropriate direct address for the active register bank. Consider
the following sequence:
USING 3
PUSH AR7
USING 1
PUSH AR7
The first push above assembles to PUSH 1FH (R7 in bank 3), whereas the second push assembles to PUSH 0FH
(R7 in bank 1).
Note that USING does not actually switch register banks; it only informs ASM51 of the active bank.
Executing 8051 instructions is the only way to switch register banks. This is illustrated by modifying the example
above as follows:

MOV PSW, #00011000B ;SELECT REGISTER BANK 3
USING 3
PUSH AR7 ;ASSEMBLE TO PUSH 1FH
MOV PSW, #00001000B ;SELECT REGISTER BANK 1
USING 1
PUSH AR7 ;ASSEMBLE TO PUSH 0FH
Symbol Definition
The symbol definition directives create symbols that represent segment, registers, numbers, and addresses. None
of these directives may be preceded by a label. Symbols defined by these directives may not have been previously
defined and may not be redefined by any means. The SET directive is the only exception. Symbol definiton
directives are described below.
Segment The format for the SEGMENT directive is shown below.
d .
symbol SEGMENT segment_type
i t e
The symbol is the name of a relocatable segment. In the use of segments, ASM51 is more complex than
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conventional assemblers, which generally support only "code" and "data" segment types. However, ASM51
defines additional segment types to accommodate the diverse memory spaces in the 8051. The following are the
defined 8051 segment types (memory spaces):
C U
CODE (the code segment)
XDATA (the external data space)
M
DATA (the internal data space accessible by direct addressing, 00H07H)
IDATA (the entire internal data space accessible by indirect addressing, 00H07H)
T C
BIT (the bit space; overlapping byte locations 20H2FH of the internal data space)
EPROM
S
For example, the statement
SEGMENT CODE
declares the symbol EPROM to be a SEGMENT of type CODE. Note that this statement simply declares what
EPROM is. To actually begin using this segment, the RSEG directive is used (see below).
EQU (Equate) The format for the EQU directive is

Symbol EQU expression
The EQU directive assigns a numeric value to a specified symbol name. The symbol must be a valid symbol
name, and the expression must conform to the rules described earlier.
The following are examples of the EQU directive:
N27 EQU 27 ;SET N27 TO THE VALUE 27
HERE EQU $ ;SET "HERE" TO THE VALUE OF
;THE LOCATION COUNTER
CR EQU 0DH ;SET CR (CARRIAGE RETURN) TO 0DH
MESSAGE: DB 'This is a message'
LENGTH EQU $ - MESSAGE ;"LENGTH" EQUALS LENGTH OF "MESSAGE"
Other Symbol Definition Directives The SET directive is similar to the EQU directive except the
symbol may be redefined later, using another SET directive.

The DATA, IDATA, XDATA, BIT, and CODE directives assign addresses of the corresponding segment
type to a symbol. These directives are not essential. A similar effect can be achieved using the EQU directive; if
used, however, they evoke powerful type-checking by ASM51. Consider the following two directives and four
instructions:
FLAG1 EQU 05H
FLAG2 BIT 05H
SETB FLAG1
SETB FLAG2
MOV FLAG1, #0
MOV FLAG2, #0
The use of FLAG2 in the last instruction in this sequence will generate a "data segment address expected" error
message from ASM51. Since FLAG2 is defined as a bit address (using the BIT directive), it can be used in a set
bit instruction, but it cannot be used in a move byte instruction. Hence, the error. Even though FLAG1 represents
d .
the same value (05H), it was defined using EQU and does not have an associated address space. This is not an
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advantage of EQU, but rather, a disadvantage. By properly defining address symbols for use in a specific memory
space (using the directives BIT, DATA, XDATA,ect.), the programmer takes advantage of ASM51's powerful
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type-checking and avoids bugs from the misuse of symbols.
Storage Initialization/Reservation
C U
The storage initialization and reservation directives initialize and reserve space in either word, byte, or bit units.
M
The space reserved starts at the location indicated by the current value of the location counter in the currently
active segment. These directives may be preceded by a label. The storage initialization/reservation directives are
described below.
[label:]
T C
DS (Define Storage)
S
The format for the DS (define storage) directive is
DS expression
The DS directive reserves space in byte units. It can be used in any segment type except BIT. The expression
must be a valid assemble-time expression with no forward references and no relocatable or external references.
When a DS statement is encountered in a program, the location counter of the current segment is incremented by
the value of the expression. The sum of the location counter and the specified expression should not exceed the
limitations of the current address space.
The following statement create a 40-byte buffer in the internal data segment:
DSEG AT 30H ;PUT IN DATA SEGMENT (ABSOLUTE, INTERNAL)
LENGTH EQU 40
BUFFER: DS LENGRH ;40 BYTES RESERVED
The label BUFFER represents the address of the first location of reserved memory. For this example, the buffer
begins at address 30H because "AT 30H" is specified with DSEG. The buffer could be cleared using the following
instruction sequence:
MOV R7, #LENGTH
MOV R0, #BUFFER
LOOP: MOV @R0, #0
DJNZ R7, LOOP
(continue)

To create a 1000-byte buffer in external RAM starting at 4000H, the following directives could be used:
XSTART EQU 4000H
XLENGTH EQU 1000
XSEG AT XSTART
XBUFFER: DS XLENGTH
This buffer could be cleared with the following instruction sequence:
MOV DPTR, #XBUFFER
LOOP: CLR A
MOVX @DPTR, A
INC DPTR
MOV A, DPL
CJNE A, #LOW (XBUFFER + XLENGTH + 1), LOOP
.
MOV A, DPH
ed
CJNE A, #HIGH (XBUFFER + XLENGTH + 1), LOOP
i t
(continue)
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This is an excellent example of a powerful use of ASM51's operators and assemble-time expressions. Since an
instruction does not exist to compare the data pointer with an immediate value, the operation must be fabricated
from available instructions. Two compares are required, one each for the high- and low-bytes of the DPTR.
U
Furthermore, the compare-and-jump-if-not-equal instruction works only with the accumulator or a register, so
C
the data pointer bytes must be moved into the accumulator before the CJNE instruction. The loop terminates only
M
when the data pointer has reached XBUFFER + LENGTH + 1. (The "+1" is needed because the data pointer is
incremented after the last MOVX instruction.)

DBIT
S T C
The format for the DBIT (define bit) directive is,
[label:] DBIT expression
The DBIT directive reserves space in bit units. It can be used only in a BIT segment. The expression must be
a valid assemble-time expression with no forward references. When the DBIT statement is encountered in a
program, the location counter of the current (BIT) segment is incremented by the value of the expression. Note
that in a BIT segment, the basic unit of the location counter is bits rather than bytes. The following directives
creat three flags in a absolute bit segment:
BSEG ;BIT SEGMENT (ABSOLUTE)
KEFLAG: DBIT 1 ;KEYBOARD STATUS
PRFLAG: DBIT 1 ;PRINTER STATUS
DKFLAG: DBIT 1 ;DISK STATUS
Since an address is not specified with BSEG in the example above, the address of the flags defined by DBIT could
be determined (if one wishes to to so) by examining the symbol table in the .LST or .M51 files. If the definitions
above were the first use of BSEG, then KBFLAG would be at bit address 00H (bit 0 of byte address 20H). If other
bits were defined previously using BSEG, then the definitions above would follow the last bit defined.
DB (Define Byte) The format for the DB (define byte) directive is,
[label:] DB expression [, expression] []
The DB directive initializes code memory with byte values. Since it is used to actually place data constants in
code memory, a CODE segment must be active. The expression list is a series of one or more byte values (each of
which may be an expression) separated by commas.

The DB directive permits character strings (enclosed in single quotes) longer than two characters as long as they
are not part of an expression. Each character in the string is converted to the corresponding ASCII code. If a label
is used, it is assigned the address of th first byte. For example, the following statements
CSEG AT 0100H
SQUARES: DB 0, 1, 4, 9, 16, 25 ;SQUARES OF NUMBERS 0-5
MESSAGE: DB 'Login:', 0 ;NULL-TERMINATED CHARACTER STRING
When assembled, result in the following hexadecimal memory assignments for external code memory:
Address Contents
0100 00
0101 01
0102 04
0103 09
.
0104 10
d
0105 19
mit e
0106 4C
0107 6F
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0108 67
0109 69
U
010A 6E
C
010B 3A
M
010C 00
DW (Define Word) The format for the DW (define word) directive is

[label:]
S T C DW expression [, expression] []
The DW directive is the same as the DB directive except two memory locations (16 bits) are assigned for each
data item. For example, the statements
CSEG AT 200H
DW $, 'A', 1234H, 2, 'BC'
result in the following hexadecimal memory assignments:
Address Contents
0200 02
0201 00
0202 00
0203 41
0204 12
0205 34
0206 00
0207 02
0208 42
0209 43
Program Linkage
Program linkage directives allow the separately assembled modules (files) to communicate by permitting
intermodule references and the naming of modules. In the following discussion, a "module" can be considered a
"file." (In fact, a module may encompass more than one file.)

Public The format for the PUBLIC (public symbol) directive is

PUBLIC symbol [, symbol] []
The PUBLIC directive allows the list of specified symbols to known and used outside the currently assembled
module. A symbol declared PUBLIC must be defined in the current module. Declaring it PUBLIC allows it to be
referenced in another module. For example,
PUBLIC INCHAR, OUTCHR, INLINE, OUTSTR
Extrn The format for the EXTRN (external symbol) directive is

EXTRN segment_type (symbol [, symbol] [], )
The EXTRN directive lists symbols to be referenced in the current module that are defined in other modules. The
list of external symbols must have a segment type associated with each symbol in the list. (The segment types
are CODE, XDATA, DATA, IDATA, BIT, and NUMBER. NUMBER is a type-less symbol defined by EQU.)
d .
The segment type indicates the way a symbol may be used. The information is important at link-time to ensure
t e
symbols are used properly in different modules.
i
The PUBLIC and EXTRN directives work together. Consider the two files, MAIN.SRC and MESSAGES.
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SRC. The subroutines HELLO and GOOD_BYE are defined in the module MESSAGES but are made available
to other modules using the PUBLIC directive. The subroutines are called in the module MAIN even though they
are not defined there. The EXTRN directive declares that these symbols are defined in another module.
MAIN.SRC:
C U
M
EXTRN CODE (HELLO, GOOD_BYE)

C
CALL HELLO
S
CALL GOOD_BYE

END
MESSAGES.SRC:
PUBLIC HELLO, GOOD_BYE

HELLO: (begin subroutine)

RET
GOOD_BYE: (begin subroutine)

RET

END
Neither MAIN.SRC nor MESSAGES.SRC is a complete program; they must be assembled separately and
linked together to form an executable program. During linking, the external references are resolved with correct
addresses inserted as the destination for the CALL instructions.
Name The format for the NAME directive is

NAME module_name

All the usual rules for symbol names apply to module names. If a name is not provided, the module takes on
the file name (without a drive or subdirectory specifier and without an extension). In the absence of any use
of the NAME directive, a program will contain one module for each file. The concept of "modules," therefore,
is somewhat cumbersome, at least for relatively small programming problems. Even programs of moderate
size (encompassing, for example, several files complete with relocatable segments) needn't use the NAME
directive and needn't pay any special attention to the concept of "modules." For this reason, it was mentioned in
the definition that a module may be considered a "file," to simplify learning ASM51. However, for very large
programs (several thousand lines of code, or more), it makes sense to partition the problem into modules, where,
for example, each module may encompass several files containing routines having a common purpose.
Segment Selection Directives

When the assembler encounters a segment selection directive, it diverts the following code or data into the
selected segment until another segment is selected by a segment selection directive. The directive may select may
.
select a previously defined relocatable segment or optionally create and select absolute segments.
ed
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RSEG (Relocatable Segment) The format for the RSEG (relocatable segment) directive is
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RSEG segment_name
Where "segment_name" is the name of a relocatable segment previously defined with the SEGMENT directive.
RSEG is a "segment selection" directive that diverts subsequent code or data into the named segment until another
U
segment selection directive is encountered.
Selecting Absolute Segments
M C
RSEG selects a relocatable segment. An "absolute" segment, on the other
hand, is selected using one of the directives:

CSEG
DSEG
ISEG
BSEG S T C
(AT
(AT
(AT
(AT
address)
address)
address)
address)
XSEG (AT address)
These directives select an absolute segment within the code, internal data, indirect internal data, bit, or external
data address spaces, respectively. If an absolute address is provided (by indicating "AT address"), the assembler
terminates the last absolute address segment, if any, of the specified segment type and creates a new absolute
segment starting at that address. If an absolute address is not specified, the last absolute segment of the specified
type is continuted. If no absolute segment of this type was previously selected and the absolute address is omitted,
a new segment is created starting at location 0. Forward references are not allowed and start addresses must be
absolute.
Each segment has its own location counter, which is always set to 0 initially. The default segment is an
absolute code segment; therefore, the initial state of the assembler is location 0000H in the absolute code segment.
When another segment is chosen for the first time, the location counter of the former segment retains the last
active value. When that former segment is reselected, the location counter picks up at the last active value. The
ORG directive may be used to change the location counter within the currently selected segment.
ASSEMBLER CONTROLS
Assembler controls establish the format of the listing and object files by regulating the actions of ASM51. For the
most part, assembler controls affect the look of the listing file, without having any affect on the program itself.
They can be entered on the invocation line when a program is assembled, or they can be placed in the source file.
Assembler controls appearing in the source file must be preceded with a dollor sign and must begin in column 1.

There are two categories of assembler controls: primary and general. Primary controls can be placed in the
invocation line or at the beginnig of the source program. Only other primary controls may precede a primary
control. General controls may be placed anywhere in the source program.
LINKER OPERATION
In developing large application programs, it is common to divide tasks into subprograms or modules containing
sections of code (usually subroutines) that can be written separately from the overall program. The term "modular
programming" refers to this programming strategy. Generally, modules are relocatable, meaning they are not
intended for a specific address in the code or data space. A linking and locating program is needed to combine the
modules into one absolute object module that can be executed.
Intel's RL51 is a typical linker/locator. It processes a series of relocatable object modules as input and creates
an executable machine language program (PROGRAM, perhaps) and a listing file containing a memory map and
symbol table (PROGRAM.M51). This is illustrated in following figure.
t ed .
m i
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FILE3.OBJ PROGRAM.ABS
FILE2.OBJ
U
FILE1.OBJ RL51
Legend
M C PROGRAM.MAP
C
Utility program
S T
User file
Linker operation
As relocatable modules are combined, all values for external symbols are resolved with values inserted into
the output file. The linker is invoked from the system prompt by
RL51 input_list [T0 output_file] [location_controls]
The input_list is a list of relocatable object modules (files) separated by commas. The output_list is the name
of the output absolute object module. If none is supplied, it defaults to the name of the first input file without any
suffix. The location_controls set start addresses for the named segments.
For example, suppose three modules or files (MAIN.OBJ, MESSAGES.OBJ, and SUBROUTINES.OBJ) are
to be combined into an executable program (EXAMPLE), and that these modules each contain two relocatable
segments, one called EPROM of type CODE, and the other called ONCHIP of type DATA. Suppose further that
the code segment is to be executable at address 4000H and the data segment is to reside starting at address 30H (in
internal RAM). The following linker invocation could be used:
RS51 MAIN.OBJ, MESSAGES.OBJ, SUBROUTINES.OBJ TO EXAMPLE & CODE
(EPROM (4000H) DATA (ONCHIP (30H))
Note that the ampersand character "&" is used as the line continuaton character.
If the program begins at the label START, and this is the first instruction in the MAIN module, then
execution begins at address 4000H. If the MAIN module was not linked first, or if the label START is not at the
beginning of MAIN, then the program's entry point can be determined by examining the symbol table in the
listing file EXAMPLE.M51 created by RL51. By default, EXAMPLE.M51 will contain only the link map. If
a symbol table is desired, then each source program must have used the SDEBUG control. The following table
shows the assembler controls supported by ASM51.

Assembler controls supported by ASM51
PRIMARY/
NAME GENERAL DEFAULT ABBREV. MEANING
DATE (date) P DATE( ) DAPlace string in header (9 char. max.)
DEBUG P NODEBUG DBOutputs debug symbol information to object file
EJECT G not applicable EJContinue listing on next page
ERRORPRINT P NOERRORPRINT EPDesignates a file to receive error messages in addition to the
(file) listing file (defauts to console)
NOERRORPRINT P NOERRORPRINT NOEP Designates that error messages will be printed in listing file
only
GEN G GENONLY GO List only the fully expanded source as if all lines generated
by a macro call were already in the source file
GENONLY G GENONLY NOGE List only the original source text in the listing file
INCLUED(file) G not applicable IC Designates a file to be included as part of the program
.
LIST G LIST LI Print subsequent lines of source code in listing file
ed
NOLIST G LIST NOLI Do not print subsequent lines of source code in lisitng file
mit
MACRO P MACRO(50) MR Evaluate and expand all macro calls. Allocate percentage of
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(men_precent) free memory for macro processing
NOMACRO P MACRO(50) NOMR Do not evalutate macro calls
MOD51 P MOD51 MO Recognize the 8051-specific predefined special function
U
registers
C
NOMOD51 P MOD51 NOMO Do not recognize the 8051-specific predefined special
M
function registers
OBJECT(file) P OBJECT(source.OBJ) OJ Designates file to receive object code
NOOBJECT P OBJECT(source.OBJ) NOOJ Designates that no object file will be created
T C
PAGING P PAGING PI Designates that listing file be broken into pages and each
S
will have a header
NOPAGING P PAGING NOPI Designates that listing file will contain no page breaks
PAGELENGTH P PAGELENGT(60) PL Sets maximun number of lines in each page of listing file
(N) (range=10 to 65536)
PAGE WIDTH (N) P PAGEWIDTH(120) PW Set maximum number of characters in each line of listing
file (range = 72 to 132)
PRINT(file) P PRINT(source.LST) PR Designates file to receive source listing
NOPRINT P PRINT(source.LST) NOPR Designates that no listing file will be created
SAVE G not applicable SA Stores current control settings from SAVE stack
RESTORE G not applicable RS Restores control settings from SAVE stack
REGISTERBANK P REGISTERBANK(0) RB Indicates one or more banks used in program module
(rb,...)
NOREGISTER- P REGISTERBANK(0) NORB Indicates that no register banks are used
BANK
SYMBOLS P SYMBOLS SB Creates a formatted table of all symbols used in program
NOSYMBOLS P SYMBOLS NOSB Designates that no symbol table is created
TITLE(string) G TITLE( ) TT Places a string in all subsequent page headers (max.60
characters)
WORKFILES P same as source WF Designates alternate path for temporay workfiles
(path)
XREF P NOXREF XR Creates a cross reference listing of all symbols used in
program
NOXREF P NOXREF NOXR Designates that no cross reference list is created

MACROS
The macro processing facility (MPL) of ASM51 is a "string replacement" facility. Macros allow frequently used
sections of code be defined once using a simple mnemonic and used anywhere in the program by inserting the
mnemonic. Programming using macros is a powerful extension of the techniques described thus far. Macros can
be defined anywhere in a source program and subsequently used like any other instruction. The syntax for macro
definition is
%*DEFINE (call_pattern) (macro_body)
Once defined, the call pattern is like a mnemonic; it may be used like any assembly language instruction by
placing it in the mnemonic field of a program. Macros are made distinct from "real" instructions by preceding
them with a percent sign, "%". When the source program is assembled, everything within the macro-body, on
a character-by-character basis, is substituted for the call-pattern. The mystique of macros is largely unfounded.
They provide a simple means for replacing cumbersome instruction patterns with primitive, easy-to-remember
.
mnemonics. The substitution, we reiterate, is on a character-by-character basisnothing more, nothing less.
ed
For example, if the following macro definition appears at the beginning of a source file,
%*DEFINE (PUSH_DPTR)
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(PUSH DPH
PUSH DPL
)
then the statement
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M
%PUSH_DPTR
will appear in the .LST file as

PUSH
PUSH
S T
DPH
DPL
C
The example above is a typical macro. Since the 8051 stack instructions operate only on direct addresses,
pushing the data pointer requires two PUSH instructions. A similar macro can be created to POP the data pointer.
There are several distinct advantages in using macros:
A source program using macros is more readable, since the macro mnemonic is generally more indicative
of the intended operation than the equivalent assembler instructions.
The source program is shorter and requires less typing.
Using macros reduces bugs
Using macros frees the programmer from dealing with low-level details.
The last two points above are related. Once a macro is written and debugged, it is used freely without the worry
of bugs. In the PUSH_DPTR example above, if PUSH and POP instructions are used rather than push and pop
macros, the programmer may inadvertently reverse the order of the pushes or pops. (Was it the high-byte or low-
byte that was pushed first?) This would create a bug. Using macros, however, the details are worked out once
when the macro is writtenand the macro is used freely thereafter, without the worry of bugs.
Since the replacement is on a character-by-character basis, the macro definition should be carefully
constructed with carriage returns, tabs, ect., to ensure proper alignment of the macro statements with the rest of
the assembly language program. Some trial and error is required.
There are advanced features of ASM51's macro-processing facility that allow for parameter passing, local
labels, repeat operations, assembly flow control, and so on. These are discussed below.

Parameter Passing
A macro with parameters passed from the main program has the following modified format:
%*DEFINE (macro_name (parameter_list)) (macro_body)
For example, if the following macro is defined,
%*DEFINE (CMPA# (VALUE))
(CJNE A, #%VALUE, $ + 3
)
then the macro call
%CMPA# (20H)
will expand to the following instruction in the .LST file:
CJNE A, #20H, $ + 3
d .
Although the 8051 does not have a "compare accumulator" instruction, one is easily created using the CJNE
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instruction with "$+3" (the next instruction) as the destination for the conditional jump. The CMPA# mnemonic
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may be easier to remember for many programmers. Besides, use of the macro unburdens the programmer from
remembering notational details, such as "$+3."
Let's develop another example. It would be nice if the 8051 had instructions such as
U
JUMP IF ACCUMULATOR GREATER THAN X
C
JUMP IF ACCUMULATOR GREATER THAN OR EQUAL TO X
M
JUMP IF ACCUMULATOR LESS THAN X
JUMP IF ACCUMULATOR LESS THAN OR EQUAL TO X
C
but it does not. These operations can be created using CJNE followed by JC or JNC, but the details are tricky.
S T
Suppose, for example, it is desired to jump to the label GREATER_THAN if the accumulator contains an ASCII
code greater than "Z" (5AH). The following instruction sequence would work:
CJNE A, #5BH, $3
JNC GREATER_THAN
The CJNE instruction subtracts 5BH (i.e., "Z" + 1) from the content of A and sets or clears the carry flag
accordingly. CJNE leaves C=1 for accumulator values 00H up to and including 5AH. (Note: 5AH-5BH<0,
therefore C=1; but 5BH-5BH=0, therefore C=0.) Jumping to GREATER_THAN on the condition "not carry"
correctly jumps for accumulator values 5BH, 5CH, 5DH, and so on, up to FFH. Once details such as these are
worked out, they can be simplified by inventing an appropriate mnemonic, defining a macro, and using the macro
instead of the corresponding instruction sequence. Here's the definition for a "jump if greater than" macro:
%*DEFINE (JGT (VALUE, LABEL))
(CJNE A, #%VALUE+1, $+3 ;JGT
JNC %LABEL
)
To test if the accumulator contains an ASCII code greater than "Z," as just discussed,the macro would be called as
%JGT ('Z', GREATER_THAN)
ASM51 would expand this into
CJNE A, #5BH, $+3 ;JGT
JNC GREATER_THAN
The JGT macro is an excellent example of a relevant and powerful use of macros. By using macros, the
programmer benefits by using a meaningful mnemonic and avoiding messy and potentially bug-ridden details.
Local Labels
Local labels may be used within a macro using the following format:
%*DEFINE (macro_name [(parameter_list)])
[LOCAL list_of_local_labels] (macro_body)
For example, the following macro definition
%*DEFINE (DEC_DPTR) LOCAL SKIP
(DEC DPL ;DECREMENT DATA POINTER
MOV A, DPL
CJNE A, #0FFH, %SKIP
DEC DPL
%SKIP: )
would be called as
%DEC_DPTR
t ed .
i
and would be expanded by ASM51 into

DEC
MOV
CJNE
DPL
A, DPL
A, #0FFH, SKIP00
Li
;DECREMENT DATA POINTER
m
DEC DPH
C U
M
SKIP00:
Note that a local label generally will not conflict with the same label used elsewhere in the source program, since
C
ASM51 appends a numeric code to the local label when the macro is expanded. Furthermore, the next use of the
T
same local label receives the next numeric code, and so on.
S
The macro above has a potential "side effect." The accumulator is used as a temporary holding place for
DPL. If the macro is used within a section of code that uses A for another purpose, the value in A would be lost.
This side effect probably represents a bug in the program. The macro definition could guard against this by saving
A on the stack. Here's an alternate definition for the DEC_DPTR macro:
%*DEFINE (DEC_DPTR) LOCAL SKIP
(PUSHACC
DEC DPL ;DECREMENT DATA POINTER
MOV A, DPL
CJNE A, #0FFH, %SKIP
DEC DPH
%SKIP: POP ACC
)
Repeat Operations
This is one of several built-in (predefined) macros. The format is
%REPEAT (expression) (text)
For example, to fill a block of memory with 100 NOP instructions,
%REPEAT (100)
(NOP
)

Control Flow Operations

The conditional assembly of section of code is provided by ASM51's control flow macro definition. The format is
%IF (expression) THEN (balanced_text)
[ELSE (balanced_text)] FI
For example,
INTRENAL EQU 1 ;1 = 8051 SERIAL I/O DRIVERS
;0 = 8251 SERIAL I/O DRIVERS
.
.
%IF (INTERNAL) THEN
(INCHAR: . ;8051 DRIVERS
.
.
OUTCHR: .
ed
.
mit
) ELSE
Li
(INCHAR: . ;8251 DRIVERS
.
OUTCHR: .
U
.
C
)
M
In this example, the symbol INTERNAL is given the value 1 to select I/O subroutines for the 8051's serial port,
or the value 0 to select I/O subroutines for an external UART, in this case the 8251. The IF macro causes ASM51
C
to assemble one set of drivers and skip over the other. Elsewhere in the program, the INCHAR and OUTCHR
S T
subroutines are used without consideration for the particular hardware configuration. As long as the program as
assembled with the correct value for INTERNAL, the correct subroutine is executed.

Appendix B: 8051 C Programming

ADVANTAGES AND DISADVANTAGES OF 8051 C
The advantages of programming the 8051 in C as compared to assembly are:
Offers all the benefits of high-level, structured programming languages such as C, including the ease of
writing subroutines
Often relieves the programmer of the hardware details that the complier handles on behalf of the
programmer
Easier to write, especially for large and complex programs
Produces more readable program source codes
Nevertheless, 8051 C, being very similar to the conventional C language, also suffers from the following
disadvantages:
d .
Processes the disadvantages of high-level, structured programming languages.
i t e
Generally generates larger machine codes
m
Programmer has less control and less ability to directly interact with hardware
Li
To compare between 8051 C and assembly language, consider the solutions to the ExampleWrite a program
using Timer 0 to create a 1KHz square wave on P1.0.
U
A solution written below in 8051 C language:
C
sbit portbit = P1^0; /*Use variable portbit to refer to P1.0*/
M
main ( )
{
C
TMOD = 1;
S T
while (1)
{
TH0 = 0xFE;
TL0 = 0xC;
TR0 = 1;
while (TF0 !=1);
TR0 = 0;
TF0 = 0;
portbit = !(P1.^0);
}
}
A solution written below in assembly language:
ORG 8100H
MOV TMOD, #01H ;16-bit timer mode
LOOP: MOV TH0, #0FEH ;-500 (high byte)
MOV TL0, #0CH ;-500 (low byte)
SETB TR0 ;start timer
WAIT: JNB TF0, WAIT ;wait for overflow
CLR TR0 ;stop timer
CLR TF0 ;clear timer overflow flag
CPL P1.0 ;toggle port bit
SJMP LOOP ;repeat
END

Notice that both the assembly and C language solutions for the above example require almost the same number
of lines. However, the difference lies in the readability of these programs. The C version seems more human than
assembly, and is hence more readable. This often helps facilitate the human programmer's efforts to write even
very complex programs. The assembly language version is more closely related to the machine code, and though
less readable, often results in more compact machine code. As with this example, the resultant machine code from
the assembly version takes 83 bytes while that of the C version requires 149 bytes, an increase of 79.5%!
The human programmer's choice of either high-level C language or assembly language for talking to the
8051, whose language is machine language, presents an interesting picture, as shown in following figure.
Human language C (high-level) language

Eg. English, Malay, Chinese Eg. for (x=0; x<9; x++)...
.
Complier
ed
mit
Assembly language
Li
Eg. MOV, ADD, SUB
Machine language
Eg. 10011101 0101010101 Assembler
C U
M
Conversion between human, high-level, assembly, and machine language
8051 C COMPILERS
T C
We saw in the above figure that a complier is needed to convert programs written in 8051 C language into
S
machine language, just as an assembler is needed in the case of programs written in assembly language. A
complier basically acts just like an assembler, except that it is more complex since the difference between C and
machine language is far greater than that between assembly and machine language. Hence the complier faces a
greater task to bridge that difference.
Currently, there exist various 8051 C complier, which offer almost similar functions. All our examples
and programs have been compiled and tested with Keil's Vision 2 IDE by Keil Software, an integrated 8051
program development envrionment that includes its C51 cross compiler for C. A cross compiler is a compiler that
normally runs on a platform such as IBM compatible PCs but is meant to compile programs into codes to be run
on other platforms such as the 8051.
DATA TYPES
8051 C is very much like the conventional C language, except that several extensions and adaptations have been
made to make it suitable for the 8051 programming environment. The first concern for the 8051 C programmer is
the data types. Recall that a data type is something we use to store data. Readers will be familiar with the basic C
data types such as int, char, and float, which are used to create variables to store integers, characters, or floating-
points. In 8051 C, all the basic C data types are supported, plus a few additional data types meant to be used
specifically with the 8051.
The following table gives a list of the common data types used in 8051 C. The ones in bold are the specific
8051 extensions. The data type bit can be used to declare variables that reside in the 8051's bit-addressable
locations (namely byte locations 20H to 2FH or bit locations 00H to 7FH). Obviously, these bit variables can only
store bit values of either 0 or 1. As an example, the following C statement:
bit flag = 0;
declares a bit variable called flag and initializes it to 0.
Data types used in 8051 C language
Data Type Bits Bytes Value Range
bit 1 0 to 1
signed char 8 1 -128 to +127
unsigned char 8 1 0 to 255
enum 16 2 -32768 to +32767
signed short 16 2 -32768 to +32767
unsigned short 16 2 0 to 65535
signed int 16 2 -32768 to +32767
unsigned int 16 2 0 to 65535
signed long 32 4 -2,147,483,648 to +2,147,483,647
unsigned long 32 4 0 to 4,294,967,295
.
float 32 4 1.175494E-38 to 3.402823E+38
ed
sbit 1 0 to 1
sfr 8 1 0 to 255
m i t
Li
sfr16 16 2 0 to 65535
The data type sbit is somewhat similar to the bit data type, except that it is normally used to declare 1-bit
C U
variables that reside in special function registes (SFRs). For example:
M
sbit P = 0xD0;
declares the sbit variable P and specifies that it refers to bit address D0H, which is really the LSB of the PSW
T C
SFR. Notice the difference here in the usage of the assignment ("=") operator. In the context of sbit declarations,
S
it indicatess what address the sbit variable resides in, while in bit declarations, it is used to specify the initial
value of the bit variable.
Besides directly assigning a bit address to an sbit variable, we could also use a previously defined sfr
variable as the base address and assign our sbit variable to refer to a certain bit within that sfr. For example:
sfr PSW = 0xD0;
sbit P = PSW^0;
This declares an sfr variable called PSW that refers to the byte address D0H and then uses it as the base address
to refer to its LSB (bit 0). This is then assigned to an sbit variable, P. For this purpose, the carat symbol (^) is used
to specify bit position 0 of the PSW.
A third alternative uses a constant byte address as the base address within which a certain bit is referred. As
an illustration, the previous two statements can be replaced with the following:
sbit P = 0xD0 ^ 0;
Meanwhile, the sfr data type is used to declare byte (8-bit) variables that are associated with SFRs. The
statement:
sfr IE = 0xA8;
declares an sfr variable IE that resides at byte address A8H. Recall that this address is where the Interrupt Enable
(IE) SFR is located; therefore, the sfr data type is just a means to enable us to assign names for SFRs so that it is
easier to remember.
The sfr16 data type is very similar to sfr but, while the sfr data type is used for 8-bit SFRs, sfr16 is used for
16-bit SFRs. For example, the following statement:
sfr16 DPTR = 0x82;

declares a 16-bit variable DPTR whose lower-byte address is at 82H. Checking through the 8051 architecture,
we find that this is the address of the DPL SFR, so again, the sfr16 data type makes it easier for us to refer to
the SFRs by name rather than address. There's just one thing left to mention. When declaring sbit, sfr, or sfr16
variables, remember to do so outside main, otherwise you will get an error.
In actual fact though, all the SFRs in the 8051, including the individual flag, status, and control bits in the
bit-addressable SFRs have already been declared in an include file, called reg51.h, which comes packaged with
most 8051 C compilers. By using reg51.h, we can refer for instance to the interrupt enable register as simply IE
rather than having to specify the address A8H, and to the data pointer as DPTR rather than 82H. All this makes
8051 C programs more human-readable and manageable. The contents of reg51.h are listed below.
/*--------------------------------------------------------------------------------------------------------------------
REG51.H
Header file for generic 8051 microcontroller.
-----------------------------------------------------------------------------------------------------------------------*/
.
/* BYTE Register */ sbit IE1 = 0x8B;
ed
sfr P0 = 0x80; sbit IT1 = 0x8A;
mit
sfr P1 = 0x90; sbit IE0 = 0x89;
Li
sfr P2 = 0xA0; sbit IT0 = 0x88;
sfr P3 = 0xB0; /* IE */
sfr PSW = 0xD0; sbit EA = 0xAF;
U
sfr ACC = 0xE0; sbit ES = 0xAC;
C
sfr B = 0xF0; sbit ET1 = 0xAB;
M
sfr SP = 0x81; sbit EX1 = 0xAA;
sfr DPL = 0x82; sbit ET0 = 0xA9;
sfr DPH = 0x83; sbit EX0 = 0xA8;
T C
sfr PCON = 0x87; /* IP */
S
sfr TCON = 0x88; sbit PS = 0xBC;
sfr TMOD = 0x89; sbit PT1 = 0xBB;
sfr TL0 = 0x8A; sbit PX1 = 0xBA;
sfr TL1 = 0x8B; sbit PT0 = 0xB9;
sfr TH0 = 0x8C; sbit PX0 = 0xB8;
sfr TH1 = 0x8D; /* P3 */
sfr IE = 0xA8; sbit RD = 0xB7;
sfr IP = 0xB8; sbit WR = 0xB6;
sfr SCON = 0x98; sbit T1 = 0xB5;
sfr SBUF = 0x99; sbit T0 = 0xB4;
/* BIT Register */ sbit INT1 = 0xB3;
/* PSW */ sbit INT0 = 0xB2;
sbit CY = 0xD7; sbit TXD = 0xB1;
sbit AC = 0xD6; sbit RXD = 0xB0;
sbit F0 = 0xD5; /* SCON */
sbit RS1 = 0xD4; sbit SM0 = 0x9F;
sbit RS0 = 0xD3; sbit SM1 = 0x9E;
sbit OV = 0xD2; sbit SM2 = 0x9D;
sbit P = 0xD0; sbit REN = 0x9C;
/* TCON */ sbit TB8 = 0x9B;
sbit TF1 = 0x8F; sbit RB8 = 0x9A;
sbit TR1 = 0x8E; sbit TI = 0x99;
sbit TF0 = 0x8D; sbit RI = 0x98;
sbit TR0 = 0x8C;
MEMORY TYPES AND MODELS

The 8051 has various types of memory space, including internal and external code and data memory. When
declaring variables, it is hence reasonable to wonder in which type of memory those variables would reside. For
this purpose, several memory type specifiers are available for use, as shown in following table.
Memory types used in 8051 C language

Memory Type Description (Size)
code Code memory (64 Kbytes)
data Directly addressable internal data memory (128 bytes)
idata Indirectly addressable internal data memory (256 bytes)
bdata Bit-addressable internal data memory (16 bytes)
xdata External data memory (64 Kbytes)
.
pdata Paged external data memory (256 bytes)
i t ed
The first memory type specifier given in above table is code. This is used to specify that a variable is to reside in
m
code memory, which has a range of up to 64 Kbytes. For example:
Li
char code errormsg[ ] = "An error occurred" ;
declares a char array called errormsg that resides in code memory.
C U
If you want to put a variable into data memory, then use either of the remaining five data memory specifiers
in above table. Though the choice rests on you, bear in mind that each type of data memory affect the speed of
M
access and the size of available data memory. For instance, consider the following declarations:
C
signed int data num1;
T
bit bdata numbit;
S
unsigned int xdata num2;
The first statement creates a signed int variable num1 that resides in inernal data memory (00H to 7FH). The next
line declares a bit variable numbit that is to reside in the bit-addressable memory locations (byte addresses 20H
to 2FH), also known as bdata. Finally, the last line declares an unsigned int variable called num2 that resides in
external data memory, xdata. Having a variable located in the directly addressable internal data memory speeds
up access considerably; hence, for programs that are time-critical, the variables should be of type data. For other
variants such as 8052 with internal data memory up to 256 bytes, the idata specifier may be used. Note however
that this is slower than data since it must use indirect addressing. Meanwhile, if you would rather have your
variables reside in external memory, you have the choice of declaring them as pdata or xdata. A variable declared
to be in pdata resides in the first 256 bytes (a page) of external memory, while if more storage is required, xdata
should be used, which allows for accessing up to 64 Kbytes of external data memory.
What if when declaring a variable you forget to explicitly specify what type of memory it should reside in, or
you wish that all variables are assigned a default memory type without having to specify them one by one? In this
case, we make use of memory models. The following table lists the various memory models that you can use.
Memory models used in 8051 C language

Memory Model Description
Small Variables default to the internal data memory (data)
Compact Variables default to the first 256 bytes of external data memory (pdata)
Large Variables default to external data memory (xdata)

A program is explicitly selected to be in a certain memory model by using the C directive, #pragma. Otherwise,
the default memory model is small. It is recommended that programs use the small memory model as it allows for
the fastest possible access by defaulting all variables to reside in internal data memory.
The compact memory model causes all variables to default to the first page of external data memory while
the large memory model causes all variables to default to the full external data memory range of up to 64 Kbytes.
ARRAYS
Often, a group of variables used to store data of the same type need to be grouped together for better readability.
For example, the ASCII table for decimal digits would be as shown below.
ASCII table for decimal digits

Decimal Digit ASCII Code In Hex
0 30H
.
1 31H
ed
mit
2 32H
3 33H
Li
4 34H
5 35H
U
6 36H
C
7 37H
M
8 38H
9 39H
T C
To store such a table in an 8051 C program, an array could be used. An array is a group of variables of the same
S
data type, all of which could be accessed by using the name of the arrary along with an appropriate index.

The array to store the decimal ASCII table is:
int table [10] =
{0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39};
Notice that all the elements of an array are separated by commas. To access an individul element, an index
starting from 0 is used. For instance, table[0] refers to the first element while table[9] refers to the last element in
this ASCII table.
STRUCTURES
Sometime it is also desired that variables of different data types but which are related to each other in some way
be grouped together. For example, the name, age, and date of birth of a person would be stored in different types
of variables, but all refer to the person's personal details. In such a case, a structure can be declared. A structure is
a group of related variables that could be of different data types. Such a structure is declared by:
struct person {
char name;
int age;
long DOB;
};
Once such a structure has been declared, it can be used like a data type specifier to create structure variables that
have the member's name, age, and DOB. For example:
struct person grace = {"Grace", 22, 01311980};

would create a structure variable grace to store the name, age, and data of birth of a person called Grace. Then in
order to access the specific members within the person structure variable, use the variable name followed by the
dot operator (.) and the member name. Therefore, grace.name, grace.age, grace.DOB would refer to Grace's name,
age, and data of birth, respectively.
POINTERS
When programming the 8051 in assembly, sometimes register such as R0, R1, and DPTR are used to store
the addresses of some data in a certain memory location. When data is accessed via these registers, indirect
addressing is used. In this case, we say that R0, R1, or DPTR are used to point to the data, so they are essentially
pointers.
Correspondingly in C, indirect access of data can be done through specially defined pointer variables. Point-
ers are simply just special types of variables, but whereas normal variables are used to directly store data, pointer
variables are used to store the addresses of the data. Just bear in mind that whether you use normal variables or
.
pointer variables, you still get to access the data in the end. It is just whether you go directly to where it is stored
t ed
and get the data, as in the case of normal variables, or first consult a directory to check the location of that data
i
before going there to get it, as in the case of pointer variables.
Li m
Declaring a pointer follows the format:
data_type *pointer_name;
where
C U
data_type refers to which type of data that the pointer is pointing to
* denotes that this is a pointer variable
pointer_name
M
is the name of the pointer
C
As an example, the following declarations:

int num;
S
int * numPtr
T
numPtr = &num;
first declares a pointer variable called numPtr that will be used to point to data of type int. The second declaration
declares a normal variable and is put there for comparison. The third line assigns the address of the num variable
to the numPtr pointer. The address of any variable can be obtained by using the address operator, &, as is used in
this example. Bear in mind that once assigned, the numPtr pointer contains the address of the num variable, not
the value of its data.
The above example could also be rewritten such that the pointer is straightaway initialized with an address
when it is first declared:
int num;
int * numPtr = &num;
In order to further illustrate the difference between normal variables and pointer variables, consider the
following, which is not a full C program but simply a fragment to illustrate our point:
int num = 7;
int * numPtr = &num;
printf ("%d\n", num);
printf ("%d\n", numPtr);
printf ("%d\n", &num);
printf ("%d\n", *numPtr);

The first line declare a normal variable, num, which is initialized to contain the data 7. Next, a pointer variable,
numPtr, is declared, which is initialized to point to the address of num. The next four lines use the printf( )
function, which causes some data to be printed to some display terminal connected to the serial port. The first
such line displays the contents of the num variable, which is in this case the value 7. The next displays the
contents of the numPtr pointer, which is really some weird-looking number that is the address of the num variable.
The third such line also displays the addresss of the num variable because the address operator is used to obtain
num's address. The last line displays the actual data to which the numPtr pointer is pointing, which is 7. The *
symbol is called the indirection operator, and when used with a pointer, indirectly obtains the data whose address
is pointed to by the pointer. Therefore, the output display on the terminal would show:
7
13452 (or some other weird-looking number)
13452 (or some other weird-looking number)
7
d .
A Pointer's Memory Type
mit e
Recall that pointers are also variables, so the question arises where they should be stored. When declaring
Li
pointers, we can specify different types of memory areas that these pointers should be in, for example:
int * xdata numPtr = & num;
This is the same as our previous pointer examples. We declare a pointer numPtr, which points to data of type int
U
stored in the num variable. The difference here is the use of the memory type specifier xdata after the *. This is
C
specifies that pointer numPtr should reside in external data memory (xdata), and we say that the pointer's memory
M
type is xdata.
C
Typed Pointers

S T
We can go even further when declaring pointers. Consider the example:
int data * xdata numPtr = &num;
The above statement declares the same pointer numPtr to reside in external data memory (xdata), and this pointer
points to data of type int that is itself stored in the variable num in internal data memory (data). The memory type
specifier, data, before the * specifies the data memory type while the memory type specifier, xdata, after the *
specifies the pointer memory type.
Pointer declarations where the data memory types are explicitly specified are called typed pointers. Typed
pointers have the property that you specify in your code where the data pointed by pointers should reside. The
size of typed pointers depends on the data memory type and could be one or two bytes.
Untyped Pointers
When we do not explicitly state the data memory type when declaring pointers, we get untyped pointers, which
are generic pointers that can point to data residing in any type of memory. Untyped pointers have the advantage
that they can be used to point to any data independent of the type of memory in which the data is stored. All
untyped pointers consist of 3 bytes, and are hence larger than typed pointers. Untyped pointers are also generally
slower because the data memory type is not determined or known until the complied program is run at runtime.
The first byte of untyped pointers refers to the data memory type, which is simply a number according to the
following table. The second and third bytes are,respectively,the higher-order and lower-order bytes of the address
being pointed to.
An untyped pointer is declared just like normal C, where:
int * xdata numPtr = &num;
does not explicitly specify the memory type of the data pointed to by the pointer. In this case, we are using
untyped pointers.
Data memory type values stored in first byte of untyped pointers

Value Data Memory Type
1 idata
2 xdata
3 pdata
4 data/bdata
5 code
FUNCTIONS
In programming the 8051 in assembly, we learnt the advantages of using subroutines to group together common
and frequently used instructions. The same concept appears in 8051 C, but instead of calling them subroutines, we
call them functions. As in conventional C, a function must be declared and defined. A function definition includes
.
a list of the number and types of inputs, and the type of the output (return type), puls a description of the internal
ed
contents, or what is to be done within that function.
i t
The format of a typical function definition is as follows:

{

Li m
return_type function_name (arguments) [memory] [reentrant] [interrupt] [using]
C U
}
where
M
return_type refers to the data type of the return (output) value
function_name is any name that you wish to call the function as
T C
arguments is the list of the type and number of input (argument) values
S
memory refers to an explicit memory model (small, compact or large)
reentrant refers to whether the function is reentrant (recursive)
interrupt indicates that the function is acctually an ISR
using explicitly specifies which register bank to use
Consider a typical example, a function to calculate the sum of two numbers:
int sum (int a, int b)
{
return a + b;
}
This function is called sum and takes in two arguments, both of type int. The return type is also int, meaning that
the output (return value) would be an int. Within the body of the function, delimited by braces, we see that the
return value is basically the sum of the two agruments. In our example above, we omitted explicitly specifying the
options: memory, reentrant, interrupt, and using. This means that the arguments passed to the function would be
using the default small memory model, meaning that they would be stored in internal data memory. This function
is also by default non-recursive and a normal function, not an ISR. Meanwhile, the default register bank is bank 0.
Parameter Passing
In 8051 C, parameters are passed to and from functions and used as function arguments (inputs). Nevertheless, the
technical details of where and how these parameters are stored are transparent to the programmer, who does not
need to worry about these techinalities. In 8051 C, parameters are passed through the register or through memory.
Passing parameters through registers is faster and is the default way in which things are done. The registers used
and their purpose are described in more detail below.

Registers used in parameter passing

Number of Argument Char / 1-Byte Pointer INT / 2-Byte Pointer Long/Float Generic Pointer
1 R7 R6 & R7 R4R7 R1R3
2 R5 R4 &R5 R4R7
3 R3 R2 & R3
Since there are only eight registers in the 8051, there may be situations where we do not have enough regist-
ers for parameter passing. When this happens, the remaining parameters can be passed through fixed memory
loacations. To specify that all parameters will be passed via memory, the NOREGPARMs control directive is
used. To specify the reverse, use the REGPARMs control directive.
Return Values
.
Unlike parameters, which can be passed by using either registers or memory locations, output values must be
d
returned from functions via registers. The following table shows the registers used in returning different types of
mit e
values from functions.
Li
Registers used in returning values from functions
Return Type Register Description
U
bit Carry Flag (C)
C
char/unsigned char/1-byte pointer R7
M
int/unsigned int/2-byte pointer R6 & R7 MSB in R6, LSB in R7
long/unsigned long R4R7 MSB in R4, LSB in R7
C
float R4R7 32-bit IEEE format
S T
generic pointer R1R3 Memory type in R3, MSB in R2, LSB in R1

Appendix C: STC12C5620AD series Electrical Characteristics

Absolute Maximum Ratings
Parameter Symbol Min Max Unit
Srotage temperature TST -55 +125
Operating temperature (I) TA -40 +85
Operating temperature (C) TA 0 +70
DC power supply (5V) VDD - VSS -0.3 +6.0 V
DC power supply (3V) VDD - VSS -0.3 +4.0 V
Voltage on any pin - -0.5 5.5 V
t ed .
i
DC Specification (5V MCU)
Sym Parameter
Min.
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Specification
Typ m Max. Unit
Test Condition
CU
VDD Operating Voltage 3.5 5.0 5.5 V
IPD Power Down Current - < 0.1 - uA 5V
IIDL Idle Current
M - 3.0 - mA 5V
C
ICC Operating Current - 4 20 mA 5V
VIL1
VIL2
VIH1
S T
Input Low Voltage(P0,P1,P2,P3)
Input Low Voltage (RESET, XTAL1)
Input High Voltage (P0,P1,P2,P3)
-
2.0
-
-
0.8
1.5
-
V
V
V
5V
5V
5V
VIH2 Input High Voltage (RESET) 3.0 - - V 5V
IOL1 Sink Current for output low (P0,P1,P2,P3) - 20 - mA 5V
Sourcing Current for output high (P0,P1,P2,P3)
IOH1 150 230 - uA 5V
(Quasi-output)
IOH2 - 20 - mA 5V
(Push-Pull, Strong-output)
IIL Logic 0 input current (P0,P1,P2,P3) - 18 50 uA Vpin=0V
ITL Logic 1 to 0 transition current (P0,P1,P2,P3) - 270 600 uA Vpin=2.0V

DC Specification (3V MCU)

Specification
Sym Parameter Test Condition
Min. Typ Max. Unit
VDD Operating Voltage 2.2 3.3 3.8 V
IPD Power Down Current - <0.1 - uA 3.3V
IIDL Idle Current - 2.0 - mA 3.3V
ICC Operating Current - 4 10 mA 3.3V
VIL1 Input Low (P0,P1,P2,P3) - - 0.8 V 3.3V
VIL2 Input low voltage (RESET,XTAL1) - - 1.5 V 3.3V
VIH1 Input High (P0,P1,P2,P3) 2.0 - - V 3.3V
VIH2 Input High (RESET) 3.0 - - V 3.3V
IOL1 Sink Current for output low (P0,P1,P2,P3) - 20 -
ed . mA 3.3V@Vpin=0.45V
mit
IOH1 40 70 - uA 3.3V
Li
(Quasi-output)
IOH2 - 20 - mA 3.3V
(Push-Pull)
CU
IIL Logic 0 input current (P0,P1,P2,P3) - 8 50 uA Vpin=0V
M
ITL Logic 1 to 0 transition current (P0,P1,P2,P3) - 110 600 uA Vpin=2.0V
S T C

Appendix D: Program for indirect addressing inner 256B RAM

;/*---------------------------------------------------------------------------------------------------------------*/
;/* --- STC MCU International Limited ------------------------------------------------------------------*/
;/* --- STC 1T Series MCU the inner 256B normal RAM (indirect addressing) Demo -----------*/
;/* --- Mobile: (86)13922809991 --------------------------------------------------------------------------*/
;/* --- Fax: 86-755-82905966 ------------------------------------------------------------------------------*/
;/* --- Tel: 86-755-82948412 -------------------------------------------------------------------------------*/
;/* --- Web: www.STCMCU.com -------------------------------------------------------------------------*/
;/* If you want to use the program or the program referenced in the --------------------------------*/
;/* article, please specify in which data and procedures from STC --------------------------------*/
;/*--------------------------------------------------------------------------------------------------------------*/
TEST_CONST EQU 5AH
t ed .
;TEST_RAM EQU 03H
m i
Li
ORG 0000H
LJMP INITIAL
C U
ORG 0050H
M
INITIAL:
MOV R0, #253
T C
MOV R1, #3H
S
TEST_ALL_RAM:
MOV R2, #0FFH
TEST_ONE_RAM:
MOV A, R2
MOV @R1, A
CLR A
MOV A, @R1
CJNE A, 2H, ERROR_DISPLAY

DJNZ R2, TEST_ONE_RAM
INC R1
DJNZ R0, TEST_ALL_RAM
OK_DISPLAY:
MOV P1, #11111110B
Wait1:
SJMP Wait1

ERROR_DISPLAY:
MOV A, R1
MOV P1, A
Wait2:
SJMP Wait2
END

Appendix E: Using Serial port expand I/O interface

STC12C5620AD series MCU serial port mode0 can be used for expand IO if UART is free in your application.
UART Mode0 is a synchronous shift register, the baudrate is fixed at fosc/12, RXD pin (P3.0) is the data I/O port,
and TXD pin (P3.1) is clock output port, data width is 8 bits, always sent / received the lowest bit at first.
(1) Using 74HC165 expand parallel input ports

Please refer to the following circuit which using 2 pcs 74HC165 to expand 16 input I/Os
12Cxx 6 5 4 3 14 13 12 11 6 5 4 3 14 13 12 11
H G F E D C B A
.
H G F E D C B A
9
d
10 9
P3.0 QH SIN QH 10
e
74HC165 SIN
mit
74HC165
P3.1 7 7
QH
Li
S/L CP QH
S/L CP
P1.0 1 15 2 8 16 1 15 2 8 16
Vcc Vcc
104 104
C U
M
74HC165 is a 8-bit parallel input shift register, when S/L (Shift/Load) pin is falling to low level, the parallel port
data is read into internal register, and now, if S/L is raising to high and ClockDisable pin (15 pin) is low level,
C
then clock signal from CP pin is enable. At this time register data will be output from the Dh pin (9 pin) with the
S T
clock input.

MOV R7,#05H ;read 5 groups data
MOV R0,#20H ;set buffer address
START: CLR P1.0 ;S/L = 0, load port data
SETB P1.0 ;S/L = 1, lock data and enable clock
MOV R1,#02H ;2 bytes per group
RXDAT:MOV SCON,#00010000B ;set serial as mode 0 and enable receive data
WAIT: JNB RI,WAIT ;wait for receive complete
CLR RI ;clear receive complete flag
MOV A,SBUF ;read data to ACC
MOV @R0,A ;save data to buffer
INC R0 ;modify buffer ptr
DJNZ R1,RXDAT ;read next byte
DJNZ R7,START ;read next group


(2) Using 74HC164 expand parallel output ports

Please refer to the following circuit which using 2 pcs 74HC164 to expand 16 output I/Os
12Cxx 3 4 5 6 10 11 12 13 3 4 5 6 10 11 12 13
1,2
QA QB QC QD QE QF QG QH QA QB QC QD QE QF QG QH
P3.0 1,2
A,B A,B
14 74HC164 14 74HC164
104 Vcc Vcc
P3.1 104
7 Gnd 7 Gnd
CLR CP CLR CP
P1.0 9 8 9 8
t ed .
m i
When serial port is working in MODE0, the serial data is input/output from RXD(P3.0) pin and serial clock is
Li
output from TXD(P3.1). Serial data is always starting transmission from the lowest bit.
C
START: MOV R7,#02H ;output 2 bytes data
M
MOV R0,#30H ;set buffer address
MOV SCON,#00000000B ;set serial as mode 0
C
SEND: MOV A,@R0 ;read data from buffer
T
MOV SBUF,A ;start send data
S
WAIT: JNB TI,WAIT ;wait for send complete
CLR TI ;clear send complete flag
INC R0 ;modify buffer ptr
DJNZ R7,SEND ;send next data


Appendix F: Use STC MCU common I/O driving LCD Display

Vcc
21K
U2
Seg10
Seg12
Seg11
Com0 0
Seg9
Seg8
43 Seg0
42 Seg1
41 Seg2
Com0
Seg3 Com1 1
Com1
Seg0 2
Seg0
44
40
6
5
4
3
3
1
Seg1 3
Seg4
Seg5
Seg7
Seg6
.
Seg1
Seg2 4
VDD
d
P1.4
P1.3
P1.2
P1.1
P1.0
P4.2
P0.0
P0.1
P0.2
P0.3
Seg2
e
Seg13 7 39 Seg3 5
Seg3
mit
VCC P1.5 P0.4
Seg14 8 38 Seg4 6
P1.6 P0.5 Seg4
C1 Seg5 7
Seg15 9 37 Seg5
Li
10F P1.7 P0.6 Seg6 8
10 36 Seg6
RST P0.7 Seg7 9
11 35 Seg7
R1 P3.0 EA VCC Seg8 10 Seg8
10K 12
P4.3 8051 P4.1 34 Seg9 11 Seg9
CU
Seg10 12
13
P3.1 ALE 33 Seg10
Seg11 13
14
P3.2 PSEN 32 Seg12
Seg11
14
M
15 31 Seg23 Seg12
P3.3 P2.7 Seg13 15
16 30 Seg22 Seg13
P3.4 P2.6 Seg14 16 Seg14
17 P3.5 P2.5 29 Seg21 Seg15 17
C
XTAL2
XTAL1
Seg15
Seg16 18
VSS
T
P3.6
P3.7
P4.0
P2.0
P2.1
P2.1
P2.3
P2.4
Seg16
Seg17 19
S
Seg17
Seg18 20
5.6K R2
5.6K R3
5.6K R4
5.6K R5
5.6K R6
5.6K R7
Seg18
18
19
20
21
22
23
24
25
26
27
28
Seg19 21 Seg19
Seg20 22 Seg20
Seg16
Seg17
Seg18
Seg19
Seg20
Seg21 23 Seg21
Seg22 24
Com1
Com2
Com0
<33pF <33pF Seg22

Seg23 25 Seg23
Com2 26 Com2

NAME LcdDriver
#include<reg52.h>
;********************************************************************************
;the LCD is 1/3 duty and 1/3 bias; 3Com*24Seg; 9 display RAM;
;
; Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
;Com0: Com0Data0: Seg7 Seg6 Seg5 Seg4 Seg3 Seg2 Seg1 Seg0
; Com0Data1: Seg15 Seg14 Seg13 Seg12 Seg11 Seg10 Seg9 Seg8
.
;
t ed
Com1Data1: Seg15 Seg14 Seg13 Seg12 Seg11 Seg10 Seg9 Seg8
i
m
Li
U
M
;Com0: P3^0,P3^1 when P3^0 = P3^1 = 1C
;********************************************************************************
then Com0=VCC(=5V);
C
; P3^0 = P3^1 = 0 then Com0=GND(=0V);
;
S T P3^0 = 1, P3^1=0
;Com1: P3^2,P3^3 the same as the Com0
;Com2: P3^4,P3^5 the same as the Com0
then Com0=1/2 VCC;
sbit SEG0 =P0^0

sbit SEG1 =P0^1
sbit SEG2 =P0^2
sbit SEG3 =P0^3
sbit SEG4 =P0^4
sbit SEG5 =P0^5
sbit SEG6 =P0^6
sbit SEG7 =P0^7
sbit SEG8 =P1^0
sbit SEG9 =P1^1
sbit SEG10 =P1^2

sbit SEG11 =P1^3
sbit SEG12 =P1^4
sbit SEG13 =P1^5
sbit SEG14 =P1^6
sbit SEG15 =P1^7
sbit SEG16 =P2^0
sbit SEG17 =P2^1
sbit SEG18 =P2^2
sbit SEG19 =P2^3
sbit SEG20 =P2^4
sbit SEG21 =P2^5
sbit SEG22 =P2^6
ed .
mit
sbit SEG23 =P2^7
Li
;*********************************************************************************
;======Interrupt===============================
CSEG AT 0000H
C U
M
LJMP start
C
CSEG AT 000BH
LJMP
S T int_t0
;======register===============================
lcdd_bit SEGMENT BIT
RSEG lcdd_bit
OutFlag: DBIT 1 ;the output display reverse flag
lcdd_data SEGMENT DATA
RSEG lcdd_data
Com0Data0: DS 1
Com0Data1: DS 1
Com0Data2: DS 1
Com1Data0: DS 1
Com1Data1: DS 1
Com1Data2: DS 1
Com2Data0: DS 1
Com2Data1: DS 1
Com2Data2: DS 1
TimeS: DS 1

;======Interrupt Code==========================
t0_int SEGMENT CODE
RSEG t0_int
USING 1
;*****************************************************************
;Time0 interrupt
;ths system crystalloid is 22.1184MHz
;the time to get the Time0 interrupr is 2.5mS
;the whole duty is 2.5mS*6=15mS, including reverse
;*****************************************************************
d .
int_t0:
i t e
ORL TL0,#00H
Li m
MOV TH0,#0EEH
PUSH ACC
PUSH PSW
MOV PSW,#08H
C U
M
ACALL OutData
POP PSW

POP ACC
RETI
S T C
;======SUB CODE================================
uart_sub SEGMENT CODE
RSEG uart_sub
USING 0
;******************************************************************
;initial the display RAM data
;if want to display other,then you may add other data to this RAM
;Com0: Com0Data0,Com0Data1,Com0Data2
;*******************************************************************
InitComData: ;it will display "11111111"
MOV Com0Data0, #24H
MOV Com0Data1, #49H
MOV Com0Data2, #92H

MOV Com1Data0, #92H

MOV Com1Data1, #24H
MOV Com1Data2, #49H
MOV Com2Data0, #00H
MOV Com2Data1, #00H
MOV Com2Data2, #00H
RET
;********************************************************************
;reverse the display data
d .
;********************************************************************
mit e
RetComData:
Li
MOV R0, #Com0Data0 ;get the first data address
MOV R7, #9
RetCom_0:
MOV A, @R0
C U
M
CPL A
MOV @R0, A
C
INC R0

RET
S T
DJNZ R7, RetCom_0
;**********************************************************************
;get the display Data and send to Output register
;**********************************************************************
OutData:
INC TimeS
MOV A, TimeS
MOV P3, #11010101B ;clear display,all Com are 1/2VCC and invalidate
CJNE A, #01H, OutData_1 ;judge the duty
MOV P0, Com0Data0
MOV P1, Com0Data1
MOV P2, Com0Data2
JNB OutFlag,OutData_00
MOV P3, #11010111B ;Com0 is work and is VCC
RET

OutData_00:
MOV P3, #11010100B ;Com0 is work and is GND
RET
OutData_1:
CJNE A, #02H,OutData_2
MOV P0, Com1Data0
MOV P1, Com1Data1
MOV P2, Com1Data2
MOV P3, #11011101B ;Com1 is work and is VCC
.
RET
ed
OutData_10:
MOV P3, #11010001B
i t
;Com1 is work and is GND
m
Li
RET
OutData_2:
U
MOV P0, Com2Data0

MOV P1,
MOV P2,
Com2Data1
Com2Data2
M C
C

MOV P3,
S T #11110101B
SJMP OutData_21
OutData_20:
;Com2 is work and is VCC
MOV P3,#11000101B ;Com2 is work and is GND

OutData_21:
MOV TimeS, #00H
ACALL RetComData
CPL OutFlag
RET
;======Main Code===============================
uart_main SEGMENT CODE
RSEG uart_main
USING 0

start:
MOV SP,#40H
CLR OutFlag
MOV TimeS,#00H
MOV TL0,#00H
MOV TH0,#0EEH
MOV TMOD,#01H
MOV IE,#82H
ACALL InitComData
SETB TR0
Main:
ed .
mit
NOP
Li
SJMP Main
END
C U
M
S T C

Appendix G: LED driven by an I/O port and Key Scan

Vcc
10K
1K
P1.7
1K
.
Vcc
10K
i t ed
P1.6
1K
Li m
U
1K
M C
It can save a lot of I/O ports that STC12C5620AD MCU I/O ports can used as the LED drivers and key detection
T C
concurrently because of their feature which they can be set to the weak pull , the strong pull (push-pull) output,
S
only input (high impedance), open drain four modes.
When driving the LED, the I/O port should be set as strongly push-pull output, and the LED will be lighted when
the output is high.
When testing the keys, the I/O port should be set as weak pull input, and then reading the status of external ports
can test the keys.

Appendix H: How to reduce the Length of Code through Keil C

Setting as shown below in Keil C can maximum reduce about 10K to the length of original code
1. Choose the "Options for Target" in "Project" menu
2. Choose the option "C51" in "Options for Target"
ed .
Li mit
C U
M
S T C
3. Code Optimization, 9 common block subroutines

4. Click "OK", compile the program once again.

Appendix I: Notes of STC12C5620AD series Application

About reset circuit
If the system frequency is below 12MHz, the external reset circuit is not required. Reset pin can be connected
to ground through the 1K resistor or can be connected directly to ground. The proposal to create PCB to
retain RC reset circuit
About Clock oscillator

If you need to use internal RC oscillator (4MHz ~ 8MHz because of manufacturing error and temperature
drift), XTAL1 pin and XTAL2 pin must be floating. If you use a external active crystal oscillator, clock
signal input from XTAL1 pin and XTAL2 pin floating.
d .
About power
t e
Power at both ends need to add a 47uF electrolytic capacitor and a 0.1uF capacitor, to remove the coupling
i
and filtering.
Li m
C U
M
S T C

Appendix J: Notes of STC12 series Replaced Traditional 8051

STC12C5620AD series MCU Timer0/Timer1/UART is fully compatible with the traditional 8051 MCU.
After power on reset, the default input clock source is the divider 12 of system clock frequency, and UART
baudrate generator is Timer 1. MCU instruction execution speed is faster than the traditional 8051 MCU 8 ~ 12
times in the same working environment,so software delay programs need to be adjusted.
ALE
Traditional 8051's ALE pin output signal on divide 6 the system clock frequency can be externally provided
clock, if disable ALE output in STC12C5620AD series system, you can get clock source from CLKOUT0/
P1.0, CLKOUT1/P1.1 or XTAL2 clock output. (Recommended a 200ohm series resistor to the XTAL2 pin).
ALE pin is an disturbance source when traditional 8051's system clock frequency is too high. STC89xx
series MCU add ALEOFFF bit in AUXR register. While STC12C5620AD series MCU directly disable ALE
d .
pin dividing 6 the system clock output, and can remove ALE disturbance thoroughly. Please compare the
mit e
following two registers.
Li
AUXR register of STC89xx series
Mnemonic Add Name Bit7 Bit6 Bit5 Bit4 Bir3 Bit2 Bit1 Bit0 Reset Value
AUXR 8EH Auxiliary register 0 - - - - - - EXTRAM ALEOFF xxxx,xx00
CU
AUXR register of STC12C5620AD series
Mnemonic Add Name Bit7 Bit6 Bit5 Bit4 Bir3 Bit2 Bit1 Bit0 Reset Value
M
AUXR 8EH Auxiliary register T0x12 T1x12 UART_M0x6 EADCI ESPI ELVDI - - 000x,xxxx
C
PSEN
S T
Traditional 8051 execute external program through the PSEN signal, STC12C5620AD series is system MCU
concept, integrated high-capacity internal program memory, do not need external program memory expansion
generally, so have no PSEN signal, PSEN pin can be used as GPIO.
General Qusi-Bidirectional I/O

Traditional 8051 access I/O (signal transition or read status) timing is 12 clocks, STC12C5620AD series
MCU is 4 clocks. When you need to read an external signal, if internal output a rising edge signal, for the
traditional 8051, this process is 12 clocks, you can read at once, but for STC12C5620AD series MCU, this
process is 4 clocks, when internal instructions is complete but external signal is not ready, so you must delay
1~2 nop operation.
I/O drive capability

STC12C5620AD series I/O port sink drive current is 20mA, has a strong drive capability, the port is not
burn out when drive high current generally. STC89 series I/O port sink drive current is only 6mA, is not
enough to drive high current. For the high current drive applications, it is strongly recommended to use
STC12C5620AD series MCU.
Power consumption
Power consumption consists of two parts: crystal oscillator amplifier circuits and digital circuits. For
crystal oscillator amplifier circuits, STC12C5620AD series is lower then STC89 series. For digital circuits,
the higher clock frequency, the greater the power consumption. STC12C5620AD series MCU instruction
execution speed is faster than theSTC89 series MCU 3~24 times in the same working environment, so if you
need to achieve the same efficiency, STC12C5620AD series required frequency is lower than STC89 series
MCU.

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www.STCMCU.

com Mobile:(86)13922809991 Tel:86-755-82948412 Fax:86-755-82905966

STC MCU Limited

Update date: 2011-7-15

STC MCU Limited. websitewww.STCMCU.com 

On-chip 768 byte RAM

STC MCU Limited. websitewww.STCMCU.com 

1.2 Block diagram

AUX-RAM RAM ADDR RAM

B Register ACC Stack

STC12C5620AD Block Diagram

 STC MCU Limited. websitewww.STCMCU.com

1.3 Pin Configurations

P2.2 1 32 VCC P2.2 1 32 VCC

ADC7/SCLK/P1.7 25 16 P1.0/ADC0/CLKOUT0 ADC7/SCLK/P1.7 25 16 P1.0/CLKOUT0

STC MCU Limited. websitewww.STCMCU.com 

P2.2 1 28 VCC P2.2 1 28 VCC

ECI/T0/P3.4 10 19 P1.1/ADC1/CLKOUT1 ECI/T0/P3.4 10 19 P1.1/CLKOUT1

STC12C5620AD series (with A/D Converter)28-Pin

Super small package : TSSOP-20, 6.4mm6.4mm

10 STC MCU Limited. websitewww.STCMCU.com

1.4 STC12C5620AD series Selection Table

STC12C5620AD series Selection Table

STC12C5604AD 5.5-3.5 4K 768 Y 4 Y Y Y 2/4-ch 10-bit Y Y Y SOP/LSSOP/DIP SOP/SKDIP SOP/LQFP

STC12C5608 5.5-3.5 8K 768 Y 4 Y Y Y 2/4-ch Y Y Y SOP/LSSOP/DIP SOP/SKDIP SOP/LQFP

STC12C5608AD 5.5-3.5 8K 768 Y 4 Y Y Y 2/4-ch 10-bit Y Y Y SOP/LSSOP/DIP SOP/SKDIP SOP/LQFP

STC12C5620AD 5.5-3.5 20K 768 Y 4 Y Y Y 2/4-ch 10-bit Y Y Y SOP/LSSOP/DIP SOP/SKDIP SOP/LQFP

STC12C5624 5.5-3.5 24K 768 Y 4 Y Y Y 2/4-ch Y Y Y SOP/LSSOP/DIP SOP/SKDIP SOP/LQFP

STC12LE5620AD series Selection Table

STC12LE5616 3.6-2.2 16K 768 Y 4 Y Y Y 2/4-ch Y Y Y SOP/LSSOP/DIP SOP/SKDIP SOP/LQFP

STC MCU Limited. websitewww.STCMCU.com 11

1.5 STC12C5620AD series Minimum Application System

About crystals circuit:

12 STC MCU Limited. websitewww.STCMCU.com

1.6 STC12C5620AD series MCU Typical Application Circuit for ISP

<33pF 7 XTAL1 ADC4/SS/P1.4 22

If External clock frequency is higher

STC MCU Limited. websitewww.STCMCU.com 13

14 STC MCU Limited. websitewww.STCMCU.com

If using internal R/C oscillator clock

STC MCU Limited. websitewww.STCMCU.com 15

16 STC MCU Limited. websitewww.STCMCU.com

<33pF 8 XTAL1 ADC4/SS/P1.4 25

STC MCU Limited. websitewww.STCMCU.com 17

1.7 Pin Descriptions

m i common I/O port PORT1[1]

18 STC MCU Limited. websitewww.STCMCU.com

STC MCU Limited. websitewww.STCMCU.com 19

1.8 Package Dimension Drawings

VARIATIONS (ALL DIMENSIONS SHOWN IN MM)

0 2. Dim D1 AND E1 does not include plastic

20 STC MCU Limited. websitewww.STCMCU.com

32-Pin Small Outline Package (SOP-32)

SYMBOL MIN NOM MAX

STC MCU Limited. websitewww.STCMCU.com 21

28-Pin Small Outline Package (SOP-28)

(UNITS OF MEASURE = MILLMETER)

SYMBOL MIN NOM MAX

22 STC MCU Limited. websitewww.STCMCU.com

STC MCU Limited. websitewww.STCMCU.com

STC MCU Limited. websitewww.STCMCU.com

STC MCU Limited. websitewww.STCMCU.com

STC MCU Limited. websitewww.STCMCU.com