Electron Device

EXP 1 P-N DIODE CHARACTERISTICS
1.1 Objective:
To study the Volt-Ampere Characteristics of Silicon P-N Junction Diode and to find
cut-in voltage, static and dynamic resistances.
1.2 Hardware Required:
S. No Apparatus Type Range Quantity
01 PN Junction Diode 1N4001 1
1k ohm, 10% tolerance,

02 Resistance 1/2 watt rating 1
03 Regulated power supply (0 30V), 2A Rating 1
04 Ammeter MC (0-30)mA, (0-500)A 1

05 Voltmeter MC (0 1)V, (0 30)V 1
06 Bread board and

connecting wires
1.3 Introduction:
Donor impurities (pentavalent) are introduced into one-side and acceptor impurities
into the other side of a single crystal of an intrinsic semiconductor to form a p-n diode with a
junction called depletion region (this region is depleted off the charge carriers). This region
gives rise to a potential barrier V called Cut- in Voltage. This is the voltage across the
diode at which it starts conducting. The P-N junction can conduct beyond this Potential.
The P-N junction supports uni-directional current flow. If +ve terminal of the input
supply is connected to anode (P-side) and ve terminal of the input supply is connected to
cathode (N- side), then diode is said to be forward biased. In this condition the height of the
potential barrier at the junction is lowered by an amount equal to given forward biasing
voltage.
Both the holes from p-side and electrons from n-side cross the junction
simultaneously and constitute a forward current ( injected minority current due to holes
crossing the junction and entering N-side of the diode, due to electrons crossing the junction
and entering P-side of the diode). Assuming current flowing through the diode to be very
large, the diode can be approximated as short-circuited switch. If ve terminal of the input
supply is connected to anode (p-side) and +ve terminal of the input supply is connected to
cathode (n-side) then the diode is said to be reverse biased. In this condition an amount equal
to reverse biasing voltage increases the height of the potential barrier at the junction.
Both the holes on p-side and electrons on n-side tend to move away from the junction
thereby increasing the depleted region. However the process cannot continue indefinitely,
thus a small current called reverse saturation current continues to flow in the diode. This
small current is due to thermally generated carriers. Assuming current flowing through the
diode to be negligible, the diode can be approximated as an open circuited switch.
The volt-ampere characteristics of a diode explained by following equation:
I = Io(exp(V/ VT)-1) I=current flowing in the diode Io=reverse saturation current V=voltage
applied to the diode
VT=volt-equivalent of temperature=kT/q=T/11,600=26mV(@ room temp). =1 (for Ge) and
2 (for Si)
Germanium diode has smaller cut-in-voltage than Silicon diode. The reverse saturation
current in Ge diode is larger in magnitude when compared to silicon diode.
1.4 Circuit diagram:

1.4.1 Forward Bias
1.4.2 Reverse Bias
1.5 Precautions:
1. While doing the experiment do not exceed the ratings of the diode. This may lead to
damage of the diode.
2. Connect voltmeter and Ammeter in correct polarities as shown in the circuit diagram.
3. Do not switch ON the power supply unless you have checked the circuit connections as
per the circuit diagram.
1.6 Characteristics of PN junction diode:

1. Breakdown voltage can be traded with switching speed. A reduction in recombination
lifetime through addition of suitable impurities will increase leakage current. This can
be countered by decreasing diode area which however will lead to reduced forward
current rating unless doping is increased. This will lead to a reduced breakdown
voltage.
2. The breakdown voltage and reverse recovery are also related together in more direct
manner. Regions which have higher doping also have a lower recombination lifetime so
that a lower breakdown voltage diode is likely to have lower lifetime and better
switching speeds. So a single diode cannot meet the diverse applications.
1.7 Procedure:
1.7.1Forward Biased Condition:
1. Connect the PN Junction diode in forward bias i.eAnode is connected to positive of the
power supply and cathode is connected to negative of the power supply .
2. Use a Regulated power supply of range (0-30) V and a series resistance of 1k.
3. For various values of forward voltage (Vf) note down the corresponding values of
forward current (If).

1.7.2Reverse biased condition:
4. Connect the PN Junction diode in Reverse bias i.e; anode is connected to negative of
the power supply and cathode is connected to positive of the power supply.
5. For various values of (Vr) note down the corresponding values of reverse current ( Ir ).
1.8 Tabular column:

1.8.1 Forward Bias:
S. No Vf (volts) If (mA)
1.8.2 Reverse Bias:
S. No Vr (volts) Ir (A)
1.9 Simulation Results
Cut In Voltage = V
Break Down Voltage = V
1.10 Model Graph:
Forward Bias
Reverse Bias
1.11 Result:
Thus the VI characteristic of PN junction diode was verified.
i. Cut in voltage = V
ii. Static forward Resistance Rdc = (Vf/If)
iii. Dynamic forward Resistance rac = (Vf/If)
iv. Static Reverse Resistance Rdc = (Vr/Ir)
v. Dynamic Reverse Resistance rac = (Vr/Ir)
1.12 Prelab Questions:

1. What is the need for doping?
2. How depletion region is formed in the PN junction?
3. What is break down voltage?
4. What is cut-in or knee voltage? Specify its value in case of Ge or Si?
5. What are the differences between Ge and Si diode?
6. What is the relationship between depletion width and the concentration of impurities?
1.13 Post lab Questions:
1. Generate input and output characteristics in PN Junction diode using PSPICE and compare
with the obtained output.
2. How does PN-junction diode acts as a switch?
3. Comment on diode operation under zero biasing condition.
4. For a uniformly doped silicon PN junction diode with an N-type doping of and a P-
type doping of 2 x , Sketch the potential within the space charge region at
equilibrium. What fraction of the built-in voltage is dropped in the N-region? Where will most
of the built-in voltage be dropped if the P type doping is much larger than the N-type doping?
5. The depletion capacitance/Area measured for a symmetrical Silicon PN junction at different
bias voltages is given below:
(a) Determine the doping of N and P-regions

(b) Determine the built-in voltage
(c) Determine the depletion width at zero bias
6. Design circuits to get the following outputs.
EXP 2 ZENER DIODE CHARACTERISTICS
2.1 Objective:
To study the Volt-Ampere characteristics of Zener diode and to measure the Zener break
down voltage.

S.
No Apparatus Type Range Quantity
01 Zener Diode IZ 6.2 1

1k ohm, 10% tolerance, 1/2 watt
02 Resistance rating 1
03 Regulated power supply (0 30V), 2A rating 1
04 Ammeter mC (0-30)mA 1
05 Voltmeter mC (0 1)V, (0 10)V 1
Bread board and
06
connecting wires
2.3 Introduction:
An ideal P-N Junction diode does not conduct in reverse biased condition. A Zener diode
conducts excellently even in reverse biased condition. These diodes operate at a precise value of
voltage called break down voltage. A Zener diode when forward biased behaves like an ordinary P-
N junction diode. A Zener diode when reverse biased can either undergo avalanche breakdown or
Zener breakdown.
Avalanche breakdown:-If both p-side and n-side of the diode are lightly doped, depletion
region at the junction widens. Application of a very large electric field at the junction may rupture
covalent bonding between electrons. Such rupture leads to the generation of a large number of
charge carriers resulting in avalanche multiplication.
Zener breakdown:-If both p-side and n-side of the diode are heavily doped, depletion region
at thejunction reduces. Application of even a small voltage at the junction ruptures covalent bonding
and generates large number of charge carriers. Such sudden increase in the number of charge carriers
results in Zener mechanism.
2.4.1 Forward Bias
2.4.2 Reverse Bias
2.4.3 Zener Diode Symbol:

2.5 Precautions:
1. While doing the experiment do not exceed the ratings of the diode. This may lead to damage of
the diode.
3. Do not switch ON the power supply unless you have checked the circuit connections as per the
circuit diagram.
2.6 Characteristics of Zener Diode:

For IZ6.2 Zener diode,
Forward Bias:
At a given (constant) diode current, V exhibits an approximately linear shift in the VI -characteristic
due to the combined effect of the temperature dependences of both IS and VT
Typically, the VI -characteristic shifts approximately -2 mV/C.
Reverse Bias:
The temperature dependence of the reverse current is that of IS alone, which changes exponentially
as a function of temperature. Typically, IS approx. doubles for every 10 C increase in Temperature.
These variations may lead to significant changes in the operation of a circuit over a large
temperature range and, in many applications, requires compensation strategies to be implemented in
the design of some circuits.
2.7 Procedure:
2.7.1 Forward Biased Condition:
1. Connect the Zener diode in forward bias i.e; anode is connected to positive of the power
supply and cathode is connected to negative of the power supply as in circuit
2. Use a Regulated power supply of range (0-30) V and a series resistance of 1k.
3. For various values of forward voltage (Vf) note down the corresponding values
of forward Current (If).
2.7.2 Reverse biased condition:

1. Connect the Zener diode in Reverse bias i.e; anode is connected to negative of the power
supply and cathode is connected to positive of the power supply as in circuit.
2. For various values of reverse voltage (Vr ) note down the corresponding values of reverse
current ( Ir ).
2.8 Tabular column:
2.8.1 Forward Bias:
S. No Vf (volts) If (mA)
2.8.2 Reverse Bias:
S. No Vr (volts) Ir (mA)
2.9 Model Graph:
Forward Bias
Reverse Bias
2.10 Simulation Results
Cut In Voltage = V
Break Down Voltage = V
2.11 Result:
The Zener diode characteristics have been verified and the following parameters were
calculated
i) Cut in voltage = V
ii) Break down voltage =. V
2.12Pre lab Questions:

1. Explain the concept of Zener breakdown?
2. How depletion region gets thin by increasing doping level in Zener diode?
3. State the reason why an ordinary diode suffers avalanche breakdown rather than Zener
breakdown?
4. Give the reasons why Zener diode acts as a reference element in the voltage regulator circuits.
5. What type of biasing must be used when a Zener diode is used as a regulator?

1. Generate input and output characteristics in Zener diode using PSPICE and compare with the
obtained output .
2. Design a DC power supply network using Zener diode.
3. What happens when the Zener diodes are connected in series?
4. Justify the use of zener diode in a stabilization circuit?

5. How will you differentiate the diodes whether it is Zener or avalanche when you are given two
diodes of rating 6.2 v and 24V?
6. How does a zener diode protect meters from excess voltage that is applied accidentally?
EXP 3 DIODE RECTIFIER CIRCUITS
3.1 Objective:
To design and construct the diode rectifier circuit and analyze the following parameters
a. To plot Output waveform of the
b. To find ripple factor using formulae
c. To find the efficiency
d. To stimulate the same using orcad pspice capture
(6-0-6 )V, 500mA, 1A

01 Step down Transformer Rating 1
470 ohm, 10% tolerance,

03 Capacitor 470F 1
04 Diode IN4001 1
Bread board and 1

05
connecting wires
3.3 Half wave rectifier

A device is capable of converting a sinusoidal input waveform into a unidirectional
waveform with non-zero average component is called a rectifier. A practical half wave rectifier with
a resistive load is shown in the circuit diagram. In positive half cycle, Diode D is forward biased and
conducts. Thus the output voltage is same as the input voltage. In the negative half cycle, Diode D is
reverse biased, and therefore output voltage is zero. A smoothing filter is induced between the
rectifier and load in order to attenuate the ripple component. The filter is simply a capacitor
connected from the rectifier output to ground. The capacitor quickly charges at the beginning of a
cycle and slowly discharges through RL after the positive peak of the input voltage. The variation in
the capacitor voltage due to charging and discharging is called ripple voltage. Generally, ripple is
undesirable, thus the smaller the ripple, the better the filtering action.
Ripple factor is a measure of effectiveness of a rectifier circuit and defined as a ratio of RMS
value of ac component to the dc component in the rectifier output.
Theoretical calculations for Ripple Factor:
Without Filter:
Vrms = Vm / 2
Ripple factor (Theoretical)
Ripple Factor(practical) where

With Filter:
Ripple Factor (Theoretical)

Where f = 50Hz, R = 1K , C = 1000 F
Ripple Factor(practical)
Percentage Regulation %
VNL = DC voltage at the load without connecting the load (Minimum current).
VFL = DC voltage at the load with load connected.
Efficiency
PAC = V2rms / RL
PDC = Vdc / RL
The ripple factor can be lowered by increasing the value of the filter capacitor or increasing the load
capacitance.
3.4 Circuit Diagram of Half Wave Rectifier
3.5 Observations:
Output
Ripple Voltage
Input Waveform Waveform
(with filter)
(without filter)
Amplitude
Time Period
Frequency
3.6 Pspice circuit diagram for Half Wave Rectifier(with out filter)
3.7 Simulation graph for Half wave rectifier without filter
3.8 Pspice circuit diagram for Half Wave Rectifier(with filter)

3.9 Simulation graph for Half wave rectifier with filter
3.10 Full wave rectifier

waveform with non zero average component is called a rectifier.
A practical half wave rectifier with a resistive load is shown in the circuit diagram. It consists of two
half wave rectifiers connected to a common load. One rectifies during positive half cycle of the input
and the other rectifying the negative half cycle. The transformer supplies the two diodes (D1 and
D2) with sinusoidal input voltages that are equal in magnitude but opposite in phase. During input
positive half cycle, diode D1 is ON and diode D2 is OFF. During negative half cycle D1 is OFF and
diode D2 is ON. Peak Inverse Voltage (PIV) is the maximum voltage that has to be withstand by a
diode when it is reverse biased. Peak inverse voltage for Full Wave Rectifier is 2V m because the
entire secondary voltage appears across the non-conducting diode .
The output of the Full Wave Rectifier contains both ac and dc components. A majority of the
applications, which cannot tolerate a high value ripple, necessitates further processing of the
rectified output. The undesirable ac components i.e. the ripple, can be minimized using filters.
Ripple Factor:
Ripple factor is defined as the ratio of the effective value of AC components to the average
DC value. It is denoted by the symbol ' '.
Efficiency:
The ratio of output DC power to input AC power is defined as efficiency.
= 81% (if R >> Rf, then Rf can be neglected).
The maximum efficiency of a Full Wave Rectifier is 81.2%.
Percentage of Regulation:
It is a measure of the variation of DC output voltage as a function of DC output current (i.e.,
variation in load).
Percentage of regulation = %
VNL = Voltage across load resistance, when minimum current flows through it.
VFL = Voltage across load resistance, when maximum current flows through.
For an ideal Full-wave rectifier, the percentage regulation is 0 percent. The percentage of regulation
is very small for a practical full wave rectifier.
Peak- Inverse - Voltage (PIV):
It is the maximum voltage that the diode has to withstand when it is reverse biased.
PIV = 2Vm
Transformer Utilization Factor

Transformer utilization factor (TUF), which is defined as the ratio of power delivered to the
load and ac rating of the transformer secondary, SoTUF = dc power delivered to the load/ac rating of
transformer secondaryTransformer Utilization Factor, TUF can be used to determine the rating of a
transformer secondary. It is determined by considering the primary and the secondary winding
separately and it gives a value of 0.693.
3.11 Theoretical Calculations:
Without filter:
Ripple factor (Theoretical) =
Ripple Factor (Practical)

With filter:
Ripple factor (Theoretical)

Where f = 50Hz, R =1K , C = 1000 F.
Ripple Factor
Percentage Regulation = %
VNL = DC voltage at the load without connecting the load (Minimum current).
VFL = DC voltage at the load with load connected.
Efficiency %u200B
PAC = V2rms / RL
PDC = Vdc / RL
3.12 Circuit Diagram
3.13 MODEL GRAPH:

3.14 Observations:
Output
Ripple Voltage
(with filter)
(without filter)
Amplitude
Time Period
Frequency
3.15 Pspice circuit diagram for Full Wave Rectifier(with filter)
3.16 Simulation graph for full wave rectifier (with filter)

3.17 Pspice circuit diagram for Full Wave Rectifier(without filter)
3.18Simulation graph for full wave rectifier (with filter)
3.19 Bridge rectifier:

waveform with non zero average component is called a rectifier. The Bridge rectifier is a circuit,
which converts an ac voltage to dc voltage using both half cycles of the input ac voltage. The Bridge
rectifier has four diodes connected to form a Bridge. The load resistance is connected between the
other two ends of the bridge.
For the positive half cycle of the input ac voltage, diode D1 and D3 conducts whereas diodes
D2 and D4 remain in the OFF state. The conducting diodes will be in series with the load resistance
RL and hence the load current flows through RL. For the negative half cycle of the input ac voltage,
diode D2 and D4 conducts whereas diodes D1 and D3 remain in the OFF state.
The conducting diodes will be in series with the load resistance RL and hence the load
current flows through RL in the same direction as in the previous half cycle. Thus a bidirectional
wave is converted into a unidirectional wave. Ripple factor is a measure of effectiveness of a
rectifier circuit and defined as a ratio of RMS value of ac component to the dc component in the
rectifier output.
3.20 Theoretical calculations:
Ripple Factor
The ripple factor for a Full Wave Rectifier is given by
The average voltage ofr the DC voltage available across the load resistance is Vdc=2Vm/
The RMS value of the voltage at the load resistance is Vrms=Vm/ 2
Ripple factor
The ripple factor can be lowered by increasing the value of the filter capacitor or increasing the load
capacitance.
Efficiency
Efficiency, is the ratio of dc output power to ac input power
The maximum efficiency of a Full Wave Rectifier is 81.2%

Transformer Utilization Factor
Transformer utilization factor (TUF), which is defined as the ratio of power delivered to the
load and ac rating of the transformer secondary,so
TUF = dc power delivered to the load/ac rating of transformer secondary
Transformer Utilization Factor, TUF can be used to determine the rating of a transformer
secondary. It is determined by considering the primary and the secondary winding separately and it
gives a value of 0.812.
3.21 Circuit Diagram:
3.22 Model Graph:
3.23 Observations:
Output Ripple
Voltage
(with filter)
(without filter)
Amplitude
Time Period
Frequency
3.24 pspice circuit diagram for Full Wave Bridge Rectifier(with ut filter)
3.25 simulation graph for full wave bridge rectifier(without filter)
3.26 pspice circuit diagram for Full Wave Bridge Rectifier(with filter)
3.27 simulation graph for full wave bridge rectifier(withfilter)
3.28 Result:
Thus the Rectifier Circuits are constructed and ripple factor, efficiency, Vp(rect), and Vdc
values for circuits has been analyzed
1. What is the PIV of rectifier circuits?

2. A bridge rectifier is preferable to a full-wave rectifier using center-tap transformer as
(a) It uses four diodes
(b) Its transformer does not require center-tap
(c) It requires much smaller transformer for the same output
(c) All of these
3. In a full-wave bridge rectifier, the current in each diode flows for
(a) Complete cycle of the input signal
(b) Half-cycle of the input signal
(c) Less than half-cycle of the input signal
(d) More than half-cycle of the input signal
4. What is the purpose of a filter in dc power supply?
5. What is TUF? Give the TUF of half wave, full wave-center tapped and bridge rectifier.

1.When a 50Hz ac signal is fed to a rectifier, the ripple frequency of the
output voltagewaveformfor full bridge rectifier is
(a) 25 Hz (b) 50 Hz (c) 100 Hz (c)150 Hz
2. Trace the current through this rectifier circuit at a moment in time when the AC sources polarity
is positive on right and negative on left as shown. Be sure to designate the convention you use for
current direction (conventional or electron flow):
Also, mark the polarity of the voltage drop across Rload.

3.For the figure shown below. Determine (a) the DC output voltage, (b) DC load current, (c) the
RMS value of the load current, (d) the DC power, (e)the AC power, (f) efficiency of rectifier, (g)
peak inverse voltage of each diode, and (h) output frequency. Assume all diodes are ideal.
EXP 4 DIODE CLIPPING AND CLAMPING CIRCUITS
4.1 Objective:
To study the use of diodes in wave-shaping (clipper) circuits and in level-shifting (clamper)
circuits.
01 PN Junction Diode IN4001 1
02 Resistance 1k ohm 1
03 Regulated power supply (0 30V) 1
Bread board and

04 connecting wires
4.3 Introduction:
Clippers:
It is frequently necessary to modify the shape of various waveforms for use in instrumentation,
controls, computation, and communications. Wave shaping is often achieved by relatively simple
combinations of diodes, resistors, and voltage sources. Such circuits are called clippers, limiters,
amplitude selectors, or slicers. Clipper circuits are primarily used to prevent a waveform from
exceeding a particular limit, either positive or negative. For example, one may need to limit a power
supplys output voltage so it does not exceed +5 V. The most widely used wave shaping circuit is the
rectifier, which you have previously studied.
Figure 4.1 shows a positive clipper circuit. As indicated, the output voltage has the entire
positive half-cycles clipped off. The circuit works as follows: During the positive half-cycle of the
input voltage, the diode turns on. For an ideal diode, the output voltage is zero. For an actual diode
the output voltage is equal to V , the cut-in voltage of the diode.
During the negative half-cycle, the diode is reverse-biased and can be approximated by an open
circuit. In many clippers, the load resistor, RL, is much larger than the series resistor, R. In which
case, essentially all of the negative half-cycle voltage appears at the output through voltage-divider
action. If RL and R are comparable, then on the negative half-cycle, the output voltage would be
given by
Vo = Vp1 = Vp (RL / (RL + R)).
Since the first V volts are used to begin conduction in the diode, the output signal is clipped near
V, rather than at 0V. If the diode polarity is reversed, the result is a negative clipper that removes
the negative half cycle. In this case, the clipping levels occur near -V.
Figure 4.1: A positive clipper circuit: (a) Sinusoidal input to clipper circuit;(b) A positive
clipper circuit; (c) Output of ideal positive clipper circuit; and (d) Output of actual
positive clipper circuit
If a constant voltage source is placed in series with the diode shown in Figure 4.1(b), the result is
a biased positive clipper, as shown in Figure 4.2(b). When the input voltage is greater than V+V,
the diode is forward biased and the output voltage is held at (V+V) volts (assuming RL>> R). When
the input voltage is less than V+V, the diode becomes an open circuit and the circuit acts as a
voltage divider. RL is usually much greater than R, in which case, essentially all of the input voltage
appears at the output. If both the diode and battery polarities are reversed, a biased negative clipper
results, with the output clipped near -(V+V) volts.
(a) (b) (C)
Figure 4.2: Biased positive clipper circuit: (a) Input to clipped circuit; (b) Biased
positive clipper circuit; and (c) Output of positive clipper circuit
Clampers
In certain instances, it may be desirable to keep the output waveform essentially unchanged, but
modify its dc level to some required value. This can be done by the use of diodes, resistors,
capacitors, and voltage sources. Such circuits are known as clampers. For example, if the input
voltage signal swings from -10V to +10V, a positive dc clamper can produce an output that keeps the
signal wave shape intact but swings the voltage from 0V to +20V. TV receivers use a dc clamper to
add a dc voltage to the video signal. Here the dc clamper is usually called a dc restorer.
In Figure 4.3(b) a positive dc clamper is shown. The clamper operates as follows: During the
negative half-cycle of the input voltage, the diode turns on as illustrated in Figure 4.4(a). At the
negative peak, the capacitor charges up to Vp with the polarity shown and the output voltage is zero.
As the voltage grows beyond the negative peak, the diode shuts off as shown in Figure 4.4(b).
(a) (b) (c)
Figure 4.3: Positive dc clamper: (a) Sinusoidal input to positive dc clamper;

(b) Positive dc clamper; and (c) Clamped sinusoidal output
The capacitor retains the voltage for a short time. The RLC time constant is deliberately made
much larger than the period, T, of the input signal. Hence, the capacitor remains almost fully charged
during the entire off time of the diode. The capacitor thus acts like a battery of Vp volts and now
only passes the ac signal, which rides on top of VP. The output voltage signal, therefore, consists of
the input signal riding on a dc voltage of +Vp volts.
Since the diode drops V volts when conducting, the capacitor voltage does not quite reach +Vp
volts. For this reason, the dc clamping is not perfect, and the negative peaks are at -V as shown in
Figure 4.4(e).
When the polarity of the diode in Figure 4.3(b) is reversed, the polarity of the capacitor voltage
reverses also, and the circuit becomes a negative dc clamper. Ideally, the output voltage consists of
the input voltage riding on a dc voltage of -Vp volts. If the diode is considered non-ideal, then the
output will consist of the input signal riding on a dc voltage of -(Vp-V) volts, and the positive peaks
will occur at V volts.
(a) (b)
(c) (d) (e)
Figure 4.4: Positive clamping circuit operation

From the above discussions, it can be seen that when the diode points upward, a positive dc
clamper results. When the diode points downward, the circuit is a negative dc clamper. The clamping
value can be modified by putting a voltage source VB in series with the diode, shifting the peak
voltage to ( V VB), depending on the sign of VB and the polarity of the diode.
4.4. EXPERIMENT:
4.4.1 IDEAL CLIPPING CIRCUITS
NOTE: Set Vin= 8VPat 1kHz with 0V DC offset and R = 1k for all circuits.
1. Clipping Circuit 1
a. Connect the circuit shown in Figure 4.5(a) using the SUPPLY+ power supply as
VB. Set the SUPPLY+ voltage to 0V using the Variable Power Supply.
b. Measure Vin and Vo using the oscilloscope. Make an accurate sketch of the input
and output waveforms on the same graph, making note of the peak values of Vo
(minimum Vo and maximum Vo) and the input voltage at which clipping occurs.
c. Set VB (SUPPLY+) = 2V and repeat step b.
Figure 4.5(a): Clipping Circuit 1
a. Connect the circuit shown in Figure 4.5(b) using the SUPPLY+ power supply as
VB. Set the SUPPLY+ voltage to 0V.
c. Set VB (SUPPLY+) = 2V and repeat step b.
Figure 4.5(b): Clipping Circuit 2
a. Connect the circuit shown in Figure 4.5(c) using the SUPPLY power supply as -
VB. Set the SUPPLY voltage to 0V.
c. Set VB = 2V (SUPPLY = -2V) and repeat step b.
Figure 4.5(c): Clipping Circuit 3

a. Connect the circuit shown in Figure 4.5(d) using the SUPPLY power supply as -
VB. Set the SUPPLY voltage to 0V.
c. Set VB = 2V (SUPPLY = -2V) and repeat step b.
Figure 4.5(d): Clipping Circuit 4
4.4.2 SERIES-BIASED CLIPPING CIRCUITS
NOTE: The Function Generator (FGEN) in the following circuits will provide both the VSIN
and VB voltages. DO NOT USE SUPPLY+ OR SUPPLY IN THE CIRCUITS.
R = 1k for all circuits.
1. Series-Biased Clipping Circuit 1
a. Connect the circuit shown in Figure 4.6(a) using the function generator to supply
both VSIN and VB. Set the AMPLITUDE voltage to 8VP. Set the frequency to
1kHz. Set the DC offset to 0V.
b. Measure VSIN and Vo using the oscilloscope using SCOPE CH0 and CH1,
respectively. Set the coupling on CH0 and CH1 to DC. Click Autoscale.
Make an accurate sketch of VSIN and Vo on the same graph, making note of the
peak values of Vo (minimum Vo and maximum Vo) and the value of VSIN at
which clipping occurs. Use the cursors as needed.
c. Set the DC offset of the function generator to 2V (which is same as VB=2V) and
repeat step b.
Figure 4.6(a): Series-Biased Clipping Circuit 1

a. Connect the circuit shown in Figure 4.6(b) using the function generator to supply
respectively. Set the coupling on CH0 and CH1 to DC. Click Autoscale. Make
an accurate sketch of VSIN and Vo on the same graph, making note of the peak
values of Vo (minimum Vo and maximum Vo) and the value of VSIN at which
clipping occurs. Use the cursors as needed.
c. Set the DC offset of the function generator to -2V (VB=2V) and repeat step b.
Figure 4.6(b): Series-Biased Clipping Circuit 2

a. Connect the circuit shown in Figure 4.6(c) using the function generator to supply
respectively. Set the coupling on CH0 and CH1 to DC. Click Autoscale. Make
an accurate sketch of VSIN and Vo on the same graph, making note of the peak
values of Vo (minimum Vo and maximum Vo) and the value of VSIN at which
clipping occurs. Use the cursors as needed.
c. Set the DC offset of the function generator to 2V (VB=2V)and repeat step b.
Figure 4.6(c): Series-Biased Clipping Circuit 3

4.4.3 CLAMPERS
Build the circuit shown in Figure 4.8 and make an accurate sketch of the input and output
waveforms for a 8VPsine wave input voltage for each of the following conditions. Eachcondition
should be relative to the circuit as shown in Figure 4.7. Be sure to record the peakvalues of both
waveforms on your sketch. A capacitor larger than 22 F will work in this circuit.
1. Circuit as shown with VDC (or SUPPLY+) = 2 volt.

2. Reverse polarity of diode and of capacitor.
3. Diode as shown with the battery reversed. (Replace SUPPLY+ with SUPPLY)
4. Reverse polarity of diode, of capacitor, and of battery. (Replace SUPPLY+
withSUPPLY)
5. Continuously vary SUPPLY+/SUPPLY to see how the waveform is shifted in each case.
Figure 4.7: Clamping circuit

4.5 Precautions:
4. While doing the experiment do not exceed the ratings of the diode. This may lead to
damage of the diode.
6. Do not switch ON the power supply unless you have checked the circuit connections as per
the circuit diagram.
4.6 Procedure:
1. Ideal Clipping Circuits Build 4 circuits (Figures 4.5 a-d)
a. Vin = 8VP, 1kHz, VB = 0 & 2V.
b. Sketch the input and output waveforms.
c. Record the voltage at which clipping occurs.

2. Series-Biased Clippers Build 4 circuits (Figures 4.6 a-c)
a. Vsin = 8VP, 1 kHz, VB = 0 & 2V.
c. Record the voltage at which clipping occurs.
3. Clamper Build circuit (Figure 4.7)
a. Vin = 8VP, 1kHz, Vdc = 2V.
4.7 Tabular column:

Clipped Value:
Amplitude Time period Frequency
Input Waveform
Output Waveform
4.8 IDEAL CLIPPING CIRCUITS
Clipping circuit 1
Figure 4.8 Circuit Diagram of Clipping Circuit 1

Figure 4.9 Input and Output waveform of Clipping Circuit 1
Clipping Circuit 2

Clipping Circuit 3
Clipping Circuit 4

SERIES-BIASED CLIPPING CIRCUITS
Series Biased Clipping Circuit 1
Figure 4.16 Circuit Diagram of Series Biased Clipping Circuit 1
Figure 4.17 Input and output waveform of Series Biased Clipping Circuit 1

CLAMPER
Figure 4.22 Circuit Diagram of Clamper Circuit
Figure 4.23 Input and output waveform of Clamper Circuit

4.9 Result:
Various clipper and clamper circuits are constructed and the input and output waveforms are
plotted.

7. What are the different types of clippers?
8. What are the applications of clippers?
9. Design a clipper circuit which limits the output signal to +1V and -1.5V.
10. What are the other names of Clamper?

7. If the diode in the figure 4.6(c) is reversed. What would be the output?
8. If the voltage VB in the figure 4.6(c) is reversed. What would be the output?
9. What is parallel biased clipper?
10. Draw the clipper circuit which clips the waveforms at two different levels.
5. ZENER DIODE VOLTAGE REGULATOR CIRCUITS
5.1 Objective
1. To design a series, shunt voltage regulator
2. To find load regulation
3. To find line regulation
5.2 Hardware Required
1 Power transistor 2N3055 1
2 Transistor BC147 1
1Z6.2,
3 1Z5.1
Zener diode 1
1K, 947, 2.48K, 2.2k,
2.75K, 49.6, 10%
4 Resistors tolerance, watt 1
5 Voltmeter MC (0 30)V 1
6 Bread board & wires
7. Decade Resistance Box 50 1
5.3 Introduction
The term regulation is the ability of the power supply source to maintain a constant
output voltage in spite of line voltage fluctuations and changes in load current
The factors of poor regulation are
1. The line voltage changes which causes a dc output change and the ripple content of the dc
input due to inadequate filtering.
2. The load current changes which causes a variable internal drop due to the internal
resistance of the regulator and the consequent change in the output voltage and
3. The temperature coefficient of the device parameters which results in a change of the
output voltage.
Voltage regulators can be classified by the method of achieving regulation as linear regulators
and switching regulators. They are also classified by the way they are connected to the load as
series regulators and shunt regulators. Standard regulator contains three basic elements namely a
precision voltage reference, an error amplifier and a power control element.
In series voltage regulator the transistor Q2functions both as a voltage comparator and dc
amplifier. Any increase in the output voltage Vo either due to the input-voltage variation or
change of load results in increase of VBE of the transistor Q2. Hence the collector current IC2
increase. Due to this the total current following through R3 increases. Hence the collector
voltage of Q2 decreases.
Since the base of Q1 is tied to the collector of T2, the base voltage of Q1.with respect to
ground decreases thereby decreasing the forward bias of the emitter junction of Q 2. Hence the
collector emitter voltage of Q1 has to increase in order to maintain the same emitter current. If
the change in VCE, of Q1 can be made equal to Vi then the output voltage will remain constant.
Since VCBI =VCEI. We can assume that if Vi dropped across R3, then the output voltage will
remain constant.
The function of a voltage regulator is to provide a stable dc voltage to electronic circuits
and capable of providing substantial output current. Since the element or component used for
voltage regulation is connected across the load, it is called as shunt voltage regulator. There are
two types of shunt voltage regulator
1. Zener diode shunt voltage regulator
2. Transistor shunt voltage regulator
A zener diode is connected in parallel with the load; a resistance (R2) is connected in series with
the zener to limit the current in the circuit. Hence the resistance is called as series current
limiting resistor. The output voltage (Vo) is taken across the load resistance (R1). Since the
reverse bias characteristics of sener diode are used in voltage regulation, the input voltage is
always maintained greater than zener voltage (Vz).
5.3.1 Line Regulation
Line regulation is a measure of the ability of the power supply to maintain its output voltage
given changes in the input line voltage. Line regulation is expressed as percent of change in the
output voltage relative to the change in the input line voltage.
Line regulation = (output voltage at High line input voltage - output voltage at low line input voltage)
x100 (High line input voltage - low line input voltage)
5.3.2 Load Regulation
Load regulation is a measure of the ability of an output channel to remain constant given
changes in the load. Depending on the control mode enabled on the output channel, the load
regulation specification can be expressed in one of two ways In constant voltage mode,
variations in the load result in changes in the output current. This variation is expressed as a
percentage of range per amp of output load and is synonymous with a series resistance. In
constant voltage mode, the load regulation specification defines how close the series resistance
of the output is to 0 ohms - the series resistance of an ideal voltage source.
In constant current mode, variations in the load result in changes to the current through
the load. This variation is expressed as a percentage of range change in current per volt of
change in the output voltage and is synonymous with a resistance in parallel with the output
channel terminals. In constant current mode, the load regulation specification defines how close
the output shunt resistance
is to infinitythe parallel resistance of an ideal current. In fact, when load regulation is
specified in constant current mode, parallel resistance is expressed as 1/load regulation.
Load Regulation can be defined as a percentage by the equation:
Where
FullLoad (EfL) is the load that draws the greatest current (is the lowest specified load
resistance - never short circuit)
MinimumLoad (EnL) is the load that draws the least current (is the highest specified load
resistance - possibly open circuit for some types of linear supplies, usually limited by pass
transistor minimum bias levels)
NominalLoad (EfL) is the typical specified operating load
5.4 Circuit Diagram - Series Voltage Regulator
R3 R4 R1
R2
Fig 5.1 Series Voltage Regulator

5.4.1 Design Specifications Series pass Transistor 2N3055
hfe=20-70
Iemax=15 amperes
Vce=70V
Ie=2 mA
hfe=125-500
ASSUMPTIONS
VL=12.4 V
IL =250 mA
ID=2.5 mA
1=28
2=188
DESIGN
VL/2 = 12.4 / 2 = 6.2 V
VL/IL = 12.4 / 250*10-3 = 49.6
(VL VZ)/ ID = (12.4 6.2) / 2.5* 10-3 = 2.48 K

(2 + )
R1= = (12.4-(0.7 + 6.2))/(2.5*103)=5.5 / 2.5 * 103 = 2.2K
1
VR2=VBE2 + VZ * (R2 / R1+R2)
0.7 + 6.2=12.4 * (R2/ (2.2*10-3 +R2))

R2=2.75 K
I2=(V2+VBE2) / R2 = 6.9 / 2.75 *103 =2.5mA
IE1=(ID+I1 + IL) = (2.5 + 2.5 + 250) mA = 255mA
IB1=IE1 / 1=255 / 28 = 9.107 mA
I3=IB1 + IC2 = 9.107 mA = 19.107 mA

25(0.7+6.2)
R3 = [VINMX (VBE1 + V2)] / I3 = = 947
19.107103
5.4.2 Model Graph
VL VL
Vin = Constant
RLVin
Fig 3.2LOAD REGULATION Fig 3.3LINE REGULATION
5.4.3 PSPICE Simulation for Series Voltage Regulator
Fig 5.4 PSPICE Simulation of Series Voltage Regulator

Fig 5.5 Line Regulation
Fig 5.6 Load Regulation

5.5 Circuit Diagram - Shunt Voltage Regulator
Fig 3.7 Shunt Voltage Regulator

Design
Let lz max = 10 mA, Vz = VL = 5.1 V Load current lL = 50 mA.
Therefore RL = VL= / lL = 5.1 V/ 50 * 10-3 A = 120 RL = 102
RL should be greater than or equal to 102
I1 = IZ + IL
= 10mA + 50 mA I1 = 60 mA
Rs = ( Vi-Vz) / I1 = (7-5.1) / (60*10-3 = 31.66
Rs = 31.66
5.5.1 PSPICE Simulation for Shunt voltage Regulator
Fig 5.8 PSPICE Simulation of Shunt Voltage Regulator
Fig 5.9 Line Regulation
Fig 5.10 Load Regulation

5.6Characteristics
Series Voltage Regulator
This series voltage regulator is suitable only for low output voltages because of the
following reasons
1. With the increase in room temperature, the values of Vbe and Vzener tend to decrease.
Thus the output voltage cannot be maintained a constant. This will further increase the
transistor base emitter voltage and thus the load.
2. There is no option to change the output voltage in the circuit.
3. Due to small amplification process provided by only one transistor(BC147), the circuit
cannot provide good regulation at high currents.
4. The power dissipation of a pass transistor is large because it is equal to VccIc and almost
all variation appears at Vce and the load current is approximately equal to collector current.
Thus for heavy load currents pass transistor has to dissipate a lot of power and, therefore,
circuit becomes hot. So some heat sink is required.
Shunt Voltage Regulator
The series resistor causes a huge amount of power loss.The circuit may have problems regarding
over voltage mishaps.
5.7 Procedure
Connect the circuit as per the circuit diagram.
1. For load regulation characteristics, keep the input voltage constant, find VL for different
values of RL. Plot the graph by taking RL in the axis and VL in the Y axis.
2. For line regulation characteristics, keep RL constant and for different values of input Vin
find VL. Plot the graph by taking Vin in x axis and VL in the y axis
5.8Tabulation
5.8.1 Line regulation RL = ------------()
S. No Vi (V) Vo (V)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10
11
12
5.8.2 Load regulation Vi = ------------ (V)
S.No RL() Vo(V)
1.
2.
3.
4.
5.
6.
5.10 Result
The series and shunt voltage regulator were designed and constructed and the
characteristics were plotted.
1. The regulated output voltage was found to be--------------V
.2. Line regulation was found to be ---------------------
3. Load regulation was found to be ----------------------
5.11Prelab Question
1. What are the three basic elements inside a standard voltage regulator?
2. What device is used as a control element? Why?
3. What are the performance measures of the regulator?
4. What is line regulation and Load regulation What is the efficiency of series voltage regulator
5. List the difference between Series and Shunt Voltage Regulator
5.12 Post Lab Question

1. Design series voltage Regulator in PSPICE and compare with obtaind line and load
regulation curves.
2. With reference to the above circuit (fig 9.4), What will be the output voltage if reference
voltage was short circuited?
3. The 7812 regulator IC provides ________.
a) 5V
b) -5V
c) 12V
d) -12V
4. what will happen if potential divider was open circuited
5. The transistor shunt regulator shown in figure has a regulated output voltage of 10 volts,
when input varies from 20 volts to 30 volts. The relevant parameters for the zener diode and
the transistor are: VZ = 9.5 volts, VBE = 0.3 votls, = 99. Neglect the current throught RB.
Then the maximum power dissipated in the zener diode (PZ) and the transistor (PT) are
EXP 6: BJT CHARACTERISTICS
6.1 Objective
To study the input and output characteristics of a bipolar junction transistor in Common
Emitter configuration and to measure h-parameters
6.2 Hardware Required

1k ohm, 10% tolerance,

04 Ammeter MC (1-30)mA, (0-500)A 1
05 Voltmeter MC (0 1)V, (0 30)V 1
Bread board and

06
connecting wires
6.3 Introduction
Bipolar junction transistor (BJT) is a 3 terminal (emitter, base, collector) semiconductor
device. There are two types of transistors namely NPN and PNP. It consists of two P-N junctions
namely emitter junction and collector junction.
In Common Emitter configuration the input is applied between base and emitter and the
output is taken from collector and emitter. Here emitter is common to both input and output and
hence the name common emitter configuration.
Input characteristics are obtained between the input current and input voltage taking
output voltage as parameter. It is plotted between VBE and IB at constant VCE in CE
configuration.
Output characteristics are obtained between the output voltage and output current taking
input current as parameter. It is plotted between VCE and IC at constant IB in CE configuration.
6.4 Pin Assignment
Fig 6.1. BJT Pin Diagram

6.5 Circuit Diagram
Fig 6.2. Circuit Diagram

6.6 Model Graph
Fig 6.3. Input characteristics Fig 6.4. Output characteristics

6.7 PSPICE Simulation for Common Emitter Transistor
Fig 6.5. PSPICE Simulation
Fig 6.6 Input Characteristics
Fig 6.7 Output Characteristics

6.8 Precautions
1. While doing the experiment do not exceed the ratings of the transistor. This may lead to
damage the transistor.
4. Make sure while selecting the emitter, base and collector terminals of the transistor.
6.9Procedure
6.9.1Input Characteristics
1. Connect the transistor in CE configuration as per circuit diagram
2. Keep output voltage VCE = 0V by varying VCC.
3. Varying VBB gradually, note down both base current IB and base - emitter voltage (VBE).
4. Repeat above procedure (step 3) for various values of VCE
6.9.2 Output Characteristics

1. Make the connections as per circuit diagram.
2. By varying VBB keep the base current I B = 20A.
3. Varying VCC gradually, note down the readings of collector-current (IC) and collector-
emitter voltage (VCE).
4. Repeat above procedure (step 3) for different values of IE

6.10Tabular Column
6.10.1 Input Characteristics
VCE = 0 V VCE = 4V
VBE (volts) IB (mA) VBE (volts) IB (mA)

6.10.2 Output Characteristics
IB = 30 A IB = 60 A
VCE (volts) Ic (mA) VCE (volts) Ic (mA)
6.11 Result
Thus the input and output characteristics of BJT in CE configuration was verified and the
graph was plotted.
a) Impedance (hie) = VBE / IB, VCE constant. =
b) Output admittance (hoe)= Ic / VEC , IB constant=
6.12Prelab Questions
1. Why is base width small?
2. Why is Silicon transistor more commonly used compared to Germanium transistor?
3. What is base width modulation?
4. The junction capacitance across collector to base junction is much lower than that across base to
emitter junction. Why?
5. What is the difference between diffusion capacitance and transition capacitance?
6. What is the voltage across the collector to emitter terminal when the transistor is
in (i) saturation (ii) cut-off (iii) active region?
6.13 Post lab Questions
1. Design a circuit to sketch the input and output characteristics of common emitter
configuration using PSPICE and compare the output with the obtained result .
2. From the above observation find forward current gain and reverse voltage gain.
3. Explain the switching action of a transistor?
4. At what region of the output characteristics, a transistor can act as an amplifier?
5. Design an NPN common emitter transistor to work as a current source. It is in which
region of the transistor?
6. Based on which parameters do we choose a transistor for a particular application?
7. CHARACTERISTICS OF METAL OXIDE SEMICONDUCTOR FIELD
EFFECT TRANSISTORS (MOSFETS) USING PSPICE
7.1 Objective
To perform drain characteristics and transfer characteristics of MOSFET using Pspice
Capture Lite Software.
7.2. Theory
In a MOSFET, current flows from the drain terminal to the source terminal through a
semiconductor channel. The resistance of the channel, and therefore its ability toconduct current,
is controlled by a voltage applied to a third terminal denoted as the gate.MOSFETs can be either
an n-channel type or a p-channel type. In a n-channel MOSFET a positive voltage is applied to
the drain terminal for operation while in a p-channel MOSFET a negative voltage is applied to
the drain terminal for operation. An n-channel and p-channel type MOSFET may be one of two
modes; enhancement mode or depletion mode. The enhancement mode MOSFET is normally
off (in cutoff and conducting no current) when no voltage is applied to the gate and is on (in
saturation and conducting current) when a voltage greater than the gate-to-source threshold is
applied to the gate. The depletion mode MOSFET is normally on (in saturation and
conducting current) when no voltage is applied to the gate and is off (in cutoff and not
conducting current) when a voltage more negative than the gate-to-source threshold is applied to
the gate.
Figure.7.1.symbol of MOSFET
7.2.1 Transfer Characteristics
In most MOSFET applications, an input signal is the gate voltage VG and the output is
the drain current ID. The ability of MOSFET to amplify the signal is given by the output/input
ratio: the transconductance, gm = dID/dVGS with VDS constant
7.2.2 Drain Characteristics

MOSFET operates in three operation mode, Cut-off when VGS<Vt,
Linear mode when VGS> Vth and VDS< ( VGS Vth ) and Saturation when VGS> Vth and VDS( VGS
Vth). Pinch off occurs when VDS= VSat= VGS Vt. The drain resistance , Rd= dVDS/dIDwith
VGSconstant
7.3 Circuit Diagram
M1
Vds
20Vdc
IRF150
Vgs
10Vdc
Figure.7.2 MOSFET Characteristics Circuit diagram.

7.4 Model Graph
7.4.1 Transfer Characteristics: 7.4.2 Drain Characteristics:
Figure 7.4 Characteristics of MOSFET

7.5 PSPICE Simulation for MOSFET Characteristics
Figure 7.4 PSPICE Simulation
Figure 7.5. MOSFET Transfer characteristics
Figure 7.6 MOSFET Drain characteristics

7.6 Handling Precautions
1. When handling power MOS FETs, the man should be ground. And Power MOS FETs,
should be handled by the package, not by the leads.
2. When handling or installing Power MOS FETs into circuits, use metal plates that it
grounded on Work Stations.
3. When testing Power MOS FETs, Test Circuit (Curve tracer, etc.) should be grounded.
4. When using soldering irons, soldering irons should be grounded. (Its better to use battery
operated soldering irons.)
5. When shipping in circuit boards, they should be placed in antistatic bags, unless the gate
and the source are connected by resistors or inductors.
6. Power MOS FETs should be placed not in plastic casesor bags, but in antistatic bags,
conductive foam, or aluminum foil.
7.7 Procedure
7.7.1 Transfer characteristics
1. Connect the MOSFET as per the circuit diagram
2. Keep the VGS =10 V, VDS =20 V
3. Set in the DC sweep primary and secondary values.
4. Place the voltage probe at source of MOSFET and simulate the circuit.
7.7.2 Drain characteristics
2. Keep the VGS =10 V, VDS =20 V
3. Set in the DC sweep primary and secondary values.
4. Place the voltage probe at source of MOSFET and simulate the circuit
7. 8 Result
The drain Characteristics and Transfer Characteristics of MOSFET was simulated using
Pspice , the transconductance = _________ and drain resistance = -------------- was found.
7.9 Pre Lab Questions
1. With the E-MOSFET, when gate input voltage is zero, what is the drain current?
2. When is a vertical channel E-MOSFET used?
3. Compare the input impedance of MOSFET with that of BJT and FET.
4. In MOSFET devices the N-channel type is better the P-channel type. How?
7.10 Post lab
1. In a MOSFET, the polarity of the inversion layer is the same as that of _____________
2. What is the difference between depletion MOSFET and JFET.
Input impedance of MOSFET is
less than of FET but more than BJT.
more than that of FET and BJT.
more than that of FET but less than BJT.

3. What are the three regions of operation in MOSFET?
4. Interpret transfer characteristics from the given drain characteristics for MOSFET.
8. BJT BIASING SCHEMES
8.1 OBJECTIVE
1. To design potential divider bias and fixed bias scheme of a transistor and to understand
the operation of the circuit.
2. To analyze the BJT bias circuit and to determine circuit voltage and current levels.
8.2 HARDWARE REQUIRED
a) Power supply Dual variable regulated low voltage DC source(0-30V,

0-2A)
b) Equipments DMM (Digital Multimeter)
c) Resistors To be calculated
d) Semiconductor BC107 or equivalent
e) Miscellaneous Bread board and wires
8.3 INTRODUCTION
Transistor Biasing is the process of setting a transistors DC operating voltage or current

conditions to the correct level so that any AC input signal can be amplified correctly by the
transistor. A transistors steady state of operation depends a great deal on its base current,
collector voltage, and collector current and therefore, if a transistor is to operate as a linear
amplifier, it must be properly biased to have a suitable operating point
8.4 POTENTIAL DIVIDER BIASING CIRCUIT OPERATION
The voltage divider is formed using external resistors R1 and R2. The voltage across
R2 forward biases the emitter junction. By proper selection of resistors R1 and R2, the operating
point of the transistor can be made independent of . In this circuit, the voltage divider holds the
base voltage fixed independent of base current provided the divider current is large compared to
the base current. However, even with a fixed base voltage, collector current varies with
temperature (for example) so an emitter resistor is added to stabilize the Q-point, similar to the
above circuits with emitter resistor.
Fig. 8.1 Potential divider bias
8.4.1 Analysis
Referring to fig. 8-1,
VB = VCC x R2/ (R1 + R2)
With VB constant, the voltage across the emitter resistor is also a constant quantity,
VE = VB VBE
This means that the emitter current is constant,
IE = (VB VBE )/ RE
The collector current is approximately equal to the emitter current, so IC is held at a constant
level.
IC IE
The collector emitter voltage is
VCE = VC VE
and the transistor collector voltage is
VC = VCC IC RC
VCE can also be determined as
VCE VCC IC (RC + RE)
Clearly with IC and IE constant, the transistor collector emitter voltage remains at a constant
level. It should be noted that the transistor hFE value is not involved in any of the above
equations.
8.4.2 DC load line and the bias point
The DC load line is the load line of the DC equivalent circuit, defined by reducing the
reactive components to zero (replacing capacitors by open circuits and inductors by short
circuits). It is used to determine the correct DC operating point, often called the Q point.
The values of IC and VCE specifies the dc operating point (Q point) and these values are
written as ICQ and VCEQ respectively. For the known values of the components and supply
voltage, we can analytically calculate the operating point.
Another approach to find the Q point is the graphical method. Here, we draw the
straight line (the dc load line) from the above equation on the IC VCE characteristics of the
transistor as shown in Fig. 1-2. After calculating the base current, we identify the curve on the
characteristics. The intersection of the load line with this characteristic curve gives the Q-point.
If the bias current changes, the Q-point will move on the load line because the
characteristic curve will change.
Fig.
8.2
Graphical determination of Q point

8.4.3 Potential divider bias circuit design.
When designing a voltage divider bias circuit the voltage divider current (I2 in Fig. 8-1)
should be selected much larger than the transistor base current IB. This makes the base voltage
VB a stable quantity largely unaffected by the transistor hFE value. However, a high level of I2
result in smaller resistance values for R1 and R2, and this gives the circuit undesirable low input
impedance.
A rule of thumb approach to selection of I2 is to use a voltage divider current

approximately equal to one tenth of the transistor collector current.
I2 = IC / 10
This gives reasonably large values for R1 and R2 while still keeping I2 much large than IB
If VE is not specified, it should be selected much larger than the transistor VBE,
VE >> VBE
This is because VBE can vary from transistor to transistor, and it can also change with
temperature increase or decrease. Making VE very much larger than VBE minimizes the effect
of VBE changes on the circuit bias conditions. Typically, as another rule of thumb, VE is
selected as 5v regardless of the supply voltage. When VCC is low, VE can be as low as 3V.
The equations used for calculating each resistor value are:
R1 = (VCC VB) / I2 RC = (VCC VCE VE )/ IC
R2 = VB / I2 RE VE / IC
8.5 DESIGN PROBLEM
Design the voltage divider bias circuit to have VCE = VE = 5V and IC = 5mA when the
supply voltage is 15V. Assume the transistor hfe is 100.
Design procedure
VE VE 5V
RE 1K (Standard value)
IE I C 5mA
(VCC VCE VE ) 15V 5V 5V
RC 1K (Standard value)
IC 5mA
IC
I2 500
10
VB = VE+VBE = 5V+0.7V = 5.7V
VB 5.7V
R2 11.4K (Use 12K standard value)
I 2 500
BC107
Fig 8.3 Voltage divider bias circuit designed
(VCC VB ) 15V 5.7V

R1 18.6K (use 18k standard value)
I2 500
8.6 FIXED BIAS CIRCUIT OPERATION
BC107
Fig 8.4 Fixed bias circuit

DC Analysis
Applying KVL to the input loop:
VCC = IBRB + VBE
From the above equation, deriving for IB, we get,
IB = [VCC VBE] /RB
The selection of RB sets the level of base current for the operating point. Applying KVL for the
output loop:
VCC = ICRC + VCE
Thus,
VCE = VCC ICRC
In circuits where emitter is grounded,
VCE = VE
VBE = VB
8.7 DESIGN PROBLEM
Design the fixed bias circuit to have VCE = VE = 5V and IC = 50mA when the supply
voltage is 10V. Assume the transistor hfe is 239
8.7.1 Design Procedure
CE 105
= = = 100
50

IB = = 50mA/ 239 = 209 A

10
RB = = = 47K
209 A
BC107
Fig 8.5 Designed Fixed Bias
When the transistor is biased such that IB is very high so as to make IC very high such
that ICRC drop is almost VCC and VCE is almost 0, the transistor is said to be in saturation.
IC sat = VCC / RC in a fixed bias circuit.
8.7.2 Verification
Whenever a fixed bias circuit is analyzed, the value of ICQ obtained could be verified with
the value of ICSat = (VCC / RC) to understand whether the transistor is in active region. In active
region, ICQ = ( ICSat /2)
8.7.3 Load line analysis
A fixed bias circuit with given values of Vcc, Rc and RB can be analyzed (means,
determining the values of IBQ, ICQ and VCEQ) using the concept of load line also. Here the input
loop KVL equation is not used for the purpose of analysis, instead, the output characteristics of
the transistor used in the given circuit.
The method of load line analysis is as below:
1. Consider the equation VCE = VCC ICRC. This relates VCE and IC for the given IB and Rc.
2. Also, we know that, VCE and IC are related through output characteristics, we know that he
equation, VCE = VCC ICRC represents a straight line which can be plotted on the output
characteristics of the transistor. Such line drawn as per the above equation is known as load
line, the slope of which is decided by the value of RC (the load).
8.7.4 Load Line
Fig. 8.6 Graphical Determination of Q point
The two extreme points on the load line can be calculated and by joining which the load
line can be drawn. To find extreme points, first, Ic is made 0 in the equation: VCE = VCC ICRC.
This gives the coordinates (VCC,0) on the x axis of the output characteristics. The other extreme
point is on the y-axis and can be calculated by making VCE = 0 in the equation VCE = VCC
ICRC which gives IC(max) = Vcc / Rc thus giving the coordinates the point as (0, Vcc / Rc). The
two extreme points so obtained are joined to form the load line. The load line intersects the
output characteristics at various points corresponding to different IBs. The actual operating
point is established for the given IB.
8.8 PROCEDURE
a. Connect the components as per the circuit diagram.
b. Calculate the theoretical value applying KVL in both input and output side.
c. Find the practical value of voltages and currents at various point in the circuits,
d. Plot the value in the tabular column.

8.9 TABULATION
Fixed Bias
PARAMETER THEORITICAL VALUE PRACTICAL VALUE
VB
VC
VBE
VCE
IB
IC
Voltage Divider Bias
PARAMETER THEORITICAL VALUE PRACTICAL VALUE
VB
VC
VE
VCE
VBE
IC
IE
8.10 PSPICE Simulation PROCEDURE
1. Open Capture Lite Edition.
2. Go to the File menu and select New Project. Select Analog or Mixed A/D
3. Create a blank project and then click OK.

4. Select Place option from tool bar. Pick and place all the required circuit components by
just clicking on the elements.
5. Connect the components as per circuit diagram using place wire button that is available
in tool bar.
6. Click on each components to give the parameter values as per design. Save the schematic.
7. Create a new simulation profile. Mention the type of analysis and simulate the circuit.
8. Measure the voltages and currents at different points and tabulate the readings
8.11 PSPICE OUTPUT
Fig 8.7 Schematic for Self Bias

Fig 8.8 Schematic for Voltage Divider Bias
8.12 PRELAB QUESTIONS
1. What do you understand by transistor biasing? What is its need?
2. What do you understand by stabilization of Q-point?
3. Define Q-point and explain the concept of dc load line.
8.13 POSTLAB QUESTIONS
1. In the implementation of voltage divider bias (VDB) circuit change the value of R1 to R2
and then to 2R1 and measure the Q-point in each case. Comment on the changes in the Q-
point values.
2. For the voltage divider bias (VDB) circuit implemented in the experiment, answer the
following questions.
Does VC increase or decrease if R1 is increased?
Does IC increase or decrease if (hfe) is reduced?
Does IC increase or decrease if VCC is reduced?
What happens to VCE if the transistor is replaced one with larger (hfe)?
What happens to IC (sat) if is increased?
What happens to VCE if the ground leg of R2 opens?
What happens to VCE if the transistor EB junction fails by becoming open?
What happens to VCE if the transistor EB junction fails by becoming a short
How will VE be affected when replacing the collector resistor with one whose
resistance is at the lower end of the tolerance range?
If the transistor collector junction becomes open, what will happen to VE?
Analyze the circuit to investigate the effect of interchanging the voltage divider
resistors.
8.14 RESULT
Potential divider bias and fixed bias scheme of a transistor was constructed and the circuit
voltage and current levels are determined.
9. MOSFETS BIASING CIRCUITS
9.1 Objective
To perform biasing of MOSFET using Pspice Capture Lite Software.
9.2. Theory
In a MOSFET, current flows from the drain terminal to the source terminal through a
semiconductor channel. The resistance of the channel, and therefore its ability toconduct current,
is controlled by a voltage applied to a third terminal denoted as the gate.MOSFETs can be either
an n-channel type or a p-channel type. In a n-channel MOSFET a positive voltage is applied to
the drain terminal for operation while in a p-channel MOSFET a negative voltage is applied to
the drain terminal for operation. An n-channel and p-channel type MOSFET may be one of two
modes; enhancement mode or depletion mode. The enhancement mode MOSFET is normally
off (in cutoff and conducting no current) when no voltage is applied to the gate and is on (in
saturation and conducting current) when a voltage greater than the gate-to-source threshold is
applied to the gate. The depletion mode MOSFET is normally on (in saturation and
conducting current) when no voltage is applied to the gate and is off (in cutoff and not
conducting current) when a voltage more negative than the gate-to-source threshold is applied to
the gate.
Figure.9.1.symbol of MOSFET
9.2.1 Voltage Divider Bias
voltage divider bias is used to produce DC gate bias voltage greater than VGS(Th).The value of
resistors used in the divider circuit is quite high as E-MOSFET gate draws very little current due
to SiO2 layer.
9.2.2 Drain Feedback Bias
This method is similar to collector feedback bias used with BJT. When MOSFET is conducting,
it has drain current of ID(on) and drain voltage VDS(on) . Since there is no gate current VGS = VDS(on)
If ID increases, VDS will decrease (since larger voltage drop across RL)
ID VDS VGS ID
E-MOSFET Small Signal Model. We find behavior of the device from its characteristics. In E-
MOSFETs we have two characteristics, transfer characteristic and drain characteristic, we will
find model from these characteristics. The equivalent is shown in the figure. Note that Vgs is the
voltage between gate to source open circuit shows that no gate current glows. There is current
source between drain and source ie drain current represented by gm. Vgs Same representation for
both n and p type MOSFETs .
9.3 Circuit Diagram
9.3.1 Voltage Divider bias
VDD
24Vdc
RD
R1 200
100k
M1
IRF150
R2
15k
Figure.9.2 MOSFET Voltage divider bias.

9.3.2 Drain Feedback bias
VDD
24Vdc
RD
4.7k
RG
10Meg
M1
IRF150
Figure.9.3 MOSFET Drain feedback bias.

9.3.3 Design Specifications voltage divider bias and drain feedback bias
R1
Vgs VDS
R1 R2
R2
VG VGS VDD
R1 R2
Vgs VDD VG
15 103
Vg 3
24
100 103
15 10
R1 15 103
R2 100 103
Vgs 24 0.6
Vgs 23.4V
I D K N (V gsVTN ) 2
1(23.4 1.5) 2
I D 0.479mA
9.4 PSPICE Simulation for Voltage divider bias and drain feedback of MOSFET
Figure.9.4 PSPICE simulation of Voltage Divider bias for MOSFET
Figure.9.5 PSPICE simulation of Drain feedback bias for MOSFET

9.5 Procedure
9.5.1 Simulation of Voltage Divider bias
2. Keep the VDS =24 V
3. Set the biasing point.
4. Simulate the circuit voltage divider circuit.
9.5.1 Simulation of Drain feedback bias
2. Keep the VDD =24 V
3. Set the biasing point.
4. Simulate the circuit drain feedback bias circuit.
9.6 Handling Precautions
1. When handling power MOS FETs, the man should be ground. And Power MOS FETs,
should be handled by the package, not by the leads.
2. When handling or installing Power MOS FETs into circuits, use metal plates that it
grounded on Work Stations.
3. When testing Power MOS FETs, Test Circuit (Curve tracer, etc.) should be grounded.
4. When using soldering irons, soldering irons should be grounded. (Its better to use battery
operated soldering irons.)
5. When shipping in circuit boards, they should be placed in antistatic bags, unless the gate
and the source are connected by resistors or inductors.
6. Power MOS FETs should be placed not in plastic cases or bags, but in antistatic bags,
conductive foam, or aluminum foil.
9.7 Result
The drain biasing of MOSFET was simulated using Pspice.
9.8 Pre Lab Questions
1. What is the meaning of voltage divider bias?
2. What is the concept of drain feedback bias?
3. Compare the biasing of MOSFET with JFET.
4. What is the difference E-MOSFET and D-MOSFET?
]9.9 Post lab
1. A very simple bias for a E-MOSFET is called -------------------------
2. What is the different type of biasing in MOSFET?
3. Compare voltage divider bias and drain voltage bias in MOSFET.
EXP 10: BJT & MOSFET SWITCHING
10.a. BJT SWITCHING
10.a.1 Objective:
To study the switching characteristics of a bipolar junction transistor in Common Emitter
configuration.
10.a.2 Hardware Required:
02 Resistance 1k & 5k, 10% tolerance, 1/2 watt rating 1
04 Ammeter MC (1-30)mA, (0-500)A 1
05 Voltmeter MC (0 1)V, (0 30)V 1
Bread board and

06
connecting wires
10.a.3 Introduction:
Bipolar junction transistor (BJT) is a 3 terminal (emitter, base, collector) semiconductor
device. There are two types of transistors namely NPN and PNP. It consists of two P-N junctions
namely emitter junction and collector junction.
In Common Emitter configuration the input is applied between base and emitter and the
output is taken from collector and emitter. Here emitter is common to both input and output and
hence the name common emitter configuration.
When BJT used as an AC signal amplifier, the transistors Base biasing voltage is applied
in such a way that it always operates within its active region, that is the linear part of the
output characteristics curves are used. However, both the NPN & PNP type bipolar transistors
can be made to operate as ON/OFF type solid state switch by biasing the transistors base
differently to that of a signal amplifier.
Solid state switches are one of the main applications for the use of transistor to switch a
DC output ON or OFF. Some output devices, such as LEDs only require a few milliamps at
logic level DC voltages and can therefore be driven directly by the output of a logic gate.
However, high power devices such as motors, solenoids or lamps, often require more power than
that supplied by an ordinary logic gate so transistor switches are used.
The areas of operation for a transistor switch are known as the Saturation Region and
the Cut-off Region. This means then that we can ignore the operating Q-point biasing and
voltage divider circuitry required for amplification, and use the transistor as a switch by driving
it back and forth between its fully-OFF (cut-off) and fully-ON (saturation) regions as shown
below.
The shaded area at the bottom of the curves represents the Cut-off region while the shaded area
to the left represents the Saturation region of the transistor. Both these transistor regions are
defined as:
Cut-off Region
Here the operating conditions of the transistor are zero input base current ( IB ), zero output
collector current ( IC ) and maximum collector voltage ( VCE ) which results in a large depletion
layer and no current flowing through the device. Therefore the transistor is switched Fully-
OFF. The cut-off characteristics circuit diagram shows
The input and Base are grounded ( 0v )
Base-Emitter voltage VBE < 0.7v
Base-Emitter junction is reverse biased
Base-Collector junction is reverse biased
Transistor is fully-OFF ( Cut-off region )
No Collector current flows ( IC = 0 )
VOUT = VCE
Transistor operates as an open switch
Then we can define the cut-off region or OFF mode when using a bipolar transistor as a
switch as being, both junctions reverse biased, VB < 0.7V and IC = 0. For a PNP transistor,
the Emitter potential must be negative with respect to the Base.
Saturation Region
Here the transistor will be biased so that the maximum amount of base current is applied,
resulting in maximum collector current resulting in the minimum collector emitter voltage drop
which results in the depletion layer being as small as possible and maximum current flowing
through the transistor. Therefore the transistor is switched Fully-ON. The saturation
characteristics circuit diagram shows
The input and Base are connected to VCC
Base-Emitter voltage VBE > 0.7v
Base-Emitter junction is forward biased
Base-Collector junction is forward biased

Transistor is fully-ON ( saturation region )
Max Collector current flows ( IC = Vcc/RL )
VCE = 0 ( ideal saturation )
VOUT = VCE = 0V
Transistor operates as a closed switch
Then we can define the saturation region or ON mode when using a bipolar transistor as
a switch as being, both junctions forward biased, VB > 0.7v andIC = Maximum. For a PNP
transistor, the Emitter potential must be positive with respect to the Base.
10.a.4 Circuit Diagram:
Vcc =10 V; RL =1K; Rin =5K
Cut-off Characteristics Saturation Characteristics
10.a.5 Design:
When the input voltage Vin is at the zero level the base current IB is also zero, and consequently,
IC is zero and VCE equals to VCC.
VCE =VCC ( IC RL )
= 10 ( 0 1k )
= 10V
In a switching circuit , IB is made large enough to produce an IC level that cause the voltage drop
across R1 to approximately equal the supply voltage VCC. With IC RL VCC
VCE VCC ( IC RL )
0
IC = ( VCC - VCE(sat)) / RL = (10V 0.2 V ) / 1k = 9.8 mA
Let Vin =5V
IB = ( Vin VBE) / Rin = (5V 0.7 V ) / 5k = 0.86mA
hFE = IC / IB = 9.8 mA/ 0.86mA =11.3
10.a.6 Precautions:
5. While doing the experiment do not exceed the ratings of the transistor. This may lead to
damage the transistor.
8. Make sure while selecting the emitter, base and collector terminals of the transistor.
10.a.7 Procedure:
Cut-off Characteristics
1. Connect the transistor in CE configuration as per circuit diagram.
2. Connect the input and Emitter to ground.
3. Keep VCC = 10V by varying Regulated power supply.
4. Measure the voltage across VCE.
Saturation Characteristics
1. Connect the transistor in CE configuration as per circuit diagram.
2. Connect the input and Base to VCC.
3. Keep VCC = 10V by varying Regulated power supply.
4. Measure the voltage across VCE.
10.a.8 Tabulation:
Cut off Saturation

Characteristics Characteristics
Vin (volts) Vout (volts) Vin (volts) Vout (volts)
10.a.9. Circuit diagram in PSPICE
10.a.10. Netlist:
Q1 0 1 2 Q2N2222
R1 0 1 5k
R2 2 3 1k
Vcc 3 0 dc 10
. print dc v(1) v(2) v(3) v(4)
.end
Q1 0 1 2 Q2N2222
R1 1 3 5k
R2 2 3 1k
Vcc 3 0 dc 10
. print dc v(1) v(2) v(3) v(4)
.end
10.a.11. Result
Thus the switching characteristics of BJT in CE configuration was verified.
10.a.12. Pre Lab Question:

1. Solid-state switching circuits usually keep their constituent transistors in one of two
modes: cutoff orsaturation. Explain what each of these terms means?
2. Explain the function of this light-switching circuit, tracing the directions of all currents
when the switch closes:
3. Trace the directions of all currents in this circuit, and determine which current is larger: the
current through resistor R1 or the current through resistor R2, assuming equal resistor values.
If switch SW2 were opened (and switch SW1 remained closed), what would happen to the
currents through R1 and R2?
If switch SW1 were opened (and switch SW2 remained closed), what would happen to the
currents through R1 and R2?
10.a.13. Post Lab Questions:
1. Calculate all component voltage drops in this circuit, assuming a supply voltage of 15 volts,
an emitter-base forward voltage drop of 0.7 volts, and a (saturated) emitter-collector voltage
drop of 0.3 volts:
2. Draw the necessary wire connections so that bridging the two contact points with
your finger (creating a high-resistance connection between those points) will turn
the light bulb on:
3. Choose the right type of bipolar junction transistor for each of these switching
applications, drawing the correct transistor symbol inside each circle:
10.b. MOSFET SWITCHING
10.b.1 Objective:
To study the switching characteristics of a Metal oxide semiconductor field effect
transistor using Pspice.
10.b.2. Theory:
We now know that there are two main differences between field effect transistors,
depletion-mode only for JFETs and both enhancement-mode and depletion-mode for
MOSFETs. In this experiment we will look at using the Enhancement-mode MOSFET as a
Switch as these transistors require a positive gate voltage to turn ON and a zero voltage to turn
OFF making them easily understood as switches and also easy to interface with logic gates.
The operation of the enhancement-mode MOSFET, or e-MOSFET, can best be described
using its i-v characteristics curves shown below. When the input voltage, ( VIN ) to the gate of
the transistor is zero, the MOSFET conducts virtually no current and the output voltage
( VOUT ) is equal to the supply voltage VDD. So the MOSFET is OFF operating within its
cut-off region.
The minimum ON-state gate voltage required to ensure that the MOSFET remains ON when
carrying the selected drain current can be determined from the v-i transfer curves above.
When VIN is HIGH or equal to VDD, the MOSFET Q-point moves to point Aalong the load line.
The drain current ID increases to its maximum value due to a reduction in the channel
resistance. ID becomes a constant value independent of VDD, and is dependent only on VGS.
Therefore, the transistor behaves like a closed switch but the channel ON-resistance does not
reduce fully to zero due to its RDS(on) value, but gets very small.
Likewise, when VIN is LOW or reduced to zero, the MOSFET Q-point moves from point A to
point B along the load line. The channel resistance is very high so the transistor acts like an open
circuit and no current flows through the channel. So if the gate voltage of the MOSFET toggles
between two values, HIGH and LOW the MOSFET will behave as a single-pole single-throw
(SPST) solid state switch and this action is defined as:
Cut-off Region
Here the operating conditions of the transistor are zero input gate voltage ( VIN ), zero drain
current ID and output voltage VDS = VDD. Therefore for an enhancement type MOSFET the
conductive channel is closed and the device is switched OFF. The cut-off characteristics
circuit diagram shows
The input and Gate are grounded ( 0v )
Gate-source voltage less than threshold voltageVGS < VTH
MOSFET is OFF ( Cut-off region )
No Drain current flows ( ID = 0 )
VOUT = VDS
MOSFET operates as an open switch
Then we can define the cut-off region or OFF mode when using an e-MOSFET as a switch as
being, gate voltage, VGS < VTH and ID = 0. For a P-channel enhancement MOSFET, the Gate
potential must be more positive with respect to the Source.
Saturation Region
In the saturation or linear region, the transistor will be biased so that the maximum amount of
gate voltage is applied to the device which results in the channel resistanceRDS(on being as small
as possible with maximum drain current flowing through the MOSFET switch. Therefore for the
enhancement type MOSFET the conductive channel is open and the device is switched ON.
The Saturation characteristics circuit diagram shows
The input and Gate are connected to VDD
Gate-source voltage is much greater than threshold voltage VGS > VTH
MOSFET is ON ( saturation region )
Max Drain current flows ( ID = VDD / RL )
VDS = 0V (ideal saturation)
Min channel resistance RDS(on) < 0.1
VOUT = VDS = 0.2V due to RDS(on)
MOSFET operates as a low resistance closed switch
Then we can define the saturation region or ON mode when using an e-MOSFET as a switch
as gate-source voltage, VGS > VTH and ID = Maximum. For a P-channel enhancement MOSFET,
the Gate potential must be more negative with respect to the Source.
10.b.3. Circuit Diagram:
10.b.4 Netlist:
R1 1 0 5k
R2 2 3 1k
VDD 3 0 dc 10V
M1 1 2 0 0 IRF150
. print dc v(1) v(2) v(3) v(4)
.end
R1 1 3 5K
R2 2 3 1k
VDD 3 0 dc 10V
M1 1 2 0 0 IRF150
. print dc v(1) v(2) v(3) v(4)
.end
10.b.5 Result
Thus the switching characteristics of MOSFET using Pspice was verified
10.b.6. Pre Lab Question:

1. What is the computational the value of drain current for gate-to-source voltage (VGS ) of
about 6V in the below drawn schematic diagram of E-MOSFET along with ID(ON) = 2mA at
VGS & VGS(threshold) of about 12V & 4V respectively?
a. 1 mA
b. 2 mA
c. 3 mA
d.4 mA
2. Which mode is produced by a positive swing in gate-to-source voltage by input ac signal with
the maximum voltage drop across load resistor in DE-MOSFET amplifier circuit?
a. Depletion mode with decrease in drain current

b. Enhancement mode with decrease in drain current
c. Depletion mode with an increase in drain current
d. Enhancement mode with an increase in drain current
3. FETs are widely applicable in oscilloscopes and voltmeters as an input amplifier as compared
to bipolar transistors due to ______.
a. ability of minimizing the loading effect with high input resistance

b. ability of maximizing the loading effect with high input resistance
c. ability of minimizing the loading effect with low input resistance
d. ability of maximizing the loading effect with low input resistance
10.b.7. Post Lab Questions:
1. How does the FET operate before the pinch-off region with small value of drain-to-source
voltage in accordance to the control of drain-to-source resistance by the bias voltage?
2. Which mode is produced by a positive swing in gate-to-source voltage by input ac signal with
the maximum voltage drop across load resistor in DE-MOSFET amplifier circuit?
a. Depletion mode with decrease in drain current

b. Enhancement mode with decrease in drain current
c. Depletion mode with an increase in drain current
d. Enhancement mode with an increase in drain current
3. FETs are widely applicable in oscilloscopes and voltmeters as an input amplifier as compared
to bipolar transistors due to ______.
a. ability of minimizing the loading effect with high input resistance

b. ability of maximizing the loading effect with high input resistance
c. ability of minimizing the loading effect with low input resistance
d. ability of maximizing the loading effect with low input resistance.
EXP 11.a: CHARACTERISTICS OF PHOTOCONDUCTIVE CELL, LIGHT EMITTING
DIODE
11.1 Objective:
To study and verify the characteristics of
(i) Photoconductive cell (LDR),
(ii) Light Emitting Diode (LED).

1 Resistors 1K,330 1
(0-30V), 2A Rating
2 Regulated power supply (0-5V) 1
3 LDR 1
4 LED Red, Green, Yellow
5 Ammeter MC (0-30)mA;(0-100)mA 1
6 Voltmeter MC (0-10)V 1
Bread board and connecting
7 1
Wires
11.3 Introduction
11.3.1 Photoconductive Cell (LDR)
Photoconductive cells are light-sensitive resistors in which resistance decreases with an
increase in light intensity when illuminated. These devices consist of a thin single-crystal or
polycrystalline film of compound semiconductor substances. Most commercially available
photoconductive cells are manufactured from cadmium sulfide (CdS), which is sensitive to light
in the visible spectrum. Other materials that are less commonly used in photoconductive cells
include lead sulfide (PbS), lead selenide (PbSe), and lead telluride (PbTe), although they react to
infrared light, not the visible spectrum.
CdS photoconductive cells (CdS cells) are often referred to as light dependant resistors
(LDR). They function within the same general spectral range as the human eye, and are therefore
widely used in applications where this type of spectral response is required.
When light of suitable frequency falls on the device, the photogeneration of charge
carriers reduces the resistance of the device and this property of LDR can be used to control the
current flow in a circuit.
11.3.2 Light Emitting Diode

A Light emitting diode is essentially a pn junction diode typically made from a direct
bandgap semiconductor such as GaAs in which the electron hole pair formation result in the
emission of photon. The emitted photon energy is approximately equal to the band gap energy.
In LED, the n side is more heavily doped compared to the p side and a forward bias
result in heavy injection of electrons to the p side which are minority carriers on this side. The
recombination of injected electrons in the depletion as well as in the neutral p side result in the
spontaneous emission of photons. The phenomenon of light emission from EHP recombination
as a result of minority carrier injection is called injection electroluminescence.
The photon energy determines the wavelength of the emitted light, and hence its color.
Different semiconductor materials with different bandgaps produce different colors of light. The
main semiconductor materials used to manufacture LEDs are Indium gallium nitride
(InGaN)( blue, green and ultraviolet high-brightness LEDs), Aluminum gallium indium
phosphide (AlGaInP-yellow, orange and red high-brightness LEDs) Aluminum gallium arsenide
(AlGaAs)-red and infrared LEDs), Gallium phosphide (GaP-yellow and green LEDs) etc.

11.4.1 LDR
Figure11a.1: Characteristics of LDR

11.4.2 Light Emitting Diode
Figure11a.2: Characteristics of LED
11.5 Tabular Column :
11.5.1 LDR
SI No Distance (cm) Voltage (V) Current (mA) Resistance(K)

11.5.2 LED
Red LED Yellow LED Green LED
SI. SI. SI.
No Voltage(V) Current(mA) No Voltage(V) Current(mA) No Voltage(V) Current(mA)
11.6 Characteristics of LDR, LED

11.6.1 LDR
1. Sensitivity: The sensitivity of LDR varies with the light wavelength.If the wavelength is
outside a certain range it will not affect its resistance at all.LDR has a lower light
sensitivity compared to photodiodes and phototransistors
2. Latency: There is a time latency between changes in illumination and changes in
resistance. It usually takes about 10 ms for resistance to drop completely when light is
applied after total darkness.
3. Photoresistor is a passive component and does not have a PN-junction. The
photoresistivity may vary depending on ambient temperature, making them unsuitable
for applications requiring precise measurement of sensitivity to light.
11.6.2 LED
1. The actual colour of a light emitting diode is determined by the wavelength of the light
emitted, which in turn is determined by the actual semiconductor compound used in
forming the PN junction during manufacture.
2. The commercially used LEDs have a typical voltage drop between 1.5 Volt to 2.5 Volt
or current between 10 to 50 milliamperes. An illumination-grade LED containing a single
semiconducting element requires the same voltage, but operating currents are much
higher, typically several hundred milliamperes.
3. LEDs require a specific electrical polarity. Applying voltage in reverse polarity can
destroy them. 5 volts is a typical maximum reverse voltage rating.
4. The forward resistance of the device is very low. Hence LED is always connected with
an external series current limiting resistor. Series resistance is determined by the
following equation,
Rs= (Vsupply-V)/I
Where, V is the voltage drop across the LED.
11.7 Precautions:
1. While doing the experiment do not exceed the ratings of the diode. This may
lead to damage the diode.
11.8 Procedure:
11.8.1 LDR:
1. Connect circuit as shown in figure 11.4.1.
2. Keep light source at a distance and switch it ON, so that it falls on the LDR
3. Note down current and voltage in ammeter and voltmeter.
4. Vary the distance of the light source and note the V & I.
5. Sketch graph between R as calculated from observed V and I and distance of light source
11.8.2 LED
1. Give the connection as per the figure 11.4.2.
2. Vary the input voltages at the RPS and note down the corresponding current for the
voltages.
3. Repeat the procedure for reverse bias condition and tabulate the corresponding voltages
and currents.
4. Plot the graph between voltage and current for forward bias and reverse bias.
11.9 Model Graph:
LDR
Figure11a.3: Characteristics of LDR
LED
Figure11a.4: V-I Characteristics of LED

11.10 Result:
Thus the characteristics of LDR and LED are studied and verified.

1. List a few applications of LDR.
2. Give the properties of the materials used for LDR.
3. List a few limitations of LDR.
4. Define the active region in an LED.
5. Give the energy band diagram of an LED.
1. Draw the V-I characteristics of LDR as a function of light intensity.
2. Explain why silicon cannot be used to manufacture LED.
3. Give suitable materials for blue LED and compare their efficiencies.
4. Calculate the wavelength of light emitted by a GaAs LED.
EXP 11.b: CHARACTERISTICS OF SOLAR CELL
11b.1 Objective:
To study the characteristics of a silicon photovoltaic cell in dark and under illuminance.
11b.2 Hardware Required
11b.3 Introduction
A solar cell (or a "photovoltaic" cell) is a device that converts photons from the sun
(solar light) into electricity.The conversion involves the photogeneration of charge carriers
(electrons and holes) in a light-absorbing material, and separation of the charge carriers to a
conductive contact that result in the flow of these photo generated charge carriers through an
external load.
The photovoltaic cell has a p-n structure with a narrow n region through which light
enters the device. Mostly the photons that are absorbed close to the depletion region result in
photogenerated carriers that are separated by the barrier potential across the pn junction and
constitute current in the external circuit.
The solar cell efficiency refers to the fraction of incident light energy converted to
electrical energy. For a given solar spectrum, this efficiency depends on the semiconductor
material properties and device structure. Most solar cells are silicon based and the efficiency
ranges from about 18% for polycrystalline to 22-24% in high efficiency single crystal devices.
In dark, the V-I characteristics lie in quadrants I and III and the current that flows is,
I=I0[exp(qV/kT)
Under illumination the curve is shifted such that the curve lies in quadrants I,III and IV. The
current in this case is,
I=I0[exp(qV/kT)-Iph
where, Iph is the light induced current and depends on the intensity of illumination.
11b.4 Characteristics of Solar cell

1. Open circuit voltage: It is measured by measuring voltage across the terminals of the cell
when no load is connected to the cell. Normally open circuit voltage of solar cell nearly
equal to 0.5 to 0.6 volt. It is normally denoted by Voc.
2. Short circuit current:The maximum current that a solar cell can deliver without harming
its own constriction. It is measured by short circuiting the terminals of the cell at most
optimized condition of the cell for producing maximum output. It is normally denoted as
Isc.
3. Maximum Power point: The maximum current that a solar cell can deliver without
harming its own constriction. It is measured by short circuiting the terminals of the cell at
most optimized condition of the cell for producing maximum output.
4. Fill factor:The ratio between product of current and voltage at maximum power point to
the product of short circuit current and open circuit voltage of the solar cell.
5. Efficiency: It is defined as the ratio of maximum electrical power output to the radiation
power input to the cell and it is expressed in percentage.
11b.5 Precautions:
4. While doing the experiment do not exceed the ratings of the device. This may
lead to damage the device.
7. Photovoltaic (PV) modules generate electricity when exposed to light, even when they are
not connected in a circuit. Shocks and burns can result from contacts with output wiring
and module itself.
8. Cover PV module front surfaces completely with an opaque cloth or other opaque material
before performing any operation involving the module or electrical connections. Use
appropriate safety equipment (insulated tools, insulating gloves, etc.) and procedures.
11b.6 Circuit diagram:
Figure 11b.1: 4 Quadrant power supply schematic with solar cell connected as load, Figure
11b.2: Solar cell as a source of power with a variable load resistor R.
11b.7 Procedure
The solar simulator housing has two cells. In order to use a single cell, connections have to be
made as shown.
Figure11b.3: Solar simulator housing connections

This allows to measure the solar cell kept on the left in the housing.
11b.7.1 Measurement using 4 quadrant power supply with solar cell as load
i) To connect cell to 4quadrant power supply, keep DPDT switch S in the EXT position.
ii) Connect the power supply to the leads of the solar cell , brought out on right side of the
lamp/ solar cell housing.
iii) Cover the solar cells with black cloth for measuring IV in the dark. Keep the lamps off and
shut the door in front of the housing.
iv) Measure IV by gradually turning the bias voltage knob located on the left side of the 4
quadrant supply (the right side knob should be kept in the extreme clockwise position and
should not be moved during the experiment).
The applied bias voltage (in volts) is read on the meter on the left. The meter on the right
measures the current in amperes. Measure IV over bias voltage from 0.7 V to +0.7 V.
v) Remove the black cloth and take it out of the box. turn on the fan. turn on the two lamp
switches l1 and l2.
vi) Adjust the bias voltage knob on the 4 quad supply till the current shows zero reading. With
this adjustment, the voltmeter reads open circuit voltage Voc. Wait until the reading
becomes stable (Vocreading will decrease initially because of rise of cell temperature due to
heat from the lamps).
When reading becomes stable, measure IV characteristics by gradually varying the biasvoltage
from 0.7 V to + 0.7 V.
vii) Turn off the lamps and turn the bias voltage knob till the voltage is zero.
11b.7.2 Measurement using solar cell as power source under illumination
For this measurement, meters on the simulator panel will be used. Change the position the
DPDT switch S to INT.
i) There are two potentiometers. Turn them both clockwise so that resistance is maximum.
ii) Turn on the fan. Turn on the two lamp switches L1 and L2.
iii) See the reading on temperature indicator. Wait (a few minutes) till the temperature
reading stabilizes.
iv) Note the readings on current meter and voltmeter. This condition is close to the open circuit
condition; voltage will be high and current low.
v) Reduce resistance by turning 0100 ohm potentiometer anticlockwise. This is a 10turn

potentiometer. Take readings of V and I as R is varied.
vi) After the 100 ohm pot reaches the minimum setting (fully anticlockwise), turn 0 10 ohm
potentiometer gradually anticlockwise and record IV readings.
vii) 10 ohm pot is single turn. Once it reaches the minimum setting, current will be the highest
and voltage is the minimum. This condition is close to short circuit.
After reaching the minimum of the two pots and recording the readings, set the 10 ohm pot to
maximum (fully clockwise). Then set the 100 ohm pot also to the maximum (fully clockwise).
Check the voltmeter reading. If it is the same as noted in the beginning of the measurement, this
checks that the temperature did not change during the above measurements.
11b.8 Tabular Columns
V-I characteristics in dark V-I characteristics under illumination
SI Voltage (mV) Current(mA) SI Voltage (mV) Current(mA)
No. No.

11b.9 Model Graph
Figure11b.4: V-I characteristics of solar cell
Figure11b.5: Characteristics of solar cell as power source

11b.10 Result
The characteristics of a silicon solar cell has been studied in dark and under illuminated
conditions.
11b.11 Pre- Lab Questions
1. How does a photovoltaic cell differs from a photo detector?

2. Compare the efficiency of amorphous and crystalline Si cells.
3. Define open circuit voltage of a solar cell.
4. Define fill factor.
11b.12 Post Lab Questions
1. Draw the VI characteristics of a solar cell as a function of light intensity.

2. Why a 4 Quadrant power supply is required to measure the characteristics under
illumination?
3. Why is it required that in a solar cell most of the photon absorption should take place
close to the depletion region?

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EXP 1 P-N DIODE CHARACTERISTICS

01 PN Junction Diode 1N4001 1

1k ohm, 10% tolerance,

03 Regulated power supply (0 30V), 2A Rating 1

04 Ammeter MC (0-30)mA, (0-500)A 1

06 Bread board and

1.4 Circuit diagram:

1.6 Characteristics of PN junction diode:

forward current (If).

1.8 Tabular column:

1.8.2 Reverse Bias:

1.10 Model Graph:

iii. Dynamic forward Resistance rac = (Vf/If)

iv. Static Reverse Resistance Rdc = (Vr/Ir)

v. Dynamic Reverse Resistance rac = (Vr/Ir)

1.12 Prelab Questions:

(a) Determine the doping of N and P-regions

2.2 Hardware Required:

01 Zener Diode IZ 6.2 1

2.4.2 Reverse Bias

2.4.3 Zener Diode Symbol:

2.6 Characteristics of Zener Diode:

of forward Current (If).

2.7.2 Reverse biased condition:

2.8.2 Reverse Bias:

2.12Pre lab Questions:

2.13 Post lab Questions:

3. What happens when the Zener diodes are connected in series?

4. Justify the use of zener diode in a stabilization circuit?

(6-0-6 )V, 500mA, 1A

470 ohm, 10% tolerance,

Bread board and 1

3.3 Half wave rectifier

Ripple factor (Theoretical)

Ripple Factor(practical) where

Ripple Factor (Theoretical)

3.7 Simulation graph for Half wave rectifier without filter

3.8 Pspice circuit diagram for Half Wave Rectifier(with filter)

3.10 Full wave rectifier

Transformer Utilization Factor

Ripple factor (Theoretical) =

Ripple Factor (Practical)

Ripple factor (Theoretical)

3.12 Circuit Diagram

3.13 MODEL GRAPH:

3.15 Pspice circuit diagram for Full Wave Rectifier(with filter)

3.16 Simulation graph for full wave rectifier (with filter)

3.18Simulation graph for full wave rectifier (with filter)

3.19 Bridge rectifier:

The maximum efficiency of a Full Wave Rectifier is 81.2%

3.22 Model Graph:

3.25 simulation graph for full wave bridge rectifier(without filter)

3.29 Prelab Questions:

1. What is the PIV of rectifier circuits?

3.30 Post lab Questions:

Also, mark the polarity of the voltage drop across Rload.

4.2 Hardware Required:

S. No Apparatus Type Range Quantity

01 PN Junction Diode IN4001 1