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    2E6 - Tutorial 2: Weeks 4,5 Michaelmas Term 2003

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    thareenda
    This document contains two tutorial questions about designing combinational logic circuits. Question 1 asks the student to minimize a logic expression using a K-map, draw the circuit, and calculate propagation delay. Adding a "don't care" condition allows further simplification. Question 2 asks the student to design a circuit that divides or multiplies a 4-bit binary number by 210 depending on if the number is even or odd. The student is asked to provide a truth table, minimized logic expressions, and circuit implementation using logic gates.

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    2E6 - Tutorial 2: Weeks 4,5 Michaelmas Term 2003

    Uploaded by

    thareenda
    16 views4 pages
    This document contains two tutorial questions about designing combinational logic circuits. Question 1 asks the student to minimize a logic expression using a K-map, draw the circuit, and calculate propagation delay. Adding a "don't care" condition allows further simplification. Question 2 asks the student to design a circuit that divides or multiplies a 4-bit binary number by 210 depending on if the number is even or odd. The student is asked to provide a truth table, minimized logic expressions, and circuit implementation using logic gates.

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    This document contains two tutorial questions about designing combinational logic circuits. Question 1 asks the student to minimize a logic expression using a K-map, draw the circuit, and calculate propagation delay. Adding a "don't care" condition allows further simplification. Question 2 asks the student to design a circuit that divides or multiplies a 4-bit binary number by 210 depending on if the number is even or odd. The student is asked to provide a truth table, minimized logic expressions, and circuit implementation using logic gates.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    16 views4 pages

    2E6 - Tutorial 2: Weeks 4,5 Michaelmas Term 2003

    Uploaded by

    thareenda
    This document contains two tutorial questions about designing combinational logic circuits. Question 1 asks the student to minimize a logic expression using a K-map, draw the circuit, and calculate propagation delay. Adding a "don't care" condition allows further simplification. Question 2 asks the student to design a circuit that divides or multiplies a 4-bit binary number by 210 depending on if the number is even or odd. The student is asked to provide a truth table, minimized logic expressions, and circuit implementation using logic gates.

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    2E6 Tutorial 2

    Weeks 4,5 Michaelmas Term 2003

    Q1
    a) Using a Karnaugh map obtain a minimal sum-of-products expression for f.

    XY

    Z
    00 01 11 10

    0 1 1 1 0

    1 1 0 0 1

    f = X .Y + Z .Y + Y . Z

    b) Sketch the circuit and count the number of gates used.

    X
    Y

    f
    Z

    7 gates used.

    c) What is the propagation delay for the output f. Assume logic gates have the propagation delays given
    in the table below.

    30ns.
    d) It is decided that the input combination X=1, Y=0 and Z=0 will never occur. How
    will the truth table change? Use a Karnaugh map to obtain a minimal sum of
    products expression for the new circuit.

    If it will never occur then the output for that line will change from 0 to X (a dont care
    condition).
    XY

    Z
    00 01 11 10

    0 1 1 1 X

    1 1 0 0 1

    f = Z +Y

    e) Sketch the new circuit and count the number of gates used. What was the effect of
    adding the dont care?

    Z
    f
    Y

    Only 3 gates required.

    Adding the dont care makes the circuit much smaller.


    Q 2. Design a combinational logic circuit which will accept a 4-bit binary number and:
    If the number is even, divide it by 210 and produce the binary result.
    If the number is odd, multiply it by 210 and produce the binary result.

    a) Sketch a truth table showing the state of the outputs for each input combination.

    D is the least significant digit, A is the most significant.

    ABCD Decimal Output F4 F3 F2 F1 F0


    0000 0 0 0 0 0 0 0
    0001 1 2 0 0 0 1 0
    0010 2 1 0 0 0 0 1
    0011 3 6 0 0 1 1 0
    0100 4 2 0 0 0 1 0
    0101 5 10 0 1 0 1 0
    0110 6 3 0 0 0 1 1
    0111 7 14 0 1 1 1 0
    1000 8 4 0 0 1 0 0
    1001 9 18 1 0 0 1 0
    1010 10 5 0 0 1 0 1
    1011 11 22 1 0 1 1 0
    1100 12 6 0 0 1 1 0
    1101 13 26 1 1 0 1 0
    1110 14 7 0 0 1 1 1
    1111 15 30 1 1 1 1 0

    b) Using Boolean algebra or Karnaugh maps, find a simplified sum of products


    expression for each output.

    F4 = AD F3 = BD
    F2 = CD + AD
    F1 = B + D

    F0 = C D

    c) Sketch an implementation of the circuit which uses AND, OR or NOT gates.

    A B C D

    F4

    F3

    F2

    F1

    F0

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