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Uvm Transaction Recording

- The current UVM transaction recording scheme provides basic functionality but has limitations. It only records limited data for each transaction and does not support automatic recording of transactions for non-sequencer components. - The paper proposes enhancements to the UVM transaction recording scheme to address these limitations. It suggests recording more debugging information for each transaction and a better scheme to automatically record transactions from non-sequencer components. It also explores using the more complete trace for advanced visualization and debugging.

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0% found this document useful (0 votes)
337 views11 pages

Uvm Transaction Recording

- The current UVM transaction recording scheme provides basic functionality but has limitations. It only records limited data for each transaction and does not support automatic recording of transactions for non-sequencer components. - The paper proposes enhancements to the UVM transaction recording scheme to address these limitations. It suggests recording more debugging information for each transaction and a better scheme to automatically record transactions from non-sequencer components. It also explores using the more complete trace for advanced visualization and debugging.

Uploaded by

nvenkatesh485
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© © All Rights Reserved
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UVMTRANSACTIONRECORDINGENHANCEMENTS

RexChen(rex_chen@springsoft.com),BindeshPatel(bindesh_patel@springsoft.com),JunZhao
(jun_zhao@springsoft.com)

Research&Development,SpringSoft,Inc.,Hsinchu,Taiwan

INTRODUCTION
SystemVerilogprovidesacompellingadvantageinaddressingtheverificationcomplexitychallenge
notsimplyasanewlanguagefordescribingcomplexstructures,butasaplatformfordrivinga
moreefficient,realistictestofthedesign.Itisnosurprisethenthattheadoptionofthelanguagefor
verificationpurposeshasbeenrapid.Alongwiththisgrowth,methodologieslikeVMM/OVMhave
beendevelopedtohelpverificationengineerstocreatetestbenchesefficientlyandwithmaximum
reuseandaconsistentwelldocumentedmethodology.However,theneedforinteroperability
amongverificationlibrarieshasbecomeacriticalissueforuserstointegratetestbenchcode
(usuallyintheformofVerificationIP)developedusingdifferentmethodologies.Thishasmotivated
anewmethodology,UniversalVerificationMethodology(UVM),tobedevelopedundertheauspices
ofAccellerafortheexpressedpurposeoffosteringuniversalverificationIPinteroperability.Ledby
electronicscompaniesandsupportedbyasuiteofcompaniesrepresentingthebreadthofthe
verificationecosystem,theUVMwillincreaseproductivitybyeliminatingexpensiveinterfacingthat
slowsverificationIPreuse.

Attheoutset,UVMprovidestheinfrastructureforatransactionrecordingschemeusingsocalled
hooksfunctionsthatcanbeimplementedbytheuserorathirdpartytorecordthetransactions
occurringinthetestbenchintosomedatabase.Thiscouldbeassophisticatedasaspecialized
debugdatabaseorassimpleasatextfile.Whilethisprovidesutilityfordebug,therearesome
limitationsinthecurrenttransactionrecordingschemeprovidedinUVM.Firstly,thecurrent
recordeddataisnotenoughforamorecompleteandefficientdebuggingview.Secondly,the
automaticrecordingfornonsequencersisclearlylackingwhencomparedtowhatispossiblefor
sequencers.Usersorthirdpartieswhowanttoovercometheselimitationshavetomodifythe
overallUVMlibrarywhichcausesunnecessaryintrusionontheusersflow.Soweproposea
convenientnonintrusiveenhancementtoUVM,sothatusersorthirdpartiescanutilizethe
enhancedrecordingwithouthavingtotouchtheUVMlibrary.Forbettervisibilityandefficiency,we
proposemoredebugginginformationtoberecordableforeachtransaction.Wealsoproposea
betterschemetorecordtransactionsfornonsequencers.

ThispaperproposestheseenhancementsforUVMtransactionrecording.Itfurtherexplores
potentialvisualizationanddebugfrontendstoleverageamorecompletecapturedtrace.

KEYWORDS
SystemVerilog,UVM,OVM,Transactions,UML,SequenceDiagram
THECURRENTUVMTRANSACTIONRECORDINGSCHEME
AverificationenvironmentbuiltontopofUVMdoesnotprovideanycapabilitytorecord
transactionsinanyformatbydefault.However,itdoesprovideahooksfunctionscapabilityfor
thirdpartiesoruserstorecordthedatatosomespecificformat.Theserelatedhooksfunctionsare
listedbelow:
uvm_create_fiber
Givenaname,createastreamwithtransactions.
uvm_set_index_attribute_by_name
Notused.
uvm_set_attribute_by_name
Addanamedattributetothistransaction.Thisisinvokedbyuvm_component::end_tr().For
monitoranddriver,userhastocallthisAPImanually.
uvm_check_handle_kind
Returnthetypeofhandle.Legaltypesare'Stream',`Fiber`and'Transaction'.
uvm_begin_transaction
Returnahandletoanewtransaction.Thenewtransactionhasavarietyofproperties:
Itbelongstoa'stream
Ithasaname
Itstartseithernoworatbegin_time,ifbegin_timeisnonzero
uvm_end_transaction
Givenanopentransactionhandle,endit.Ifend_timeisnonzero,thenendthetransactionat
end_time.
uvm_link_transaction
Giventwotransactionhandles,createa"relationship"betweenthem
uvm_free_transaction_handle
Givenatransactionhandle,releasestorageforit.Callingfree_transaction_handle()means
thatthehandleisnolongertobeusedanywhere.

Thesefunctionsareemptyintheoriginaluvm_misc.svfile.Thatis,thereisnoimplementationand
aremeantforusersorthirdpartiestoimplementaspertheirrequirements.Vendorsoruserscan
determinehowtostoretherecordedtransactions.Forexample,ifauserwantstorecordthe
transactionsintoatextfile,hecanimplementthefollowingfunctionsaslisted:
uvm_create_fiber:
Generateandreturnthestreamhandle.Logthestreamnameintothetextfile.
uvm_set_index_attribute_by_name:
Calluvm_set_attribute_by_name().
uvm_set_attribute_by_name
Logtheattributename,value,radix,andnumberofbitsintothetextfile.
uvm_check_handle_kind:
Returnthetypeofhandle.Thetypeofhandlecouldbestreamortransaction.
uvm_begin_transaction
Logthetransactionnameandbegintimeoftransactionintothetextfile.
uvm_end_transction:
Logthetransactionnameandendtimeoftransactionintothetextfile
uvm_link_transaction:
Logthenamesoftwotransactionsandtheirrelationshipintothetextfile.
uvm_free_transaction_handle
Logthefreedtransactionhandle.

UsuallythesefunctionimplementationsarewrittenintoaSystemVerilogfile.Letssaythefilename
ishooks.sv.
Now,toenableautomaticrecordingoftransactions,theuserwouldhaveto:
1. Includethetransactionhookfilehook.svinuvm_misc.sv.
2. Enabletransactionrecordinginthebuildfunctionoftestbyadding:
set_config_int("*","recording_detail",UVM_FULL);
3.Compilethedesignandrunsimulation

Thissocalledhooksmechanismonlyrecordstransactionsfromsequencersautomaticallywhen
usersturnontherecordingscheme.Torecordthetransactionsfromothercomponentslikedrivers
ormonitors,usershavetoadduvm_component::begin_tr()anduvm_component::end_tr()intheir
testbenchcode.

Figure2showsthewaveformviewrealizationofrecordingUVMtransactionsintoadebug
databaseusingthecurrentrecordingschemeprovided.

DISADVANTAGESOFTHECURRENTUVMTRANSACTIONRECORDINGCAPABILITIES
BasedonthecurrentrecordingschemeprovidedinUVM,thefollowinginformationisrecorded:
Stream(thecollectionofrelatedtransactions)name,scope
Transactionname,beginandendtime
Attributenameandvalue
Relationbetweensubsequenceandsequence

Whilethisinformationisuseful,thecurrentrecordedinformationisnotsufficientforefficient
debugging.LetsillustratethisusingtherecordingresultoftheXBusexampleintheUVMlibrary.
Figure1showsthearchitectureoftheXbusexample.
Figure1:XBusDemoArchitecture

Thexbus_envcomponentcontainsanynumberofXBusmasterandslaveagents.Intheexample
showninFigure1,thexbus_envisconfiguredtocontainjustonemasterandoneslaveagent.The
xbus_master_andxbus_slave_agentarestructuredidenticallywiththeonlydifferencebeingthe
protocolspecificfunctionofitssubcomponents.TheXBusmasteragentcontainsuptothree
subcomponents:thesequencer,driver,andmonitor.Bydefault,allthreearecreated.
Figure2:TherecordingresultofXBusexamplebeforeenhancements

Figure2showsthetransactionrecordingresultoftheXBusexamplebeforetheenhancementsthat
willbeproposedlaterinthisdocument.Thexbus[0]#master[0]#sequencerstreamcontainsthe
sequenceread_modify_write_seqbecausethecomponentxbus[0]#master[0]#sequencersends
thesequenceread_modify_write_seq.Thesequenceread_modify_write_seqconsistsofthree
subsequences:read_byte_seq0,write_byte_seq0,andread_byte_seq0.Assuch,theyhavea
parentchildrelationship.Eachsubsequencecontainsonesequenceitemreq.Theattributesand
valuesofsequenceitemreqareallrecordedanddisplayedasatrributes.Forthereq(60,60)
sequenceitem,itsbeginandendtimeis60and60respectively.Theattributesofreq(60,60)have
thefollowingvalues:
addr=12
read_write=READ
size=1
data.data[0]=1a
state.wait_state[0]=5
error_pos=3e8
transmit_delay=0
master=
slave=
Thestreamxbus[0]#slave[0]#sequencercontainssequenceslave_memory_seqbecausethe
componentxbus[0]#slave[0]#sequencersendsthesequenceslave_memory_seq.Thereisa
sequenceitemreqinit.

Whilethisrecordeddataisuseful,itisnotcomplete.ReferringtoFigure2:
1. Wedonotknowthedestinationcomponentofthesequenceitemorsequence.Tomakeit
complete,weproposetorecordthenameandtypeofinitiator/targetcomponent.
2. Wedonotknowwhichsubsequencethesequenceitemreqbelongsto.Therefore,wesuggest
bindingthefullsequencepathnametoit.Forexample,
read_modify_write_seq.read_byte_seq0.reqisthefullsequencepathnameofreq(60,60).
3. Thereisnorelationinformationrecordedbetweensequenceitemsandsubsequences.For
example,wecannottellwhetherthesubsequenceread_byte_seq0consistsofoneormore
sequenceitems.Therefore,weproposethateachsequenceitemorsequenceshouldhavea
uniqueid.Thensequenceitemorsubsequencecanuseanidarraytodescribethehierarchy
relation.Forexample,wecanseesevensequenceitemsandsequencesonstream
xbus[0]#master[0]#sequencer.Letssaytheuniqueidsofread_modify_write_seq,
read_byte_seq0,write_byte_seq0,read_byte_seq0,req,reqandreqare
1,2,3,4,5,6,and7respectively.Theidarrayofthethreereqsequenceitemsare
1.2.5,1.3.6and1.4.7.Soweknowthatthethreesequenceitemsreqbelongtodifferent
subsequences,buttheybelongtothesamesequenceread_modify_write_seq.
4. Anattributeisneededtoindicateifthesequenceitemisaresponseitemfromdriver.

Besidesthecompletenessofthedatadiscussedabove,anotherconsiderationisthatinthecurrent
scheme,onlythesequenceitemsorsequencesfromsequencersarerecordedautomatically.
Therefore,wecannotseethesequencesfromnonsequencercomponents.Inthisexample,we
cannotseesequencesfromthemonitorunlessweaddbegin_tr()andend_tr()inthemonitorclass
manually.Figure3showstherecordingresultofthesequencerandmonitorafterweinsert
begin_tr()andend_tr()manuallyinthemonitorclass.

Figure3:therecordingresultofsequencerandmonitor
ENHANCEMENTSFORUVMTRANSACTIONRECORDING
Asdiscussed,thecurrentrecordingschemedoesnotprovidesufficientinformationforefficient
debugging.Additionally,torecordnonsequencercomponents,usershavetocall
uvm_component::begin_tr()anduvm_component::end_tr()manually.Ifusersforgettocalloneof
them,therecordedtransactionswillbeincomplete.Therefore,weneedabetterschemetoenforce
thepairingofbegin_tr()/end_tr().Wewillnextproposeenhancementstoaddressthesetwo
drawbackswiththecurrentscheme.

ToenhancetheUVMtransactionrecording,weproposethefollowingadditionalinformationtobe
recordedforeachtransaction:
Thecomponentnamethatthetransactioncomesfrom.
Thecomponenttypethatthetransactioncomesfrom.
Thecomponentnamethatthetransactiongoesto.Therecouldbemultipledestinations.
Thecomponenttypethatthetransactiongoesto.
Thefullsequencepathnameofthetransaction.
Theidarraythatcorrespondstothefullsequencepathname.
Whetherthetransactionisresponseitemfromdriver.
Theuniqueidoftransaction.
Withthisadditionalinformation,userswillhaveamorecompletedatabaseofthetrafficbetween
thetestbenchcomponents.

Fornonsequencercomponents,weproposethatusersonlyberequiredtoaddbegin_tr()intheir
testbenchcode.Theend_tr()willbecalledautomaticallyintheportfunctionthatsendsthe
transaction.Forexample,theuserusuallycallsuvm_analysis_port::write()tosendtransactionin
monitor.Theend_tr()shouldbecalledinthisfunctionanditwouldcheckifthebegin_tr()iscalled
ornot.Ifusersforgetstocallbegin_tr(),theportfunctionwillcallitautomatically.Inthiscase,the
timecouldbeincorrect.Evenwiththisdrawback,thismechanismisstillbetterthantheoriginal
oneinthatatleastthedatawillberecorded(ratherthannothingbeingrecorded).Userscanalways
addbegin_tr()intheirtestbenchcodestomakeitright.

Figure4showsthewaveformrealizationoftherecordingresultaftertheproposedenhancements
areputintoeffect.
Figure4:TherecordingresultforXBusexampleafterenhancements

Ascanbeseen,thefollowingadditionalattributesarerecordedaftertheenhancements:
1. initiator_comp_type=uvm_sequencer(Theinitiatorcomponenttype)
2. target_comp_type=uvm_driver(Thetargetcomponenttype)
3. initiator_comp_name=uvm_test_top.xbus_demo_tb0.xbus0.masters[0].sequencer(Theinitiator
componentname)
4. target_comp_name=uvm_test_top.xbus_demo_tb0.xbus0.masters[0].driver(Thetarget
componentname)
5. full_seq_path=read_modify_write_seq.read_byte_seq0.req(Thefullsequencepathname)
6. seq_id_arr=4.6.8(Theidarrayofthecorrespondingfullsequencepathname)
7. unique_id=8(Theuniqueidofthissequenceitem)
8. is_response=0(Thisisnotaresponseitem)

Fromtheenhancedrecordeddata,wecantellthatthesequenceitemreq(60,60)issentfromthe
sequenceruvm_test_top.xbus_demo_tb0.xbus0.masters[0].sequencertodriver
uvm_test_top.xbus_demo_tb0.xbus0.masters[0].driver.Itsfullsequencenameis
read_modify_write_seq.read_byte_seq0.req.Therefore,thissequenceitembelongstosub
sequenceread_byte_seq0.Thesubsequenceread_byte_seq0belongstosequence
read_modify_write_seq.Theidarray4.6.8indicatesthattheidsof
ead_modify_write_seq,read_byte_seq0andreqare4,6and8respectively.Thissequence
itemisnotaresponseitemfromthedriver.Clearlythisisamorecompleterecordoftheactivity
andprovidestheuserbettervisibilityintothetestbench.
ENHANCEDVISUALIZATION
Comparingthewaveformviewsbeforeandaftertheproposedenhancements(Figure2andFigure
4),wecanseethattheadditionalattributesareindeedrecordedaftertheproposedenhancements
areimplemented.However,thewaveformviewofthetransactionsdoesnotprovideaclearpicture
ofthecomponenttraffic.Theadditionalattributescanonlybeviewedinatextformat.

Forabettermorenaturalrealizationoftherecordeddata,wecanderiveinspirationfromthe
UnifiedModelingLanguage(UML)andspecificallyitssequencediagramspecification.Whilethe
UMLsequencediagramisprimarilyusedfordocumentationforsoftwaresystems,therehasbeen
researchinusingittovisualizetheexecutionofprogramsforwhichatracehasbeenrecorded[2].
Withtheadditionalrecordedattributes,itbecomespossibletorealizeasequencediagramtypeof
viewforbettervisualizationofthetrafficinaSystemVerilogtestbench.

Figure5:ThesequencediagramforXBusexample

Figure5showsthesequencediagramfortheXBusexample.Theverticallinerepresentssimulation
time.Thebrownrectanglesonthetopofthesequencediagramarethecomponentsinthe
testbench.Inthisexample,wecanseethesequencer,driver,interface,monitorand
scoreboardcomponents..Thebluearrowsarethesequenceitemsorsequencesbetween
components.Therefore,wecanseethatthesequencersends
read_modify_write_seq,read_byte_seq0,bus_transfer_inst(req),write_byte_seq0,bus_transf
er_inst(req),read_byte_seq0andbus_transfer_inst(req)tothedriver.Likewise,themonitor
sendsthreesequenceitemsxbus_transfer_intstothescoreboard.Mappingthebluearrowstothe
timeline,wecanfigureoutthebegintimeofeachsequenceitemorsequence.

Sincethesequenceitemsandsequencesfromsequencershaveahierarchicalrelationship,wecan
collapsethesequenceitemsintosubsequences.Figure6showsthecollapsedresult.

Figure6:Collapsethesequenceitemsintosubsequence

Thegreyareasbetweenthedriver/interfaceandinterface/monitorarepossiblefunctionsto
transformsequenceitems(transactions)tosignalsorviceversa.Sincewehavenodynamicdatafor
thetransformationfunctions,theonlywaytoderivethisinformationistoanalyzethesourcecode
tofindthepossiblefunctions.Inthisexample,thepossibletransformationfunctionsinthedriver
classareget_and_drive(),reset_signals().drive_read_write().Thesequenceitemsaretransformed
tosignalsandsenttotheinterfaceusingthesefunctions.Ontheotherside,thefunctions
obseve_reset(),collect_arbitration_phase(),collect_address_phase()andcollect_data_phase()inthe
monitorclasscollectthesignalsfromtheDUTandtransformthemintosequenceitems
(transactions).

CONCLUSION
UVMprovidesatransactionrecordingschemewhichisimportantforvisualizationanddebugging
oftransactionleveltrafficinthetestbench,whichinturnhelpswiththedebugofthetestbenchand
DUT.However,therecordedinformationisnotsufficientanditisnotconvenienttorecorddatafor
nonsequencercomponents.Weproposeanenhancedschemewhichinvolvesrecordingadditional
attributesandprovidingabettermechanismfortransactionrecordingofnonsequencers.
Moreover,withtheadditionalrecordedattributes,weintroduceasequencediagramviewtoshow
thetestbenchtrafficmoreclearlyandnaturally.

REFERENCES
1. UVMUserGuideandReferenceManual,http://www.accellera.org/activities/vip
2. OVMUserGuideandReferenceManual,http://www.ovmworld.org/resources.php
3. KatharinaMehnerandBerndWeymann.VisualizationandDebuggingofConcurrentJava
ProgramswithUML.Dissertation,UniversityofPaderborn,February2005
4. KatharinaMehner.JaVis:AUMLBasedVisualizationandDebuggingEnvironmentfor
ConcurrentJavaPrograms.RevisedLecturesonSoftwareVisualizationInternationalSeminar,
May2001.
5. ObjectManagementGroup.UnifiedModelingLanguage.http://www.uml.org/

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