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    B .Tech IV Year I Semester (R07) Supplementary Examinations June 2015

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    subbu
    This document is an exam for a VLSI Design course covering topics such as MOSFET body effect, channel length modulation, fabrication of diodes and resistors in bipolar processes, implementing logic functions using CMOS logic, sheet resistance and its application to calculating ON resistance of an NMOS inverter, parasitic capacitances of an NMOS transistor, FPGA technologies including antifuse and static RAM technologies, goals of VHDL synthesis, how register transfer level descriptions provide optimized synthesis net lists, state diagram of a TAP controller, and how observability is used to test gates within larger circuits. Students are to choose 5 of 8 questions to answer in the exam.

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    B .Tech IV Year I Semester (R07) Supplementary Examinations June 2015

    Uploaded by

    subbu
    10 views1 page
    This document is an exam for a VLSI Design course covering topics such as MOSFET body effect, channel length modulation, fabrication of diodes and resistors in bipolar processes, implementing logic functions using CMOS logic, sheet resistance and its application to calculating ON resistance of an NMOS inverter, parasitic capacitances of an NMOS transistor, FPGA technologies including antifuse and static RAM technologies, goals of VHDL synthesis, how register transfer level descriptions provide optimized synthesis net lists, state diagram of a TAP controller, and how observability is used to test gates within larger circuits. Students are to choose 5 of 8 questions to answer in the exam.

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    r7411001 Vlsi Design

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    This document is an exam for a VLSI Design course covering topics such as MOSFET body effect, channel length modulation, fabrication of diodes and resistors in bipolar processes, implementing logic functions using CMOS logic, sheet resistance and its application to calculating ON resistance of an NMOS inverter, parasitic capacitances of an NMOS transistor, FPGA technologies including antifuse and static RAM technologies, goals of VHDL synthesis, how register transfer level descriptions provide optimized synthesis net lists, state diagram of a TAP controller, and how observability is used to test gates within larger circuits. Students are to choose 5 of 8 questions to answer in the exam.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    10 views1 page

    B .Tech IV Year I Semester (R07) Supplementary Examinations June 2015

    Uploaded by

    subbu
    This document is an exam for a VLSI Design course covering topics such as MOSFET body effect, channel length modulation, fabrication of diodes and resistors in bipolar processes, implementing logic functions using CMOS logic, sheet resistance and its application to calculating ON resistance of an NMOS inverter, parasitic capacitances of an NMOS transistor, FPGA technologies including antifuse and static RAM technologies, goals of VHDL synthesis, how register transfer level descriptions provide optimized synthesis net lists, state diagram of a TAP controller, and how observability is used to test gates within larger circuits. Students are to choose 5 of 8 questions to answer in the exam.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
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    Code: R7411001 R07

    B.Tech IV Year I Semester (R07) Supplementary Examinations June 2015


    VLSI DESIGN
    (Common to EIE & ECC)
    Time: 3 hours Max. Marks: 80

    Answer any FIVE questions


    All questions carry equal marks
    *****
    1 (a) Clearly explain the body effect of the MOSFET.
    (b) Clearly explain about channel length modulation of the MOSFET.

    2 With neat sketches, explain how diodes and resistors are fabricated in bipolar
    process.

    3 Implement following logic functions using CMOS logic:


    (a) .
    (b) .

    4 Explain the concept of sheet resistance and apply it to compute the ON


    resistance ( of an NMOS inverter having pull up to pull down ratio of
    4:1, if n channel resistance is Rsn = 104 per square.

    5 Explain clearly about different parasitic capacitances of an NMOS transistor.

    6 Clearly discuss about the following FPGA technology:


    (a) Anti fuse technology.
    (b) Static RAM technology.

    7 (a) What is the goal of VHDL synthesis step in design flow?


    (b) Explain how register transfer level description provides optimized synthesis net
    list.

    8 (a) Draw the state diagram of TAP controller and explain how it provides the control
    signals for test data and instruction register.
    (b) Explain how observability is used to test the output of a gate within a larger
    circuit.

    *****

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