1.

Name of Course: VLSI CIRCUIT DESIGN

Course Code: BEE 3243
2. Synopsis:
Techniques for rapid implementation of very large scale integration (VLSI) circuits. Selection of technology and logic. Design
process. Design rules and layout procedures. Design aids for layout, rule checking and circuit simulation. Timing and
testability. Choice of architectures for VLSI. Design and layout.

3. Name(s) of academic staff: HARISH MS

4. Semester and Year offered: Semester 1 Year 3
5. Credit Value: 3
6. Prerequisite/co-requisite (if any): Nil
7. Course Learning Outcomes:
At the end of this course, students will be able to:
CLO1 Explain the Fundamentals of VLSI Fabrication process, Layout generation, FPGA architecture
(C2,PLO1) (Exam)
CLO2 Design different types of adders, multipliers and memories (C6,PLO3) (Exam)
CLO3 Prepare an assignment based on VLSI process technologies, FPGA and Layout design using
valid online resources (A4, PLO12) (Assignment)

CLO4 Organize lab reports on experiments based on the topics related to VLSI Circuit
( C6, PLO2)(Lab Report)

CLO5 Demonstrate the working of FPGA through practical assessment

( P5, PLO4) (Practical Assessment)

8. Mapping of the Course Learning Outcomes to the Programme Learning Outcomes, Teaching Methods and
Assessment:
Programme Learning Outcomes (PLO)
PLO
Teaching
Assessment
PLO PLO PLO PLO PLO PLO PLO PLO PLO PLO PLO PLO Methods
Methods
CLO 1 2 3 4 5 6 7 8 9 10 11 12

CLO1 √ Lecture Exam

CLO2 √ Lecture Exam

CLO3 √ Project Assignment

Practical Lab Report
CLO4 √
Practical Practical
CLO5 √ Assessment
9. Transferable Skills:
Transferable skills developed within this course include:
 Critical Thinking and Problem solving
 Information Management and Life Long Learning
10. Distribution of Student Learning Time
Teaching and
Guided
Learning
Learning
No Course Content Outline Activities Independent SLT
CLO (NF2F)
Guided Learning
e.g: e-
Learning(F2F) (NF2F)
learning
L T P O
Fabrication And Devices
 Introduction to IC
Technology
 Basic MOS Transistors
 CMOS Technology
 Fabrication Process
 BiCMOS Technology
1  Layout Design 1,5 2 2 3.5 7.5
 CMOS Inverter
 Id-Vds Relationship
Lab Experiments:
 Layout Generation of
Logic Gates
 Introduction to Micro
wind Tool
Logic Gates
 Combinational Logic
Function
 Complementary Gates
 Alternative gate Circuits
 Delay through
Interconnects
2  Gates as IP 1,5 2 2 3.5 7.5

Lab Experiments:
 Introduction to XILINX
ISE
 Introduction to HDL
Languages

Digital Design Using HDL

 History of VHDL and
3 Verilog 1, 5 2 2 2.5 4.5
 VHDL Elements and
Abstraction
 Objects and Classes
 Variable Assignment
  Usage of Subprograms

Lab Experiments:
 Simulation of Logic
Gates
 Simulation of Adder and
Subtractor
 Simulation of Multiplexer
and Demultiplexer

Sequential Logic Design

 Latches and Flip-
Flops
 Sequential Systems
and Clocking
 Clock Generation
 Power Optimization
4 1, 5 2 2 3.5 7.5
 Design Validation
and
Sequential Testing

Lab Experiments:
 Simulation of Flip-
Flops
 Counters HDL

Subsystem Design
 ALU
 Multipliers
 Field-Programmable
Gate Arrays
 Programmable Logic
5 Arrays 1,5 2 4 2.5 4.5
 Data Paths
 Control Path
Lab Experiments:
 Simulation of ALU
 Introduction to
FPGA Kit
Combinational Logic Design
 Examples Of
Combinational Logic
6  Elmore‟S Constant 1,3 2 3.5 7.5
 Pass Transistor Logic
 Transmission Gates
 Static And Dynamic
 CMOS Design
 Power Dissipation
 Low Power Design
Principles

Designing Arithmetic Building

Blocks
 Architectures For Ripple
Carry Adder
 Carry Look Ahead
Adders
7  High Speed Adders 1,5 2 3 3 6
 Barrel Shifters
 Speed and Area Trade-
off
Lab Experiments:
 Simulation of Ripple
Carry Adder
Architecture Design 1:
 Register-Transfer Design
8  Pipelining 2,3 2 2.5 4.5
 High-Level Synthesis
 GALS Systems
Architecture Design 2:
 Full Custom And Semi
Custom Design
 Standard Cell Design
And Cell Libraries
 FPGA Building Block
9 Architectures 1,5 2 3 2.5 4.5
 FPGA Interconnect
Routing Procedures.

Lab Experiments:
 Implementation 4-Bit
Comparator using FPGA
Floor-planning
 Floor planning Methods
 Global Interconnect
10  Floor plan Design 1 2 4 9
 Off-Chip Connections

VLSI Design Issues

11  VLSI Design issues and 2,3 2 4.5 10.5
design trends
 Design for testability
  power calculations,
package selection
 Introduction to SoC
design

CMOS Testing
 CMOS Testing, Need for
testing,
 Test Principles, Design
12 Strategies for test, 1,2 2 4.5 10.5
 Chip-level
Test Techniques
 System-level Test
Techniques
Design for Testability:
 Introduction
 Fault Types and
Models
13  Scan-Based 2, 3 2 2.5 4.5
Techniques
 Built-In Self-Test
(BIST) Techniques
Current Monitoring IDDQ Test.

Semiconductor Memories
 Introduction
 Dynamic Random
Access Memory
(DRAM)
 Static Random
Access Memory
14  Non-volatile Memory 1,5 2 2 2.5 4.5

Lab Experiments:
 Simulation of SRAM
 Design of SRAM using
Microwind

28 0 20 - - 45 93
Continuous Assessment Percentage (%) F2F NF2F SLT
1. 1 Lab report (1500 words) 30 0 9 9
2. 2 Practical Assessment 15 1 3 4
3. Assignment (850 words) 15 0 5 5
TOTAL= 18
Final Assessment Percentage (%) F2F NF2F SLT
1. 1 Final Exam 40 3 9 12
 TOTAL= 12
GRAND TOTAL SLT= 123
11. Identify special requirement or resources to deliver the course (e.g., software, nursery, computer lab, simulation room):
Computer lab – XILINX ISE/ SPARTAN FPGA KIT/ MICROWIND
12. Main references supporting the course:
1.  Micheal Vei, 2017, 1st Edition, VLSI Design, CRC Press, ISBN-13: 978-0849318764
2.  J. Bhasker, 2018 , 1st Edition, Verilog HDL Synthesis, Star Galaxy Publication, ISBN-13: 978-0984629220
3.  Shonak Bansal, 2017, 1st Edition, Design of Digital Systems Using HDL by Examples, Independently Published,
ISBN-13: 978-1521548714
4  Gerardus Blokdyk, , August 2018 ,1st Edition, Application-Specific Integrated Circuit: ASIC A Complete Guide , 5 Star
cooks Publishers, ISBN-13: 978-0655330240
5 Tomasz Wojcicki, 2017, 1st Edition, VLSI Circuits for emerging Applications, CRC Press, ISBN-13: 978-1138076051
6 Joseph Cavanagh, 2017, 1st Kindle Edition, Verilog HDL Digital Design and Modeling, CRC Press, ISBN-13: 978-
1420051544
Additional References supporting the course:
1.  Kamran Eshraghian, Douglas and A.Pucknell and Sholeh Eshraghian, 2009 Edition ,Essentials of VLSI
Circuits and Systems, Prentice–Hall of India Private Limited, ISBN-13: 978-8120327726
2. M.J. Smith, 1997, Application Specific Integrated Circuits, Addisson Wesley, ISBN-13: 978-2101500222

3. Indian Institute of Technology, NPTEL Video Lectures on VLSI DESIGN

13. Other additional information: Nil

3 Credits = 1 Credit Lab And 2 Credits Theory (Year III And Year IV)

1 CREDIT FOR LAB (1 Credit = 40 Hours)

* 1 Credit = 6 Experiments
LAB FACE TO FACE SLT
Practical hrs 3hrs x 6 Exp 10 hrs
= 18 hrs (Preparation Time)
Safety instructions 2 hrs -

Lab Report (1500 Words) - 9

Practical Assessment 1 hr 3 hrs
Total 21 hrs 22 hrs
Total = 43 (1 Credit)

2 CREDIT THEORY (2 Credits = 80 Hours)

THEORY FACE TO FACE SLT

Lecture 2hr X 14 weeks= 28 1.5 hr X 14 weeks= 35

Assignment (850 Words) - 5 hrs

Exam 3 hrs 9 hrs
Total 31 49
Total = 80 (2 Credits)

*80+43=121 hrs = 123 Credits

Face to Face SLT TLT

L T P O L T P O
28 - 20 4 35 - 10 26 123

CALCULATION OF COURSEWORK PERCENTAGE

COU RSEWORK CALCULATION PERCENTAGE

EXAM 12 40%
∗ 100 = 40
30
ASSIGNMENT 5 15%
∗ 100 = 16.5
30
PRACTICAL ASSESSMENT 4 15%
∗ 100 = 13.5
30
LAB REPORT 9 30%
∗ 100 = 30
30