Usc Ee479 HW1 2018

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M. S.W.

Chen
EE479L Fall 2018

University of Southern California

EE479 Fall 2017

Homework 1 (Due Sept 8 in class)

1. Using the figure below, estimate the transistor model (Level 1) parameters: VTO ,
γ, k, and λ. Assume W/L=10, ϕf =0.3V. Explain your method.

2. An NMOS transistor has the following parameters: W=0.65 um, L= 65 nm, VTO =0.3 V,
=0.5V1/2 , k=100 μA/V 2 , and =0.01V −1 . Sketch gm-Vds characteristics for Vds from 0
to 1V and Vbs=0 V and −0.5V, assuming Vgs=1V.

3. The figure below is the loge(Id)-Vgs characteristic with and without subthreshold
modeling. Assuming the subthreshold current can be approximated with
M. S.W. Chen

Vgs −Vth
Id = I0 e nVT

,where VT=26mV. Estimate the value of n in this model.

4. Show that two MOS transistors connected in series with channel lengths of L1 and L2 and
identical channel widths of W can be modeled as one equivalent MOS transistor whose
width is W and whose length is L1 + L2, as shown in the figure. Assume the transistors are
identical except for their channel lengths. Ignore the body effect and channel-length
modulation.
M. S.W. Chen

5. Sketch Ix and the transconductance of the transistor as a function of Vx for each circuit in
the figure as Vx varies from 0 to VDD.

VDD VDD
Ix
R1 Ix R1 Ix

+2V R1 Vx
R2 M1 R2 M1 M1
Vin
Vx Vx I1

(a) (b) (c)

Ix VDD
+2V
M1
I1

R1 `

Vx R1 Ix

I1
M1
Vx

(d) (e)

6. Sketch Vout as a function of Vin for each circuit in the figure as Vin varies from 0 to
VDD.

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