ADC0809 With CKT, Flow Code
ADC0809 With CKT, Flow Code
ADC0809 With CKT, Flow Code
Features
Easy interface to all microprocessors
Operates ratiometrically or with 5 VDC or analog span
adjusted voltage reference
No zero or full-scale adjust required
8-channel multiplexer with address logic
0V to 5V input range with single 5V power supply
Outputs meet TTL voltage level specifications
Standard hermetic or molded 28-pin DIP package
28-pin molded chip carrier package
Functional Description
Multiplexer Selection.
The device contains an 8-channel single-ended analog signal multiplexer. A
particular input channel is selected by using the address decoder.
Table below shows the input states for the address lines to select any
channel. The address is latched into the decoder on the low-to-high
transition of the address latch enable signal.
Converter Section
The heart of this single chip data acquisition system is its 8-bit analog-
to-digital converter. The converter is designed to give fast, accurate, and
repeatable conversions over a wide range of temperatures. The converter is
partitioned into 3 major sections: the 256R ladder network, the successive
approximation register, and the comparator. The converter’s digital outputs
are positive true.
The 256R ladder network approach was chosen over the conventional
R/2R ladder because of its inherent monotonicity, which guarantees no
missing digital codes. Monotonicity is particularly important in closed loop
feedback control systems. A non-monotonic relationship can cause
oscillations that will be catastrophic for the system. Additionally, the 256R
network does not cause load variations on the reference voltage.
The bottom resistor and the top resistor of the ladder network in
Figure are not the same value as the remainder of the network. The
difference in these resistors causes the output characteristic to be
symmetrical with the zero and
Full-scale points of the transfer curve. The first output transition occurs
when the analog signal has reached +1⁄2 LSB and succeeding output
transitions occur every 1 LSB later up to full-scale.
Clock Specifications
2.2.1. Block Diagram
2.2.2. Pin Diagram
The digital o/p is fed into the Microcontroller Ports for further processing.
+5V
U 1
F LE X4 1 2 8 F LE X3
2 IN 3 IN 2 2 7
F LE X5 IN 4 IN 1 F LE X2
3 2 6 F LE X1
4 IN 5 IN 0 2 5
IN 6 AD D A A D C 09_M U X_A
5 2 4 A D C 09_M U X_B
6 IN 7 AD D B 2 3
S TA R T AD D C A D C 09_M U X_C
7 2 2
8 EO C ALE 2 1
2 (5 ) 2 (1 )M S B A D C 7
9 2 0 A D C 6
10 O /P E N 2 (2 ) 1 9
AD C 09_S TAR T C LK C LO C K 2 (3 ) A D C 5
AD C 09_EO C 11 1 8 A D C 4
12 VC C 2 (4 ) 1 7
AD C 09_O P_EN V R E F (+ ) 2 (8 )L S B A D C 3
AD C 09_ALE 13 1 6 A D C 2
14 G N D V R E F (-) 1 5
2 (7 ) 2 (6 ) A D C 1
A D C 0
AD C 0809
+5V
C LK
+5V
+5V
1
R 1
100E U 2
2
1
C 1 0 .1 u F 1 8 1 R 2 1K 2
2 1 2 G N D VC C 7
3 TR IG D IS C H 6 1 R 3 1K 2 J5
O U T TH R E S
2
4 5 1 2 B U R G _ 2 P IN
R ESET C O N T 0 .1 u F C 2
5 5 5 T IM E R
ADC0809
No