Subject: CAO (ECEg 3143) Chapter: 4 Input Output Systems

CHAPTER 4
Input Output Systems

1. Input / Output Organization…Introduction

The computer system's input/output (I/O) architecture is its interface to the outside world. Till now
we have discussed the two important modules of the computer system -
 The processor and
 The memory module.
The third key component of a computer system is a set of I/O modules. Each I/O module interfaces
to the system bus and controls one or more peripheral devices. There are several reasons why an
I/O device or peripheral device is not directly connected to the system bus. Some of them are as
follows -
 There are a wide variety of peripherals with
various methods of operation. It would be
impractical to include the necessary logic within
the processor to control several devices.
 The data transfer rate of peripherals is often much
slower than that of the memory or processor.
Thus, it is impractical to use the high-speed
system bus to communicate directly with a
peripheral.
 Peripherals often use different data formats and
word lengths than the computer to which they are Fig: Generic Model of an I/O Module

attached.
Thus, an I/O module is required.

2. Input / Output Modules

The major functions of an I/O module are categorized as follows –
 Control and timing  Data Buffering
 Processor & Device Communication  Error Detection
During any period of time, the processor may communicate with one or more external devices in
unpredictable manner, depending on the program's need for I/O. The internal resources, such as
main memory and the system bus, must be shared among a number of activities, including data I/O.

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Subject: CAO (ECEg 3143) Chapter: 4 Input Output Systems

2.1 Control & timings:

The I/O function includes a control and timing requirement to co-ordinate the flow of traffic between
internal resources and external devices. For example, the control of the transfer of data from an
external device to the processor might involve the following sequence of steps –
a) The processor interacts with the I/O module to check the status of the attached device.
b) The I/O module returns the device status.
c) If the device is operational and ready to transmit, the processor requests the transfer of data, by
means of a command to the I/O module.
d) The I/O module obtains a unit of data from external device.
e) The data are transferred from the I/O module to the processor.
If the system employs a bus, then each of the interactions between the processor and the I/O module
involves one or more bus arbitrations.

2.2 Processor & Device Communication

During the I/O operation, the I/O module must communicate with the processor and with the external
device. Processor communication involves the following -
Command decoding: The I/O module accepts command from the processor, typically sent as
signals on control bus.
Data: Data are exchanged between the processor and the I/O module over the data bus.
Status Reporting: Because peripherals are so slow, it is important to know the status of the I/O
module. For example, if an I/O module is asked to send data to the processor (read), it may not
be ready to do so because it is still working on the previous I/O command. This fact can be
reported with a status signal. Common status signals are BUSY and READY.
Address Recognition: Just as each word of memory has an address, so thus each of the I/O
devices. Thus an I/O module must recognize one unique address for each peripheral it controls.
One the other hand, the I/O must be able to perform device communication. This communication
involves command, status information and data.

2.3 Data Buffering:

An essential task of an I/O module is data buffering. The data buffering is required due to the
mismatch of the speed of CPU, memory and other peripheral devices. In general, the speed of CPU
is higher than the speed of the other peripheral devices. So, the I/O modules store the data in a data
buffer and regulate the transfer of data as per the speed of the devices.
In the opposite direction, data are buffered so as not to tie up the memory in a slow transfer
operation. Thus the I/O module must be able to operate at both device and memory speed.

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Subject: CAO (ECEg 3143) Chapter: 4 Input Output Systems

2.4 Error Detection:

Another task of I/O module is error detection and for subsequently reporting error to the processor.
One class or error includes mechanical and electrical malfunctions reported by the device (e.g. paper
jam). Another class consists of unintentional changes to the bit pattern as it is transmitted from
devices to the I/O module.

3. I/O Module Structure

Following figure provides a general block
diagram of an I/O module. The module
connects to the rest of the computer through a
set of signal lines (e.g., system bus lines). Data
transferred to and from the module are
buffered in one or more data registers. There
may also be one or more status registers that
Fig: Block Diagram of an I/O Module
provide current status information. A status
register may also function as a control register, to accept detailed control information from the
processor. The logic within the module interacts with the processor via a set of control lines. The
processor uses the control lines to issue commands to the I/O module.
Some of the control lines may be used by the I/O module (e.g., for arbitration and status signals).
The module must also be able to recognize and generate addresses associated with the devices it
controls. Each I/O module has a unique address or, if it controls more than one external device, a
unique set of addresses. Finally, the I/O module contains logic specific to the interface with each
device that it controls.

4. Input / Output Subsystem

There are three basic forms of input and output systems –
 Programmed I/O: With programmed I/O, the processor executes a program that gives its
direct control of the I/O operation, including sensing device status, sending a read or write
command, and transferring the data.
 Interrupt driven I/O: With interrupt driven I/O, the processor issues an I/O command,
continues to execute other instructions, and is interrupted by the I/O module when the I/O
module completes its work.
 Direct Memory Access (DMA): In Direct Memory Access (DMA), the I/O module and main
memory exchange data directly without processor involvement.
With both programmed I/O and Interrupt driven I/O, the processor is responsible for extracting data
from main memory for output operation and storing data in main memory for input operation.

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Subject: CAO (ECEg 3143) Chapter: 4 Input Output Systems

4.1 Programmed I/O

When a processor is executing a program and encounters an instruction relating to I/O, it executes
that I/O instruction by issuing a command to the appropriate I/O module. The I/O module will perform
the requested action and then set the appropriate bits in the I/O status register. The I/O module
takes no further action to alert the processor. In particular, it does not interrupt the processor. It is
the responsibility of the processor to check periodically the status of the I/O module until it finds that
the operation is complete.

4.1.1 I/O Commands

To execute an I/O-related instruction, the processor issues an address, specifying the particular I/O
module and external device, and an I/O command. There are four types of I/O commands that an I/O
module will receive when it is addressed by a processor:
 Control: Used to activate a peripheral device and instruct it what to do. For example, a magnetic
tape unit may be instructed to rewind or to move forward one record. These commands are
specific to a particular type of peripheral device.
 Test: Used to test various status conditions associated
with an I/O module and its peripherals. The processor will
want to know if the most recent I/O operation is completed
or any error has occurred.
 Read: Causes the I/O module to obtain an item of data
from the peripheral and place it in the internal buffer.
 Write: Causes the I/O module to take an item of data (byte
or word) from the data bus and subsequently transmit the
data item to the peripheral.
Following figure gives an example of the use of programmed
I/O to read in a block of data from a peripheral device (e.g., a
record from tape) into memory. Data are read in one word
(e.g., 16 bits) at a time. For each word that is read in, the
processor must remain in a status-checking cycle until it
determines that the word is available in the I/O module’s data
register. This flowchart highlights the main disadvantage of this
technique that it is a time-consuming process that keeps the Fig: Programmed I/O

processor busy needlessly.

4.1.2 I/O Instructions

There will be many I/O devices connected through I/O modules to the system. Each device will be
identified by a unique address.

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Subject: CAO (ECEg 3143) Chapter: 4 Input Output Systems

When the processor issues an I/O command, the command contains the address of the device that
is used by the command. The I/O module must interpret the address lines to check if the command
is for itself.
Generally in most of the processors, the processor, main memory and I/O share a common bus
(data address and control bus). Two types of addressing are possible:
 Memory-mapped I/O
 Isolated or I/O mapped I/O
Memory-mapped I/O: There is a single address space for memory locations and I/O devices. The
processor treats the status and address register of the I/O modules as memory location. For
example, if the size of address bus of a processor is 16, then there are 216 combinations and all
together 216 address locations can be addressed with these 16 address lines.
Out of these 216 address locations, some address locations can be used to address I/O devices and
other locations are used to address memory locations. Since I/O devices are included in the same
memory address space, so the status and address registers of I/O modules are treated as memory
location by the processor. Therefore, the same machine instructions are used to access both
memory and I/O devices.
Isolated or I/O -mapped I/O: In this scheme, the full range of addresses may be available for both.
The address refers to a memory location or an I/O device is specified with the help of a command
line. In general IO/M command line is used to identify a memory location or an I/O device.
if IO/M = 1, it indicates that the address present in address bus is the address of an I/O device.
if IO/M = 0, it indicates that the address present in address bus is the address of a memory location.
Since full range of address is available for both memory and I/O devices, so, with 16 address lines,
the system may now support both 216 memory locations and 216 I/O addresses.

4.2 Interrupt driven I/O

The problem with programmed I/O is that the processor has to wait a long time for the I/O module
of concern to be ready for either reception or transmission of data. The processor, while waiting,
must repeatedly interrogate the status of the I/O module. This type of I/O operation, where the CPU
constantly tests a part to see if data is available, is polling, that is, the CPU Polls (asks) the port if it
has data available or if it is capable of accepting data. Polled I/O is inherently inefficient.
The solution to this problem is to provide an interrupt mechanism. In this approach the processor
issues an I/O command to a module and then go on to do some other useful work. The I/O module
then interrupt the processor to request service when it is ready to exchange data with the processor.
The processor then executes the data transfer. Once the data transfer is over, the processor then
resumes its former processing.
Let us consider how it works
A. From the point of view of the I/O module:

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Subject: CAO (ECEg 3143) Chapter: 4 Input Output Systems

 For input, the I/O module services a READ command from the processor.
 The I/O module then proceeds to read data from an associated peripheral device.
 Once the data are in the modules data register, the module issues an interrupt to the
processor over a control line.
 The module then waits until its data are requested by the processor.
 When the request is made, the module places its data on the data bus and is then ready for
another I/O operation.
B. From the processor point of view; the action for an input is as follows:
 The processor issues a READ command.
 It then does something else (e.g. the processor may be
working on several different programs at the same time)
 At the end of each instruction cycle, the processor
checks for interrupts
 When the interrupt from an I/O module occurs, the
processor saves the context (e.g. program counter &
processor registers) of the current program and
processes the interrupt.
 In this case, the processor reads the word of data from
the I/O module and stores it in memory.
 It then restores the context of the program it was working
on and resumes execution.
Following figure shows the use of interrupt I/O for reading in a
block of data. Interrupt I/O is more efficient than programmed
I/O because it eliminates needless waiting. However, interrupt
I/O still consumes a lot of processor time, because every word
of data that goes from memory to I/O module or from I/O module
Fig: Interrupt I/O
to memory must pass through the processor.

4.2.1 Interrupt Processing

The occurrence of an interrupt triggers a number of events, both in the processor hardware and in
software as shown in below given figure.
When an I/O device completes an I/O operation, the following sequences of hardware events occurs:
1. The device issues an interrupt signal to the processor.
2. The processor finishes execution of the current instruction before responding to the interrupt.

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Subject: CAO (ECEg 3143) Chapter: 4 Input Output Systems

3. The processor tests for the interrupt;

if there is one interrupt pending, then
the processor sends an
acknowledgement signal to the device
which issued the interrupt. After getting
acknowledgement, the device removes
its interrupt signals.
4. The processor now needs to prepare
to transfer control to the interrupt
routine. It needs to save the information
needed to resume the current program
at the point of interrupt. The minimum
information required to save is the
processor status word (PSW) and the
location of the next instruction to be
executed which is nothing but the Fig: Simple Interrupt Processing

contents of program counter. These can be pushed into the system control stack.
5. The processor now loads the program counter with the entry location of the interrupt handling
program that will respond to the interrupt.
Once the program counter has been loaded, the processor proceeds to the next instruction cycle,
which begins with an interrupt fetch. The control will transfer to interrupt handler routine for the
current interrupt. The following operations are performed at this point.
6. At the point, the program counter and PSW relating to the interrupted program have been saved
on the system stack. In addition to that some more information must be saved related to the current
processor state which includes the control of the processor registers, because these registers may
be used by the interrupt handler. Typically, the interrupt handler will begin by saving the contents of
all registers on stack.
7. The interrupt handles next processes the interrupt. This includes an examination of status
information relating to the I/O operation or, other event that caused an interrupt.
8. When interrupt processing is complete, the saved register values are retrieved from the stack and
restored to the registers.
9. The final act is to restore the PSW and program counter values from the stack. As a result, the
next instruction to be executed will be from the previously interrupted program.

4.3 Direct Memory Access

We have discussed the data transfer between the processor and I/O devices. We have discussed
two different approaches namely programmed I/O and Interrupt-driven I/O. Both the methods require

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Subject: CAO (ECEg 3143) Chapter: 4 Input Output Systems

the active intervention of the processor to transfer data between memory and the I/O module, and
any data transfer must transverse a path through the processor. Thus both these forms of I/O suffer
from two inherent drawbacks.
 The I/O transfer rate is limited by the speed with which the processor can test and service a
device.
 The processor is tied up in managing an I/O transfer; a number of instructions must be
executed for each I/O transfer.
To transfer large block of data at high speed, a special control unit may be provided to allow transfer
of a block of data directly between an external device and the main memory, without continuous
intervention by the processor. This approach is called direct memory access or DMA.
DMA transfers are performed by a control circuit associated with the I/O device and this circuit is
referred as DMA controller. The DMA controller allows direct data transfer between the device and
the main memory without involving the processor.

4.3.1 DMA Function

To transfer data between memory and I/O devices,
DMA controller takes over the control of the system
from the processor and transfer of data take place
over the system bus. For this purpose, the DMA
controller must use the bus only when the processor
does not need it, or it must force the processor to
suspend operation temporarily. The later technique
is more common and is referred to as cycle stealing,
because the DMA module in effect steals a bus
cycle. The typical block diagram of a DMA controller
is shown in the figure. Fig: Typical DMA Block Diagram

When the processor wishes to read or write a block of data, it issues a command to the DMA module,
by sending to the DMA module the following information.
 Whether a read or write is requested, using the read or write control line between the
processor and the DMA module.
 The address of the I/O devise involved, communicated on the data lines.
 The starting location in the memory to read from or write to, communicated on data lines and
stored by the DMA module in its address register.
 The number of words to be read or written again communicated via the data lines and stored
in the data count register.
The processor then continues with other works. It has delegated this I/O operation to the DMA
module. The DMA module checks the status of the I/O devise whose address is communicated to

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Subject: CAO (ECEg 3143) Chapter: 4 Input Output Systems

DMA controller by the processor. If the specified I/O devise is ready for data transfer, then DMA
module generates the DMA request to the processor. Then the processor indicates the release of
the system bus through DMA acknowledge. The DMA module transfers the entire block of data, one
word at a time, directly to or from memory, without going through the processor.
When the transfer is completed, the DMA module sends an interrupt signal to the processor. After
receiving the interrupt signal, processor takes over the system bus. Thus the processor is involved
only at the beginning and end of the transfer. During that time the processor is suspended.
It is not required to complete the current instruction to suspend the processor. The processor may
be suspended just after the completion of the current bus cycle. On the other hand, the processor
can be suspended just before the need of the system bus by the processor, because DMA controller
is going to use the system bus, it will not use the processor. The point where in the instruction cycle
the processor may be suspended shown in the figure.

Fig: DMA and Interrupt Breakpoints during an Instruction Cycle

When the processor is suspended, then the DMA module transfer one word and return control to
the processor. During that time processor may perform some other task which does not involve the
system bus. In the worst situation processor will wait for some time, till the DMA releases the bus.
The net effect is that the processor will go slow. But the net effect is the enhancement of
performance, because for a multiple word I/O transfer, DMA is far more efficient than interrupt driven
or programmed I/O.

Compiled By: Rituraj Jain Page: 9 Wollega University, Nekemte