UCC1895, UCC2895, UCC3895

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BiCMOS Advanced Phase-Shift PWM Controller

Check for Samples: UCC1895, UCC2895, UCC3895

1FEATURES DESCRIPTION
• Programmable-Output Turnon Delay The UCC3895 is a phase-shift PWM controller that
implements control of a full-bridge power stage by
• Adaptive Delay Set phase shifting the switching of one half-bridge with
• Bidirectional Oscillator Synchronization respect to the other. The device allows constant
• Voltage-Mode, Peak Current-Mode, or Average frequency pulse-width modulation in conjunction with
Current-Mode Control resonant zero-voltage switching to provide high
efficiency at high frequencies. The part is used either
• Programmable Softstart, Softstop and Chip as a voltage-mode or current-mode controller.
Disable via a Single Pin
• 0% to 100% Duty-Cycle Control While the UCC3895 maintains the functionality of the
UC3875/6/7/8 family and UC3879, it improves on that
• 7-MHz Error Amplifier controller family with additional features such as
• Operation to 1 MHz enhanced control logic, adaptive delay set, and
• Typical 5-mA Operating Current at 500 kHz shutdown capability. Because the device is built using
the BCDMOS process, it operates with dramatically
• Very Low 150-μA Current During UVLO less supply current than it’s bipolar counterparts. The
UCC3895 operates with a maximum clock frequency
APPLICATIONS of 1 MHz.
• Phase-Shifted Full-Bridge Converters
• Off-Line, Telecom, Datacom and Servers
• Distributed Power Architecture
• High-Density Power Modules

UCC3895
Q1
1 EAN EAP 20
7
VOUT

2 EAOUT SS/DISB 19

3 RAMP OUTA 18

4 REF OUTB 17
A C

5 GND PGND 16
VIN

6 SYNC VCC 15 VBIAS

7 CT OUTC 14
B D

8 RT OUTD 13

9 DELAB CS 12

10 DELCD ADS 11

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION
PACKAGED DEVICES
TA
SOIC-20 (DW) (1) PDIP-20 (N) TSSOP-20 (PW) (1) PLCC-20 (FN) (1) LCCC-20 (FK) CDIP-20 (J)
–55°C to +125°C UCC1895L UCC1895J
–40°C to +85°C UCC2895DW UCC2895N UCC2895PW UCC2895Q
0°C to 70°C UCC3895DW UCC3895N UCC3895PW UCC3895Q

(1) The DW, PW and Q packages are available taped and reeled. Add TR suffix to device type (for example: UCC2895DWTR) to order
quantities of 2000 devices per reel for DW.

ABSOLUTE MAXIMUM RATINGS

All voltage values are with respect to the network ground terminal unless otherwise noted. (1)
VALUE UNIT
MIN MAX
Supply voltage 17 V
Output current 100
Reference current 15 mA
Supply current 30
Analog inputs EAP, EAN, EAOUT, RAMP, SYNC, ADS, CS, –0.3 REF + 0.3 V
SS/DISB
Drive outputs OUTA, OUTB, OUTC, OUTD –0.3 VCC + 0.3
Power dissipation at TA = 25°C DW-20 package 650 mW
N-20 package 1 W
TJ Junction temperature range –55 150
Lead temperature 1.6 mm (1/16 in) from case for 10 seconds 300 °C
Tstg Storage temperature range –65 150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to Absolute Maximum Rated conditions for extended periods may affect device reliability

THERMAL CHARACTERISTICS
PART TJA TJC UNIT
UCC2895DW 90 25
UCC2895N 80 35
UCC2895PW 125 14
°C/W
UCC2895Q 75 34
UCC1895J 85 28
UCC1895L 80 20

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RECOMMENDED OPERATING CONDITIONS (1)

MIN NOM MAX UNIT
VDD Supply voltage 10 16.5 V
VDD Supply voltage bypass capacitor (2) 10 × CREF
CREF Reference bypass capacitor (UCC1895) (3) 0.1 1.0 µF
(3)
CREF Reference bypass capacitor (UCC2895, UCC3895) 0.1 4.7
CT Timing capacitor (for 500-kHz switching frequency) 220 pF
RT Timing resistor (for 500-kHz switching frequency) 82
kΩ
RDEL_AB, RDEL_CD Delay resistor 2.5 40
TJ Operating junction temperature (4) –55 125 °C

(1) TI recommends that there be a single point grounded between GND and PGND directly under the device. There must be a separate
ground plane associated with the GND pin and all components associated with pins 1 through 12, plus 19 and 20, be located over this
ground plane. Any connections associated with these pins to ground must be connected to this ground plane.
(2) The VDD capacitor must be a low ESR, ESL ceramic capacitor located directly across the VDD and PGND pins. A larger bulk capacitor
must be located as physically close as possible to the VDD pins.
(3) The VREF capacitor must be a low ESR, ESL ceramic capacitor located directly across the REF and GND pins. If a larger capacitor is
desired for the VREF then it must be located near the VREF cap and connected to the VREF pin with a resistor of 51 Ω or greater. The bulk
capacitor on VDD must be a factor of 10 greater than the total VREF capacitance.
(4) TI does not recommended that the device operate under conditions beyond those specified in this table for extended periods of time.

ELECTRICAL CHARACTERISTICS
VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 0.1 μF and no load on the
outputs, TA = TJ. TA = 0°C to 70°C for UCC3895x, TA = –40°C to +85°C for UCC2895x and TA = –55°C to +125°C for the
UCC1895x. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UVLO (UNDERVOLTAGE LOCKOUT)
UVLO(on) Start-up voltage threshold 10.2 11 11.8
UVLO(off) Minimum operating voltage after 8.2 9 9.8
V
start-up
UVLO(hys) Hysteresis 1 2 3
SUPPLY
ISTART Start-up current VDD = 8 V 150 250 µA
IDD Operating current 5 6 mA
VDD_CLAMP VDD clamp voltage IDD = 10 mA 16.5 17.5 18.5 V
VOLTAGE REFERENCE
VREF Output voltage TJ = 25°C 4.94 5 5.06
10 V < VDD < VDD_CLAMP 4.85 5 5.15 V
0 mA < IREF < 5 mA
temperature
ISC Short circuit current REF = 0 V, TJ = 25°C 10 20 mA
ERROR AMPLIFIER
Common-mode input voltage range –0.1 3.6 V
VIO Offset voltage –7 7 mV
IBIAS Input bias current (EAP, EAN) –1 1 µA
EAOUT_VOH High-level output voltage EAP-EAN = 500 mV, IEAOUT = –0.5 mA 4 4.5 5
V
EAOUT_VOL Low-level output voltage EAP-EAN = –500 mV, IEAOUT = 0.5 mA 0 0.2 0.4
ISOURCE Error amplifier output source current EAP-EAN = 500 mV, EAOUT = 2.5 V 1 1.5
mA
ISINK Error amplifier output sink current EAP-EAN = –500 mV, EAOUT = 2.5 V 2.5 4.5
AVOL Open-loop dc gain 75 85 dB
(1)
GBW Unity gain bandwidth 5 7 mHz
Slew rate (1) 1 V < EAN <0 V, EAP = 500 mV 1.5 2.2 V/µs
0.5 V < EAOUT < 3 V

(1) Ensured by design. Not production tested.

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ELECTRICAL CHARACTERISTICS (continued)

VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 0.1 μF and no load on the
outputs, TA = TJ. TA = 0°C to 70°C for UCC3895x, TA = –40°C to +85°C for UCC2895x and TA = –55°C to +125°C for the
UCC1895x. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
No-load comparator turn-off threshold 0.45 0.5 0.55
No-load comparator turn-on threshold 0.55 0.6 0.69 V
No-load comparator hysteresis 0.035 0.1 0.165
OSCILLATOR
fOSC Frequency TJ = 25°C 473 500 527 kHZ
Frequency total variation( Over line, temperature 2.5% 5%
VIH_SYNC SYNC input threshold, SYNC 2.05 2.1 2.4
VOH_SYNC High-level output voltage, SYNC ISYNC = –400 μA, VCT = 2.6 V 4.1 4.5 5 V
VOL_SYNC Low-level output voltage, SYNC ISYNC = 100 μA, VCT = 0 V 0 0.5 1
Sync output pulse width LOADSYNC = 3.9 kΩ and 30 pF in parallel 85 135 ns
VRT Timing resistor voltage 2.9 3 3.1
VCT(peak) Timing capacitor peak voltage 2.25 2.35 2.55 v
VCT(valley) Timing capacitor valley voltage 0 0.2 0.4
CURRENT SENSE
ICS(bias) Current sense bias current 0 V < CS < 2.5 V –4.5 20 µA
0 V ADS < 2.5 V
Peak current threshold 1.9 2 2.1 V
Overcurrent threshold 2.4 2.5 2.6 V
Current sense to output delay 0 V ≤ CS ≤ 2.3 V 75 110 ns
DELAB = DELCD = REF
SOFT-START/SHUTDOWN
ISOURCE Softstart source current SS/DISB = 3.0 V –40 –35 –30 µA
CS = 1.9 V
ISINK Softstart sink current SS/DISB = 3.0 V, 325 350 375 µA
CS = 2.6 V
Softstart/disable comparator 0.44 0.5 0.56 V
threshold
ADAPTIVE DELAY SET (ADS)
DELAB/DELCD output voltage ADS = CS = 0 V 0.45 0.5 0.55
ADS = 0 V 1.9 2 2.1 V
CS = 2 V
tDELAY Output delay (2) (3) ADS = CS = 0 V 450 560 620 ns
ADS bias current 0 V < ADS < 2.5 V –20 20 µA
0 V < CS < 2.5 V

(2) Ensured by design. Not production tested.

(3) Output delay is measured between OUTA and OUTB, or OUTC and OUTD. Output delay is defined as shown below where: tf(OUTA) =
falling edge of OUTA signal, tr(OUTB) = rising edge of OUTB signal (see Figure 1 and Figure 2).

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ELECTRICAL CHARACTERISTICS (continued)

VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 0.1 μF and no load on the
outputs, TA = TJ. TA = 0°C to 70°C for UCC3895x, TA = –40°C to +85°C for UCC2895x and TA = –55°C to +125°C for the
UCC1895x. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT
VOH High--level output voltage (all IOUT = –10 mA, VDD to output 250 400 mV
outputs)
VOL Low-level output voltage (all outputs) IOUT = 10 mA 150 250 mV
tR Rise time (4) CLOAD = 100 pF 20 35 ns
tF Fall time (4) CLOAD = 100 pF 20 35 ns
PWM COMPARATOR
EAOUT to RAMP input offset voltage RAMP = 0 V 0.72 0.85 1.05 V
DELAB = DELCD = REF
Minimum phase shift (5) RAMP = 0 V 0.0% 0.85% 1.4%
(OUTA to OUTC, OUTB to OUTD) EAOUT = 650 mV
tDELAY Delay (6) 0 V < RAMP < 2.5 V, EAOUT = 1.2 V 70 120 ns
(RAMP to OUTC, RAMP to OUTD) DELAB = DELCD = REF
IR(bias) RAMP bias current RAMP < 5 V, CT = 2.2 V –5 5 µA
IR(sink) RAMP sink current RAMP = 5 V, CT = 2.6 V 12 19 mA

(4) Ensured by design. Not production tested.

(5) Minimum phase shift is defined as:
t f (OUTC ) - t f (OUTA ) t f (OUTC ) - t f (OUTB )
F = 180 ´ or F = 180 ´
tPERIOD tPERIOD
where
(a) tf(OUTA) = falling edge of OUTA signal
(b) tf(OUTB) = falling edge of OUTB signal
(c) tf(OUTC) = falling edge of OUTC signal,
(d) tf(OUTD) = falling edge of OUTD signal
(e) tPERIOD = period of OUTA or OUTB signal

(6) Output delay is measured between OUTA and OUTB, or OUTC and OUTD. Output delay is defined as shown below where: tf(OUTA) =
falling edge of OUTA signal, tr(OUTB) = rising edge of OUTB signal (see Figure 1 and Figure 2).

tPERIOD

OUTA

OUTA
tDELAY = tR(OUTB) - tf(OUTA)
tDELAY = tf(OUTA) - tf(OUTC)

OUTB

OUTC

Figure 1. Same Applies to OUTB and OUTD Figure 2. Same Applies to OUTC and OUTD

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DEVICE INFORMATION

PW AND DW PACKAGE DRAWINGS N AND J PACKAGE DRAWINGS

(TOP VIEW) (TOP VIEW)
PW and DW PACKAGE
EAN 1 20 EAP
(TOP VIEW)
EAOUT 2 19 SS/DISB
EAN 1 20 EAP
RAMP 3 18 OUTA
EAOUT 2 19 SS/DISB
RAMP 3 18 OUTA REF 4 17 OUTB

REF 4 17 OUTB GND 5 16 PGND

GND 5 16 PGND
SYNC 6 15 VDD
SYNC 6 15 VDD
CT 7 14 OUTC CT 7 14 OUTC

RT 8 13 OUTD RT 8 13 OUTD
DELAB 9 12 CS
DELAB 9 12 CS
DELCD 10 11 ADS
DELCD 10 11 ADS

FN AND FK PACKAGE DRAWINGS

(TOP VIEW)
EAN
EAOUT EAP
RAMP SS/DISB

3 2 1 20 19

REF 4 18 OUTA
GND 5 17 OUTB
SYNC 6 16 PGND
CT 7 15 VDD
RT 8 14 OUTC
9 10 11 12 13

DELAB OUTD
DELCD CS
ADS

TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
The adaptive-delay-set pin sets the ratio between the maximum and minimum programmed output delay
ADS 11 I
dead time.
CS 12 I Current sense input for cycle-by-cycle current limiting and for over-current comparator.
Oscillator timing capacitor for programming the switching frequency. The UCC3895 oscillator charges CT via
CT 7 I
a programmed current.
The delay-programming between complementary-outputs pin, DELAB, programs the dead time between
DELAB 9 I
switching of output A and output B.
The delay-programming between complementary-outputs pin, DELCD, programs the dead time between
DELCD 10 I
switching of output C and output D.
EAOUT 2 I/O Error amplifier output.
EAP 20 I Non-inverting input to the error amplifier. Keep below 3.6 V for proper operation.
EAN 1 I Inverting input to the error amplifier. Keep below 3.6 V for proper operation.
GND 5 - Chip ground for all circuits except the output stages.

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TERMINAL FUNCTIONS (continued)

TERMINAL
I/O DESCRIPTION
NAME NO.
OUTA 18 O
OUTB 17 O The four outputs are 100-mA complementary MOS drivers, and are optimized to drive FET driver circuits
OUTC 14 O such as UCC27424 or gate drive transformers.
OUTD 13 O
PGND 16 - Output stage ground.
RAMP 3 I Inverting input of the PWM comparator.
5 V, ±1.2%, 5 mA voltage reference. For best performance, bypass with a 0.1-μF low ESR, low ESL
REF 4 O
capacitor to ground. Do not use more than 4.7 μF of total capacitance on this pin.
RT 8 I Oscillator timing resistor for programming the switching frequency.
SS/DISB 19 I Soft-start and disable pin which combines the two independent functions.
SYNC 6 I/O The oscillator synchronization pin is bidirectional.
The power supply input pin, VDD, must be bypassed with a minimum of a 1-μF low ESR, low ESL capacitor
VDD 15 I
to ground. The addition of a 10-μF low ESR, low ESL between VDD and PGND is recommended.

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BLOCK DIAGRAM

IRT
RT 8 Q 15 VDD
D S Q
8(IRT) OSC
CT 7 Q OUTA
18
D S Q DELAY A
Q
R
9 DELAB
SYNC 6
PWM R Q DELAY B
17 OUTB
COMPARATOR
RAMP 3
+

0.8 V +

EAOUT 2 OUTC
14
D S Q DELAY C
ERROR
AMP NO LOAD
EAP 20 10 DELCD
COMPARATOR
+
+
R Q DELAY D
EAN 1 13 OUTD
CURRENT SENSE
COMPARATOR 0.5 V / 0.6 V
2V + 16 PGND

CS 12
11 ADS
OVER CURRENT
ADAPTIVE DELAY
COMPARATOR
+ SET AMPLIFIER
2.5 V
+ 0.5V

Q S UVLO COMPARATOR
+
REF Q R
11 V / 9 V
DISABLE
IRT REF
COMPARATOR REF 4
HI=ON
0.5 V
REFERENCE OK
SS 19 + COMPARATOR
HI=ON 4V
5 GND
10(IRT) +

REF VREF

RT 8IRT

RT IRT

CT
2.5 V S Q CLOCK
+

CT

0.2 V + R

SYNC CLOCK

Figure 3. Oscillator Block Diagram

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REF

0.5 V

TO DELAY A
100 k: 75 k: + AND DELAY B
BLOCKS
CS DELAB
+
100 k:
ADS
75 k: REF

TO DELAY C
+ AND DELAY D DELCD
BLOCKS

Figure 4. Adaptive Delay Set Block Diagram

REF

BUSSED CURRENT
FROM ADS CIRCUIT

3.5 V
DELAB/CD
FROM PAD DELAYED
2.5 V CLOCK
SIGNAL

CLOCK

Figure 5. Delay Block Diagram (One Delay Block Per Outlet)

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DETAILED PIN DESCRIPTION

ADS (Adaptive Delay Set)

This function sets the ratio between the maximum and minimum programmed output-delay dead time. When the
ADS pin is directly connected to the CS pin, no delay modulation occurs. The maximum delay modulation occurs
when ADS is grounded. In this case, delay time is four-times longer when CS = 0 than when CS = 2 V (the peak-
current threshold), ADS changes the output voltage on the delay pins DELAB and DELCD by Equation 1.
VDEL = éë0.75 ´ (VCS - VADS )ùû + 0.5 V

where
• VCS and VADS are in volts (1)
ADS must be limited to between 0 V and 2.5 V and must be less-than or equal-to CS. DELAB and DELCD are
clamped to a minimum of 0.5 V.

CS (Current Sense)
The CS input connects to the inverting input of the current-sense comparator and the non-inverting input of the
overcurrent comparator and the ADS amplifier. The current sense signal is used for cycle-by-cycle current
limiting in peak current-mode control, and for overcurrent protection in all cases with a secondary threshold for
output shutdown. An output disable initiated by an overcurrent fault also results in a restart cycle, called soft-stop,
with full soft-start.

CT (Oscillator Timing Capacitor)

The UCC3895 oscillator charges CT via a programmed current. The waveform on CT is a sawtooth, with a peak
voltage of 2.35 V. The approximate oscillator period is calculated by Equation 2.
5 ´ R T ´ CT
t OSC = + 120 ns
48
where
• CT is in Farads
• RT is in Ohms
• tOSC is in seconds
• CT can range from 100 to 880 pF. (2)

NOTE
A large CT and a small RT combination results in extended fall times on the CT waveform.
The increased fall time increases the SYNC pulse width, hence limiting the maximum
phase shift between OUTA, OUTB and OUTC, OUTD outputs, which limits the maximum
duty cycle of the converter (see to Figure 3).

DELAB and DELCD (Delay Programming Between Complementary Outputs)

DELAB programs the dead time between switching of OUTA and OUTB. DELCD programs the dead time
between OUTC and OUTD. This delay is introduced between complementary outputs in the same leg of the
external bridge. The UCC2895N allows the user to select the delay, in which the resonant switching of the
external power stages takes place. Separate delays are provided for the two half-bridges to accommodate
differences in resonant-capacitor charging currents. The delay in each stage is set according to Equation 3.

tDELAY =
(25 ´ 10 )´ R
-12
DEL
+ 25 ns
VDEL
where
• VDEL is in volts
• RDEL is in Ohms
• tDELAY is in seconds (3)

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DELAB and DELCD source about 1 mA maximum. Choose the delay resistors so that this maximum is not
exceeded. Programmable output delay is defeated by tying DELAB and, or, DELCD to REF. For an optimum
performance keep stray capacitance on these pins at less than 10 pF.

EAOUT, EAP, and EAN (Error Amplifier)

EAOUT connects internally to the non-inverting input of the PWM comparator and the no-load comparator.
EAOUT is internally clamped to the soft-start voltage. The no-load comparator shuts down the output stages
when EAOUT falls below 500 mV, and allows the outputs to turn on again when EAOUT rises above 600 mV.
EAP is the non-inverting and the EAN is the inverting input to the error amplifier.

OUTA, OUTB, OUTC, and OUTD (Output MOSFET Drivers)

The four outputs are 100-mA complementary MOS drivers, and are optimized to drive MOSFET driver circuits.
OUTA and OUTB are fully complementary, (assuming no programming delay) and operate near 50% duty cycle
and one-half the oscillator frequency. OUTA and OUTB are intended to drive one half-bridge circuit in an external
power stage. OUTC and OUTD drive the other half-bridge and have the same characteristics as OUTA and
OUTB. OUTC is phase shifted with respect to OUTA, and OUTD is phase shifted with respect to OUTB.

NOTE
Changing the phase relationship of OUTC and OUTD with respect to OUTA and OUTB
requires other than the nominal 50% duty ratio on OUTC and OUTD during those
transients.

PGND (Power Ground)

To keep output switching noise from critical analog circuits, the UCC3895 has two different ground connections.
PGND is the ground connection for the high-current output stages. Both GND and PGND must be electrically tied
together. Also, because PGND carries high current, board traces must be low impedance.

RAMP (Inverting Input of the PWM Comparator)

This pin receives either the CT waveform in voltage and average current-mode controls, or the current signal
(plus slope compensation) in peak current-mode control.

REF (Voltage Reference)

The 5-V ± 1.2% reference supplies power to internal circuitry, and also supplies up to 5 mA to external loads.
The reference is shutdown during undervoltage lockout but is operational during all other disable modes. For
best performance, bypass with a 0.1-μF low-ESR low-ESL capacitor to GND. To ensure the stability of the
internal reference, do not use more than 1.0 μF of total capacitance on this pin for the UCC1895.
For the UCC2895 and the UCC3895, this capacitance increases as per the limits defined in the
RECOMMENDED OPERATING CONDITIONS table of this specification.

RT (Oscillator Timing Resistor)

The oscillator in the UCC3895 operates by charging an external timing capacitor, CT, with a fixed current
programmed by RT. RT current is calculated with Equation 4.
3V
IRT (A ) =
RT (W ) (4)
RT ranges from 40 to 120 kΩ. Soft-start charging and discharging currents are also programmed by IRT (Refer to
Figure 3).

GND (Analog Ground)

This pin is the chip ground for all internal circuits except the output stages.

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SS/DISB (Soft-Start/Disable)
This pin combines two independent functions.
Disable Mode: A rapid shutdown of the chip is accomplished by externally forcing SS/DISB below 0.5 V,
externally forcing REF below 4 V, or if VDD drops below the undervoltage lockout threshold. In the case of REF
being pulled below 4 V or an undervoltage condition, SS/DISB is actively pulled to ground via an internal
MOSFET switch.
If an overcurrent fault is sensed (CS = 2.5 V), a soft-stop is initiated. In this mode, SS/DISB sinks a constant
current of (10 × IRT). The soft-stop continues until SS/DISB falls below 0.5 V. When any of these faults are
detected, all outputs are forced to ground immediately.

NOTE
If SS/DISB is forced below 0.5 V, the pin starts to source current equal to IRT. The only
time the part switches into low IDD current mode, though, is when the part is in
undervoltage lockout.

Soft-start Mode: After a fault or disable condition has passed, VDD is above the start threshold, and, or,
SS/DISB falls below 0.5 V during a soft-stop, SS/DISB switches to a soft-start mode. The pin then sources
current, equal to IRT. A user-selected resistor/capacitor combination on SS/DISB determines the soft start time
constant.

NOTE
SS/DISB actively clamps the EAOUT pin voltage to approximately the SS/DISB pin
voltage during both soft-start, soft-stop, and disable conditions.

SYNC (Oscillator Synchronization)

This pin is bidirectional (refer to Figure 3). When used as an output, SYNC is used as a clock, which is the same
as the internal clock of the device. When used as an input, SYNC overrides the internal oscillator of the chip and
acts as the clock signal. This bidirectional feature allows synchronization of multiple power supplies. Also, the
SYNC signal internally discharge the CT capacitor and any filter capacitors that are present on the RAMP pin.
The internal SYNC circuitry is level sensitive, with an input-low threshold of 1.9 V, and an input-high threshold of
2.1 V. A resistor as small as 3.9 kΩ may be tied between SYNC and GND to reduce the sync pulse width.

VDD (Chip Supply)

This is the input pin to the chip. VDD must be bypassed with a minimum of 1-μF low ESR, low ESL capacitor to
ground. The addition of a 10-μF low ESR, low ESL between VDD and PGND is recommended.

12 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated

Product Folder Links: UCC1895 UCC2895 UCC3895

 UCC1895, UCC2895, UCC3895
www.ti.com SLUS157P – DECEMBER 1999 – REVISED JUNE 2013

TYPICAL CHARACTERISTICS
OUTPUT DELAY (tDELAY) OSCILLATOR FREQUENCY (fSW)
vs vs
DELAY RESISTANCE (RDEL) TIMING CAPACITANCE (CT)
2000 1600
Vcs = 0 V RT = 47 k
1800 1400 RT = 62 k
Vcs = 2 V RT = 82 k

Oscillator Frequency (kHz)

1600
1200 RT = 100 k
1400
Output Delay (ns)

1200 1000

1000 800
800 600
600
400
400
200 200

0 0
0 10 20 30 40 100 1000
Delay Resistance (k C001 Timing Capacitance (pF) C002

Figure 6. Figure 7.

EAOUT to RAMP OFFSET (VOFFSET) AMPLIFIER GAIN AND PHASE MARGIN

vs vs
TEMPERATURE (TA) FREQUENCY (fOSC)
1.00 100 200

80 160
EAOUT to Ramp Offset (V)

0.95

Phase Margin (ƒC)

60 120
Gain (dB)

0.90 40 80

20 40
0.85 Gain (dB)

Phase Margin (°C)

0 0
1 10 100 1k 10k 100k 1M 10M
0.80 Frequency (Hz) C004
±60 ±40 ±20 0 20 40 60 80 100 120
Temperature (ƒC) C003

Figure 8. Figure 9.

INPUT CURRENT (IDD) INPUT CURRENT (IDD)

vs vs
OSCILLATOR FREQUENCY (fOSC) OSCILLATOR FREQUENCY (fOSC)
9 13
Vdd = 10 V Vdd = 10 V
Vdd = 12 V 12 Vdd = 12 V
Vdd = 15 V Vdd = 15 V
8 11
Vdd = 17 V Vdd = 17 V
10
7
Idd (mA)

Idd (mA)

8
6
7

5 6

4 4
0 400 800 1200 1600 0 400 800 1200 1600
Oscillator Frequency (kHz) C005 Oscillator Frequency (kHz) C006

Figure 10. Figure 11.

Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: UCC1895 UCC2895 UCC3895
UCC1895, UCC2895, UCC3895
SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 www.ti.com

APPLICATION INFORMATION

Programming DELAB, DELCD and the Adaptive Delay Set

The UCC2895N allows the user to set the delay between switch commands within each leg of the full-bridge
power circuit according to Equation 5.

tDELAY =
(25 ´ 10 )´ R
-12
DEL
+ 25 NS
VDEL (5)
From Equation 5 VDEL is determined in conjunction with the desire to use (or not) the ADS feature from
Equation 6.
VDEL = éë0.75 ´ (VCS - VADS )ùû + 0.5 V (6)
Figure 12 illustrates the resistors needed to program the delay periods and the ADS function.
UCC3895

CS 12
9 DELAB
RDELAB

10 DELCD ADS 11

RDELCD

Figure 12. Programming Adaptive Delay Set

The ADS allows the user to vary the delay times between switch commands within each of the two legs of the
converter. The delay-time modulation is implemented by connecting ADS (pin 11) to CS, GND, or a resistive
divider from CS through ADS to GND to set VADS as shown in Figure 12. From Equation 6 for VDEL, if ADS is tied
to GND then VDEL rises in direct proportion to VCS, causing a decrease in tDELAY as the load increases. In this
condition, the maximum value of VDEL is 2 V.
If ADS is connected to a resistive divider between CS and GND, the term (VCS – VADS) becomes smaller,
reducing the level of VDEL. This reduction decreases the amount of delay modulation. In the limit of ADS tied to
CS, VDEL = 0.5 V and no delay modulation occurs. Figure 13 graphically shows the delay time versus load for
varying adaptive delay set feature voltages (VADS).
In the case of maximum delay modulation (ADS = GND), when the circuit goes from light load to heavy load, the
variation of VDEL is from 0.5 to 2 V. This change causes the delay times to vary by a 4:1 ratio as the load is
changed.
The ability to program an adaptive delay is a desirable feature because the optimum delay time is a function of
the current flowing in the primary winding of the transformer, and changes by a factor of 10:1 or more as circuit
loading changes. Reference 5 (see References) describes the many interrelated factors for choosing the
optimum delay times for the most efficient power conversion, and illustrates an external circuit to enable ADS
using the UC3879. Implementing this adaptive feature is simplified in the UCC3895 controller, giving the user the
ability to tailor the delay times to suit a particular application with a minimum of external parts.

14 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated

Product Folder Links: UCC1895 UCC2895 UCC3895

 UCC1895, UCC2895, UCC3895
www.ti.com SLUS157P – DECEMBER 1999 – REVISED JUNE 2013

DELAY TIME
vs
CURRENT SENSE VOLTAGE
A = VADS/VCS RDELAY = 10k

500 A=1.0

DELAY TIME (ns)

400

300 A=0.8

A=0.6
200
A=0.4
A=0.2
A=0.1
100
0 0.5 1.0 1.5 2.0 2.5
CURRENT SENSE VOLTAGE (V)
Figure 13. Delay Time Under Varying ADS Voltages

CLOCK

RAMP
&
COMP

PWM
SIGNAL

OUTPUT A

OUTPUT B

OUTPUT C

OUTPUT D

No Output Delay Shown, COMP to RAMP offset not included.

Figure 14. UCC3895 Timing Diagram

Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: UCC1895 UCC2895 UCC3895
UCC1895, UCC2895, UCC3895
SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 www.ti.com

References
1. M. Dennis, A Comparison Between the BiCMOS UCC3895 Phase Shift Controller and the UC3875,
Application Note (SLUA246).
2. L. Balogh, The Current-Doubler Rectifier: An Alternative Rectification Technique for Push--Pull and Bridge
Converters, Application Note (SLUA121).
3. W. Andreycak, Phase Shifted, Zero Voltage Transition Design Considerations, Application Note (SLUA107).
4. L. Balogh, The New UC3879 Phase Shifted PWM Controller Simplifies the Design of Zero Voltage Transition
Full-Bridge Converters, Application Note (SLUA122).
5. L. Balogh, Design Review: 100 W, 400 kHz, dc-to-dc Converter with Current Doubler Synchronous
Rectification Achieves 92% Efficiency, Unitrode Power Supply Design Seminar Manual, SEM-1100, 1996,
Topic 2.
6. UC3875 Phase Shift Resonant Controller, Datasheet (SLUS229).
7. UC3879 Phase Shift Resonant Controller, Datasheet (SLUS230).
8. UCC3895EVM--1, Configuring the UCC3895 for direct Control Driven Synchronous Rectification (SLUU109).
9. UCC3895,CD Output Asymetrical Duty Cycle Operation (SLUA275).
10. Texas Instrument’s Literature Number SLUA323.
11. Synchronous Rectifiers of a Current Doubler (SLUA287).

16 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated

Product Folder Links: UCC1895 UCC2895 UCC3895

 UCC1895, UCC2895, UCC3895
www.ti.com SLUS157P – DECEMBER 1999 – REVISED JUNE 2013

REVISION HISTORY

Changes from Revision N (May 2009) to Revision O Page

• Added thermal information table. .......................................................................................................................................... 2

• Changed REF pin description from “Do not use more than 1.0 μF of total capacitance on this pin.” to “Do not use
more than 4.7 μF of total capacitance on this pin.” ............................................................................................................ 11

Changes from Revision O (April 2010) to Revision P Page

• Changed Q package drawing to updated FN throughout ..................................................................................................... 2

• Changed L package drawing to updated FK throughout and corresponding package type from CLCC to updated
LCCC throughout .................................................................................................................................................................. 2
• Added The CS input connects to text to the beginning of the CS Detailed Pin Description. ............................................. 10
• Added second paragraph to detailed REF Pin Description and included the UCC1895 at the end of the first
paragraph to differentiate capacitance capabilities of the devices. .................................................................................... 11
• Changed UCC3895 Timing Diagram in the Application Information section to reflect the maximum duty cycle
conditions ............................................................................................................................................................................ 15

Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: UCC1895 UCC2895 UCC3895
 PACKAGE OPTION ADDENDUM

www.ti.com 22-Mar-2019

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

UCC1895J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 UCC1895J

UCC1895L ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 UCC1895L

UCC2895DW ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2895DW
& no Sb/Br)
UCC2895DWG4 ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2895DW
& no Sb/Br)
UCC2895DWTR ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2895DW
& no Sb/Br)
UCC2895DWTRG4 ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2895DW
& no Sb/Br)
UCC2895N ACTIVE PDIP N 20 18 Green (RoHS CU NIPDAU | Call TI N / A for Pkg Type -40 to 85 UCC2895N
& no Sb/Br)
UCC2895PW ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2895
& no Sb/Br)
UCC2895PWTR ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 UCC2895
& no Sb/Br)
UCC3895DW ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3895DW
& no Sb/Br)
UCC3895DWG4 ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3895DW
& no Sb/Br)
UCC3895DWTR ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3895DW
& no Sb/Br)
UCC3895DWTRG4 ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3895DW
& no Sb/Br)
UCC3895N ACTIVE PDIP N 20 18 Green (RoHS CU NIPDAU | Call TI N / A for Pkg Type 0 to 70 UCC3895N
& no Sb/Br)
UCC3895NG4 ACTIVE PDIP N 20 18 Green (RoHS Call TI N / A for Pkg Type 0 to 70 UCC3895N
& no Sb/Br)
UCC3895PW ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3895
& no Sb/Br)
UCC3895PWTR ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3895
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 22-Mar-2019

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

UCC3895PWTRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 UCC3895
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UCC1895, UCC2895, UCC3895 :

• Catalog: UCC3895

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 22-Mar-2019

• Automotive: UCC2895-Q1
• Enhanced Product: UCC2895-EP
• Military: UCC1895

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC2895PWTR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
UCC3895DWTR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Feb-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC2895PWTR TSSOP PW 20 2000 367.0 367.0 38.0
UCC3895DWTR SOIC DW 20 2000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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