DESIGN SIMULATION and ANALYSIS of 5T-SRAM

Cell Using Different Foundries

Preeti Singh Rajesh Mehra

ME Scholar Associate Professor
Electronics & Communication Department Electronics & Communication Department
NITTTR, Chandigarh NITTTR, Sector-26
singh.preeti060@yahoo.com Chandigarh, India

ABSTRACT: A comparative analysis of power RAM) and DRAM (Dynamic RAM) both holds the
dissipation and surface area of the 5T Static data but in different manners (1).But DRAM
Random access memory cell has been presented requires the data to be refreshed periodically in
in this paper. Many advance processors now order to retain the data. SRAM does not need to be
have on chip instructions and data memory refreshed as the transistors inside would continue to
using SRAMs. The major contribution of power hold the data as long as the power supply is not cut
dissipation in SRAM cell is off-state leakage off. The additional circuitry and timing are needed
current. Thus, improving the power efficiency of to refresh the DRAM periodically, which makes
a SRAM cell is critical to the overall system DRAM memory slower and less desirable than
power dissipation. Analysis is based on the SRAM. One complication is the much higher
observation of a 5T SRAM cell for high density power used by DRAM One complication is the
and low power applications which can retain its much higher power used by DRAM memory.
data with leakage current and positive feedback
without refresh cycle .The developed circuit has With the advantages of high speed and ease of
been implemented on 45 nm and 65 nm use, static random access memory (SRAM) has
technology and their performances has been been widely used in system-on-chips (SoC).
compared in terms of power dissipation and According to the International Technology
surface area. This paper investigates the Roadmap for Semiconductors (ITRS) forecast,
effectiveness of 5T SRAM circuit design Memory is going to occupy 90% of the SoC area
techniques and power dissipation and chip by 2013 memory [3]. The International Technology
density analysis. 5T SRAM cell is designed with Roadmap for Semiconductors predicts the gate
the schematic design technique for the analysis equivalent oxide thickness as low as 0.5nm for
of power dissipation and area using DSCH and future CMOS technologies [1]. Since the gate
microwind3.1 Tool leakage current of MOS transistors increases
exponentially with the reduction of the oxide
Keywords: 5TSRAM Cell, CMOS, Surface Area thickness over the active region of a transistor, the
Leakage Current gate leakage power dissipation is expected to
become a significant fraction of the overall chip
I. INTRODUCTION power dissipation in nanometre CMOS design
processes.
SRAM stands for static random access memory.
SRAM is volatile in nature; it means that it Present day workstations, low-power processors,
contains the data as long as power supply is not computers and super computers are using fast
turned off. Semiconductor memories, particularly SRAMs and will require, in the future, larger
SRAMs are widely used in electronic system [1]. A density memories with faster access time [4]. High-
significant percentage of the total area and power density, low-power SRAMs are needed for
of many digital chips are due to SRAMs. For these applications such as hand-held terminals, laptops,
chips, the SRAM leakage dominates the total chip notebooks and IC memory cards, due to the fact
leakage. Lowering the supply voltage (VDD) for that these devices frequently use battery as power
SRAMs may reduce the leakage and switching source and hence it should consume power as low
power consumptions [2]. Static Random Access as possible, also it is necessary for maintaining low
Memory is mainly used in various kinds of portable cooling and packing costs for these devices. The
Devices systems. SRAM plays an important role power dissipation reduction in SRAMs is not only
in modern mobile phones, microprocessors, due to power supply voltage reduction, but also due
microcontrollers, and computers etc. SRAM (Static
to low-power circuit techniques. An SRAM cell the bit line input-drivers are designed to be much
must be designed such that it provides a non- stronger than the relatively weak transistors in the
destructive read operation and a reliable write cell itself, so that they can easily override the
operation. These two requirements impose previous state of the cross-coupled inverters.
contradicting requirements SRAM cell sizing Careful sizing of the transistors in an SRAM cell is
needed to ensure proper operation.
2 .5T SRAM CELL:

Fig 3.Timing Diagram (write operation)

3. SCHEMATIC DESIGN:
Fig.1 5T SRAM Cell
There may exist several variants of the 45 nm
Read Operation: Prior to initiating a read operation, Process technology. One corresponds to the highest
the bit line is pre charged to VDD. The read possible speed; at the very high leakage current
operation is initiated by enabling the word line .This technology is called high speed as it is
(WL) and connecting the pre charged bit lines, BL dedicated to supplications for which the primary
to the internal nodes of the cell. Upon read access objective is the highest speed.
shown in Figure 2, the bit line voltage VBL
remains at the pre charge level [2].

Fig4. Schematic Design

Fig.2 Timing Diagram (Read Operation)

Write Operation: The start of a write cycle begins

by applying the value to be written to the bit lines
[2]. If we wish to write a 0, we would apply a 0 to
the bit lines, i.e. setting BL to 1 and BL to 0. This
is similar to applying a reset pulse to an SR-latch,
which causes the flip flop to change state [3]. A 1 is
written by inverting the values of the bit lines. WL
is then asserted and the value that is to be stored is
latched in. Note that the reason this works is that Fig5. Schematic simulation waveform
4.LAYOUT DESIGN received surface area obtain is 2.3µm2 and power
consumption is 3.805 microwatt
The layouts of SRAM and conventional SRAM
cells Drawn in a 45nm & 65 standard CMOS
technology are given in Fig.4 & 5. We have used
the layout guidelines which are a scaled version of
the 90nm technology. They could also be obtained
by scaling the sizes and dimensions.

Fig 8: 65 nm layout simulation waveform

Fig 6. LAYOUT of 5T SRAM cell in 65 nm

Foundry
Fig 9: 65 nm layout simulation waveform

.
Fig 10. 45 nm layout simulated waveforms

Fig 7.LAYOUT of 5T SRAM cell in 45 nm

Foundry

We have done a proper simulation of 5T SRAM cell

by microwind 3.1 simulation tool in 45 nm CMOS
technology and 65 nm cmos technologies. A
comparative analysis of 5T SRAM cell is done on
the basis of surface area and power consumption
shown in table1.In simulation time we analyse that
in 65 nm technology total surface area calculated is
4.5 µm2 and the power consumption by the circuit
is 70.910 microwatt. In 45 nm cmos technology Fig 11. 45 nm layout simulated waveform
 Table 1
5)Sunil Kumar Ojha & P.R. Vaya,
Width: 2.0µm 70.910 A Novel Architecture of SRAM Cell for
65 nm
(57 lambda) microwatt Low-Power Application.ISSN
Height: 2.3µm (Print): 2278-8948, Volume-2, Issue-4, 2013
(65 lambda)
Surf: 4.5µm2
(0.0 mm)

Width: 1.4µm
45 nm 3.805
(57 lambda)
Height: 1.6µm
microwatt
(65 lambda)
Surf: 2.3µm2
(0.0 mm2)

5. CONCLUSION:

In this paper, a comparative analysis of 5T SRAM

cell has done in 45 nm & 65 nm technology and
been proposed to construct in 45 nm technology
giving better performance parameter than other one.
Low power consuming 45 nm technology
accomplish better read stability, reduce bit line
leakage problem, and provides low leakage current
Simulation results show that the SRAM cell in 45
nm technology achieves about 94% percent power
saving and Reduce surface area by 48.88%
compared with conventional.5T SRAM cell using
65 nm CMOS technology.

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and Low Leakage Current Based 5T, 2011 IEEE

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