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The document describes 11 test cases for scan insertion lab observations. For each test case, inputs like the synthesis netlist and library model and outputs like the scan inserted netlist are listed. 14 observation points are provided to analyze and document for each test case.

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senthilkumar
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44 views

Details

The document describes 11 test cases for scan insertion lab observations. For each test case, inputs like the synthesis netlist and library model and outputs like the scan inserted netlist are listed. 14 observation points are provided to analyze and document for each test case.

Uploaded by

senthilkumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

SCAN INSERTION LAB OBSERVATIONS


Test Case 1: -
Problem Definition: -
Inputs: -

 Synthesis Netlist
 Library Model
 Dofile commands
Outputs: -

 Scan inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def
What is issue?
How resolved?
Observations: -
1) Write block diagram with all DFT inputs?
2) How many clock domains?
3) How many resets?
4) Number of scan chains
5) Clock mixing or not clock mixing?
6) How many Lackup-latches are added during scan insertion?
7) Is it top-down or bottom up approach?
8) How many terminal lockup latches are added?
9) Number of scan flops and non-scan flops in the design?
10) Chain length?
11) Number of DRC violations?
12) Write diagram with issues?
13) Write diagram with solution?
14) Log file: - please note your observations from the log file

Vlsiguru Confidential 1
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

Test Case 2: -
Problem Definition: -
Inputs: -

 Synthesis Netlist
 Library Model
 Dofile commands
Outputs: -

 Scan inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def
What is issue?
How resolved?
Observations: -
1) Write block diagram with all DFT inputs?
2) How many clock domains?
3) How many resets?
4) Number of scan chains?
5) Clock mixing or not clock mixing?
6) How many Lackup-latches are added during scan insertion?
7) Is it top-down or bottom up approach?
8) How many terminal lockup latches are added?
9) Number of scan flops and non-scan flops in the design?
10) Chain length?
11) Number of DRC violations?
12) Write diagram with issues?
13) Write diagram with solution?
14) Log file: - please note your observations

Vlsiguru Confidential 2
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

Test Case 3: -
Problem Definition: -
Inputs: -

 Synthesis Netlist
 Library Model
 Dofile commands
Outputs: -

 Scan inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def
What is issue?
How resolved?
Observations: -
1) Write block diagram with all DFT inputs?
2) How many clock domains?
3) How many resets?
4) Number of scan chains
5) Clock mixing or not clock mixing?
6) How many Lackup-latches are added during scan insertion?
7) Is it top-down or bottom up approach?
8) How many terminal lockup latches are added?
9) Number of scan flops and non-scan flops in the design?
10) Chain length?
11) Number of DRC violations?
12) Write diagram with issues?
13) Write diagram with solution?
14) Log file: - please note your observations from the log file

Vlsiguru Confidential 3
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

Test Case 4: -
Problem Definition: -
Inputs: -

 Synthesis Netlist
 Library Model
 Dofile commands
Outputs: -

 Scan inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def
What is issue?
How resolved?
Observations: -
1) Write block diagram with all DFT inputs?
2) How many clock domains?
3) How many resets?
4) Number of scan chains
5) Clock mixing or not clock mixing?
6) How many Lackup-latches are added during scan insertion?
7) Is it top-down or bottom up approach?
8) How many terminal lockup latches are added?
9) Number of scan flops and non-scan flops in the design?
10) Chain length?
11) Number of DRC violations?
12) Write diagram with issues?
13) Write diagram with solution?
14) Log file: - please note your observations from the log file

Vlsiguru Confidential 4
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

Test Case 5: -
Problem Definition: -
Inputs: -

 Synthesis Netlist
 Library Model
 Dofile commands
Outputs: -

 Scan inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def
What is issue?
How resolved?
Observations: -
1) Write block diagram with all DFT inputs?
2) How many clock domains?
3) How many resets?
4) Number of scan chains
5) Clock mixing or not clock mixing?
6) How many Lackup-latches are added during scan insertion?
7) Is it top-down or bottom up approach?
8) How many terminal lockup latches are added?
9) Number of scan flops and non-scan flops in the design?
10) Chain length?
11) Number of DRC violations?
12) Write diagram with issues?
13) Write diagram with solution?
14) Log file: - please note your observations from the log file

Vlsiguru Confidential 5
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

Test Case 6: -
Problem Definition: -
Inputs: -

 Synthesis Netlist
 Library Model
 Dofile commands
Outputs: -

 Scan inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def
What is issue?
How resolved?
Observations: -
1) Write block diagram with all DFT inputs?
2) How many clock domains?
3) How many resets?
4) Number of scan chains
5) Clock mixing or not clock mixing?
6) How many Lackup-latches are added during scan insertion?
7) Is it top-down or bottom up approach?
8) How many terminal lockup latches are added?
9) Number of scan flops and non-scan flops in the design?
10) Chain length?
11) Number of DRC violations?
12) Write diagram with issues?
13) Write diagram with solution?
14) Log file: - please note your observations from the log file

Vlsiguru Confidential 6
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

Test Case 7: -
Problem Definition: -
Inputs: -

 Synthesis Netlist
 Library Model
 Dofile commands
Outputs: -

 Scan inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def
What is issue?
How resolved?
Observations: -
1) Write block diagram with all DFT inputs?
2) How many clock domains?
3) How many resets?
4) Number of scan chains
5) Clock mixing or not clock mixing?
6) How many Lackup-latches are added during scan insertion?
7) Is it top-down or bottom up approach?
8) How many terminal lockup latches are added?
9) Number of scan flops and non-scan flops in the design?
10) Chain length?
11) Number of DRC violations?
12) Write diagram with issues?
13) Write diagram with solution?
14) Log file: - please note your observations from the log file

Vlsiguru Confidential 7
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

Test Case 8: -
Problem Definition: -
Inputs: -

 Synthesis Netlist
 Library Model
 Dofile commands
Outputs: -

 Scan inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def
What is issue?
How resolved?
Observations: -
1) Write block diagram with all DFT inputs?
2) How many clock domains?
3) How many resets?
4) Number of scan chains
5) Clock mixing or not clock mixing?
6) How many Lackup-latches are added during scan insertion?
7) Is it top-down or bottom up approach?
8) How many terminal lockup latches are added?
9) Number of scan flops and non-scan flops in the design?
10) Chain length?
11) Number of DRC violations?
12) Write diagram with issues?
13) Write diagram with solution?
14) Log file: - please note your observations from the log file

Vlsiguru Confidential 8
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

Test Case 9: -
Problem Definition: -
Inputs: -

 Synthesis Netlist
 Library Model
 Dofile commands
Outputs: -

 Scan inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def
What is issue?
How resolved?
Observations: -
1) Write block diagram with all DFT inputs?
2) How many clock domains?
3) How many resets?
4) Number of scan chains
5) Clock mixing or not clock mixing?
6) How many Lackup-latches are added during scan insertion?
7) Is it top-down or bottom up approach?
8) How many terminal lockup latches are added?
9) Number of scan flops and non-scan flops in the design?
10) Chain length?
11) Number of DRC violations?
12) Write diagram with issues?
13) Write diagram with solution?
14) Log file: - please note your observations from the log file

Vlsiguru Confidential 9
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

Test Case 10: -


Problem Definition: -
Inputs: -

 Synthesis Netlist
 Library Model
 Dofile commands
Outputs: -

 Scan inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def
What is issue?
How resolved?
Observations: -
1) Write block diagram with all DFT inputs?
2) How many clock domains?
3) How many resets?
4) Number of scan chains
5) Clock mixing or not clock mixing?
6) How many Lackup-latches are added during scan insertion?
7) Is it top-down or bottom up approach?
8) How many terminal lockup latches are added?
9) Number of scan flops and non-scan flops in the design?
10) Chain length?
11) Number of DRC violations?
12) Write diagram with issues?
13) Write diagram with solution?
14) Log file: - please note your observations from the log file

Vlsiguru Confidential 10
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

Test Case 11: -


Problem Definition: -
Inputs: -

 Synthesis Netlist
 Library Model
 Dofile commands
Outputs: -

 Scan inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def
What is issue?
How resolved?
Observations: -
1) Write block diagram with all DFT inputs?
2) How many clock domains?
3) How many resets?
4) Number of scan chains
5) Clock mixing or not clock mixing?
6) How many Lackup-latches are added during scan insertion?
7) Is it top-down or bottom up approach?
8) How many terminal lockup latches are added?
9) Number of scan flops and non-scan flops in the design?
10) Chain length?
11) Number of DRC violations?
12) Write diagram with issues?
13) Write diagram with solution?
14) Log file: - please note your observations from the log file

Vlsiguru Confidential 11
VLSIGURU DFT TRAINING SCAN INSERTION LAB OBSERVATIONS

Test Case 12: -


Problem Definition: -
Inputs: -

 Synthesis Netlist
 Library Model
 Dofile commands
Outputs: -

 Scan inserted Netlist


 ATPG Dofile
 ATPG Testproc
 Scan Def
What is issue?
How resolved?
Observations: -
1) Write block diagram with all DFT inputs?
2) How many clock domains?
3) How many resets?
4) Number of scan chains
5) Clock mixing or not clock mixing?
6) How many Lackup-latches are added during scan insertion?
7) Is it top-down or bottom up approach?
8) How many terminal lockup latches are added?
9) Number of scan flops and non-scan flops in the design?
10) Chain length?
11) Number of DRC violations?
12) Write diagram with issues?
13) Write diagram with solution?
14) Log file: - please note your observations from the log file

Vlsiguru Confidential 12

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