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    Memory Locations, Address, Instructions and Instruction Sequencing

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    PRASANTH S 17EIR070
    This document discusses computer memory organization and instruction sequencing. It explains that memory stores both instructions and data using an addressing scheme. It describes how memory is addressed using a number of address bits and how many memory locations are available given the address width. The document also discusses byte ordering schemes and provides an example of memory addressing. Finally, it introduces the concept of instruction sequencing and common CPU instruction formats, emphasizing the use of registers to improve performance over multiple memory accesses.

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    Memory Locations, Address, Instructions and Instruction Sequencing

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    PRASANTH S 17EIR070
    38 views13 pages
    This document discusses computer memory organization and instruction sequencing. It explains that memory stores both instructions and data using an addressing scheme. It describes how memory is addressed using a number of address bits and how many memory locations are available given the address width. The document also discusses byte ordering schemes and provides an example of memory addressing. Finally, it introduces the concept of instruction sequencing and common CPU instruction formats, emphasizing the use of registers to improve performance over multiple memory accesses.

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    Microprocessor 8085

    Original Title

    Lecture 5

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    This document discusses computer memory organization and instruction sequencing. It explains that memory stores both instructions and data using an addressing scheme. It describes how memory is addressed using a number of address bits and how many memory locations are available given the address width. The document also discusses byte ordering schemes and provides an example of memory addressing. Finally, it introduces the concept of instruction sequencing and common CPU instruction formats, emphasizing the use of registers to improve performance over multiple memory accesses.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    38 views13 pages

    Memory Locations, Address, Instructions and Instruction Sequencing

    Uploaded by

    PRASANTH S 17EIR070
    This document discusses computer memory organization and instruction sequencing. It explains that memory stores both instructions and data using an addressing scheme. It describes how memory is addressed using a number of address bits and how many memory locations are available given the address width. The document also discusses byte ordering schemes and provides an example of memory addressing. Finally, it introduces the concept of instruction sequencing and common CPU instruction formats, emphasizing the use of registers to improve performance over multiple memory accesses.

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    You are on page 1of 13

    Memory Locations, Address,

    Instructions and Instruction Sequencing

    Read pages 28-40


    Memory locations and addresses

    • The simple computer is a good start to


    understand computer organizations
    • We need to study
    – how data/instructions are organized in the main
    memory?
    – how is memory addressed? – addressing mode
    Memory
    • Holds both instructions and data
    • With k address bits and n bits per location
    Address
    k Number of locations 0 n-1 ... 1 0
    10 2
    10
    = 1024 = 1K 1
    16 2
    16 2 = 65,536 = 64K .
    20
    20 2 = 1,048,576 = 1M .
    24 .
    24 2 = 16,777,216 = 16M
    k
    2 -1

    • n is typically 8 (byte), 16 (word), 32 (long word), ….


    Memory stores both data and instructions
    • Consider 32-bit long word in each location which can store
    – 32-bit 2’s complement number (integer):
    n-1 n-1
    (-2 ) – (2 – 1)
    30
    • If n = 32: - 2G – 2G-1 (recall that G = 2 )
    – 4 ASCII characters
    - It is often
    convenient to
    byte byte byte byte address operands
    which are as short
    – A machine instruction as 1 byte

    byte 3 bytes

    Op Code Address information


    Dealing with strings of characters
    • Byte addressable machine is almost universal
    - Successive addresses refer to successive byte locations
    - There are two different schemes for addressing byte:
    big-endian little – endian
    Address Address
    0 0 1 2 3 0 3 2 1 0
    4 4 5 6 7 4 7 6 5 4
    8 8
    . .
    . .
    . .

    - Also bit can be numbered the other way around: bit 0


    is the MSB
    Memory addressing Example – for a
    Computer
    - Word = 16 bits
    - Byte addressable – uses big-endian
    - Long word = 4 bytes
    - 24 bits used for address 16 M bytes or 8 M
    words
    Instructions and instruction sequencing
    • Example computer instruction format:
    - Uses multiple words of 16 bits
    Op Code Address Inf.
    Opcode word
    4 bits 12 bits (plus some addressing inf.)
    Second word

    Third word

    - Typical instruction is Add: C = A+B


    - Most general instruction is to add 2 numbers in
    memory and store in a 3rd location
    Add A, B, C [A]+[B]  C
    Problems for instructions with multiple
    memory locations
    1. Long instructions
    - Address of an operand = 24 bits
    - Instruction length = 3 x 24 bits + opcode (4 bits) = 76 bits
    – too much memory space
    - Solutions: a) Use one- or two-address instruction:
    Add A, B: [A]+[B]  B
    Add A: [A]+[AC]  AC
    b) Use general-purpose CPU register
    Often 8-64 bits of them
    - 8 registers  use only 3 bits to select a CPU reg.
    Problems for instructions with multiple
    memory locations (continued)
    2. Memory access time is too long
    – Recall that memory access is always slow
    – Multiple memory access consumes a lot of time
    – Solutions: use CPU registers to store operands and
    temporary results
    – Minimizing the frequency with which data moved back
    and forth between main memory
    Modern CPUs are designed with the above two issues
    in mind
    e.g. ADD A, D1 [A]+[D1]  D1
    Registers on
    CPU

    All are visible to


    programmer.
    Compare with our simple computer

    1. D7 – D0 are equivalent to AC (accumulator)


    2. A7 - A0 are equivalent to ? – none in our simple
    computer
    3. PC (program counter) is the same as PC
    4. SR (status register) – none in our simple computer
    5. Where are X, MDR, MAR, and IR?
    6. Those are not visible to the programmer
    7. Guess how many invisible registers in the CPU?
    Some instructions for illustration
    • ADD -- 2 operand instruction
    – e.g. ADD B, D0 [B]+[D0]  D0

    Memory location, data register 0


    – Either source or destination must be one of the 8 data
    registers
    – Both can be data register
    • MOVE – similar to ADD
    – e.g. MOVE A, D0 [A]  D0
    – To do C = A+B MOVE.L A, D0
    ADD.L B, D0
    MOVE.L D0, C
    Some instructions for illustration (continued)
    • SUB (subtract)
    – e.g. SUB B, D0 [D0] - [B]  D0
    • CMP (compare)
    – e.g. CMP B, D0 [D0] - [B] and set/reset N, Z, V, C
    • MOVEA (move address)
    – e.g. MOVEA ADDR, A3 [ADDR]  A3
    • CLR A 0A (clear data register or
    – Can use .B, .W, or .L memory location)
    • TST A [A] – 0 and set/reset N, Z; make V, C=0
    – Can use .B, .W, or .L
    • ADDQ #2, D5 [D5] + 2  D5 quick addition
    • SUBQ #1, D4 [D4] - 1  D4 quick subtraction

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