ELECTRICAL, COMPUTER, TELECOMMUNICATIONS ENGINEERING TECHNOLOGY

Embedded Systems Design I 0618-561

Using Program Controlled Input and Output

Educational Objective
The educational objective of this lab relates to the learning objectives the course. After completing this lab, you
will
1. Understand how to work with programmed I/O devices.
2. Understand the advantages and disadvantages of polling and interrupt I/O devices.
3. Improve your understanding with embedded programming for Nios II processor using Assembly and C
programming language.
4. Improve your VHDL by using the concepts of hierarchical design and reuse.

Technical Objective
The technical objective of this laboratory is to investigate the use of devices that provide input and output
capabilities for a processor and are controlled by software. This laboratory will examine these program-controlled
I/O operations from both the hardware and software points of view. It will make use of parallel interfaces, PIOs, in
a Nios II system implemented on the Altera DE2 board.

Pre-Laboratory
1. Read and understand the deliverables you are expected to submit to the dropbox at the end of the lab.
2. Read and understand the lab procedure section.
3. Review Programming Style and Coding Guideline.
4. Read and understand the PIO Core (see Embedded Peripheral User Guide)
5. Write the programs for parts II, III, IV and V.

Documentation
This lab sheet is provided to you as reference and may not contain every step or configuration will be provided. It
is your responsibility as a Design Engineer to collect and understand all the requirements needed to complete the
lab. This includes obtaining any additional information from the discussion board on myCourses, any previous lab
or from any course lecture material.
It is also your responsibility to fully document the lab requirements and results in your laboratory portfolio so that
you have enough information to reference later.

Deliverables
For this lab, you will submit the following files so that the design may be re-compiled and verified on the DE2
board if needed. The file will be organized into directories as requested below and then submitted to the
appropriate myCourses dropbox as a Window’s compressed file.
NOTE: Remember to make sure your code is fully commented following the Programming Style and Coding
Guidelines before submitting.

Create a directory labeled Lab3/Quartus/part3 and place the archive file (*.qar) of your Quartus II design.
When you create the archive file, make sure all you VHDL files and *.qsys file are included in the archive. The
archive file should contain all the files that are required to allow your design to be regenerated.
Create a directory labeled Lab3/Quartus/part4 and place the archive file (*.qar) of your Quartus II design.
When you create the archive file, make sure all you VHDL files and *.qsys file are included in the archive. The
archive file should contain all the files that are required to allow your design to be regenerated.

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Embedded Systems Design I 0618-561

Using Program Controlled Input and Output

Create a directory labeled Lab3/Quartus/part5 and place the archive file (*.qar) of your Quartus II design. This
archive file will contains all the files that are required to allow your design to be regenerated.
Create a directory labeled Lab3/Nios/Part3. In this directory you will place your source code files for part3.
Create a directory labeled Lab3/Nios/Part4. In this directory you will place your source code files for part4.
Create a directory labeled Lab3/Nios/Part5. In this directory you will place your source code files for part5.

Lab-Procedure
The application task in this exercise consists of adding together a set of signed 8-bit numbers that are entered via
the toggle switches on Altera’s DE2 board. The resulting sum is displayed on the LEDs and 7-segment displays.
A high-level block diagram of the final design is shown in below in Figure 1.

Figure 1: High-level Block Diagram of Design

Part 1
This lab is broken into multiple parts. Each part builds on the previous part so you must do all the steps in order.
Read the instructions carefully and do not skip any steps.
Use 8 toggle switches, SW7−0, as inputs for entering numbers. Use the green lights, LEDG7−0, to display the
number defined by the toggle switches. Use the 16 red lights, LEDR15−0, to display the accumulated sum. A Nios
II system, which includes three PIO interfaces, is the hardware needed for the task. One PIO circuit, connected to
the toggle switches, will provide the input data that can be read by the processor. Two other PIO circuits,

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Embedded Systems Design I 0618-561

Using Program Controlled Input and Output

connected to the green and red lights, will serve as the output interfaces to allow displaying the number selected
by the switches and the accumulated sum, respectively.
Realize the required hardware by implementing a Nios II system on the DE2 board, as follows:
1. Create a new Quartus II project that is stored in the directory Lab3/Quartus/part1. Select Cyclone II
EP2C35F672C6 as the target chip, which is the FPGA chip on the Altera DE2 board.
2. Use the QSYS system builder to generate the desired circuit, called nios_system, which comprises:
• Nios II/s processor with Embedded Multipliers for Hardware Multiply, Hardware Divide and JTAG
Debug Module Level 1
• On-chip memory - RAM mode and 32 Kbytes in size
• An 8-bit PIO input circuit for the switches
• An 8-bit PIO output circuit for the green LEDS
• A 16-bit PIO output circuit for the red LEDS
• System ID Peripheral with unique system ID
3. The QSYS will automatically assign the names such as pio_0, pio_1 and pio_2 to the three PIO
components. You can change these names to something that is more meaningful in the context of a
specific design. For example, we can choose the names switches, grn_leds and red_leds.
4. Export the PIO ports as external connection named as switches and grn_leds and red_leds.
5. From the System menu, select System > Auto‐‐Assign Base Addresses. This will assign addresses to
all components in the designed system. Record the assigned addresses for the PIO.
6. Instantiate the generated Nios II system within a VHDL module following good VHDL coding style. Also
add the Quartus IP variation file (.qip) that was generated by QSYS to your Quartus II project.
7. Assign the pins needed to make the necessary connections, by importing the pin-assignment file
DE2_pin_assignments_csv.
8. Compile the Quartus II project.
9. Program and configure the Cyclone II FPGA on the DE2 Board to implement the generated system.

Part 2
Implement the desired task using the Nios II, as follows:
1. Open the Nios II Software Build Tools for Eclipse Program and create a new BSP named
Lab3_Part2_BSP. Remember to unclick the Use default location to keep the Nios II design under the
nios directory.
2. Next create a new application project named Lab3_Part2_APP.

3. Create a new file and name it Lab3_Part2.c

4. Configure the editor preferences to insert spaces for tabs and set the tab size width 2 spaces. Also set
you debug preference to hexadecimal.
5. Write a C program that reads the contents of the switches, displays the corresponding value on the green
LEDs, adds this number to a sum that is being accumulated, and displays the sum on the red LEDs.
(Hint: Think about the data type you pick to define your variables.)
6. Use the Nios II Software Build Tools for Eclipse to compile and download your program.
7. Single-step through the program and verify its correctness by inputting several numbers. Note that single-
stepping through the program will allow you change the input numbers without reading the same number
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Embedded Systems Design I 0618-561

Using Program Controlled Input and Output

multiple times. You may want to put a break point at the end of the loop so the program stops after each
loop.
8. Take the time to verify your program is working before moving to the next part.

Part 3
In this part, we will add the ability to run the application program continuously and control the reading of new
numbers by including a pushbutton switch which is activated by the user when a new number is ready to be read.
The desired operation is that the user provides the next number by setting the toggle switches accordingly and
then pressing a pushbutton switch to indicate that the number is ready for reading.
To accomplish this task it is necessary to implement a mechanism that monitors the status of the circuit used to
input the numbers. A commonly-used I/O scheme is to use a status flag which is originally cleared to 0. This flag
is then set to 1 as soon as the I/O device interface is ready for the next data transfer. Upon transferring the data,
the flag is again cleared to 0. Thus, the processor can poll the status flag to determine when an I/O data transfer
can be made.
In our case, the I/O device is the user who manually sets the toggle switches. The I/O interface is a PIO circuit
generated by QSYS. To provide a status flag, we will generate a special one-bit PIO circuit and use its edge-
capture capability. This PIO is very similar to the regular PIO, and it conforms to the register map in PIO Interface
document.
In addition to the PIO modification, we would like to expand this design so that the accumulated sum is also
displayed using the seven segment display in hexadecimal. As in any embedded design, you have to determine if
the seven segment display should be controlled by the software or the hardware. Since the seven-segment
display is unique to the hardware, we will use VHDL to display the accumulated sum on the seven segment
display.
Perform the following steps:
1. You are going to add to the design you created in Part 1 but before you change anything, make sure you
backup your design and then copy your Part 2 design into a new folder called lab3/quartus/part3.
2. Inside of QSYS, generate a status-flag PIO by adding another PIO component as shown in the figure
below. This PIO component will be configure as an input port that is one bit wide. Also, under the Edge
capture register section, check the synchronously capture feature for the Falling edge. Normally the
push buttons on the DE2 board are active high so to detect the button being pushed we want the falling
edge.

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Embedded Systems Design I 0618-561

Using Program Controlled Input and Output

Figure 2: PIO Configuration

3. The PIO core has an option called “Enable bit-clearing for edge capture register” which is turned off by
default. When this option is disabled, writing any value to the edge-capture register clears all bits in the
register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. (Refer to PIO Core in
Embedded Peripherals IP User Guide for more information).
4. Name the new PIO to pushbutton and remember create an export named pushbutton for the
component.
5. Update the QSYS connections and base address as needed and generate the new Nios II subsystem.
6. Modify your VHDL file that specifies the complete system. Use the pushbutton switch KEY1 as the input
to the status-flag PIO.
7. Now create a VHDL module named hex_2_seven_seg that you can instantiate into your design to drive
the seven-segment display with the same signal used to drive the red LEDS. Your VHDL module should
accept 2 inputs named enable and hex_number(4 downto 0) and 1 output named seven_segment(6
downto 0). If the signal enable is asserted high then the VHDL should drive the hex_number to seven-
segment display. Otherwise if enable is de-asserted, the seven-segment display should be blank.
8. Update your design to display this sum as a hexadecimal number on the 7-segment displays HEX3-
HEX0, in addition to the red LEDs. HEX7-HEX4 should be disabled and not display anything.
9. Update the pin assignment and compile the project in Quartus II.

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Embedded Systems Design I 0618-561

Using Program Controlled Input and Output

10. Open the Nios II Software Build Tools for Eclipse Program and select File > New > Nios II Board
Support Package to create a new BSP named Lab3_Part3_BSP.
11. Select File > New > Nios II Application to create a new design project named Lab3_Part3_APP with
the new source file named Lab3_Part3.c
12. Modify your application program to accept a new number only when the pushbutton switch is pressed.
When the pushbutton is pressed, a status flag bit in the edge-capture register will be set to 1. After adding
the number to the accumulated sum, your program should clear the status flag by writing a 0 into the
edge-capture register. (Hint: When you program starts, it is a good idea to set the hardware to a know
state first. This means that you should set the LEDs, seven segment displays and clear the status flag of
the push button.)
13. Download and run your program to verify that it works properly. The program should run continuously and
a new number should be added each time the pushbutton switch is pressed. The sum will be displayed to
both the LEDs and seven segments.
14. Obtain sign-off of your design.

Part 4
In this part, we want to display the accumulated sum on the 7-segment displays as a decimal (rather than
hexadecimal) number. Your program running in the Nios II should perform the necessary number conversion.
HINT: Add a PIO port to Nios to output the sum as a BCD number. Be careful when defining the number of bits
required to display the BCD number (0xFFFF = 65,536).
Perform the following steps:
1. You are going to add to the design you created in Part 3 but before you change anything, make sure you
backup your design and then copy your Part 4 design into a new folder called lab3/quartus/part4.
2. Augment your QSYS design by adding a new PIO port named bcd_number to support your decimal
number output.
3. Using Nios II Software Build Tools for Eclipse Program create a new BSP named Lab3_Part4_BSP and
new application project named Lab3_Part4_APP.
• In a new source file named Lab3_Part4.c, modify your Nios II application code to create a function
that will convert the running sum to a BCD value that will allow you to output a decimal number. Note:
You can use the div instruction only if you specified the Hardware Divide option in Part 1. Use a C
function for the conversion process.
4. Download and run your program to verify that the entire design works properly.
5. Obtain sign-off of your design.

Part 5
In Part 3, polling was used to monitor the value of the status bit. This approach may not always be the best
solution as it wastes processing time checking to see if the pushbutton has been pressed. A better method would
to have the push button PIO core interrupt the processor when the pushbutton has been pressed. For Part 5, you
will perform the following steps:
1. You are going to add to the design you created in Part 4 but before you change anything, make sure you
backup your design and then copy your Part 4 design into a new folder called lab3/quartus/part5.
2. The PIO core provides the capability to generate an interrupt as soon as the button is pushed. In QSYS,
edit the configuration of your 1-bit push button PIO core. Under the interrupt section, select Generate IRQ
and choose Edge for the IRQ Type. Click Finish when done.

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Embedded Systems Design I 0618-561

Using Program Controlled Input and Output

3. Notice the push button will generate an interrupt but we need to connect that interrupt to an IRQ signal of
the Nios II processor. Move your mouse to IRQ column within QSYS and assign IRQ0 to the interrupt
going to the Nios processor as shown in Figure 3.

Figure 3: IRQ Configuration

4. Modify your Nios II application code to register your interrupt handler. This can be done using the
alt_ic_isr_register() function call (see Nios II Software Developer’s Handbook). After you register
the interrupt handler, enable the interrupts from the PIO core. (Why would you want to register the
interrupt handler before you enable the interrupt?) Your interrupt handler should perform the reading of
the switches and processing.
5. Download and run your program to verify that the entire design works properly.
6. Obtain sign-off of your design.

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