FAN4800A/C, FAN4801/1S/2/2L PFC/PWM Controller Combination: Features Description

FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination
March 2009
FAN4800A/C, FAN4801/1S/2/2L
PFC/PWM Controller Combination
Features Description
Pin-to-Pin Compatible with ML4800 and FAN4800 The highly integrated FAN4800A/C and
and CM6800 and CM6800A FAN4801/1S/2/2L are specially designed for power
supplies that consist of boost PFC and PWM. They
PWM Configurable for Current-mode or require very few external components to achieve
Feed-forward Voltage-Mode Operation versatile protections / compensation. They are available
Internally Synchronized Leading-Edge PFC and in 16-pin DIP and SOP packages.
Trailing-Edge PWM in one IC The PWM can be used in either current or voltage
Low Operating Current mode. In voltage mode, feed-forward from the PFC
output bus can reduce the secondary output ripple.
Innovative Switching-Charge Multiplier Divider
Compared with older productions, ML4800 and
Average-Current-Mode for Input-Current Shaping FAN4800, FAN4800A/C and FAN4801/1S/2/2L have
PFC Over-Voltage and Under-Voltage Protections lower operation current that save power consumption in
external devices. FAN4800A/C and FAN4801/1S/2/2L
PFC Feedback Open-Loop Protection have accurate 49.9% maximum duty of PWM that
Cycle-by-Cycle Current Limiting for PFC/PWM makes the hold-up time longer. Specifically, the
brownout protection and PFC soft-start functions are not
Power-on Sequence Control and Soft-Start in ML4800 and FAN4800.
Brownout Protection To start evaluating FAN4800A/C, FAN4801/1S/2/2L for
Interleaved PFC/PWM Switching replacing existing FAN4800 and ML4800 boards, five
things must be done before the fine-tuning procedure:
FAN4801/1S/2/2L Improve Efficiency at Light Load
1. Change RAC resister from the old value to a higher
fRTCT=4•fPFC=4•fPWM for FAN4800A and resister: between 6MΩ to 8MΩ.
FAN4801/1S
2. Change RT/CT pin from the existing values to
fRTCT=4•fPFC=2•fPWM for FAN4800C and RT=6.8KΩ and CT=1000pF to have fPFC=64KHz,
FAN4802/2L fPWM=64KHz.
3. VRMS pin needs to be 1.224V at VIN=85 VAC for
Applications universal input application from line input from
85VAC to 270 VAC. Both poles for the Vrms of
Desktop PC Power Supply FAN4801/1S/2/2L don’t need to substantially
Internet Server Power Supply slower than FAN4800; about 5 to 10 times.
LCD TV, Monitor Power Supply 4. At full load, the average VEA needs to ~4.5V and
the ripple on the VEA needs to be less than 400mV.
UPS
5. Soft-Start pin, the soft-start current has been
Battery Charger reduced to half from the FAN4800 capacitor.
DC Motor Power Supply
Monitor Power Supply Related Resources
Telecom System Power Supply
Complete design instructions are detailed in application
Distributed Power note AN-6078SC (available in Chinese only).
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1
Ordering Information
Operating Eco Packing
Part Number Package
Temperature Range Status Method
FAN4800ANY -40°C to +105°C Green 16-pin Dual In-Line Package (DIP) Tube
FAN4800CNY -40°C to +105°C Green 16-pin Dual In-Line Package (DIP) Tube
FAN4800AMY -40°C to +105°C Green 16-pin Small Out-Line Package (SOP) Tape & Reel
FAN4800CMY -40°C to +105°C Green 16-pin Small Out-Line Package (SOP) Tape & Reel
FAN4801NY -40°C to +105°C Green 16-pin Dual In-Line Package (DIP) Tube
FAN4801SNY -40°C to +105°C Green 16-pin Dual In-Line Package (DIP) Tube
FAN4802NY -40°C to +105°C Green 16-pin Dual In-Line Package (DIP)) Tube
FAN4802LNY -40°C to +105°C Green 16-pin Dual In-Line Package (DIP)) Tube
FAN4801MY -40°C to +105°C Green 16-pin Small Out-Line Package (SOP) Tape & Reel
FAN4801SMY -40°C to +105°C Green 16-pin Small Out-Line Package (SOP) Tape & Reel
FAN4802MY -40°C to +105°C Green 16-pin Small Out-Line Package (SOP) Tape & Reel
FAN4802LMY -40°C to +105°C Green 16-pin Small Out-Line Package (SOP) Tape & Reel
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Part Number PFC:PWM Frequency Ratio Brown Out / In Range In / Out

FAN4800ANY 1:1 1.05V / 1.90V N.A
FAN4800AMY 1:1 1.05V / 1.90V N.A
FAN4800CNY 1:2 1.05V / 1.90V N.A
FAN4800CMY 1:2 1.05V / 1.90V N.A
FAN4801NY 1:1 1.05V / 1.90V 1.95V / 2.45V
FAN4801SNY 1:1 1.05V / 1.90V 2.80V / 3.35V
FAN4802NY 1:2 1.05V / 1.90V 1.95V / 2.45V
FAN4802LNY 1:2 0.90V / 1.65V 1.95V / 2.45V
FAN4801MY 1:1 1.05V / 1.90V 1.95V / 2.45V
FAN4801SMY 1:1 1.05V / 1.90V 2.80V / 3.35V
FAN4802MY 1:2 1.05V / 1.90V 1.95V / 2.45V
FAN4802LMY 1:2 0.90V / 1.65V 1.95V / 2.45V

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 2
Application Diagram
IEA VEA
IAC FBPFC
ISENSE VREF
VDD
VRMS VDD
SS OPFC
FBPWM OPWM
RT/CT GND
RAMP ILIMIT
VREF
FAN4800A/C
FAN4801/1S/2/2L
Secondary
Figure 1. Typical Application Current Mode

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 3
Application Diagram
IEA VEA
IAC FBPFC
ISENSE VREF
VDD
VRMS VDD
SS OPFC
FBPWM OPWM
RT/CT GND
RAMP ILIMIT
VREF
FAN4800A/C
FAN4801/1S/2/2L
VREF
Secondary
Figure 2. Typical Application Voltage Mode

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 4
Block Diagram
Figure 3. FAN4800A/C Function Block Diagram
Figure 4. FAN4801/1S/2/2L Function Block Diagram

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 5
Marking Information
F – Fairchild logo
Z – Plant code
X – 1 digit year code
Y – 1 digit week code
TT – 2 digits die run code
T – Package type (N:DIP, M:SOP)
P – Y: Green package
M – Manufacture flow code
Figure 5. Top Mark

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 6
Pin Configuration
Figure 6. Pin Configuration (Top View)
Pin Definitions
Pin # Name Description
Output of PFC Current Amplifier. The signal from this pin is compared with an internal
1 IEA
sawtooth to determine the pulse width for PFC gate drive.
Input AC Current. For normal operation, this input provides current reference for the multiplier.
2 IAC
The suggested maximum IAC is 100µA.
PFC Current Sense. The non-inverting input of the PFC current amplifier and the output of
3 ISENSE
multiplier and PFC ILIMIT comparator.
4 VRMS Line-Voltage Detection. Line voltage detection. The pin is used for PFC multiplier.
PWM Soft-Start. During startup, the SS pin charges an external capacitor with a 10µA
5 SS constant current source. The voltage on FBPWM is clamped by SS during startup. In the event
of a protection condition occurring and/or PWM disabled, the SS pin is quickly discharged.
6 FBPWM PWM Feedback Input. The control input for voltage-loop feedback of PWM stage.
7 RT/CT Oscillator RC Timing Connection. Oscillator timing node; timing set by RT and CT.
PWM RAMP Input. In current mode, this pin functions as the current sense input; when in
8 RAMP
voltage mode, it is the feed forward sense input from PFC output 380V (feedforward ramp).
9 ILIMIT Peak Current Limit Setting for PWM. The peak current limits setting for PWM.
10 GND Ground.
PWM Gate Drive. The totem-pole output drive for PWM MOSFET. This pin is internally
11 OPWM
clamped under 15V to protect the MOSFET.
PFC Gate Drive. The totem pole output drive for PWM MOSFET. This pin is internally clamped
12 OPFC
under 15V to protect the MOSFET.
Supply. The power supply pin. The threshold voltages for startup and turn-off are 11V and
13 VDD
9.3V, respectively. The operating current is lower than 10mA.
14 VREF Reference Voltage. Buffered output for the internal 7.5V reference.
Voltage Feedback Input for PFC. The feedback input for PFC voltage loop. The inverting
15 FBPFC
input of PFC error amplifier. This pin is connected to the PFC output through a divider network.
Output of PFC Voltage Amplifier. The error amplifier output for PFC voltage feedback loop.
16 VEA
A compensation network is connected between this pin and ground.

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 7
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Unit

VDD DC Supply Voltage 30 V
VH SS, FBPWM, RAMP, OPWM, OPFC -0.3 30.0 V
VL IAC, VRMS, RT/CT, ILIMIT, FBPFC, VEA -0.3 7.0 V
VVREF VREF 7.5 V
VIEA IEA 0 VVREF+0.3 V
VN ISENSE -5.0 0.7 V
IAC Input AC Current 1 mA
IREF VREF Output Current 5 mA
IPFC-OUT Peak PFC OUT Current, Source or Sink 0.5 A
IPWM-OUT Peak PWM OUT Current, Source or Sink 0.5 A
PD Power Dissipation TA < 50°C 800 mW
DIP 80.80 °C/W
RΘ j-a Thermal Resistance (Junction to Air)
SOP 104.10 °C/W
TJ Operating Junction Temperature -40 +125 °C
TSTG Storage Temperature Range -55 +150 °C
TL Lead Temperature (Soldering) +260 °C
Electrostatic Discharge Human Body Model 4.5 kV
ESD
Capability Charged Device Model 1000 V
Notes:
1. All voltage values, except differential voltage, are given with respect to GND pin.
2. Stresses beyond those listed under “absolute maximum ratings “may cause permanent damage to the device.
Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol Parameter Min. Typ. Max. Unit

TA Operating Ambient Temperature -40 +105 °C

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 8
Electrical Characteristics
VDD=15V, TA=25°C, RT=6.8kΩ, CT=1000pF unless noted operating specifications.
Symbol Parameter Conditions Min. Typ. Max. Units

VDD Section
IDD ST Startup Current VDD=VTH-ON-0.1V; OPFC OPWM Open 30 80 µA
IDD-OP Operating Current VDD=13V; OPFC OPWM Open 2.0 2.6 5.0 mA
Turn-on Threshold
VTH-ON 10 11 12 V
Voltage
ΔVTH Hysteresis 1.5 1.9 V
VDD-OVP VDD OVP 27 28 29 V
ΔVDD-OVP VDD OVP Hysteresis 1 V
Oscillator
fOSC-RT/CT RT/CT Frequency RT=6.8kΩ, CT=1000pF 240 256 268 kHz
PFC & PWM Frequency 60 64 67
fOSC FAN4800C,FAN4802/02L RT=6.8kΩ, CT=1000pF kHz
120 128 134
PWM Frequency
fDV Voltage Stability 11V ≦ VDD ≦ 22V 2 %
fDT Temperature Stability -40°C ~ +105°C 2 %
Total Variation (PFC &
fTV (1) Line, Temperature 58 70 kHz
PWM)
(1)
fRV Ramp Voltage Valley to Peak 2.8 V
IDischarge Discharge Current VRAMP=0V, VRT/CT=2.5V 6.5 15.0 mA
(1)
fRANGE Frequency Range 50 75 kHz
tPFCD PFC Dead Time RT=6.8kΩ, CT=1000pF 400 600 800 ns
VREF
VVREF Reference Voltage IREF=0mA, CREF=0.1µF 7.4 7.5 7.6 V
Load Regulation of CREF=0.1µF, IREF=0mA to 3.5mA
ΔVVREF1 30 50 mV
Reference Voltage VVDD=14V, Rise/Fall Time > 20µs
Line Regulation of
ΔVVREF2 CREF=0.1µF, VVDD=11V to 22V 25 mV
Reference Voltage
(1)
ΔVVREF-DT Temperature Stability -40°C ~ +105°C 0.4 0.5 %
(1)
ΔVVREF-TV Total Variation Line, Load, Temp 7.35 7.65 V
(1)
ΔVVREF-LS Long-Term Stability TJ=125°C, 0 ~ 1000HRs 5 25 mV
IREF-MAX. Maximum Current VVREF > 7.35V 5 mA
(1)
IOS Output Short Circuit 25 mA
PFC OVP Comparator
VPFC-OVP Over-Voltage Protection 2.70 2.75 2.80 V
ΔVPFC-OVP PFC OVP Hysteresis 200 250 300 mV
Low-Power Detect Comparator
VEAOFF VEA Voltage OFF OPFC 0.2 0.3 0.4 V
VIN OK Comparator
Voltage Level on FBPFC
VRD-FBPFC to Enable OPWM During 2.3 2.4 2.5 V
Startup
ΔVRD-FBPFC Hysteresis 1.15 1.25 1.35 V

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 9
Electrical Characteristics (Continued)

Voltage Error Amplifier
(1)
FBPFC Input Voltage Range 0 6 V
Vref Reference Voltage at T=25°C 2.45 2.50 2.55 V
(1)
AV Open-Loop Gain 35 42 dB
Gmv Transconductance VNONINV=VINV, VVEA=3.75V at T=25°C 50 70 90 µmho
IFBPFC-L Maximum Source Current VFBPFC=2V, VVEA=1.5V 40 50 µA
IFBPFC-H Maximum Sink Current VFBPFC=3V, VVEA=6V -50 -40 µA
IBS Input Bias Current -1 1 µA
Output High Voltage on
VVEA-H 5.8 6 V
VVEA
Output Low Voltage on
VVEA-L 0.1 0.4 V
VVEA
Current Error Amplifier
Input Voltage Range
VISENSE (1) -1.5 0.7 V
(ISENSE pin)
GmI Transconductance VNONINV=VINV, VIEA=3.75V 78 88 100 µmho
VOFFSET Input Offset Voltage VVEA=0V, IAC Open -10 10 mV
VIEA-H Output High Voltage 6.8 7.4 8.0 V
VIEA-L Output Low Voltage 0.1 0.4 V
IL Source Current VISENSE=-0.6V, VIEA=1.5V 35 50 µA
IH Sink Current VISENSE=+0.6V, VIEA=4.0V -50 -35 µA
(1)
AI Open-Loop Gain 40 50 dB
Tri-Fault Detect
(1) VFBPFC=VPFC-UVP to FBPFC OPEN,
tFBPFC_OPEN Time to FBPFC Open 2 4 ms
470pF from FBPFC to GND
PFC Feedback Under-
VPFC-UVP 0.4 0.5 0.6 V
Voltage Protection
Gain Modulator
(1)
IAC Input for AC Current Multiplier Linear Range 0 100 µA
IAC=17.67µA, VRMS=1.080V
7.50 9.00 10.50
VFBPFC=2.25V, at T=25°C
IAC=20µA, VRMS=1.224V VFBPFC=2.25V,
6.30 7.00 7.70
at T=25°C
(2) IAC=25.69µA, VRMS=1.585V
GAIN GAIN Modulator 3.80 4.20 4.60
0.95 1.05 1.16
0.66 0.73 0.80
(1)
BW Bandwidth IAC=40µA 2 kHz
Output Voltage=5.7kΩ × IAC=20µA, VRMS=1.224V VFBPFC=2.25V,
Vo(gm) (1) 0.74 0.82 0.90 V
(ISENSE-IOFFSET) at T=25°C

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 10

PFC ILIMIT Comparator
Peak Current Limit
VPFC-ILIMIT Threshold Voltage, -1.25 -1.15 -1.05 V
Cycle-by-Cycle Limit
PFC ILIMIT-Gain IAC=17.67µA, VRMS=1.08V VFBPFC=2.25V,
ΔVpk 200 mV
Modulator Output at T=25°C
PFC Output Driver
Gate Output Clamping
VGATE-CLAMP VDD=22V 13 15 17 V
Voltage
VGATE-L Gate Low Voltage VDD=15V; IO=100mA 1.5 V
VGATE-H Gate High Voltage VDD=13V; IO=100mA 8 V
tr Gate Rising Time VDD=15V; CL=4.7nF; O/P=2V to 9V 40 70 120 ns
tf Gate Falling Time VDD=15V; CL=4.7nF; O/P=9V to 2V 40 60 110 ns
DPFC-MAX Maximum Duty Cycle VIEA<1.2V 94 97 %
DPFC-MIN Minimum Duty Cycle VIEA>4.5V 0 %
Brown Out
FAN4800A/C, FAN4801/1S/2 1.00 1.05 1.10 V
VRMS-UVP VRMS Threshold Low
FAN4802L 0.85 0.90 0.95 V
FAN4800A/C, FAN4801/1S/2 1.85 1.90 1.95 V
VRMS-UVP VRMS Threshold High
FAN4802L 1.60 1.65 1.70 V
FAN4800A/C, FAN4801/1S/2 750 850 950 mV
ΔVRMS-UVP Hysteresis
FAN4802L 650 750 850 mV
Under-Voltage
tUVP 340 410 480 ms
Protection Delay Time
Soft Start
VSS-MAX Maximum Voltage VDD=15V 9.5 10.0 10.5 V
ISS Soft-Start Current 10 µA
PWM ILIMIT Comparator
VPWM-ILIMIT Threshold Voltage 0.95 1.00 1.05 V
tPD Delay to Output 250 ns
Leading-Edge Blanking
tPWM-Bnk 170 250 350 ns
Time
Range (FAN4801/1S/2/2L)
VRMS-L RMS AC Voltage Low When VRMS=1.95V at132Vrms 1.90 1.95 2.00 V
VRMS-H RMS AC Voltage High When VRMS=2.45V at150Vrms 2.40 2.45 2.50 V
VEA Low When VVEA=1.95V at 30% Loading, 1.90 1.95 2.00
VEA-L V
VEA Low (FAN4801S) When VVEA=2.80V at 60% Loading 2.75 2.80 2.85
VEA High When VVEA=2.45V at 40% Loading, 2.40 2.45 2.50
VEA-H V
VEA High (FAN4801S) When VVEA=3.35V at 70% Loading 3.30 3.35 3.40
Itc Two-Level Current FBPFC Two-Level Current 18 20 22 µA

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 11

PWM Output Driver
VGATE-CLAMP Gate Output Clamping Voltage VDD=22V 13 15 17 V
VGATE-L Gate Low Voltage VDD=15V; IO=100mA 1.5 V
VGATE-H Gate High Voltage VDD=13V; IO=100mA 8 V
tr Gate Rising Time VDD=15V; CL=4.7nF 30 60 120 ns
tf Gate Falling Time VDD=15V; CL=4.7nF 30 50 110 ns
DPWM-MAX Maximum Duty Cycle 49.0 49.5 50.0 %
VPWM-LS PWM Comparator Level Shift 1.3 1.5 1.8 V
Notes:
3. This parameter, although guaranteed by design, is not 100% production tested.
2 -1 -1
4. Gain=K × 5.3 × (VRMS ) ; K=( ISENSE － IOFFSET) × [IAC × (VEA － 0.7V)] ; VEA (MAX.)=5.6V.

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 12
Typical Characteristics
20.0 2.96
18.0 2.94
16.0 2.92
14.0
2.90
IDD-OP(uA)
IDD-ST(uA)
12.0
2.88
10.0
2.86
8.0
2.84
6.0
4.0 2.82
2.0 2.80
0.0 2.78
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 7. IDD-ST vs. Temperature Figure 8. IDD-OP vs. Temperature
11.4 2.0
11.3 1.9
1.8
11.2
VTH-ON (V)
1.7
△VTH(V)
11.1
1.6
11.0
1.5
10.9 1.4
10.8 1.3
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 9. VTH-ON vs. Temperature Figure 10. ΔVTH vs. Temperature
28.04 65.0
28.02 64.9
28.00
64.8
FOSC-FAN4801/1S(kHz)
27.98
VDD-OVP(V)
64.7
27.96
64.6
27.94
64.5
27.92
64.4
27.90
27.88 64.3
27.86 64.2
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 11. VDD-OVP vs. Temperature Figure 12. fOSC-FAN4801/1S vs. Temperature
130.0 655
129.8 650
129.6 645
FOSC-FAN4802/2L(kHz)
129.4 640
tPFCD(ns)
129.2 635
129.0 630
128.8 625
128.6 620
128.4 615
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 13. fOSC-FAN4802/2L vs. Temperature Figure 14. tPFCD vs. Temperature

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 13
7.520 6
7.515
5
7.510
7.505 4
△ VVREF1(mV)
VVREF(V)
7.500
3
7.495
7.490 2
7.485
1
7.480
7.475 0
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 15. VVREF vs. Temperature Figure 16. ΔVVREF1 vs. Temperature
0.20 21.5
0.18
21.0
0.16
0.14 20.5
△ VVREF2(mV)
IREF-MAX.(mA)
0.12
20.0
0.10
0.08 19.5
0.06
0.04 19.0
0.02
18.5
0.00
-0.02 18.0
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 17. ΔVVREF2 vs. Temperature Figure 18. IREF-MAX. vs. Temperature
2.742 252.2
2.740 252.0
251.8
△ VPFC-OVP(mV)
2.738
VPFC-OVP(V)
251.6
2.736
251.4
2.734
251.2
2.732
251.0
2.730 250.8
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 19. VPFC-OVP vs. Temperature Figure 20. ΔVPFC-OVP vs. Temperature
2.400 1.275
1.270
2.398
1.265
△ VRD-FBPFC(V)
2.396
VRD-FBPFC(V)
1.260
2.394
1.255
2.392
1.250
2.390 1.245
2.388 1.240
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 21. VRD-FBPFC vs. Temperature Figure 22. ΔVRD-FBPFC vs. Temperature
FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 14
2.502 74
2.500
73
2.498
Gmv(umho)
73
2.496
Vref(V)
2.494
72
2.492
72
2.490
2.488 71
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 23. Vref vs. Temperature Figure 24. GmV vs. Temperature
4.5 94
4.0 92
3.5
90
3.0
VOFFSET(mV)
Gm I(umho)
88
2.5
86
2.0
84
1.5
82
1.0
0.5 80
0.0 78
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 25. VOFFSET vs. Temperature Figure 26. GmI vs. Temperature
7.10 6.1
7.05 6.0
7.00
5.9
6.95
Rmul(kΩ)
5.8
GAIN2
6.90
5.7
6.85
5.6
6.80
6.75 5.5
6.70 5.4
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 27. GAIN2 vs. Temperature Figure 28. Rmul vs. Temperature
-1.1775 295
-1.1780
290
-1.1785
285
-1.1790
280
VPFC-ILIMIT(V)
△ Vpk(mV)
-1.1795
275
-1.1800
270
-1.1805
265
-1.1810
-1.1815 260
-1.1820 255
-1.1825 250
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 29. VPFC-ILIMIT vs. Temperature Figure 30. ΔVpk vs. Temperature

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 15
1.010 10.1
10.0
1.009
9.9
1.008
9.8
VPWM-ILIMIT (V)
1.007
9.7
ISS(uA)
1.006 9.6
9.5
1.005
9.4
1.004
9.3
1.003
9.2
1.002 9.1
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 31. VPWM-ILIMIT vs. Temperature Figure 32. ISS vs. Temperature
1.048 867.5
1.047 867.0
1.046 866.5
866.0
1.045
△ VRMS-UVP(mV)
865.5
VRMS-UVP(V)
1.044
865.0
1.043
864.5
1.042
864.0
1.041
863.5
1.040 863.0
1.039 862.5
1.038 862.0
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 33. VRMS-UVP vs. Temperature Figure 34. ΔVRMS-UVP vs. Temperature
1.940 2.446
1.939 2.445
2.444
1.938
2.443
1.937
VRMS-L(V)
2.442
VRMS-H(V)
1.936
2.441
1.935
2.440
1.934 2.439
1.933 2.438
1.932 2.437
1.931 2.436
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 2.435
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 35. VRMS-L vs. Temperature Figure 36. VRMS-H vs. Temperature
1.942 2.436
1.940 2.434
1.938
2.432
VEA-H(V)
VEA-L(V)
1.936
2.430
1.934
2.428
1.932
2.426
1.930
2.424
1.928 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110 125
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ ℃ ℃
Figure 37. VEA-L vs. Temperature Figure 38. VEA-H vs. Temperature

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 16
14.7 14.4
14.6 14.3
VGATE-CLAMP-PFC(V)
14.5 14.2
VGATE-CLAMP-PWM(V)
14.4 14.1
14.3
14.0
14.2
13.9
14.1
13.8
14.0
13.7
13.9
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ 13.6
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 39. VGATE-CLAMP-PFC vs. Temperature Figure 40. VGATE-CLAMP-PWM vs. Temperature
96.06 49.80
96.04
49.75
96.02
DPWM-MAX(%)
96.00 49.70
DPFC-MAX(%)
95.98 49.65
95.96
49.60
95.94
95.92 49.55
95.90
49.50
95.88 -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110 125
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ ℃ ℃
Figure 41. DPFC-MAX vs. Temperature Figure 42. DPWM-MAX vs. Temperature
21.0 1.460
20.8
1.455
20.6
1.450
VPWM-LS(V)
20.4
Itc(uA)
20.2 1.445
20.0
1.440
19.8
1.435
19.6
19.4 1.430
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃ -40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 43. Itc vs. Temperature Figure 44. VPWM-LS vs. Temperature

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 17
Functional Description
The FAN4800A/C and FAN4801/1S/2/2L consist of an IAC × (VEA − 0.7)
average current controlled, continuous boost Power IGAINMOD = ×K (1)
VRMS 2
Factor Correction (PFC) front-end and a synchronized
Pulse Width Modulator (PWM) back-end. The PWM
can be used in current or voltage mode. In voltage Note that the output current of the gain modulator is
mode, feed forward from the PFC output bus can be limited around 159μA and the maximum output voltage
used to improve the line regulation of PWM. In either of the gain modulator is limited to 159μA x
mode, the PWM stage uses conventional trailing-edge, 5.7K=0.906V. This 0.906V also determines the
duty-cycle modulation. This patented leading/trailing maximum input power.
edge modulation results in a higher usable PFC error
amplifier bandwidth and can significantly reduce the However, IGAINMOD cannot be measured directly from
size of the PFC DC bus capacitor. ISENSE. ISENSE=IGAINMOD – IOFFSET and IOFFSET can
only be measured when VEA is less than 0.5V and
The synchronization of the PWM with the PFC IGAINMOD is 0A. Typical IOFFSET is around 31μA ~ 48μA.
simplifies the PWM compensation due to the controlled
ripple on the PFC output capacitor (the PWM input
capacitor). The PWM section of the FAN4800A,
Selecting RAC for IAC Pin
FAN4801/1S operates at the same frequency as the The IAC pin is the input of the gain modulator and also
PFC; and FAN4800C, FAN4802/2L operates at double a current mirror input and requires current input.
with PFC. Selecting a proper resistor RAC provides a good sine
wave current derived from the line voltage and helps
In addition to power factor correction, a number of program the maximum input power and minimum input
protection features are built into this series. They line voltage. RAC=VIN peak x 56KΩ. For example, if the
include soft-start, PFC over-voltage protection, peak minimum line voltage is 75VAC, the RAC=75 x 1.414 x
current limiting, brownout protection, duty cycle limiting, 56KΩ=6MΩ.
and under-voltage lockout (UVLO).
Current Amplifier Error, IEA
Gain Modulator
The current error amplifier’s output controls the PFC
The gain modulator is the heart of the PFC, as the duty cycle to keep the average current through the
circuit block controls the response of the current loop to boost inductor a linear function of the line voltage. At
line voltage waveform and frequency, RMS line voltage, the inverting input to the current error amplifier, the
and PFC output voltages. There are three inputs to the output current of the gain modulator is summed with a
gain modulator: current, which results in a negative voltage being
1. A current representing the instantaneous input impressed upon the ISENSE pin.
voltage (amplitude and wave shape) to the PFC. The negative voltage on ISENSE represents the sum of
The rectified AC input sine wave is converted to a all currents flowing in the PFC circuit and is typically
proportional current via a resistor and is fed into the derived from a current sense resistor in series with the
gain modulator at IAC. Sampling current in this way negative terminal of the input bridge rectifier.
minimizes ground noise, required in high-power,
switching-power conversion environments. The gain The inverting input of the current error amplifier is a
modulator responds linearly to this current. virtual ground. Given this fact, and the arrangement of
the duty cycle modulator polarities internal to the PFC,
2. A voltage proportional to the long-term RMS AC line an increase in positive current from the gain modulator
voltage, derived from the rectified line voltage after causes the output stage to increase its duty cycle until
scaling and filtering. This signal is presented to the the voltage on ISENSE is adequately negative to
gain modulator at VRMS. The output of the gain cancel this increased current. Similarly, if the gain
modulator is inversely proportional to VRMS (except modulator’s output decreases, the output duty cycle
at unusually low values of VRMS, where special gain decreases to achieve a less negative voltage on the
contouring takes over to limit power dissipation of ISENSE pin.
the circuit components under brownout conditions).
3. The output of the voltage error amplifier, VEA. The PFC Cycle-By-Cycle Current Limiter
gain modulator responds linearly to variations in this
As well as being a part of the current feedback loop,
voltage.
the ISENSE pin is a direct input to the cycle-by-cycle
The output of the gain modulator is a current signal, in current limiter for the PFC section. If the input voltage
the form of a full wave rectified sinusoid at twice the at this pin is less than -1.15V, the output of the PFC is
line frequency. This current is applied to the virtual disabled until the protection flip-flop is reset by the
ground (negative) input of the current error amplifier. In clock pulse at the start of the next PFC power cycle.
this way, the gain modulator forms the reference for the
current error loop and ultimately controls the
instantaneous current draw of the PFC from the power
line. The general form of the output of the gain
modulator is:
FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 18
TriFault Detect™ Error Amplifier Compensation
To improve power supply reliability, reduce system The PWM loading of the PFC can be modeled as a
component count, and simplify compliance to UL 1950 negative resistor because an increase in the input
safety standards, the FAN4800A/C, FAN4801/1S/2/2L voltage to the PWM causes a decrease in the input
includes TriFault Detect. This feature monitors FBPFC current. This response dictates the proper
for certain PFC fault conditions. compensation of the two transconductance error
amplifiers. Figure 45 shows the types of compensation
In a feedback path failure, the output of the PFC could networks most commonly used for the voltage and
exceed safe operating limits. With such a failure, current error amplifiers, along with their respective
FBPFC exceeds its normal operating area. Should return points. The current-loop compensation is
FBPFC go too low, too high, or open, TriFault Detect returned to VREF to produce a soft-start characteristic
senses the error and terminates the PFC output drive. on the PFC: As the reference voltage increases from
TriFault detect is an entirely internal circuit. It requires 0V, it creates a differentiated voltage on IEA, which
no external components to serve its protective function. prevents the PFC from immediately demanding a full
duty cycle on its boost converter. Complete design is
referred in application note AN-6078SC.
PFC Over-Voltage Protection
In the FAN4800A/C, FAN4801/1S/2/2L, the PFC OVP There is an RC filter between Rsense and ISENSE pin.
comparator serves to protect the power circuit from There are two reasons to add a filter at the ISENSE pin:
being subjected to excessive voltages if the load 1. Protection: During startup or inrush current
changes suddenly. A resistor divider from the high- conditions, there is a large voltage across Rsense,
voltage DC output of the PFC is fed to FBPFC. When which is the sensing resistor of the PFC boost
the voltage on FBPFC exceeds 2.75V, the PFC output converter. It requires the ISENSE filter to attenuate
driver is shut down. The PWM section continues to the energy.
operate. The OVP comparator has 250mV of hysteresis
and the PFC does not restart until the voltage at 2. To reduce L, the boost inductor: The ISENSE filter
FBPFC drops below 2.50V. VDD OVP can also serve as also can reduce the boost inductor value since the
a redundant PFC OVP protection. VDD OVP threshold is ISENSE filter behaves like an integrator before the
28V with 1V hysteresis. ISENSE pin, which is the input of the current error
amplifier, IEA.
Selecting PFC Rsense The ISENSE filter is an RC filter. The resistor value of
Rsense is the sensing resistor of the PFC boost the ISENSE filter is between 100Ω and 50Ω because
converter. During the steady state, line input current x IOFFSET x RFILTER can generate a negative offset voltage
Rsense equals IGAINMOD x 5.7KΩ. of IEA. Selecting an RFILTER equal to 50Ω keeps the
offset of the IEA less than 3mV. Design the pole of
At full load, the average VEA needs to around 4.5V and ISENSE filter at fPFC/6, one sixth of the PFC switching
ripple on the VEA needs to be less than 400mV. frequency, so the boost inductor can be reduced six
Choose the resistance of the sensing resistor: times without disturbing the stability. The capacitor of
the ISENSE filter, CFILTER, is approximately 100nF.
Rsense =
( 4.5 − 0.7 ) × 5.7K Ω × IAC × Gain × VIN × 2
(2)
2 × ( 5.6 − 0.7 ) × Line input Power
where 5.6 is VEA maximum output.
PFC Soft-Start
PFC startup is controlled by VEA level. Before FBPFC
voltage reaches 2.4V, the VEA level is around 2.8V. At
90VAC, the PFC soft-start time is 90ms.
PFC Brownout
The AC UVP comparator monitors the AC input
voltage. The FAN4800A/C, FAN4801/1S/2 disables
PFC as lower AC input that the VRMS is less than
1.05V. The brownout voltage of FAN4802L is lower
than FAN4801/1S/2 that the VRMS is less than 0.9V.
Figure 45. Compensation Network Connection for the

Voltage and Current Error Amplifiers

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 19
Two-Level PFC Function Pulse Width Modulator (PWM)
To improve the efficiency, the system can reduce PFC The operation of the PWM section is straightforward,
switching loss at low line and light load by reducing the but there are several points that should be noted.
PFC output voltage. The two-level PFC output of Foremost among these is the inherent synchronization
FAN4801/1S/2/2L can be programmable. of PWM with the PFC section of the device, from which
it also derives its basic timing. The PWM is capable of
As Figure 46 shows, FAN4801/1S/2/2L detect VEA pin current-mode or voltage-mode operation. In current-
and VRMS pin to determine the system operates low mode applications, the PWM ramp (RAMP) is usually
line and light load or not. At the second-level PFC, derived directly from a current sensing resistor or
there is a current of 20µA through RF2 from FBPFC pin. current transformer in the primary of the output stage. It
So the second-level PFC output voltage can be is thereby representative of the current flowing in the
calculated as. converter’s output stage. ILIMIT, which provides cycle-by-
RF 1 + RF 2 cycle current limiting, is typically connected to RAMP in
Output ≅ × (2.5V − 20uA × RF 2 ) (3) such applications. For voltage-mode operation and
RF 2
certain specialized applications, RAMP can be
For example, if the second-level PFC output voltage is connected to a separate RC timing network to generate
expected as 300V and normal voltage is 387V, a voltage ramp against which FBPWM is compared.
according to the equation, RF2 is 28kΩ RF1 is 4.3MΩ. Under these conditions, the use of voltage feed-forward
The programmable range of second level PFC output from the PFC bus can assist in line regulation accuracy
voltage is 340V ~ 300V. and response. As in current-mode operation, the ILIMIT
input is used for output stage over-current protection.
No voltage error amplifier is included in the PWM
stage, as this function is generally performed on the
output side of the PWM’s isolation boundary. To
facilitate the design of opto-coupler feedback circuitry,
an offset has been built into the PWM’s RAMP input
that allows FBPWM to command a 0% duty cycle for
input voltages below typical 1.5V.
PWM Cycle-By-Cycle Current Limiter

The ILIMIT pin is a direct input to the cycle-by-cycle
current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output flip-flop is
reset by the clock pulse at the start of the next PWM
Figure 46. Two-Level PFC Scheme power cycle. When the ILIMIT triggers the cycle-by-cycle
bi-cycle current, it limits the PWM duty cycle mode and
the power dissipation is reduced during the dead-short
Oscillator (RT/CT) condition.
The oscillator frequency is determined by the values of
RT and CT, which determine the ramp and off-time of VIN OK Comparator
the oscillator output clock:
The VIN OK comparator monitors the DC output of the
1 PFC and inhibits the PWM if the voltage on FBPFC is
fRT / CT = (4) less than its nominal 2.4V. Once the voltage reaches
tRT / CT + tDEAD
2.4V, which corresponds to the PFC output capacitor
The dead time of the oscillator is derived from the being charged to its rated boost voltage, the soft-start
following equation: begins.
⎛ VREF − 1 ⎞
tRT / CT = CT × RT × ln ⎜ ⎟ (5) PWM Soft-Start (SS)
⎝ VREF − 3.8 ⎠
at VREF=7.5V and tRT/CT=CT x RT x 0.56. PWM startup is controlled by selection of the external
The dead time of the oscillator is determined using: capacitor at soft-start. A current source of 10µA
supplies the charging current for the capacitor and
2.8V startup of the PWM begins at 1.5V.
tDEAD = × CT = 360 × CT (6)
7.78mA
The dead time is so small (tRT/CT>>tDEAD) that the
operating frequency can typically be approximated by:
1
fRT / CT = (7)
tRT / CT

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 20
PWM Control (RAMP) Leading/Trailing Modulation
When the PWM section is used in current mode, RAMP Conventional PWM techniques employ trailing-edge
is generally used as the sampling point for a voltage, modulation, in which the switch turns on right after the
representing the current in the primary of the PWM’s trailing edge of the system clock. The error amplifier
output transformer. The voltage is derived either from a output is then compared with the modulating ramp up.
current sensing resistor or a current transformer. In The effective duty cycle of the trailing edge modulation
voltage mode, RAMP is the input for a ramp voltage is determined during the on-time of the switch.
generated by a second set of timing components
(RRAMP, CRAMP) that have a minimum value of 0V and a In the case of leading-edge modulation, the switch is
peak value of approximately 6V. In voltage mode, feed turned off exactly at the leading edge of the system
forward from the PFC output bus is an excellent way to clock. When the modulating ramp reaches the level of
derive the timing ramp for the PWM stage. the error amplifier output voltage, the switch is turned
on. The effective duty-cycle of the leading-edge
modulation is determined during off-time of the switch.
Generating VDD
After turning on the FAN4800A/C, FAN4801/1S/2/2L at
11V, the operating voltage can vary from 9.3V to 28V.
The threshold voltage of the VDD OVP comparator is
28V and its hysteresis is 1V. When VDD reaches 28V,
OPFC is LOW, and the PWM section is not disturbed.
There are two ways to generate VDD: use auxiliary
power supply around 15V or use bootstrap winding to
self-bias the FAN4800A/C, FAN4801/1S/2/2L system.
The bootstrap winding can be taped from the PFC
boost choke or the transformer of the DC-to-DC stage.

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 21
Physical Dimensions
A
19.68
18.66
16 9
6.60
6.09
1 8
(0.40)
TOP VIEW
0.38 MIN 8.13

5.33 MAX 7.62
3.42
3.17
3.81
2.92
15
2.54 0.58 A 0.35 0
0.20
0.35
1.78
1.14 8.69
17.78
SIDE VIEW
NOTES: UNLESS OTHERWISE SPECIFIED

A THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BB
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR PROTRUSIONS
D) CONFORMS TO ASME Y14.5M-1994
E) DRAWING FILE NAME: N16EREV1
Figure 47. 16-pin Dual In-Line Package (DIP)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 22
Physical Dimensions (Continued)
Figure 48. 16-Pin Small Outline Package (SOIC)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 23

FAN4800A/C, FAN4801/1S/2/2L • Rev. 1.0.1 24

FAN4800A/C, FAN4801/1S/2/2L PFC/PWM Controller Combination: Features Description

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FAN4800A/C, FAN4801/1S/2/2L — PFC/PWM Controller Combination

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

Part Number PFC:PWM Frequency Ratio Brown Out / In Range In / Out

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Figure 1. Typical Application Current Mode

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Figure 2. Typical Application Voltage Mode

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Figure 3. FAN4800A/C Function Block Diagram

Figure 4. FAN4801/1S/2/2L Function Block Diagram

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Figure 5. Top Mark

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Figure 6. Pin Configuration (Top View)

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Symbol Parameter Min. Max. Unit

Recommended Operating Conditions

Symbol Parameter Min. Typ. Max. Unit

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Symbol Parameter Conditions Min. Typ. Max. Units

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Symbol Parameter Conditions Min. Typ. Max. Units

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Symbol Parameter Conditions Min. Typ. Max. Units

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Symbol Parameter Conditions Min. Typ. Max. Units

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Figure 7. IDD-ST vs. Temperature Figure 8. IDD-OP vs. Temperature

Figure 9. VTH-ON vs. Temperature Figure 10. ΔVTH vs. Temperature

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Figure 45. Compensation Network Connection for the

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

PWM Cycle-By-Cycle Current Limiter

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

0.38 MIN 8.13

NOTES: UNLESS OTHERWISE SPECIFIED

Figure 47. 16-pin Dual In-Line Package (DIP)

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Figure 48. 16-Pin Small Outline Package (SOIC)

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

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