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Verilog Examples

This document contains behavioral models for 3 basic digital logic components: 1) A 2-to-1 multiplexer that selects between 16-bit inputs A and B based on a single-bit selection signal. 2) A 2-to-4 decoder that activates one of four outputs based on a 2-bit input and enable signal. 3) A full adder module that calculates the sum and carry outputs from three 1-bit inputs.

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mohamed
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27 views

Verilog Examples

This document contains behavioral models for 3 basic digital logic components: 1) A 2-to-1 multiplexer that selects between 16-bit inputs A and B based on a single-bit selection signal. 2) A 2-to-4 decoder that activates one of four outputs based on a 2-bit input and enable signal. 3) A full adder module that calculates the sum and carry outputs from three 1-bit inputs.

Uploaded by

mohamed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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2x1 mux

* Behavioral Model of a 2 to 1 MUX (16-bit inputs)


*******************************************************************
***/
//*********************************************************
module mux_2to1(Y, A, B, sel);
//*********************************************************
output [15:0] Y;
input [15:0] A, B;
input sel;
reg [15:0] Y;
always @(A or B or sel)
if (sel == 1'b0)
Y = A;
else
Y = B;
endmodule
2 to 4 decoder
* Module of a 2 to 4 Decoder with an active high enable input and
* and active low outputs. This model uses behavioral modeling via
* via the "case" statement.
*******************************************************************/
//*********************************************************
module decoder_2to4(Y3, Y2, Y1, Y0, A, B, en);
//*********************************************************
output Y3, Y2, Y1, Y0;
input A, B;
input en;
reg Y3, Y2, Y1, Y0;
always @(A or B or en) begin
if (en == 1'b1)
case ( {A,B} )
2'b00: {Y3,Y2,Y1,Y0} = 4'b1110;
2'b01: {Y3,Y2,Y1,Y0} = 4'b1101;
2'b10: {Y3,Y2,Y1,Y0} = 4'b1011;
2'b11: {Y3,Y2,Y1,Y0} = 4'b0111;
default: {Y3,Y2,Y1,Y0} = 4'bxxxx;
endcase
if (en == 0)
{Y3,Y2,Y1,Y0} = 4'b1111;
end
endmodule
Full Adder
module full_adder
(
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);

input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;

wire w_WIRE_1;
wire w_WIRE_2;
wire w_WIRE_3;

assign w_WIRE_1 = i_bit1 ^ i_bit2;


assign w_WIRE_2 = w_WIRE_1 & i_carry;
assign w_WIRE_3 = i_bit1 & i_bit2;

assign o_sum = w_WIRE_1 ^ i_carry;


assign o_carry = w_WIRE_2 | w_WIRE_3;
// FYI: Code above using wires will produce the same results as:
// assign o_sum = i_bit1 ^ i_bit2 ^ i_carry;
// assign o_carry = (i_bit1 ^ i_bit2) & i_carry) | (i_bit1 & i_bit2);

// Wires are just used to be explicit.

endmodule full_adder

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