Hardware Description

Language

RTL Hardware Design Chapter 2 1

by P. Chu
 Outline
1. Overview on hardware description
language
2. Basic VHDL Concept via an example
3. VHDL in development flow

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 1. Overview on hardware
description language

RTL Hardware Design Chapter 2 3

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 Programming language
• Can we use C or Java as HDL?
• A computer programming language
– Semantics (“meaning”)
– Syntax (“grammar”)
• Develop of a language
– Study the characteristics of the underlying processes
– Develop syntactic constructs and their associated
semantics to model and express these
characteristics.

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 Traditional PL
• Modeled after a sequential process
– Operations performed in a sequential order
– Help human's thinking process to develop an
algorithm step by step
– Resemble the operation of a basic computer
model

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 HDL
• Characteristics of digital hardware
– Connections of parts
– Concurrent operations
– Concept of propagation delay and timing
• Characteristics cannot be captured by
traditional PLs
• Require new languages: HDL

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 Use of an HDL program
• Formal documentation
• Input to a simulator
• Input to a synthesizer

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 Modern HDL
• Capture characteristics of a digital circuit:
– entity
– connectivity
– concurrency
– timing
• Cover description
– in Gate level and RT level
– In structural view and behavioral view

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• Highlights of modern HDL:
– Encapsulate the concepts of entity, connectivity,
concurrency, and timing
– Incorporate propagation delay and timing information
– Consist of constructs for structural implementation
– Incorporate constructs for behavioral description
(sequential execution of traditional PL)
– Describe the operations and structures in gate level and
RT level.
– Consist of constructs to support hierarchical design
process

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by P. Chu
 Two HDLs used today
– VHDL and Verilog
– Syntax and ``appearance'' of the two
languages are very different
– Capabilities and scopes are quite similar
– Both are industrial standards and are
supported by most software tools

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 VHDL
– VHDL: VHSIC (Very High Speed Integrated
Circuit) HDL
– Initially sponsored by DoD as a hardware
documentation standard in early 80s
– Transferred to IEEE and ratified it as IEEE
standard 1176 in 1987 (known as VHDL-87)
– Major modification in ’93 (known as VHDL-93)
– Revised continuously

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 IEEE Extensions
– IEEE standard 1076.1 Analog and Mixed Signal
Extensions (VHDL-AMS)
– IEEE standard 1076.2 VHDL Mathematical Packages
– IEEE standard 1076.3 Synthesis Packages
– IEEE standard 1076.4 VHDL Initiative Towards ASIC
Libraries (VITAL)
– IEEE standard 1076.6 VHDL Register Transfer Level
(RTL) Synthesis
– IEEE standard 1164 Multivalue Logic System for
VHDL Model Interoperability
– IEEE standard 1029 VHDL Waveform and Vector
Exchange to Support Design and Test Verification
(WAVES)

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 2. Basic VHDL Concept
via an example

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 Even parity detection circuit
• Input: a(2), a(1), a(0)
• output: even

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 VHDL Listing 2.1

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• Entity declaration
– i/o ports (“outline” of the circuit)
• Architecture body
– Signal declaration
– Each concurrent statement
• Can be thought s a circuit part
• Contains timing information
– Arch body can be thought as a “collection of
parts”
• What’s the difference between this and a
C program

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 Conceptual interpretation

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 VHDL Listing 2.2

• Same entity declaration

• Implicit δ-delay (delta delay)
RTL Hardware Design Chapter 2 18
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 Structural description
• In structural view, a circuit is constructed
by smaller parts.
• Structural description specifies the types
of parts and connections.
• Essentially a textual description of a
schematic
• Done by using “component” in VHDL
– First declared (make known)
– Then instantiated (used)

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 Example

• Even detector using previously

designed components (xor2 and not1)

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 VHDL Listing 2.3

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 Somewhere in library

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 “Behavioral” description
• No formal definition on “behavioral” in VHDL
• VHDL “process”: a language construct to
encapsulate “sequential semantics”
– The entire process is a concurrent statement
– Syntax:

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 Listing 2.5

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 Conceptual interpretation

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 Listing 2.6

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 Testbench
• a “virtual” experiment table
– Circuit to be tested
– Input stimuli (e.g., function generator)
– Output monitor (e.g., logic analyzer)
• e.g.,

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 VHDL Listing 2.7

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 Configuration
• Multiple architecture bodies can be associated with an
entity declaration
– Like IC chips and sockets
• VHDL configuration specifies the binding
• E.g.,

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 3. VHDL in development flow

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 Scope of VHDL

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 Coding for synthesis
• “Execution” of VHDL codes
– Simulation:
• Design “realized” in a virtual environment
(simulation software)
• All language constructs can be “realized”
• “realized” by a single CPU

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 – “Synthesis
• Design realized by hardware components
• Many VHDL constructs can be synthesized (e,g,
file operation, floating-point data type, division)
• Only small subset can be used
• E.g., 10 additions
• Syntactically correct code ≠ Synthesizable code
• Synthesizable code ≠ Efficient code
• Synthesis software only performs transformation
and local search

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 • The course focuses on hardware, not
VHDL (i.e., the “H”, not “L” of HDL)
• Emphasis on coding for synthesis:
– Code accurately describing the underlying
hardware structure
– Code providing adequate info to guide
synthesis software to generate efficient
implementation

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by P. Chu