ENGI 3861 – Digital Logic

II. COMBINATIONAL LOGIC DESIGN

Combinational Logic ⇒ output of digital system is only dependent

on current inputs (i.e., no memory)

(a) Boolean Algebra

- developed by George Boole in 1850s

- algebra defined on a set of 2 elements, {0, 1}, with binary

operators multiply (AND), add (OR), and invert (NOT):

X⋅Y ≡ X AND Y
X+Y ≡ X OR Y
Xʹ′ or X ≡ NOT (X)

- Boolean algebra theorems:

One Variable Theorems

Label “⋅” “+”
Identities X⋅1 = X X+0 = X
Null elements X⋅0 = 0 X+1 = 1
Idempotency X⋅X = X X+X = X
Complements X⋅Xʹ′ = 0 X+Xʹ′ = 1
Involution (Xʹ′)ʹ′ = X
Two/Three Variable Theorems
Commutativity X⋅Y = Y⋅X X+Y = Y+X
Associativity (X⋅Y)⋅Z = X⋅(Y⋅Z) (X+Y)+Z = X+(Y+Z)
Distributivity (X+Y)⋅(X+Z) = X+Y⋅Z X⋅Y+X⋅Z = X⋅(Y+Z)
DeMorgan’s (X⋅Y)ʹ′ = Xʹ′+Yʹ′ (X+Y)ʹ′ = Xʹ′⋅Yʹ′

- duality: to get “+” column from “⋅” column (and vice versa),
swap “+” with “⋅” operators and swap 0s and 1s

- literal ≡ primed or unprimed variable

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Example: Show (X⋅Y)ʹ′ = Xʹ′+Yʹ′ using a truth table.

Example: Prove that X + X⋅Y = X.

Example: Prove distributivity for “⋅” using other theorems.

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- two/three variable theorems can be generalized to n variables

→ for example, DeMorgan’s theorem

(A+B+C+D+…)ʹ′ = Aʹ′Bʹ′Cʹ′Dʹ′…
(ABCD…)ʹ′ = Aʹ′+Bʹ′+Cʹ′+Dʹ′…

Note: will often leave out “⋅” operator for convenience.

- more on DeMorgan’s:

AND + NOT ≡ NAND

by DeMorgan’s (NOTs + OR)

NAND ≡

- similarly, for NOR can show:

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Example: Consider F = Xʹ′YZʹ′ + Xʹ′Yʹ′Z and apply DeMorgan's:

Fʹ′ =

- previous example reflects generalized DeMorgan's theorem

which can be used to get Fʹ′, given F:

→ take dual of function F and complement literals

e.g., Given F = Xʹ′YZʹ′ + Xʹ′Yʹ′Z, dual is

Fdual =

Fʹ′ = as expected.

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Canonical Sum-of-Products and Product-of-Sums Forms

minterm: AND (product) term which evaluates to 1 for given input

maxterm: OR (sum) term which evaluates to 0 for given input

XYZ Minterm Maxterm

000 m0 = M0 =
001 m1 = M1 =
010 m2 = M2 =
011 m3 = M3 =
100 m4 = M4 =
101 m5 = M5 =
110 m6 = M6 =
111 m7 = M7 =

- canonical sum of products (SoP) form of Boolean function F

≡ sum of minterms corresponding to F = 1
(also called "standard sum of products")

- canonical product of sums (PoS) form of Boolean function F

≡ product of maxterms corresponding to F = 0
(also called "standard product of sums")

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Example:
XYZ F
F =
000 0
001 1
010 0 =
011 0
100 1 (canonical SoP)
101 0
110 0
111 1

now, F' =

so, F = (F')' =

(generalized DeMorgan)

hence, F =

(canonical PoS)

- sometimes minterm list or maxterm list notation is used:

F = m1 + m4 + m7 ⇒ F = ΣXYZ(1, 4, 7)
and F = M0M2M3M5M6 ⇒ F = Π XYZ (0, 2, 3, 5, 6)

- SoP and PoS forms can usually be simplified to minimize

literals → no longer “canonical”
e.g., simplified SoP: F1 = Yʹ′ + XY + Xʹ′YZʹ′
simplified PoS: F2 = X(Yʹ′+Z)(Xʹ′+Y+Zʹ′)

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(b) Realization of Circuits

Design Objectives

(1) minimum number of gates

(2) minimum number of inputs to a gate
(3) minimum propagation time through circuit
(4) minimum number of interconnections

Boolean Function Input

Example: F = Yʹ′ + XY + Xʹ′YZʹ′ (SoP form) leads to

- SoP form leads to 2 levels of logic:

AND-OR logic → AND gates followed by OR gates

(ignoring NOTs and assuming that any number of
inputs to a gate is allowed)

- similarly, PoS form leads to 2 levels of logic:

OR-AND logic → OR gates followed by AND gates

(ignoring NOTs and assuming that any number of
inputs to a gate is allowed)

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Truth Table to Gates

Example: (same as earlier example)

XYZ F
SoP:
000 1
F=
001 1
010 1
011 0
100 1
101 1 leading to
110 1
111 1

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- using canonical SoP directly to gates often takes many gates and
gates are large (in this example, 7 input OR gate!)
→ large gates can be built using smaller gates

e.g.,

6 2-input ORs ≡ 1 7-input OR, but 3 layers of logic gates

⇒ longer propagation delay ⇒ circuit slower (to come)

- in order to minimize circuit, desirable to simplify canonical SoP

- from canonical SoP, using Boolean algebra:

F =

= (reduced SoP form)

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→ a lot of work and difficult to know exactly what steps to

take when using algebra
→ not guaranteed to find mimimal circuit
⇒ for this example, F = X + Yʹ′ + Zʹ′
(easily derived using canonical PoS form)

→ some other reduction/minimization/simplification

methods exist such as Karnaugh maps for small
functions and computer algorithms exist to minimize
larger functions

- any logic function can be implemented using AND, OR, and

NOT gates (by starting with SoP or PoS forms), but CMOS
technology lends itself to efficient implementation of
NANDs and NORs
→ any logic function can be implemented with exclusively
NAND (or NOR) gates

Recall: (A⋅B)' = A' + B'

AND NAND + NOT 2 NOTs + NOR

OR NOR + NOT 2 NOTs + NAND

NOT NAND NOR

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Example: Implement F = Y' +XY+X'YZ' using only NAND gates.

- similarly all NOR circuit can be derived (most easily for OR-
AND circuit)

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(c) Logic Minimization

- as we have seen, can use Boolean algebra theorems to reduce

number and size of gates in a circuit
→ logic minimization or logic simplification

- also, there are computer-aided design (CAD) tools for

minimization which can find minimal or near-minimal circuit
for most expressions with dozens of inputs and hundreds of
product terms

- generally assume that Xʹ′ is readily available and to use Xʹ′ at gate
input has no more cost that using X

Karnaugh Maps (K-maps)

- good systematic visual method for minimizing 3 and 4 input

Boolean functions

3 input map
YZ
F: X 00 01 11 10 Note: adjacent
columns differ
0 m0 m1 m3 m2
in only 1 bit
⇒ adjacent
1 m4 m5 m7 m6
squares differ
in only 1 bit

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Examples:

(1) K-map of F:

YZ
X 00 01 11 10

0 0 0 1 1

1 1 1 0 0

(2) K-map of F:
YZ
X 00 01 11 10

0 0 0 1 0

1 1 0 1 1

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(3) K-map of F:
YZ
X 00 01 11 10

0 0 1 1 1

1 0 1 1 0

- for 3 input K-map:

1 square ≡ term with 3 literals
2 squares ≡ term with 2 literals
4 squares ≡ term with 1 literal

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4 input map

F: YZ
WX 00 01 11 10

00 m0 m1 m3 m2

01 m4 m5 m7 m6

11 m12 m13 m15 m14

10 m8 m9 m11 m10

→ again adjacent squares only differ in 1 bit

Examples:

(1) K-map of F:

YZ
WX 00 01 11 10

00 1 1 0 1
F=
01 1 1 0 1

11 1 1 0 1

10 1 1 0 0

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(2) K-map of F:
YZ
WX 00 01 11 10

00 1 1 0 1

01 0 0 0 1

11 0 0 0 0

10 1 1 0 1

F=

(3) K-map of F:
YZ
WX 00 01 11 10

00 0 0 1 0

01 1 0 1 1

11 1 1 1 1

10 0 0 1 0

F=

Objective: (1) find large circles (fewer literals) and

(2) minimize number of circles (fewer AND gates)

- for 4 input K-map:

1 / 2 / 4 / 8 squares ≡ term with 4 / 3 /2 / 1 literals

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K-maps for PoS

Example:
YZ
X 00 01 11 10

0 1 1 0 1
F = M3⋅M5⋅M7
1 1 0 0 1

F = (X+Y'+Z')⋅(X'+Y+Z')⋅(X'+Y'+Z')

= (X+Y'+Z')⋅(X'+Y+Z')⋅(X'+Y'+Z')⋅(X'+Y'+Z')
(repeat M7 term)

= (X+[Y'+Z'])⋅(X'+[Y'+Z'])⋅(X'+Y+Z')⋅(X'+Y'+Z')
(move terms around)

= ( XX'+X[Y'+Z']+[Y'+Z']X'+[Y'+Z'][Y'+Z'] )
⋅(X'+Y+Z')⋅(X'+Y'+Z')
(multiplying out left 2 brackets)

= ( )
⋅(X'+Y+Z')⋅(X'+Y'+Z')
(simplifying 1st bracket)

= ( )⋅(X'+Y+Z')⋅(X'+Y'+Z')
(simplifying 1st bracket)

= ( )⋅( )
(simplifying right 2 brackets → try it!)

(Note also, F = using K-map for SoP)

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Don’t Cares

- in some cases, outputs for given inputs can be either “0” or “1”,
whichever is convenient for design ⇒ “don’t care”

→ indicated by “X” in values of truth table and K-map

- “don’t cares” can be exploited to help minimize circuit

e.g.,
XYZ F
000 1
001 X
010 1
011 1
100 0
101 0
110 X
111 1

YZ
X 00 01 11 10

0 1 X 1 1

1 0 0 1 X

F =

(Compare to F = Xʹ′⋅Zʹ′ + Y⋅Z if “don’t cares” assumed to be “0”.)

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Multiple Output Minimization

- in many cases, there are multiple circuit outputs and considering

them together can result in fewer gates

e.g., F = XY + XZ + Yʹ′Z, G = Xʹ′Y + XYZ, H = Xʹ′YZ + XZ

→ implemented independently:

5 2-input ANDs
2 3-input ANDs
2 2-input ORs
1 3-input OR

→ implemented together:

6 2-input ANDs (+1)

0 3-input ANDs (−2)
2 2-input ORs
1 3-input OR

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(d) Combinational Logic Design Examples

Example 1: Temperature Controller

- temperature sensor produces following inputs to controller:

Temperature 4-bit Input Code Action

WXYZ
<15° 0000
15° 0001 heat on, fan on high
16° 0010
17° 0011
18° 0100 heat on, fan on low
19° 0101
20° 0110 heat off, AC off
21° 0111
22° 1000
23° 1001
AC on
24° 1010
25° 1011
>25° 1100

- controller should control furnace/AC unit with 3 outputs with the

objective of keeping the temperature at 20°:

H (heat+fan on/off) 1 ≡ on, 0 ≡ off

F (fan low/high) 0 ≡ low, 1 ≡ high
C (AC on/off) 1 ≡ on, 0 ≡ off

Design a NAND-only circuit to implement the controller logic.

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WXYZ H F C
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

H:
YZ
WX 00 01 11 10

00

01
11

10

H=

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F:
YZ
WX 00 01 11 10

00

01
11

10

F=

C:
YZ
WX 00 01 11 10

00

01
11

10

C=

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Resulting circuit using NANDs only:

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Example 2: 2-out-of-5 Encoding

- 2-out-of-5 encoder encodes digits as follows:

Digit Code Aside: What is value of 2-out-of-5 encoding?

0 11000
1 00011
2 00101
3 00110
4 01001 Design a logic circuit to convert a
5 01010 binary representation of a digit to a
6 01100 2-out-of-5 code.
7 10001
8 10010
9 10100 Truth table:

WXYZ A B C D E
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

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A: YZ
WX 00 01 11 10

00

01
11

10

A=

B: YZ
WX 00 01 11 10

00

01
11

10

B=

C: YZ
WX 00 01 11 10

00

01
11

10

C=

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D: YZ
WX 00 01 11 10

00

01
11

10

D=

E: YZ
WX 00 01 11 10

00

01
11

10

E=

Draw circuit. Be sure to share gates where possible across multiple

outputs.

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Example 3: 2-bit Multiplier

A digital combinational logic circuit is required to multiply two

2-bit unsigned binary numbers. Assume that the two inputs are
represented by X1X0 and Y1Y0 and the output, which is 4 bits in
size, is represented by Z3Z2Z1Z0. Design the minimized circuit to
implement the multiplier using any appropriate method. Your
solution must include a complete diagram of the final circuit.
You may use any appropriate gates.

X 1X 0 Y 1Y 0 Z3Z2Z1Z0
00 00
00 01
00 10
00 11
01 00
01 01
01 10
01 11
10 00
10 01
10 10
10 11
11 00
11 01
11 10
11 11

Z3 =

(No simplification possible!)

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Y1 Y0
Z2:
X1 X0 00 01 11 10

00
Z2 =
01
11

10

Y1 Y0
Z1:
X1 X0 00 01 11 10

00
Z1 =
01
11

10

Y1 Y0
Z0:
X1 X0 00 01 11 10

00
Z0 =
01
11

10

Draw circuit to realize Z3Z2Z1Z0.

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(e) Practical Considerations for Digital Circuits

- practical circuits are constructed using digital electronics

comprised of nonlinear devices such as transistors

- most popular digital logic technology today is

Complementary Metal Oxide Semiconductor (CMOS)
→ voltage level represents binary value with typical levels:
“0” → 0−1.5 V, “1” → 3.5−5.0 V

How do we implement gates? → using electronic switches

Inverter (NOT)

- switches can be implemented using transistors based on

semiconductor material such as n-doped silicon (NMOS) or
p-doped silicon (PMOS)

- note that, although logic diagrams do not show it, all gates
require a voltage or power supply
→ in our labs, we use Vdd = 5.0 V

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Logic Families

TTL – Transistor-Transistor Logic (Bipolar Logic)

- uses bipolar junction transistor
→ will learn about in ENGI 4854 – Electronic Devices
- popular in 1970s, but now supplanted by CMOS

CMOS – Complementary Metal Oxide Semiconductor

- takes much less power that TTL
- many sub-families
→ high speed, lower power, and/or TTL compatibility
- to operate CMOS at high speed, use supply voltage VDD ≈ 5 V
- to operate CMOS at lower power, use lower supply voltage
of, say, VDD ≈ 3.3 V

- 7400 series ICs are SSI and MSI packages for building digital
systems out of discrete components
→ in practice, digital systems are now integrated into one or
at most a few ICs ⇒ LSI, VLSI

Electrical Characteristics of CMOS

Static Behaviour
- input and output signals of gates are not changing
→ static power consumption, noise immunity, tolerances
between input and output levels

Dynamic Behaviour
- input and output signals of gates are changing
→ dynamic power consumption, timing from input change to
output change

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Logic Levels and Noise Margin

I/O Characteristic
of CMOS Inverter:

- inputs allowed over wider range than precise outputs

e.g., Vin < 1.5 V produces Vout very close to 5 V
Vin > 3.5 V produces Vout very close to 0 V

- noise margin (NM) is amount of noise to corrupt an output so

that the input of the subsequent gate not properly recognized

- consider the following specification for a device (which can be

obtained from the device's data sheet)
VOHmin = 4.4 V , VIHmin = 3.15 V → NMH = 4.4 − 3.15 = 1.25 V
VILmax = 1.35 V, VOLmax = 0.1 V → NML = 1.35 − 0.1 = 1.25 V

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Fan-out

- fan-out is number of gates that can be connected to an output to

ensure that a device continues to operate properly

Fan-in

- fan-in is the number of inputs to a gate

→ practical considerations limit fan-in of a CMOS gate
to typically ≤ 6

Power Consumption and Leakage Current

- power in CMOS circuits can be categorized into 2 types:

(1) dynamic power

→ current drawn from power source when gates are
switching (i.e., changing their output values)
→ until recently CMOS technology scales, dynamic
power comprised the majority of power consumed
by a circuit

(2) static power

→ small amount of current drawn from power source
due to leakage current even when values are not
changing in the circuit
→ recent CMOS technologies, while being very low
power, have reduced dynamic power to the point
where static power has become significant
fraction of overall power consumption

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Electrostatic Discharge

- in CMOS devices, static electricity may discharge across

transistor thereby destroying device

→ sometimes necessary to be careful when handling CMOS

devices, e.g., wear wrist strap that connects to ground to
avoid static charge build up

→ CMOS devices used in lab should be robust enough to avoid

electrostatic damage without any special precautions

Transition Time

- when a gate’s output changes, it needs to charge/discharge stray

capacitances caused by transistors and wires

- tr and tf affect speed of switching, i.e., rate of gate changes

- usually, for most operating conditions and circuits speeds,

transition time is negligible and ignored

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Propagation Delay

- propagation delay is time required for input signal to cause a

change in output signal of a gate due to change of state
required on internal transistors prior to state change at output

idealized inverter timing

realistic inverter timing

- propagation delays can be significant in high speed circuits and

propagation delay is a fundamental constraint on the speed of
a synchronous digital circuit as we shall see

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(f) Timing Hazards

Static Hazards

Consider AND-OR circuit:

- recall each gate has a propagation delay, which is typically

different for different types of gates and can even vary
somewhat from gate to gate of same type

→ for convenience, assume all gates in above circuit have same

propagation delay, tprop

Timing Diagram

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→ F should stay at 1, but drops to 0 momentarily

⇒ static-1 hazard
“static” ⇒ because output should not change, but does
experience a momentary glitch
“hazard” ⇒ possibility that glitch can occur

- static-0 hazards would exist with OR-AND circuits (circuits built

from PoS form)

- note: a circuit with a static hazard may experience a glitch, but

may not → depends on propagation delay of gates

- also, hazard may not matter to functionality of circuit

→ e.g., not critical in synchronous sequential logic but
critical in asynchronous sequential logic design

- can use K-maps to identify and remove:

YZ
X 00 01 11 10

0 0 0 1 0

1 1 0 1 1

→ no AND term covers XYZ = 110 and 111

⇒ moving between these inputs could cause a glitch

→ to resolve, add extra gate to cover these 2 minterms resulting in

- no glitch possible
⇒ no static hazard

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Dynamic Hazards

- in some cases, output of circuit should be

but becomes

- hence, circuit has “dynamic hazard” ≡ possibility of output

changing more than once due to a single input change

- hazards (both static and dynamic) can cause problems in

asynchronous logic circuits, but risks can be eliminated
with a proper synchronous design (to come)

(g) Summary of Combinational Logic Design

(1) Inputs
→ wording, truth table, Boolean function, K-map
(2) Objectives
→ minimize # and size of gates, minimize timing delay
(3) Constraints
→ NANDs only, maximum timing delays, limits on gate
driving capabilities (fan-out) and/or gate size (fan-in)
(4) Tools
→ Boolean algebra, SoP/PoS forms, Karnaugh maps (for
small circuits with few inputs), computer-aided design
(CAD) tools (for large circuits)

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