Features: CMOS 16-Bit Microprocessor

DATASHEET
80C86 FN2957
CMOS 16-Bit Microprocessor Rev 5.00
Jul 13, 2018
The 80C86 high performance 16-bit CMOS CPU is Features

manufactured using a self-aligned silicon gate CMOS
process (Scaled SAJI IV). Two modes of operation, • Compatible with NMOS 8086
minimum for small systems and maximum for larger • Completely static CMOS design
applications such as multiprocessing, allow user - DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2)
configurations to achieve the highest performance level. Full
• Low power operation
TTL compatibility (with the exception of CLOCK) and
industry standard operation allow use of existing NMOS - lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA max
8086 hardware and software designs. - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . .10mA/MHz typ
• 1MByte of direct memory addressing capability
Related Literature
• 24 operand addressing modes
For a full list of related documents, visit our website
• Bit, Byte, Word and Block Move operations
• 80C86 product page
• 8-Bit and 16-Bit signed/unsigned arithmetic
- Binary, or decimal
- Multiply and divide
• Wide operating temperature range
- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
- M80C86 . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
• Pb-free available (RoHS compliant)
Ordering Information
PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. #
CP80C86-2Z (Note 1) CP80C86-2Z 0 to +70 40 Ld PDIP (Note 2) E40.6

(RoHS compliant)
MD80C86-2/883 MD80C86-2/883 -55 to +125 40 Ld CERDIP F40.6
MD80C86-2/B MD80C86-2/B -55 to +125 40 Ld CERDIP F40.6
8405202QA 8405202QA -55 to +125 40 Ld CERDIP (SMD) F40.6
NOTES:
1. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
FN2957 Rev 5.00 Page 1 of 39

Jul 13, 2018
80C86
Table of Contents
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Minimum Mode System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Maximum Mode System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Static Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Internal Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Minimum and Maximum Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I/O Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Processor RESET and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Hold Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Interrupt Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Non-Maskable Interrupt (NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Maskable Interrupt (INTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read/Modify/Write (Semaphore) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operations Using Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
External Synchronization Using TEST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Basic System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
System Timing - Minimum System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bus Timing - Medium Size Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC Electrical Specifications – Minimum Complexity SystemAC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC Electrical Specifications – Maximum Mode SystemAC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC Testing Input, Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Burn-In Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Metallization Topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Metallization Mask Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Dual-In-Line Plastic Packages (PDIP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Ceramic Dual-In-Line Frit Seal Packages (CERDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
FN2957 Rev 5.00 Page 2 of 39

Jul 13, 2018
80C86
Functional Diagram
EXECUTION UNIT BUS INTERFACE UNIT
REGISTER FILE RELOCATION
REGISTER FILE
DATA POINTER SEGMENT REGISTERS
AND AND
INDEX REGS INSTRUCTION POINTER
(8 WORDS) (5 WORDS)
BHE/S7
16-BIT ALU A19/S6
4
A16/S3
FLAGS
16 AD15-AD0
BUS INTERFACE UNIT
3 INTA, RD, WR
4 DT/R, DEN, ALE, M/IO
6-BYTE
INSTRUCTION
QUEUE
TEST
INTR LOCK
NMI
CONTROL AND TIMING 2 QS0, QS1
RQ/GT0, 1 2
HOLD 3 S2, S1, S0
HLDA
3
CLK RESET READY MN/MX GND
VCC
MEMORY INTERFACE
C-BUS
INSTRUCTION
STREAM BYTE
B-BUS QUEUE
ES
BUS CS
INTERFACE SS
UNIT DS
IP
EXECUTION UNIT
CONTROL SYSTEM
A-BUS
AH AL
BH BL ARITHMETIC/
LOGIC UNIT
CH CL
EXECUTION DH DL
UNIT
SP
BP
SI
DI FLAGS
FIGURE 1. FUNCTIONAL DIAGRAM
FN2957 Rev 5.00 Page 3 of 39

Jul 13, 2018
80C86
Pinout
40 LD PDIP, CERDIP
TOP VIEW
MAX (MIN)
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4
AD11 5 36 A18/S5
AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 RQ/GT0 (HOLD)
AD5 11 30 RQ/GT1 (HLDA)
AD4 12 29 LOCK (WR)
AD3 13 28 S2 (M/IO)
AD2 14 27 S1 (DT/R)
AD1 15 26 S0 (DEN)
AD0 16 25 QS0 (ALE)
NMI 17 24 QS1 (INTA)
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET
Pin Descriptions
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct
multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
PIN
SYMBOL NUMBER TYPE DESCRIPTION
AD15-AD0 2-16, 39 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed memory/lO address (t1) and data
(t2, t3, tW, t4) bus. A0 is analogous to BHE for the lower byte of the data bus, pins D7-D0. It is LOW
during Ti when a byte is to be transferred on the lower portion of the bus in memory or I/O operations.
8-bit oriented devices tied to the lower half would normally use A0 to condition chip select functions
(see BHE). These lines are active HIGH and are held at high impedance to the last valid logic level
during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”.
A19/S6 35-38 O ADDRESS/STATUS: During t1, these are the four most significant address lines for memory
A18/S5 operations. During I/O operations these lines are LOW. During memory and I/O operations, status
A17/S4 information is available on these lines during t2, t3, tW, t4. S6 is always LOW. The status of the
A16/S3 interrupt enable FLAG bit (S5) is updated at the beginning of each clock cycle. S4 and S3 are encoded
as shown.
This information indicates which segment register is presently being used for data accessing.
These lines are held at high impedance to the last valid logic level during local bus “hold acknowledge”
or “grant sequence”.
S4 S3 CHARACTERISTICS
0 0 Alternate Data
0 1 Stack
1 0 Code or None
1 1 Data
FN2957 Rev 5.00 Page 4 of 39

Jul 13, 2018
80C86
Pin Descriptions (Continued)

The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct
multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
PIN
BHE/S7 34 O BUS HIGH ENABLE/STATUS: During t1 the bus high enable signal (BHE) should be used to enable
data onto the most significant half of the data bus, pins D15-D8. 8-bit oriented devices tied to the upper
half of the bus would normally use BHE to condition chip select functions. BHE is LOW during t1 for
read, write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion of
the bus. The S7 status information is available during t2, t3, and t4. The signal is active LOW, and is
held at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold
acknowledge” or “grant sequence”, it is LOW during t1 for the first interrupt acknowledge cycle.
BHE A0 CHARACTERISTICS
0 0 Whole Word
0 1 Upper Byte From/to Odd Address
1 0 Lower Byte From/to Even address
1 1 None
RD 32 O READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depending
on the state of the M/IO or S2 pin. This signal is used to read devices which reside on the 80C86 local
bus. RD is active LOW during t2, t3, and tW of any read cycle, and is guaranteed to remain HIGH in
t2 until the 80C86 local bus has floated.
This line is held at a high impedance logic one state during “hold acknowledge” or “grand sequence”.
READY 22 I READY: The acknowledgment from the addressed memory or I/O device that completes the data
transfer. The RDY signal from memory or I/O is synchronized by the 82C84A Clock Generator to form
READY. This signal is active HIGH. The 80C86 READY input is not synchronized. Correct operation
is not guaranteed if the Setup and Hold Times are not met.
INTR 18 I INTERRUPT REQUEST: A level triggered input which is sampled during the last clock cycle of each
instruction to determine if the processor should enter into an interrupt acknowledge operation. A
subroutine is vectored to using an interrupt vector lookup table located in system memory. It can be
internally masked by software resetting the interrupt enable bit.
lNTR is internally synchronized. This signal is active HIGH.
TEST 23 I TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,
otherwise the processor waits in an “Idle” state. This input is synchronized internally during each clock
cycle on the leading edge of CLK.
NMI 17 I NON-MASKABLE INTERRUPT: An edge triggered input which causes a Type 2 interrupt. A
subroutine is vectored to using an interrupt vector lookup table located in system memory. NMI is not
maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the end of the
current instruction. This input is internally synchronized.
RESET 21 I RESET: Causes the processor to immediately terminate its present activity. The signal must transition
LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution, as described
in the “Instruction Set Summary” on page 31 when RESET returns LOW. RESET is internally
synchronized.
CLK 19 I CLOCK: Provides the basic timing for the processor and bus controller. It is asymmetric with a 33%
duty cycle to provide optimized internal timing.
VCC 40 VCC: +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for
decoupling.
GND 1, 20 GND: Ground. Note: Both must be connected. A 0.1µF capacitor between pins 1 and 20 is
recommended for decoupling.
MN/MX 33 I MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are
discussed in the following sections.
FN2957 Rev 5.00 Page 5 of 39

Jul 13, 2018
80C86
Minimum Mode System

The following pin function descriptions are for the 80C86 in minimum mode (that is, MN/MX = VCC). Only the pin functions which are unique to
minimum mode are described; all other pin functions are as described in the following.
PIN
M/IO 28 O STATUS LINE: Logically equivalent to S2 in the maximum mode. It is used to distinguish a memory
access from an I/O access. M/lO becomes valid in the t4 preceding a bus cycle and remains valid until
the final t4 of the cycle (M = HIGH, I/O = LOW). M/lO is held to a high impedance logic one during local
bus “hold acknowledge”.
WR 29 O WRITE: Indicates that the processor is performing a write memory or write I/O cycle, depending on
the state of the M/IO signal. WR is active for t2, t3, and tW of any write cycle. It is active LOW, and is
held to high impedance logic one during local bus “hold acknowledge”.
INTA 24 O INTERRUPT ACKNOWLEDGE: Used as a read strobe for interrupt acknowledge cycles. It is active
LOW during t2, t3, and tW of each interrupt acknowledge cycle. Note that INTA is never floated.
ALE 25 O ADDRESS LATCH ENABLE: Provided by the processor to latch the address into the 82C82/82C83
address latch. It is a HIGH pulse active during clock LOW of t1 of any bus cycle. Note that ALE is never
floated.
DT/R 27 O DATA TRANSMIT/RECEIVE: Needed in a minimum system that desires to use a data bus transceiver.
It is used to control the direction of data flow through the transceiver. Logically,
DT/R is equivalent to S1 in maximum mode, and its timing is the same as for M/IO (T = HIGH,
R = LOW). DT/R is held to a high impedance logic one during local bus “hold acknowledge”.
DEN 26 O DATA ENABLE: Provided as an output enable for a bus transceiver in a minimum system which uses
the transceiver. DEN is active LOW during each memory and I/O access and for INTA cycles. For a
read or INTA cycle it is active from the middle of t2 until the middle of t4, while for a write cycle it is
active from the beginning of t2 until the middle of t4. DEN is held to a high impedance logic one during
local bus “hold acknowledge”.
HOLD 31, 30 I HOLD: Indicates that another master is requesting a local bus “hold”. To be acknowledged, HOLD
HLDA O must be active HIGH. The processor receiving the “hold” issues a “hold acknowledge” (HLDA) in the
middle of a t4 or TI clock cycle. Simultaneously with the issuance of HLDA, the processor floats the
local bus and control lines. After HOLD is detected as being LOW, the processor lowers HLDA, and
when the processor needs to run another cycle, it again drives the local bus and control lines.
HOLD is not an asynchronous input. External synchronization should be provided if the system cannot
otherwise guarantee the setup time.
Maximum Mode System

The following pin function descriptions are for the 80C86 system in maximum mode (for example, MN/MX - GND). Only the pin functions which are
unique to maximum mode are described in the following.
PIN
S0 26 O STATUS: is active during t4, t1, and t2 and is returned to the passive state (1, 1, 1) during t3 or during
S1 27 O tW when READY is HIGH. This status is used by the 82C88 Bus Controller to generate all memory
S2 28 O and I/O access control signals. Any change by S2, S1, or S0 during t4 is used to indicate the beginning
of a bus cycle, and the return to the passive state in t3 or tW is used to indicate the end of a bus cycle.
These signals are held at a high impedance logic one state during “grant sequence”.
S2 S1 S0 CHARACTERISTICS
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive
FN2957 Rev 5.00 Page 6 of 39

Jul 13, 2018
80C86
Maximum Mode System (Continued)

The following pin function descriptions are for the 80C86 system in maximum mode (for example, MN/MX - GND). Only the pin functions which are
unique to maximum mode are described in the following.
PIN
RQ/GT0 31, 30 I/O REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the
RQ/GT1 local bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GTO having
higher priority than RQ/GT1. RQ/GT has an internal pull-up bus hold device so it can be left
unconnected. The request/grant sequence is as follows (see RQ/GT Sequence Timing)
1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (“hold”) to the
80C86 (pulse 1).
2. During a t4 or TI clock cycle, a pulse 1 CLK wide from the 80C86 to the requesting master
(pulse 2) indicates that the 80C86 has allowed the local bus to float and that it will enter the “grant
sequence” state at the next CLK. The CPU’s bus interface unit is disconnected logically from the
local bus during “grant sequence”.
3. A pulse 1 CLK wide from the requesting master indicates to the 80C86 (pulse 3) that the “hold”
request is about to end and that the 80C86 can reclaim the local bus at the next CLK. The CPU
then enters t4 (or TI if no bus cycles pending). Each Master-Master exchange of the local bus is
a sequence of 3 pulses. There must be one idle CLK cycle after each bus exchange. Pulses are
active low.
If the request is made while the CPU is performing a memory cycle, it releases the local bus during t4
of the cycle when all the following conditions are met:
1. Request occurs on or before t2.
2. Current cycle is not the low byte of a word (on an odd address).
3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made, the two possible events follow:
1. The local bus is released during the next cycle.
2. A memory cycle starts within three clocks. Now the four rules for a currently active memory cycle
apply with condition number 1 already satisfied.
LOCK 29 O LOCK: output indicates that other system bus masters are not to gain control of the system bus while
LOCK is active LOW. The LOCK signal is activated by the “LOCK” prefix instruction and remains active
until the completion of the next instruction. This signal is active LOW, and is held at a high impedance
logic one state during “grant sequence”. In MAX mode, LOCK is automatically generated during t2 of
the first INTA cycle and removed during t2 of the second INTA cycle.
QS1, QSO 24, 25 O QUEUE STATUS: The queue status is valid during the CLK cycle after which the queue operation is
performed.
QS1 and QS0 provide status to allow external tracking of the internal 80C86 instruction queue. Note
that QS1, QS0 never become high impedance.
QSI QSO
0 0 No operation
0 1 First byte of op code from queue
1 0 Empty the queue
1 1 Subsequent byte from queue
FN2957 Rev 5.00 Page 7 of 39

Jul 13, 2018
80C86
Functional Description Memory Organization

The processor provides a 20-bit address to memory, which
Static Operation
locates the byte being referenced. The memory is organized
All 80C86 circuitry is of static design. Internal registers, as a linear array of up to 1 million bytes, addressed as
counters and latches are static and require no refresh as with 00000(H) to FFFFF(H). The memory is logically divided into
dynamic circuit design. This eliminates the minimum operating code, data, extra, and stack segments of up to 64k bytes each,
frequency restriction placed on other microprocessors. The with each segment falling on 16-byte boundaries (see Figure 2).
CMOS 80C86 can operate from DC to the specified upper
frequency limit. The processor clock can be stopped in either FFFFFH
state (HIGH/LOW) and held there indefinitely. This type of
operation is especially useful for system debug or power
64k-BIT CODE SEGMENT
critical applications.
The 80C86 can be single stepped using only the CPU clock. XXXXOH
This state can be maintained as long as is necessary. Single
step clock operation allows simple interface circuitry to provide
STACK SEGMENT
critical information for bringing up your system. + OFFSET
Static design also allows very low frequency operation (down

to DC). In a power critical situation, this can provide extremely SEGMENT
REGISTER FILE
low power operation because 80C86 power dissipation is DATA SEGMENT
CS
directly related to operating frequency. As the system
SS
frequency is reduced, so is the operating power until,
DS
ultimately, at a DC input frequency, the 80C86 power
ES
requirement is the standby current, (500µA maximum).
EXTRA SEGMENT
Internal Architecture
The internal functions of the 80C86 processor are partitioned
00000H
logically into two processing units. The first is the Bus Interface
Unit (BlU) and the second is the Execution Unit (EU) as shown
in the “Functional Diagram” on page 3. FIGURE 2. 80C86 MEMORY ORGANIZATION
These units can interact directly, but for the most part perform as
TABLE 1.
separate asynchronous operational processors. The bus
interface unit provides the functions related to instruction TYPE OF DEFAULT ALTERNATE
fetching and queuing, operand fetch and store, and address MEMORY SEGMENT SEGMENT
REFERENCE BASE BASE OFFSET
relocation. This unit also provides the basic bus control. The
overlap of instruction pre-fetching provided by this unit serves to Instruction Fetch CS None IP
increase processor performance through improved bus Stack Operation SS None SP
bandwidth utilization. Up to six bytes of the instruction stream
Variable (except DS CS, ES, SS Effective
can be queued while waiting for decoding and execution.
following) Address
The instruction stream queuing mechanism allows the BIU to String Source DS CS, ES, SS SI
keep the memory used very efficiently. Whenever there is
space for at least two bytes in the queue, the BlU attempts a String Destination ES None DI
word fetch memory cycle. This greatly reduces “dead time” on BP Used as Base SS CS, DS, ES Effective
the memory bus. The queue acts as a First-In-First-Out (FIFO) Register Address
buffer, from which the EU extracts instruction bytes as
required. If the queue is empty (following a branch instruction, All memory references are made relative to base addresses
for example), the first byte into the queue immediately contained in high speed segment registers. The segment types
becomes available to the EU. were chosen based on the addressing needs of programs. The
segment register to be selected is automatically chosen
The execution unit receives pre-fetched instructions from the BlU according to the specific rules of Table 1. All information in one
queue and provides un-relocated operand addresses to the BlU. segment type share the same logical attributes (that is, code or
Memory operands are passed through the BIU for processing by data). By structuring memory into re-locatable areas of similar
the EU, which passes results to the BIU for storage. characteristics and by automatically selecting segment
registers, programs are shorter, faster, and more structured
(see Table 1).
FN2957 Rev 5.00 Page 8 of 39

Jul 13, 2018
80C86
Word (16-bit) operands can be located on even or odd address the MN/MX pin is strapped to GND, the 80C86 defines pins 24
boundaries and thus, are not constrained to even boundaries through 31 and 34 in maximum mode. When the MN/MX pin is
as is the case in many 16-bit computers. For address and data strapped to VCC, the 80C86 generates bus control signals itself
operands, the least significant byte of the word is stored in the on pins 24 through 31 and 34.
lower valued address location and the most significant byte in
The minimum mode 80C86 can be used with either a
the next higher address location. The BIU automatically
multiplexed or demultiplexed bus. This architecture provides
performs the proper number of memory accesses; one, if the
the 80C86 processing power in a highly integrated form.
word operand is on an even byte boundary and two, if it is on
an odd byte boundary. Except for the performance penalty, this The demultiplexed mode requires two 82C82 latches (for 64k
double access is transparent to the software. The performance addressability) or three 82C82 latches (for a full megabyte of
penalty does not occur for instruction fetches; only word addressing). An 82C86 or 82C87 transceiver can also be used if
operands. data bus buffering is required (see Figure Figure 7A on
page 16.) The 80C86 provides DEN and DT/R to control the
Physically, the memory is organized as a high bank (D15-D8)
transceiver, and ALE to latch the addresses. This configuration
and a low bank (D7-D0) of 512k bytes addressed in parallel by
of the minimum mode provides the standard demultiplexed bus
the processor’s address lines.
structure with heavy bus buffering and relaxed bus timing
Byte data with even addresses is transferred on the D7-D0 bus requirements.
lines, while odd addressed byte data (A0 HIGH) is transferred
The maximum mode employs the 82C88 bus controller (see
on the D15-D8 bus lines. The processor provides two enable
Figure 7B on page 16). The 82C88 decodes status lines S0,
signals, BHE and A0, to selectively allow reading from or
S1, and S2, and provides the system with all bus control
writing into either an odd byte location, even byte location, or
signals.
both. The instruction stream is fetched from memory as words
and is addressed internally by the processor at the byte level Moving the bus control to the 82C88 provides better source
as necessary. and sink current capability to the control lines, and frees the
80C86 pins for extended large system features. Hardware
In referencing word data, the BlU requires one or two memory
lock, queue status, and two request/grant interfaces are
cycles depending on whether the starting byte of the word is on
provided by the 80C86 in maximum mode. These features
an even or odd address, respectively. Consequently, in
allow coprocessors in local bus and remote bus configurations.
referencing word operands performance can be optimized by
locating data on even address boundaries. This is an especially Bus Operation
useful technique for using the stack, because odd address The 80C86 has a combined address and data bus commonly
references to the stack may adversely affect the context referred to as a time multiplexed bus. This technique provides
switching time for interrupt processing or task multiplexing. the most efficient use of pins on the processor while permitting
Certain locations in memory are reserved for specific CPU the use of a standard 40 Ld package. This “local bus” can be
operations (see Figure 3 on page 11). Locations from address buffered directly and used throughout the system with address
FFFF0H through FFFFFH are reserved for operations including latching provided on memory and I/O modules. In addition, the
a jump to the initial program loading routine. Following RESET, bus can also be demultiplexed at the processor with a single
the CPU always begins execution at location FFFF0H where the set of 82C82 address latches if a standard non-multiplexed bus
jump must be located. Locations 00000H through 003FFH are is desired for the system.
reserved for interrupt operations. Each of the 256 possible Each processor bus cycle consists of at least 4 CLK cycles.
interrupt service routines is accessed through its own pair of These are referred to as t1, t2, t3, and t4 (see Figure 4 on
16-bit pointers (segment address pointer and offset address page 12). The address is emitted from the processor during t1
pointer). The first pointer, used as the offset address, is loaded and data transfer occurs on the bus during t3 and t4. t2 is used
into the lP and the second pointer, which designates the base primarily for changing the direction of the bus during read
address is loaded into the CS. At this point, program control is operations. In the event that a “NOT READY” indication is
transferred to the interrupt routine. The pointer elements are given by the addressed device, “Wait” states (tW) are inserted
assumed to have been stored at the respective places in between t3 and t4. Each inserted wait state is the same
reserved memory prior to occurrence of interrupts. duration as a CLK cycle. Periods can occur between 80C86
Minimum and Maximum Operation Modes driven bus cycles. These are referred to as idle” states (TI) or
inactive CLK cycles. The processor uses these cycles for
The requirements for supporting minimum and maximum 80C86
internal housekeeping and processing.
systems are sufficiently different that they cannot be met
efficiently using 40 uniquely defined pins. Consequently, the During t1 of any bus cycle, the ALE (Address Latch Enable)
80C86 is equipped with a strap pin (MN/MX) which defines the signal is emitted (by either the processor or the 82C88 bus
system configuration. The definition of a certain subset of the controller, depending on the MN/MX strap). At the trailing edge
pins changes, dependent on the condition of the strap pin. When of this pulse, a valid address and certain status information for
the cycle can be latched.
FN2957 Rev 5.00 Page 9 of 39

Jul 13, 2018
80C86
Status bits S0, S1, and S2 are used by the bus controller, in I/O Addressing
maximum mode, to identify the type of bus transaction In the 80C86, I/O operations can address up to a maximum of
according to Table 2. 64k I/O byte registers or 32k I/O word registers. The I/O
TABLE 2.
address appears in the same format as the memory address
on bus lines A15-A0. The address lines A19-A16 are zero in
S2 S1 S0 CHARACTERISTICS I/O operations. The variable I/O instructions which use register
0 0 0 Interrupt DX as a pointer have full address capability while the direct I/O
instructions directly address one or two of the 256 I/O byte
0 0 1 Read I/O
locations in page 0 of the I/O address space.
0 1 0 Write I/O
I/O ports are addressed in the same manner as memory
0 1 1 Halt
locations. Even addressed bytes are transferred on the D7-D0
1 0 0 Instruction Fetch bus lines and odd addressed bytes on D15-D8. Care must be
1 0 1 Read Data from Memory taken to ensure that each register within an 8-bit peripheral
located on the lower portion of the bus be addressed as even.
1 1 0 Write Data to Memory
1 1 1 Passive (No Bus Cycle)
Status bits S3 through S7 are time multiplexed with high order

address bits and the BHE signal, and are therefore valid during
t2 through t4. S3 and S4 indicate which segment register (see
“Instruction Set Summary” on page 31) was used for this bus
cycle in forming the address, according to Table 3.
S5 is a reflection of the PSW interrupt enable bit. S3 is always

zero and S7 is a spare status bit.
TABLE 3.
S4 S3 CHARACTERISTICS
0 0 Alternate Data (Extra Segment)

0 1 Stack
1 0 Code or None
1 1 Data
FN2957 Rev 5.00 Page 10 of 39

Jul 13, 2018
80C86
FFFFFH RESET BOOTSTRAP

FFFF0H PROGRAM JUMP
3FFH TYPE 225 POINTER

3FCH (AVAILABLE)
AVAILABLE
INTERRUPT
POINTERS
(224)
TYPE 33 POINTER
084H (AVAILABLE)
TYPE 32 POINTER
080H (AVAILABLE)
TYPE 31 POINTER
07FH (AVAILABLE)
RESERVED
INTERRUPT
POINTERS
(27)
TYPE 5 POINTER
014H (RESERVED)
TYPE 4 POINTER
010H OVERFLOW
TYPE 3 POINTER
00CH 1 BYTE INT INSTRUCTION
DEDICATED TYPE 2 POINTER
INTERRUPT NON MASKABLE
008H
POINTERS
(5) TYPE 1 POINTER
004H SINGLE STEP
TYPE 0 POINTER CS BASE ADDRESS
000H DIVIDE ERROR IP OFFSET
16 BITS
FIGURE 3. RESERVED MEMORY LOCATIONS
FN2957 Rev 5.00 Page 11 of 39

Jul 13, 2018
80C86
(4 + NWAIT) = TCY (4 + NWAIT) = TCY

t1 t2 t3 tWAIT t4 t1 t2 t3 tWAIT t4
CLK
GOES INACTIVE IN THE STATE

JUST PRIOR TO t4
ALE
S2-S0
ADDR/ BHE, S7-S3 BHE S7-S3

STATUS A19-A16 A19-A16
BUS RESERVED
FOR DATA IN
D15-D0
ADDR/DATA A15-A0 A15-A0 DATA OUT (D15-D0)
VALID
RD, INTA
READY READY
READY
WAIT WAIT
DT/R
DEN
MEMORY ACCESS TIME
WR
FIGURE 4. BASIC SYSTEM TIMING
External Interface location FFFF0H (see Figure 3 on page 11). The RESET input is
internally synchronized to the processor clock. At initialization,
Processor RESET and Initialization the HIGH-to-LOW transition of RESET must occur no sooner
Processor initialization or start-up is accomplished with than 50µs (or four CLK cycles, whichever is greater) after
activation (HIGH) of the RESET pin. The 80C86 RESET is power-up, to allow complete initialization of the 80C86.
required to be HIGH for greater than four CLK cycles. The
NMl is not recognized prior to the second CLK cycle following
80C86 terminates operations on the high-going edge of RESET
the end of RESET. If NMl is asserted sooner than nine clock
and remains dormant as long as RESET is HIGH. The low-going
cycles after the end of RESET, the processor may execute one
transition of RESET triggers an internal reset sequence for
instruction before responding to the interrupt.
approximately seven CLK cycles. After this interval, the 80C86
operates normally beginning with the instruction in absolute
FN2957 Rev 5.00 Page 12 of 39

Jul 13, 2018
80C86
Bus Hold Circuitry the lNTA sequence. These are restored upon execution of an
To avoid high current conditions caused by floating inputs to Interrupt Return (IRET) instruction.
CMOS devices and to eliminate need for pull-up/down resistors, Non-Maskable Interrupt (NMI)
“bus-hold” circuitry has been used on the 80C86 pins 2-16,
The processor provides a single non-maskable interrupt pin
26-32, and 34-39 (see Figures 5A and 5B). These circuits
(NMI) which has higher priority than the maskable interrupt
maintain the last valid logic state if no driving source is present
request pin (INTR). A typical use would be to activate a power
(for example, an unconnected pin or a driving source which
failure routine. The NMI is edge-triggered on a LOW-to-HIGH
goes to a high impedance state). To overdrive the “bus hold”
transition. The activation of this pin causes a Type 2 interrupt.
circuits, an external driver must be capable of supplying
approximately 400µA minimum sink or source current at valid NMl is required to have a duration in the HIGH state of greater
input voltage levels. Because this “bus hold” circuitry is active than two CLK cycles, but is not required to be synchronized to
and not a “resistive” type element, the associated power supply the clock. Any positive transition of NMI is latched on-chip and
current is negligible and power dissipation is significantly is serviced at the end of the current instruction or between
reduced when compared to the use of passive pull-up resistors. whole moves of a block-type instruction. Worst case response
to NMI would be for multiply, divide, and variable shift
instructions. There is no specification on the occurrence of the
BOND
PAD low-going edge; it may occur before, during or after the
EXTERNAL
OUTPUT PIN servicing of NMI. Another positive edge triggers another
DRIVER response if it occurs after the start of the NMI procedure. The
signal must be free of logical spikes in general and be free of
INPUT
BUFFER bounces on the low-going edge to avoid triggering extraneous
INPUT
PROTECTION
responses.
CIRCUITRY
Maskable Interrupt (INTR)
FIGURE 5A. BUS HOLD CIRCUITRY PINS 2-16, 34-39 The 80C86 provides a single interrupt request input (lNTR)
which can be masked internally by software with the resetting
of the interrupt enable flag (IF) status bit. The interrupt request
BOND signal is level triggered. It is internally synchronized during
PAD EXTERNAL
VCC P PIN each clock cycle on the high-going edge of CLK. To be
OUTPUT
DRIVER responded to, lNTR must be present (HIGH) during the clock
period preceding the end of the current instruction or the end of
INPUT a whole move for a block type instruction. lNTR can be
BUFFER
INPUT removed anytime after the falling edge of the first INTA signal.
PROTECTION
CIRCUITRY During the interrupt response sequence further interrupts are
disabled. The enable bit is reset as part of the response to any
FIGURE 5B. BUS HOLD CIRCUITRY PINS 26-32
interrupt (lNTR, NMI, software interrupt or single-step),
FIGURE 5. INTERNAL BUS HOLD DEVICES
although the FLAGS register which is automatically pushed
onto the stack reflects the state of the processor prior to the
Interrupt Operations interrupt. Until the old FLAGS register is restored, the enable
Interrupt operations fall into two classes: software or hardware bit is zero unless specifically set by an instruction.
initiated. The software initiated interrupts and software aspects During the response sequence (see Figure 6 on page 14) the
of hardware interrupts are specified in the “Instruction Set processor executes two successive (back-to-back) interrupt
Summary” on page 31. Hardware interrupts can be classified acknowledge cycles. The 80C86 emits the LOCK signal (Max
as non-maskable or maskable. mode only) from t2 of the first bus cycle until t2 of the second. A
local bus “hold” request is not honored until the end of the second
Interrupts result in a transfer of control to a new program
bus cycle. In the second bus cycle, a byte is supplied to the
location. A 256-element table containing address pointers to
80C86 by the 82C59A Interrupt Controller, which identifies the
the interrupt service program locations resides in absolute
source (type) of the interrupt. This byte is multiplied by 4 and used
locations 0 through 3FFH, which are reserved for this purpose.
as a pointer into the interrupt vector lookup table. An INTR signal
Each element in the table is 4 bytes in size and corresponds to
left HIGH is continually responded to within the limitations of the
an interrupt “type”. An interrupting device supplies an 8-bit type
enable bit and sample period. The INTERRUPT RETURN
number during the interrupt acknowledge sequence, which is
instruction includes a FLAGS pop which returns the status of
used to “vector” through the appropriate element to the new
the original interrupt enable bit when it restores the FLAGS.
interrupt service program location. All flags and both the Code
Segment and Instruction Pointer register are saved as part of
FN2957 Rev 5.00 Page 13 of 39

Jul 13, 2018
80C86
when it regains control of the bus. The WAIT instruction is then

.
t1 t2 t3 t4 TI t1 t2 t3 t4 refetched, and re-executed.

ALE TABLE 4. 80C86 REGISTER
AX AH AL ACCUMULATOR
LOCK
BX BH BL BASE
CX CH CL COUNT
INTA DX DH DL DATA
AD0- FLOAT TYPE SP STACK POINTER

AD15 VECTOR
BP BASE POINTER
SI SOURCE INDEX
FIGURE 6. INTERRUPT ACKNOWLEDGE SEQUENCE
DI DESTINATION INDEX
Halt
When a software “HALT” instruction is executed, the processor IP INSTRUCTION POINTER
indicates that it is entering the “HALT” state in one of two ways FLAGSH FLAGSL STATUS FLAG
depending upon which mode is strapped. In minimum mode,
the processor issues one ALE with no qualifying bus control CS CODE SEGMENT
signals. In maximum mode the processor issues appropriate DS DATA SEGMENT
HALT status on S2, S1, S0, and the 82C88 bus controller SS STACK SEGMENT
issues one ALE. The 80C86 does not leave the “HALT” state ES EXTRA SEGMENT
when a local bus “hold” is entered while in “HALT”. In this case,
the processor reissues the HALT indicator at the end of the
Basic System Timing
local bus hold. An NMI or interrupt request (when interrupts
enabled) or RESET, forces the 80C86 out of the “HALT” state. Typical system configurations for the processor operating in
minimum mode and in maximum mode are shown in
Read/Modify/Write (Semaphore) Figures 7A and 7B on page 16, respectively. In minimum
mode, the MN/MX pin is strapped to VCC and the processor
Operations Using Lock emits bus control signals (that is, RD, WR, etc.) directly. In
The LOCK status information is provided by the processor when maximum mode, the MN/MX pin is strapped to GND and the
consecutive bus cycles are required during the execution of an processor emits coded status information which the 82C88 bus
instruction. This gives the processor the capability of performing controller uses to generate MULTIBUS compatible bus control
read/modify/write operations on memory (using the Exchange signals. Figure 4 on page 12 shows the signal timing
Register With Memory instruction, for example) without another relationships.
system bus master receiving intervening memory cycles. This is
System Timing - Minimum System
useful in multiprocessor system configurations to accomplish “test
and set lock” operations. The LOCK signal is activated (forced The read cycle begins in t1 with the assertion of the Address
LOW) in the clock cycle following decoding of the software Latch Enable (ALE) signal. The trailing (low-going) edge of this
“LOCK” prefix instruction. It is deactivated at the end of the last signal is used to latch the address information, which is valid
bus cycle of the instruction following the “LOCK” prefix instruction. on the address/data bus (AD0-AD15) at this time, into the
While LOCK is active a request on a RQ/GT pin is recorded and 82C82/82C83 latch. The BHE and A0 signals address the low,
then honored at the end of the LOCK. high or both bytes. From t1 to t4 the M/lO signal indicates a
memory or I/O operation. At t2, the address is removed from
External Synchronization Using TEST the address/data bus and the bus is held at the last valid logic
As an alternative to interrupts, the 80C86 provides a single state by internal bus hold devices. The read control signal is
software-testable input pin (TEST). This input is used by also asserted at t2. The read (RD) signal causes the
executing a WAIT instruction. The single WAIT instruction is addressed device to enable its data bus drivers to the local
repeatedly executed until the TEST input goes active (LOW). bus. Some time later, valid data is available on the bus and the
The execution of WAIT does not consume bus cycles once the addressed device drives the READY line HIGH. When the
queue is full. processor returns the read signal to a HIGH level, the
addressed device again three-states its bus drivers. If a
If a local bus request occurs during WAIT execution, the 80C86
transceiver (82C86/82C87) is required to buffer the 80C86
three-states all output drivers while inputs and I/O pins are held
local bus, signals DT/R and DEN are provided by the 80C86.
at valid logic levels by internal bus-hold circuits. If interrupts are
enabled, the 80C86 recognizes interrupts and processes them A write cycle also begins with the assertion of ALE and the
emission of the address. The M/IO signal is again asserted to
FN2957 Rev 5.00 Page 14 of 39

Jul 13, 2018
80C86
indicate a memory or I/O write operation. In t2, immediately Bus Timing - Medium Size Systems
following the address emission, the processor emits the data to For medium complexity systems the MN/MX pin is connected
be written into the addressed location. This data remains valid to GND and the 82C88 Bus Controller is added to the system
until at least the middle of t4. During t2, t3, and tW, the as well as an 82C82/82C83 latch for latching the system
processor asserts the write control signal. The write (WR) address, and an 82C86/82C87 transceiver to allow for bus
signal becomes active at the beginning of t2 as opposed to the loading greater than the 80C86 is capable of handling. Signals
read which is delayed somewhat into t2 to provide time for ALE, DEN, and DT/R are generated by the 82C88 instead of
output drivers to become inactive. the processor in this configuration, although their timing
The BHE and A0 signals are used to select the proper byte(s) remains relatively the same. The 80C86 status outputs (S2, S1
of the memory/lO word to be read or written according to and S0) provide type-of-cycle information and become 82C88
Table 5. inputs. This bus cycle information specifies read (code, data or
I/O), write (data or I/O), interrupt acknowledge, or software
TABLE 5. halt. The 82C88 issues control signals specifying memory read
BHE A0 CHARACTERISTICS or write, I/O read or write, or interrupt acknowledge. The
0 0 Whole word
82C88 provides two types of write strobes, normal and
advanced, to be applied as required. The normal write strobes
0 1 Upper Byte From/To Odd Address have data valid at the leading edge of write. The advanced
1 0 Lower Byte From/To Even Address write strobes have the same timing as read strobes, and
1 1 None
hence, data is not valid at the leading edge of write. The
82C86/82C87 transceiver receives the usual T and OE inputs
from the 82C88 DT/R and DEN signals.
I/O ports are addressed in the same manner as memory
location. Even addressed bytes are transferred on the D7-D0 The pointer into the interrupt vector table, which is passed
bus lines and odd address bytes on D15-D8. during the second INTA cycle, can be derived from an 82C59A
located on either the local bus or the system bus. If the master
The basic difference between the interrupt acknowledge cycle
82C59A Priority Interrupt Controller is positioned on the local
and a read cycle is that the interrupt acknowledge signal
bus, the 82C86/82C87 transceiver must be disabled when
(INTA) is asserted in place of the read (RD) signal and the
reading from the master 82C59A during the interrupt
address bus is held at the last valid logic state by internal bus
acknowledge sequence and software “poll”.
hold devices (see Figure 5 on page 13). In the second of two
successive INTA cycles a byte of information is read from the
data bus (D7-D0) as supplied by the interrupt system logic
(such as, 82C59A Priority Interrupt Controller). This byte
identifies the source (type) of the interrupt. It is multiplied by 4
and used as a pointer into an interrupt vector lookup table, as
described earlier.
FN2957 Rev 5.00 Page 15 of 39

Jul 13, 2018
80C86
VCC
MN/MX VCC
M/IO
82C8A/85 INTA
CLOCK CLK
GENERATOR RD
READY
WR
RES RESET
RDY
DT/R
DEN
WAIT ALE
GND STATE
GENERATOR 80C86
CPU STB
GND OE
GND ADDR
AD0-AD15
1 A16-A19 ADDR/DATA 82C82
VCC C1 LATCH
BHE 2 OR 3
GND
20
C2
T
VCC
40 OE
82C86 DATA
C1 = C2 = 0.1µF
TRANSCEIVER A0
(2) BHE
OPTIONAL EH EL W G E G CS RD WR
FOR INCREASED HM-6516 HM-6616 CMOS
DATA BUS DRIVE CMOS RAM CMOS PROM (2) 82CXX
2k x 8 2k x 8 2k x 8 2k x 8 PERIPHERALS
FIGURE 7A. MINIMUM MODE 80C86 TYPICAL CONFIGURATION
VCC
MN/MX GND CLK MRDC

82C84A/85 CLK S0 MWTC
S0
CLOCK 82C88
GENERATOR/ READY S1 S1 BUS AMWC NC
RES RESET S2 S2 CTRLR IORC
RDY DEN IOWC
80C86 DT/R AIOWC NC
CPU
ALE INTA
WAIT LOCK NC
GND STATE
GENERATOR
STB
GND OE
GND ADDR
AD0-AD15
1 A16-A19 ADDR/DATA 82C82
VCC C1 (2 OR 3)
BHE
GND
20
C2
T
VCC
40 OE DATA
82C86
C1 = C2 = 0.1µF TRANSCEIVER A0
(2) BHE
EH EL W G E G CS RDWR
HM-65162 HM-6616 CMOS
CMOS RAM CMOS PROM (2) 82CXX
2k x 8 2k x 8 2k x 8 2k x 8 PERIPHERALS
FIGURE 7B. MAXIMUM MODE 80C86 TYPICAL CONFIGURATION
FN2957 Rev 5.00 Page 16 of 39

Jul 13, 2018
80C86
Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Thermal Resistance (Typical) JA (oC/W) JC (oC/W)
Input, Output or I/O Voltage . . . . . . . . . . . . . . GND -0.5V to VCC +0.5V PDIP Package* (Note 1) . . . . . . . . . . . 50 N/A
Gate Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9750 Gates CERDIP Package (Notes 1, 2) . . . . . . 30 6
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Storage Temperature Range . . . . . . . . . . . . . . . . . . -65°C to +150°C
Junction Temperature
Operating Conditions Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Operating Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
M80C86-2 ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see TB493
Temperature Range
*Pb-free PDIPs can be used for through hole wave solder processing
C80C86-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
M80C86-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See
TB379.
2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
DC Electrical Specifications
VCC = 5.0V, ±10%; TA = 0°C to +70°C (C80C86, C80C86-2)
VCC = 5.0V, ±10%; TA = -55°C to +125°C (M80C86)
VCC = 5.0V, ±5%; TA = -55°C to +125°C (M80C86-2). Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested.
SYMBOL PARAMETER TEST CONDITION MIN MAX UNIT
VlH Logical One C80C86 (Note 6) 2.0 V
Input Voltage M80C86 (Note 6) 2.2 V

VIL Logical Zero Input Voltage 0.8 V
VIHC CLK Logical One Input Voltage VCC - 0.8 V
VILC CLK Logical Zero Input Voltage 0.8 V

VOH Output High Voltage lOH = -2.5mA 3.0 V
lOH = -100µA VCC - 0.4 V
VOL Output Low Voltage lOL = +2.5mA 0.4 V

II Input Leakage Current VIN = GND or VCC DIP -1.0 1.0 µA
Pins 17-19, 21-23, 33
lBHH Input Current-Bus Hold High VIN = - 3.0V (Note 3) -40 -400 µA
lBHL Input Current-Bus Hold Low VIN = - 0.8V (Note 4) 40 400 µA
IO Output Leakage Current VOUT = GND (Note 6) - -10.0 µA
ICCSB Standby Power Supply Current VCC = - 5.5V (Note 5) - 500 µA
ICCOP Operating Power Supply Current FREQ = Max, VIN = VCC or GND, - 10 mA/MHz
Outputs Open (Note 7)
FN2957 Rev 5.00 Page 17 of 39

Jul 13, 2018
80C86
Capacitance TA = +25°C
SYMBOL PARAMETER TEST CONDITIONS TYPICAL UNIT
CIN Input Capacitance FREQ = 1MHz. All measurements are referenced to device GND 25 pF
COUT Output Capacitance FREQ = 1MHz. All measurements are referenced to device GND 25 pF
CI/O I/O Capacitance FREQ = 1MHz. All measurements are referenced to device GND 25 pF
NOTES:
3. lBHH should be measured after raising VIN to VCC and then lowering to 3.0V on the following pins 2-16, 26-32, 34-39.
4. IBHL should be measured after lowering VIN to GND and then raising to 0.8V on the following pins: 2-16, 34-39.
5. lCCSB tested during clock high time after halt instruction executed. VIN = VCC or GND, VCC = 5.5V, Outputs unloaded.
6. IO should be measured by putting the pin in a high impedance state and then driving VOUT to GND on the following pins: 26-29 and 32.
7. MN/MX is a strap option and should be held to VCC or GND.
AC Electrical Specifications – Minimum Complexity System

VCC = 5.0V ±10%; TA = 0°C to +70°C (C80C86, C80C86-2)
VCC = 5.0V ±100%; TA = -55°C to +125°C (M80C86)
VCC = 5.0V ±5%; TA = -55°C to +125°C (M80C86-2). Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
80C86 80C86-2
TEST
SYMBOL PARAMETER CONDITIONS MIN MAX MIN MAX UNIT
MINIMUM COMPLEXITY SYSTEM
Timing Requirements
(1) TCLCL Cycle Period 200 125 ns
(2) TCLCH CLK Low Time 118 68 ns
(3) TCHCL CLK High Time 69 44 ns
(4) TCH1CH2 CLK Rise Time From 1.0V to 3.5V 10 10 ns
(5) TCL2C1 CLK FaIl Time From 3.5V to 1.0V 10 10 ns
(6) TDVCL Data In Setup Time 30 20 ns
(7) TCLDX1 Data In Hold Time 10 10 ns
(8) TR1VCL RDY Setup Time into 82C84A 35 35 ns

(Notes 8, 9)
(9) TCLR1X RDY Hold Time into 82C84A (Notes 8, 9) 0 0 ns
(10) TRYHCH READY Setup Time into 80C86 118 68 ns
(11) TCHRYX READY Hold Time into 80C86 30 20 ns
(12) TRYLCL READY Inactive to CLK (Note 10) -8 -8 ns
(13) THVCH HOLD Setup Time 35 20 ns
(14) TINVCH lNTR, NMI, TEST Setup Time (Note 9) 30 15 ns
(15) TILIH Input Rise Time (Except CLK) From 0.8V to 2.0V 15 15 ns
(16) TIHIL Input FaIl Time (Except CLK) From 2.0V to 0.8V 15 15 ns
Timing Responses
(17) TCLAV Address Valid Delay CL = 100pF 10 110 10 60 ns
(18) TCLAX Address Hold Time CL = 100pF 10 10 ns
(19) TCLAZ Address Float Delay CL = 100pF TCLAX 80 TCLAX 50 ns

(20) TCHSZ Status Float Delay CL = 100pF 80 50 ns
(21) TCHSV Status Active Delay CL = 100pF 10 110 10 60 ns
(22) TLHLL ALE Width CL = 100pF TCLCH - 20 TCLCH - 10 ns
FN2957 Rev 5.00 Page 18 of 39

Jul 13, 2018
80C86
AC Electrical Specifications – Minimum Complexity System

VCC = 5.0V ±10%; TA = 0°C to +70°C (C80C86, C80C86-2)
VCC = 5.0V ±100%; TA = -55°C to +125°C (M80C86)
Temperature limits established by characterization and are not production tested. (Continued)
80C86 80C86-2
TEST
SYMBOL PARAMETER CONDITIONS MIN MAX MIN MAX UNIT
(23) TCLLH ALE Active Delay CL = 100pF 80 50 ns
(24) TCHLL ALE Inactive Delay CL = 100pF 85 55 ns
(25) TLLAX Address Hold Time to ALE Inactive CL = 100pF TCHCL - 10 TCHCL - 10 ns
(26) TCLDV Data Valid Delay CL = 100pF 10 110 10 60 ns
(27) TCLDX2 Data Hold Time CL = 100pF 10 10 ns
(28) TWHDX Data Hold Time After WR CL = 100pF TCLCL - 30 TCLCL - 30 ns
(29) TCVCTV Control Active Delay 1 CL = 100pF 10 110 10 70 ns
(30) TCHCTV Control Active Delay 2 CL = 100pF 10 110 10 60 ns

(31) TCVCTX Control Inactive Delay CL = 100pF 10 110 10 70 ns
(32) TAZRL Address Float to READ Active CL = 100pF 0 0 ns
(33) TCLRL RD Active Delay CL = 100pF 10 165 10 100 ns
(34) TCLRH RD Inactive Delay CL = 100pF 10 150 10 80 ns

(35) TRHAV RD Inactive to Next Address Active CL = 100pF TCLCL - 45 TCLCL - 40 ns
(36) TCLHAV HLDA Valid Delay CL = 100pF 10 160 10 100 ns
(37) TRLRH RD Width CL = 100pF 2TCLCL - 75 2TCLCL - 50 ns

(38) TWLWH WR Width CL = 100pF 2TCLCL - 60 2TCLCL - 40 ns
(39) TAVAL Address Valid to ALE Low CL = 100pF TCLCH - 60 TCLCH - 40 ns
(40) TOLOH Output Rise Time From 0.8V to 2.0V 20 15 ns

(41) TOHOL Output Fall Time From 2.0V to 0.8V 20 15 ns
NOTES:
8. Signal at 82C84A shown for reference only.
9. Setup requirement for asynchronous signal only to ensure recognition at next CLK.
10. Applies only to t2 state (8ns into t3).
FN2957 Rev 5.00 Page 19 of 39

Jul 13, 2018
80C86
Waveforms
t1 t2 t3 t4
(5) tW
(1)
TCLCL TCL2CL1
TCH1CH2
CLK (82C84A OUTPUT) (4)
(3) (2)
TCHCL TCLCH TCHCTV
(30) TCHCTV (30)
M/IO
(17) (26) TCLDV (17)

TCLAV (18) TCLAX TCLAV
BHE/S7, A19/S6-A16/S3 BHE, A19-A16 S7-S3
(23) TCLLH TLHLL

(22) TLLAX
(25)
ALE
(24)
TCHLL TR1VCL (8)
RDY (82C84A INPUT) VIH
TAVAL
(See Note 11) (39)
VIL
TCLR1X (9)
(12)
TRYLCL
(11)
READY (80C86 INPUT)
TCHRYX
(10)
TRYHCH (7)
(19) (16) TCLDX1
TCLAZ TDVCL
AD15-AD0 AD15-AD0 DATA IN
(32) TAZRL (34) TCLRH TRHAV (35)
RD
READ CYCLE (30) (30)
TRLRH TCHCTV
(WR, INTA = VOH) TCHCTV TCLRL (37)
(33)
DT/R
(29) TCVCTV TCVCTX

(31)
DEN
FIGURE 8A. BUS TIMING - MINIMUM MODE SYSTEM
NOTE:
11. Signals at 82C84A are shown for reference only. RDY is sampled near the end of t2, t3, tW to determine if TW machine states are to be inserted.
FN2957 Rev 5.00 Page 20 of 39

Jul 13, 2018
80C86
Waveforms (Continued)
t1 t2 t3 tW t4
(4) (5)
TCH1CH2 TCL2CL1
CLK (82C84A OUTPUT) TW
(26) (27)
(17) TCLDV TCLDX2
TCLAV TCLAX (18)
AD15-AD0 AD15-AD0 DATA OUT
TWHDX (28)
TCVCTV (29) (31) TCVCTX
WRITE CYCLE
(RD, INTA, DEN
DT/R = VOH)
(29) TCVCTV (38)
TWLWH
WR
TCVCTX (31)
(19)
TCLAZ TDVCL (6)
TCLDX1 (7)
AD15-AD0 POINTER
TCHCTV (30)
TCHCTV
(30)
DT/R
INTA CYCLE
(See Note 12) (29) TCVCTV
(RD, WR = VOH
BHE = VOL) INTA
TCVCTX
(29) TCVCTV
(31)
DEN
SOFTWARE HALT -
AD15-AD0 INVALID ADDRESS SOFTWARE HALT
DEN, RD,
WR, INTA = VOH TCLAV
(17)
DT/R = INDETERMINATE
FIGURE 8B. BUS TIMING - MINIMUM MODE SYSTEM
NOTE:
12. Two INTA cycles run back-to-back. The 80C86 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown for the
second INTA cycle.
FN2957 Rev 5.00 Page 21 of 39

Jul 13, 2018
80C86
AC Electrical Specifications – Maximum Mode System

VCC = 5.0V ±10% TA = 0°C to +70°C (C80C86, C80C86-2)
VCC = 5.0V ±10%; TA = -55°C to +125°C (M80C86)
TIMING REQUIREMENTS 80C86 80C86-2
SYMBOL PARAMETER TEST CONDITIONS MIN MAX MIN MAX UNIT

MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
Timing Requirements
(1) TCLCL CLK Cycle Period 200 125 ns
(2) TCLCH CLK Low Time 118 68 ns
(3) TCHCL CLK High Time 69 44 ns
(4) TCH1CH2 CLK Rise Time From 1.0V to 3.5V 10 10 ns

(5) TCL2CL1 CLK Fall Time From 3.5V to 1.0V 10 10 ns
(6) TDVCL Data in Setup Time 30 20 ns
(7) TCLDX1 Data In Hold Time 10 10 ns
(8) TR1VCL RDY Setup Time into 82C84A 35 35 ns

(Notes 13, 14)
(9) TCLR1X RDY Hold Time into 82C84A 0 0 ns

(Notes 13, 14)
(10) TRYHCH READY Setup Time into 80C86 118 68 ns
(11) TCHRYX READY Hold Time into 80C86 30 20 ns
(12) TRYLCL READY Inactive to CLK (Note 15) -8 -8 ns

(13) TlNVCH Setup Time for Recognition (lNTR, NMl, 30 15 ns
TEST) (Note 14)
(14) TGVCH RQ/GT Setup Time 30 15 ns

(15) TCHGX RQ Hold Time into 80C86 (Note 16) 40 TCHCL + 30 TCHCL + ns
10 10
(16) TILlH Input Rise Time (Except CLK) From 0.8V to 2.0V 15 15 ns
(17) TIHIL Input Fall Time (Except CLK) From 2.0V to 0.8V 15 15 ns
Timing Responses
(18) TCLML Command Active Delay (Note 13) CL = 100pF for All 5 35 5 35 ns
80C86 Outputs (In
Addition to 80C86 Self
Load)
(19) TCLMH Command Inactive (Note 13) CL = 100pF for All 5 35 5 35 ns

80C86 Outputs (In
Load)
(20) TRYHSH READY Active to Status Passive CL = 100pF for All 110 65 ns
(Notes 15, 17) 80C86 Outputs (In
Load)
(21) TCHSV Status Active Delay CL = 100pF for All 10 110 10 60 ns

80C86 Outputs (In
Load)
FN2957 Rev 5.00 Page 22 of 39

Jul 13, 2018
80C86

VCC = 5.0V ±10% TA = 0°C to +70°C (C80C86, C80C86-2)
VCC = 5.0V ±10%; TA = -55°C to +125°C (M80C86)
(22) TCLSH Status Inactive Delay (Note 17) CL = 100pF for All 10 130 10 70 ns
80C86 Outputs (In
Load)
(23) TCLAV Address Valid Delay CL = 100pF for All 10 110 10 60 ns

80C86 Outputs (In
Load)
(24) TCLAX Address Hold Time CL = 100pF for All 10 10 ns
80C86 Outputs (In
Load)
(25) TCLAZ Address Float Delay CL = 100pF for All TCLAX 80 TCLAX 50 ns
80C86 Outputs (In
Load)
(26) TCHSZ Status Float Delay CL = 100pF for All 80 50 ns

80C86 Outputs (In
Load)
(27) TSVLH Status Valid to ALE High (Note 13) CL = 100pF for All 20 20 ns
80C86 Outputs (In
Load)
(28) TSVMCH Status Valid to MCE High (Note 13) CL = 100pF for All 30 30 ns
80C86 Outputs (In
Load)
(29) TCLLH CLK low to ALE Valid (Note 13) CL = 100pF for All 20 20 ns
80C86 Outputs (In
Load)
(30) TCLMCH CLK low to MCE High (Note 13) CL = 100pF for All 25 25 ns
80C86 Outputs (In
Load)
(31) TCHLL ALE Inactive Delay (Note 13) CL = 100pF for All 4 18 4 18 ns
80C86 Outputs (In
Load)
(32) TCLMCL MCE Inactive Delay (Note 13) CL = 100pF for All 15 15 ns
80C86 Outputs (In
Load)
(33) TCLDV Data Valid Delay CL = 100pF for All 10 110 10 60 ns

80C86 Outputs (In
Load)
FN2957 Rev 5.00 Page 23 of 39

Jul 13, 2018
80C86

VCC = 5.0V ±10% TA = 0°C to +70°C (C80C86, C80C86-2)
VCC = 5.0V ±10%; TA = -55°C to +125°C (M80C86)
(34) TCLDX2 Data Hold Time CL = 100pF for All 10 10 ns

80C86 Outputs (In
Load)
(35) TCVNV Control Active Delay (Note 13) CL = 100pF for All 5 45 5 45 ns
80C86 Outputs (In
Load)
(36) TCVNX Control Inactive Delay (Note 13) CL = 100pF 10 45 10 45 ns
(37) TAZRL Address Float to Read Active CL = 100pF 0 0 ns
(38) TCLRL RD Active Delay CL = 100pF 10 165 10 100 ns

(39) TCLRH RD Inactive Delay CL = 100pF 10 150 10 80 ns
(40) TRHAV RD Inactive to Next Address Active CL = 100pF TCLCL TCLCL ns

- 45 - 40
(41) TCHDTL Direction Control Active Delay CL = 100pF 50 50 ns

(Note 13)
(42) TCHDTH Direction Control Inactive Delay CL = 100pF 30 30 ns

(Note 13)
(43) TCLGL GT Active Delay CL = 100pF 10 85 0 50 ns
(44) TCLGH GT Inactive Delay CL = 100pF 10 85 0 50 ns
(45) TRLRH RD Width CL = 100pF 2TCLCL 2TCLCL ns

- 75 - 50
(46) TOLOH Output Rise Time From 0.8V to 2.0V 20 15 ns
(47) TOHOL Output Fall Time From 2.0V to 0.8V 20 15 ns
NOTES:
13. Signal at 82C84A or 82C88 shown for reference only.
14. Setup requirement for asynchronous signal only to ensure recognition at next CLK.
15. Applies only to t2 state (8ns into t3).
16. The 80C86 actively pulls the RQ/GT pin to a logic one on the following clock low time.
17. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.
FN2957 Rev 5.00 Page 24 of 39

Jul 13, 2018
80C86
Waveforms
t1 t2 t3 t4
(4)
TCH1CH2
(1) (5)
TCLCL TCL2CL1 tW
CLK
(23)
TCLAV TCLCH
TCHCL (3)
(2)
QS0, QS1
TCLSH
(21) TCHSV (22)
S2, S1, S0 (EXCEPT HALT) (33) (See Note 20)
(23) TCLAV TCLDV TCLAV (23)

TCLAX (24)
BHE/S7, A19/S6-A16/S3 BHE, A19-A16 S7-S3

TSVLH
(27) TCHLL (31)
ALE (82C88 OUTPUT) TCLLH

(29)
(See Note 18) TR1VCL (8)
RDY (82C84 INPUT)

TCLR1X (9)
(12) TRYLCL
(11)
READY 80C86 INPUT) TCHRYX
TRYHSH
(24) (20)
TCLAX
(10)
TRYHCH
(7)
(25) (6) TCLDX1
READ CYCLE TCLAV (23) TCLAZ TDVCL
AD15-AD0 AD15-AD0 DATA IN
(37) TAZRL (39) TCLRH TRHAV (40)
RD
(42)
(41) TCHDTL TCHDTH
TRLRH
TCLRL (45)
DT/R (38)
TCLML (18) TCLMH (19)

82C88
MRDC OR IORC
OUTPUTS
(See Notes 18, 19)
(35) TCVNV
DEN
TCVNX (36)
FIGURE 9A. BUS TIMING - MAXIMUM MODE (USING 82C88)

NOTES:
18. Signals at 82C84A or 82C88 are shown for reference only. RDY is sampled near the end of t2, t3, tW to determine if TW machine states are to
be inserted.
19. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA, and DEN) lags the active high
82C88 CEN.
20. Status inactive in state just prior to t4.
FN2957 Rev 5.00 Page 25 of 39

Jul 13, 2018
80C86
t1 t2 t3 tW t4
CLK
TCHSV (21)
S2, S1, S0 (EXCEPT HALT) (See Note 23)
(23)
TCLDV (33) (22) TCLDX2 (34)
WRITE CYCLE TCLAV TCLSH
TCLAX (24)
AD15-AD0 DATA
TCVNV TCVNX (36)

(35)
DEN
TCLMH
(19)
82C88 (18) TCLML
OUTPUTS
AMWC OR AIOWC
(See Notes 21, 22)
(18)TCLML TCLMH (19)
MWTC OR IOWC
INTA CYCLE
AD15-AD0 RESERVED FOR
(See Notes 24, 25) CASCADE ADDR
(25) TCLAZ (6) TDVCL TCLDX1 (7)
AD15-AD0 POINTER
TCLMCL (32)
(28) TSVMCH
(41)
MCE/PDEN TCHDTL
(30) TCLMCH (42) TCHDTH
DT/R
82C88 OUTPUTS (18) TCLML

(See Notes 21, 22) INTA
TCVNV (19) TCLMH

(35)
DEN
TCVNX
SOFTWARE (36)
HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH
AD15-AD0 INVALID ADDRESS
TCLAV
(23)
S2
TCHSV TCLSH
(21) (22)
FIGURE 9B. BUS TIMING - MAXIMUM MODE (USING 82C88)

NOTES:
21. Signals at 82C84A or 82C86 are shown for reference only.
22. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high
82C88 CEN.
23. Status inactive in state just prior to t4.
24. Cascade address is valid between first and second INTA cycles.
25. Two INTA cycles run back-to-back. The 80C86 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is shown
for second INTA cycle.
FN2957 Rev 5.00 Page 26 of 39

Jul 13, 2018
80C86
ANY >0-CLK
CLK
CYCLE CYCLES
CLK
TCLGH (44) TGVCH (14) TCLGL TCLGH (44)

(1) (43)
TCLCL TCHGX (15) PULSE 2
80C86 GT
RQ/GT
PULSE 1 PULSE 3
COPROCESSOR COPROCESSOR
PREVIOUS GRANT RQ TCLAZ (25) RELEASE
AD15-AD0 80C86 COPROCESSOR
TCHSV (21)
TCHSZ (26) (See Note 26)
RD, LOCK
BHE/S7, A19/S0-A16/S3
S2, S1, S0
NOTE:
26. The coprocessor may not drive the busses outside the region shown without risking contention.
FIGURE 10. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
1CLK 1 OR 2
CYCLE CYCLES
CLK
THVCH (13) THVCH (13)
HOLD
TCLHAV (36) TCLHAV (36)
HLDA
TCLAZ (19)
AD15-AD0 80C86 COPROCESSOR 80C86
TCHSZ (20) TCHSV (21)

BHE/S7, A19/S6-A16/S3
RD, WR, M/IO, DT/R, DEN
FIGURE 11. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)
CLK
ANY CLK CYCLE
ANY CLK CYCLE
(13) CLK
NMI TINVCH (See Note 27)
TCLAV TCLAV
(23) (23)
INTR SIGNAL
TEST LOCK
NOTE:
27. Setup requirements for asynchronous signals only to
guarantee recognition at next CLK.
FIGURE 12. ASYNCHRONOUS SIGNAL RECOGNITION FIGURE 13. BUS LOCK SIGNAL TIMING (MAXIMUM MODE
ONLY)
FN2957 Rev 5.00 Page 27 of 39

Jul 13, 2018
80C86
50µs
VCC
CLK
(7) TCLDX1
(6) TDVCL
RESET
4 CLK CYCLES
FIGURE 14. RESET TIMING
AC Test Circuit
OUTPUT FROM TEST POINT

DEVICE UNDER TEST
CL (See Note 28)
NOTE:
28. Includes stay and jig capacitance.
AC Testing Input, Output Waveform
INPUT OUTPUT
VIH + 20% VIH
VOH
1.5V 1.5V
VOL
VIL - 50% VIL
NOTE: AC Testing: All input signals (other than CLK) must switch between VILMAX -50% VIL and VIHMIN +20% VIH. CLK must switch between 0.4V
and VCC - 0.4V. Input rise and fall times are driven at 1ns/V.
FN2957 Rev 5.00 Page 28 of 39

Jul 13, 2018
80C86
Burn-In Circuits
MD80C86 CERDIP
C
GND
GND 1 GND VCC 40 VCC
RIO RIO
GND 2 AD14 AD15 39 VCL
RIO RO
VCL 3 AD13 AD16 38 VCC/2
RIO RO
GND 4 AD12 AD17 37 VCC/2
RIO RO
GND 5 AD11 AD18 36 VCC/2
RIO RO
VCL 6 AD10 AD19 35 VCC/2
RIO RO
GND 7 AD9 BHE 34 VCC/2
RIO
GND 8 AD8 MX 33 GND
RIO RO
GND 9 AD7 RD 32 VCC/2
RIO RI
VCL 10 AD6 RQ0 31 VCL
RIO RO
VCL 11 AD5 RQ1 30 VCL
RIO RO
VCL 12 AD4 LOCK 29 VCC/2
RO
OPEN 13 AD3 S2 28 VCC/2
RO
RO
RO
OPEN 16 AD0 QS0 25 VCC/2
RO
GND 17 NMI QS2 24 VCC/2
GND 18 INTR TEST 23 GND
RC RI
F0 19 CLK READY 22 VCL
RI
GND 20 GND RESET 21 NODE A
FROM
PROGRAM
CARD
NOTES: COMPONENTS:
29. VCC = 5.5V±0.5V, GND = 0V. 1. RI = 10kΩ ±5%, 1/4W
30. Input voltage limits (except clock): 2. RO = 1.2kΩ ±5%, 1/4W
VIL (maximum) = 0.4V 3. RIO = 2.7kΩ ±5%, 1/4W
VIH (minimum) = 2.6V, VIH (clock) = (VCC - 0.4V) minimum. 4. RC = 1kΩ ±5%, 1/4W
31. VCC/2 is external supply set to 2.7V ±10%. 5. C = 0.01µF (Minimum)
32. VCL is generated on program card (VCC - 0.65V).
33. Pins 13 - 16 input sequenced instruction from internal hold devices.
34. F0 = 100kHz ±10%.
35. Node A = a 40µs pulse every 2.56ms.
FN2957 Rev 5.00 Page 29 of 39

Jul 13, 2018
80C86
Metallization Topology GLASSIVATION:

Type: SiO2
DIE DIMENSIONS:
Thickness: 8kÅ 1kÅ
249.2x290.9x19
WORST CASE CURRENT DENSITY:
METALLIZATION:
1.5 x 105 A/cm2
Type: Silicon - Aluminum
Thickness: 11kÅ 2kÅ
Metallization Mask Layout

80C86
AD11 AD12 AD13 AD14 GND VCC AD15 A16/S3 A17/S4 A18/S5
A19/S6
AD10
AD9
BHE/S7
MN/MX
AD8
AD7 RD
AD6 RQ/GT0
AD5
RQ/GT1
AD4
AD3
LOCK
S2
AD2
AD1 S1
AD0 S0
NMI INTR CLK GND RESET READY TEST QS1 QS0
FN2957 Rev 5.00 Page 30 of 39

Jul 13, 2018
80C86
Instruction Set Summary

INSTRUCTION CODE
MNEMONIC AND DESCRIPTION 76543210 76543210 76543210 76543210
DATA TRANSFER
MOV = Move:
Register/Memory to/from Register 100010dw mod reg r/m
Immediate to Register/Memory 1100011w mod 0 0 0 r/m data data if w 1
Immediate to Register 1 0 1 1 w reg data data if w 1
Memory to Accumulator 1010000w addr-low addr-high
Accumulator to Memory 1010001w addr-low addr-high
Register/Memory to Segment Register †† 10001110 mod 0 reg r/m
Segment Register to Register/Memory 10001100 mod 0 reg r/m
PUSH = Push:
Register/Memory 11111111 mod 1 1 0 r/m
Register 0 1 0 1 0 reg
Segment Register 0 0 0 reg 1 1 0
POP = Pop:
Register/Memory 10001111 mod 0 0 0 r/m
Segment Register 0 0 0 reg 1 1 1
XCHG = Exchange:
Register/Memory with Register 1000011w mod reg r/m

Register with Accumulator 1 0 0 1 0 reg
IN = Input from:
Fixed Port 1110010w port
Variable Port 1110110w
OUT = Output to:
Fixed Port 1110011w port

Variable Port 1110111w
XLAT = Translate Byte to AL 11010111
LEA = Load EA to Register2 10001101 mod reg r/m
LDS = Load Pointer to DS 11000101 mod reg r/m
LES = Load Pointer to ES 11000100 mod reg r/m
LAHF = Load AH with Flags 10011111

SAHF = Store AH into Flags 10011110
PUSHF = Push Flags 10011100
POPF = Pop Flags 10011101

ARITHMETIC
ADD = Add:
Register/Memory with Register to Either 000000dw mod reg r/m
Immediate to Register/Memory 100000sw mod 0 0 0 r/m data data if s:w = 01
Immediate to Accumulator 0000010w data data if w = 1
FN2957 Rev 5.00 Page 31 of 39

Jul 13, 2018
80C86
Instruction Set Summary (Continued)
INSTRUCTION CODE
ADC = Add with Carry:
Register/Memory with Register to Either 000100dw mod reg r/m
Immediate to Register/Memory 100000sw mod 0 1 0 r/m data data if s:w = 01
INC = Increment:
Register/Memory 1111111w mod 0 0 0 r/m
AAA = ASCll Adjust for Add 00110111

DAA = Decimal Adjust for Add 00100111
SUB = Subtract:
Register/Memory and Register to Either 001010dw mod reg r/m
Immediate from Register/Memory 100000sw mod 1 0 1 r/m data data if s:w = 01
Immediate from Accumulator 0010110w data data if w = 1
SBB = Subtract with Borrow
Immediate from Register/Memory 100000sw mod 0 1 1 r/m data data if s:w = 01
Immediate from Accumulator 0001110w data data if w = 1
DEC = Decrement:
Register/Memory 1111111w mod 0 0 1 r/m
NEG = Change Sign 1111011w mod 0 1 1 r/m
CMP = Compare:
Register/Memory and Register 001110dw mod reg r/m
Immediate with Register/Memory 100000sw mod 1 1 1 r/m data data if s:w = 01

Immediate with Accumulator 0011110w data data if w = 1
AAS = ASCll Adjust for Subtract 00111111
DAS = Decimal Adjust for Subtract 00101111

MUL = Multiply (Unsigned) 1111011w mod 1 0 0 r/m
IMUL = Integer Multiply (Signed) 1111011w mod 1 0 1 r/m
AAM = ASCll Adjust for Multiply 11010100 00001010
DlV = Divide (Unsigned) 1111011w mod 1 1 0 r/m
IDlV = Integer Divide (Signed) 1111011w mod 1 1 1 r/m
AAD = ASClI Adjust for Divide 11010101 00001010

CBW = Convert Byte to Word 10011000
CWD = Convert Word to Double Word 10011001
LOGIC
NOT = Invert 1111011w mod 0 1 0 r/m
SHL/SAL = Shift Logical/Arithmetic Left 110100vw mod 1 0 0 r/m
SHR = Shift Logical Right 110100vw mod 1 0 1 r/m
FN2957 Rev 5.00 Page 32 of 39

Jul 13, 2018
80C86
INSTRUCTION CODE
SAR = Shift Arithmetic Right 110100vw mod 1 1 1 r/m
ROL = Rotate Left 110100vw mod 0 0 0 r/m
ROR = Rotate Right 110100vw mod 0 0 1 r/m
RCL = Rotate Through Carry Flag Left 110100vw mod 0 1 0 r/m
RCR = Rotate Through Carry Right 110100vw mod 0 1 1 r/m
AND = And:
Reg./Memory and Register to Either 0010000dw mod reg r/m
Immediate to Register/Memory 1000000w mod 1 0 0 r/m data data if w = 1

TEST = And Function to Flags, No Result:
Register/Memory and Register 1000010w mod reg r/m
Immediate Data and Register/Memory 1111011w mod 0 0 0 r/m data data if w = 1
Immediate Data and Accumulator 1010100w data data if w = 1
OR = Or:
XOR = Exclusive Or:
STRING MANIPULATION
REP = Repeat 1111001z
MOVS = Move Byte/Word 1010010w

CMPS = Compare Byte/Word 1010011w
SCAS = Scan Byte/Word 1010111w
LODS = Load Byte/Word to AL/AX 1010110w

STOS = Stor Byte/Word from AL/A 1010101w
CONTROL TRANSFER
CALL = Call:
Direct Within Segment 11101000 disp-low disp-high
Indirect Within Segment 11111111 mod 0 1 0 r/m
Direct Intersegment 10011010 offset-low offset-high

seg-low seg-high
Indirect Intersegment 11111111 mod 0 1 1 r/m
JMP = Unconditional Jump:
Direct Within Segment 11101001 disp-low disp-high
Direct Within Segment-Short 11101011 disp
Indirect Within Segment 11111111 mod 1 0 0 r/m
FN2957 Rev 5.00 Page 33 of 39

Jul 13, 2018
80C86
INSTRUCTION CODE
Direct Intersegment 11101010 offset-low offset-high
seg-low seg-high
Indirect Intersegment 11111111 mod 1 0 1 r/m
RET = Return from CALL:
Within Segment 11000011
Within Seg Adding lmmed to SP 11000010 data-low data-high
Intersegment 11001011
Intersegment Adding Immediate to SP 11001010 data-low data-high

JE/JZ = Jump on Equal/Zero 01110100 disp
JL/JNGE = Jump on Less/Not Greater or Equal 01111100 disp
JLE/JNG = Jump on Less or Equal/ Not Greater 01111110 disp
JB/JNAE = Jump on Below/Not Above or Equal 01110010 disp
JBE/JNA = Jump on Below or Equal/Not Above 01110110 disp
JP/JPE = Jump on Parity/Parity Even 01111010 disp
JO = Jump on Overflow 01110000 disp
JS = Jump on Sign 01111000 disp
JNE/JNZ = Jump on Not Equal/Not Zero 01110101 disp
JNL/JGE = Jump on Not Less/Greater or Equal 01111101 disp
JNLE/JG = Jump on Not Less or Equal/Greater 01111111 disp

JNB/JAE = Jump on Not Below/Above or Equal 01110011 disp
JNBE/JA = Jump on Not Below or Equal/Above 01110111 disp
JNP/JPO = Jump on Not Par/Par Odd 01111011 disp
JNO = Jump on Not Overflow 01110001 disp
JNS = Jump on Not Sign 01111001 disp
LOOP = Loop CX Times 11100010 disp

LOOPZ/LOOPE = Loop While Zero/Equal 11100001 disp
LOOPNZ/LOOPNE = Loop While Not Zero/Equal 11100000 disp
JCXZ = Jump on CX Zero 11100011 disp
INT = Interrupt
Type Specified 11001101 type
Type 3 11001100
INTO = Interrupt on Overflow 11001110
IRET = Interrupt Return 11001111
PROCESSOR CONTROL
CLC = Clear Carry 11111000
CMC = Complement Carry 11110101
STC = Set Carry 11111001
CLD = Clear Direction 11111100
FN2957 Rev 5.00 Page 34 of 39

Jul 13, 2018
80C86
INSTRUCTION CODE
STD = Set Direction 11111101
CLl = Clear Interrupt 11111010
ST = Set Interrupt 11111011
HLT = Halt 11110100
WAIT = Wait 10011011
ESC = Escape (to External Device) 11011xxx mod x x x r/m
LOCK = Bus Lock Prefix 11110000
NOTES: if s:w = 01, 16-bits of immediate data form the operand.

AL = 8-bit accumulator if s:w. = 11, an immediate data byte is sign extended
AX = 16-bit accumulator to form the 16-bit operand.
CX = Count register if v = 0, “count” = 1; if v = 1, “count” in (CL)
DS = Data segment x = don't care
ES = Extra segment z is used for string primitives for comparison with ZF FLAG.
Above/below refers to unsigned value.
Greater = more positive; SEGMENT OVERRIDE PREFIX
Less = less positive (more negative) signed values
if d = 1, “to” reg; if d = 0, “from” reg 001 reg 11 0
if w = 1, word instruction; if w = 0, byte instruction REG is assigned according to the following table:
if mod = 11, r/m is treated as a REG field
if mod = 00, DISP = O†, disp-low and disp-high 16-BIT (w = 1) 8-BIT (w = 0) SEGMENT
are absent
if mod = 01, DISP = disp-low sign-extended 000 AX 000 AL 00 ES
16-bits, disp-high is absent 001 CX 001 CL 01 CS
if mod = 10, DISP = disp-high:disp-low
if r/m = 000, EA = (BX) + (SI) + DISP 010 DX 010 DL 10 SS
if r/m = 001, EA = (BX) + (DI) + DISP
011 BX 011 BL 11 DS
if r/m = 010, EA = (BP) + (SI) + DISP
if r/m = 011, EA = (BP) + (DI) + DISP 100 SP 100 AH 00 ES
if r/m = 100, EA = (SI) + DISP
101 BP 101 CH 00 ES
if r/m = 101, EA = (DI) + DISP
if r/m = 110, EA = (BP) + DISP † 110 SI 110 DH 00 ES
if r/m = 111, EA = (BX) + DISP
DISP follows 2nd byte of instruction (before data 111 DI 111 BH 00 ES
if required)
Instructions which reference the flag register file as a 16-bit object
† except if mod = 00 and r/m = 110,
use the symbol FLAGS to represent the file:
EA = disp-high: disp-low.
†† MOV CS, REG/MEMORY not allowed. FLAGS =
X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)
Mnemonics Intel, 1978
FN2957 Rev 5.00 Page 35 of 39

Jul 13, 2018
80C86
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE REVISION CHANGE
Jul 13, 2018 FN2957.5 Page 1 - added Related Literature

Page 30, changed GLASSIVATION:
Type: from: Nitrox to: SiO2
Thickness: from: 10kA +-2kA to: 8kA +-1kA
Removed About Intersil section.
Added Renesas disclaimer, last page.
Aug 19, 2015 FN2957.4 Added Rev History beginning with Rev 4
Added About Intersil Verbiage.
Updated Ordering Information Table on page 1.
FN2957 Rev 5.00 Page 36 of 39

Jul 13, 2018
80C86
Dual-In-Line Plastic Packages (PDIP) For the most recent package outline drawing, see E40.6.
E40.6 (JEDEC MS-011-AC ISSUE B)

N 40 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX INCHES MILLIMETERS
AREA 1 2 3 N/2
SYMBOL MIN MAX MIN MAX NOTES
-B-
A - 0.250 - 6.35 4
-A-
D E A1 0.015 - 0.39 - 4
BASE A2 0.125 0.195 3.18 4.95 -
PLANE A2
-C- A B 0.014 0.022 0.356 0.558 -
SEATING
PLANE L C
L
B1 0.030 0.070 0.77 1.77 8
D1 A1 eA C 0.008 0.015 0.204 0.381 -
D1
B1 e D 1.980 2.095 50.3 53.2 5
eC C
B
eB D1 0.005 - 0.13 - 5
0.010 (0.25) M C A B S
E 0.600 0.625 15.24 15.87 6
NOTES: E1 0.485 0.580 12.32 14.73 5
36. Controlling Dimensions: INCH. In case of conflict between English e 0.100 BSC 2.54 BSC -
and Metric dimensions, the inch dimensions control.
eA 0.600 BSC 15.24 BSC 6
37. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eB - 0.700 - 17.78 7
38. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95. L 0.115 0.200 2.93 5.08 4
39. Dimensions A, A1 and L are measured with the package seated N 40 40 9
in JEDEC seating plane gauge GS-3.
Rev. 0 12/93
40. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
41. E and eA are measured with the leads constrained to be per-
pendicular to datum -C- .
42. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
43. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
44. N is the maximum number of terminal positions.
45. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
FN2957 Rev 5.00 Page 37 of 39

Jul 13, 2018
80C86
Ceramic Dual-In-Line Frit Seal Packages (CERDIP) For the most recent package outline drawing, see F40.6.
c1 LEAD FINISH F40.6 MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A)

-A- -D- 40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
BASE INCHES MILLIMETERS

(c)
METAL
E SYMBOL MIN MAX MIN MAX NOTES
b1 A - 0.225 - 5.72 -
M M
-B- (b)
b 0.014 0.026 0.36 0.66 2
SECTION A-A
b1 0.014 0.023 0.36 0.58 3
bbb S C A-B S D S
b2 0.045 0.065 1.14 1.65 -
D
BASE b3 0.023 0.045 0.58 1.14 4
PLANE Q
-C- A c 0.008 0.018 0.20 0.46 2
SEATING
PLANE L c1 0.008 0.015 0.20 0.38 3

S1 D - 2.096 - 53.24 5
A A eA
b2 E 0.510 0.620 12.95 15.75 5
b e eA/2 c e 0.100 BSC 2.54 BSC -
ccc M C A-B S D S aaa M C A - B S D S eA 0.600 BSC 15.24 BSC -
eA/2 0.300 BSC 7.62 BSC -
NOTES:
46. Index area: A notch or a pin one identification mark shall be located L 0.125 0.200 3.18 5.08 -
adjacent to pin one and shall be located within the shaded area Q 0.015 0.070 0.38 1.78 6
shown. The manufacturer’s identification shall not be used as a pin
S1 0.005 - 0.13 - 7
one identification mark.
47. The maximum limits of lead dimensions b and c or M shall be mea-  90o 105o 90o 105o -
sured at the centroid of the finished lead surfaces, when solder dip aaa - 0.015 - 0.38 -
or tin plate lead finish is applied.
bbb - 0.030 - 0.76 -
48. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness. ccc - 0.010 - 0.25 -
49. Corner leads (1, N, N/2, and N/2+1) may be configured with a par- M - 0.0015 - 0.038 2, 3
tial lead paddle. For this configuration dimension b3 replaces di- N 40 40 8
mension b2.
Rev. 0 4/94
50. This dimension allows for off-center lid, meniscus, and glass over-
run.
51. Dimension Q shall be measured from the seating plane to the base
plane.
52. Measure dimension S1 at all four corners.
53. N is the maximum number of terminal positions.
54. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
55. Controlling dimension: INCH.
FN2957 Rev 5.00 Page 38 of 39

Jul 13, 2018
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by
you or third parties arising from the use of these circuits, software, or information.
2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or
arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application
examples.
3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.
4. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by
you or third parties arising from such alteration, modification, copying or reverse engineering.
5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the
product’s quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; industrial robots; etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.
Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are
not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause
serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all
liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or
other Renesas Electronics document.
6. When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the
reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation
characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified
ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury
or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult
and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you.
8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and
sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics
products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable
laws and regulations.
9. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or
transactions.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third
party in advance of the contents and conditions set forth in this document.
11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.4.0-1 November 2017)
SALES OFFICES http://www.renesas.com

Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.

1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A.
Tel: +1-408-432-8888, Fax: +1-408-434-5351
Renesas Electronics Canada Limited
9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3
Tel: +1-905-237-2004
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700, Fax: +44-1628-651-804
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-6503-0, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
Room 1709 Quantum Plaza, No.27 ZhichunLu, Haidian District, Beijing, 100191 P. R. China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, 200333 P. R. China
Tel: +86-21-2226-0888, Fax: +86-21-2226-0999
Renesas Electronics Hong Kong Limited
Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2265-6688, Fax: +852 2886-9022
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics India Pvt. Ltd.
No.777C, 100 Feet Road, HAL 2nd Stage, Indiranagar, Bangalore 560 038, India
Tel: +91-80-67208700, Fax: +91-80-67208777
Renesas Electronics Korea Co., Ltd.
17F, KAMCO Yangjae Tower, 262, Gangnam-daero, Gangnam-gu, Seoul, 06265 Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5338
© 2018 Renesas Electronics Corporation. All rights reserved.

Colophon 7.0

Features: CMOS 16-Bit Microprocessor

Uploaded by

Copyright:

Available Formats

Features: CMOS 16-Bit Microprocessor

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Features: CMOS 16-Bit Microprocessor

Uploaded by

Copyright:

Available Formats

DATASHEET

The 80C86 high performance 16-bit CMOS CPU is Features

CP80C86-2Z (Note 1) CP80C86-2Z 0 to +70 40 Ld PDIP (Note 2) E40.6

MD80C86-2/883 MD80C86-2/883 -55 to +125 40 Ld CERDIP F40.6

MD80C86-2/B MD80C86-2/B -55 to +125 40 Ld CERDIP F40.6

8405202QA 8405202QA -55 to +125 40 Ld CERDIP (SMD) F40.6

FN2957 Rev 5.00 Page 1 of 39

FN2957 Rev 5.00 Page 2 of 39

4 DT/R, DEN, ALE, M/IO

FIGURE 1. FUNCTIONAL DIAGRAM

FN2957 Rev 5.00 Page 3 of 39

FN2957 Rev 5.00 Page 4 of 39

Pin Descriptions (Continued)

0 1 Upper Byte From/to Odd Address

1 0 Lower Byte From/to Even address

FN2957 Rev 5.00 Page 5 of 39

Minimum Mode System

Maximum Mode System

0 0 1 Read I/O Port

0 1 0 Write I/O Port

FN2957 Rev 5.00 Page 6 of 39

Maximum Mode System (Continued)

0 1 First byte of op code from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

FN2957 Rev 5.00 Page 7 of 39

Functional Description Memory Organization

Static design also allows very low frequency operation (down

FN2957 Rev 5.00 Page 8 of 39

FN2957 Rev 5.00 Page 9 of 39

1 1 1 Passive (No Bus Cycle)

Status bits S3 through S7 are time multiplexed with high order

S5 is a reflection of the PSW interrupt enable bit. S3 is always

0 0 Alternate Data (Extra Segment)

FN2957 Rev 5.00 Page 10 of 39

FFFFFH RESET BOOTSTRAP

3FFH TYPE 225 POINTER

FIGURE 3. RESERVED MEMORY LOCATIONS

FN2957 Rev 5.00 Page 11 of 39

(4 + NWAIT) = TCY (4 + NWAIT) = TCY

GOES INACTIVE IN THE STATE

ADDR/ BHE, S7-S3 BHE S7-S3

MEMORY ACCESS TIME

FIGURE 4. BASIC SYSTEM TIMING

FN2957 Rev 5.00 Page 12 of 39

FN2957 Rev 5.00 Page 13 of 39

when it regains control of the bus. The WAIT instruction is then

t1 t2 t3 t4 TI t1 t2 t3 t4 refetched, and re-executed.

AD0- FLOAT TYPE SP STACK POINTER

FN2957 Rev 5.00 Page 14 of 39

FN2957 Rev 5.00 Page 15 of 39

FIGURE 7A. MINIMUM MODE 80C86 TYPICAL CONFIGURATION

MN/MX GND CLK MRDC

FIGURE 7B. MAXIMUM MODE 80C86 TYPICAL CONFIGURATION

FN2957 Rev 5.00 Page 16 of 39

Absolute Maximum Ratings Thermal Information

SYMBOL PARAMETER TEST CONDITION MIN MAX UNIT

VlH Logical One C80C86 (Note 6) 2.0 V

Input Voltage M80C86 (Note 6) 2.2 V