64K SPI Bus Low-Power Serial SRAM: Device Selection Table
64K SPI Bus Low-Power Serial SRAM: Device Selection Table
64K SPI Bus Low-Power Serial SRAM: Device Selection Table
Features: Description:
• Max. Clock 20 MHz The Microchip Technology Inc. 23X640 are 64 Kbit
• Low-Power CMOS Technology: Serial SRAM devices. The memory is accessed via a
- Read Current: 3 mA at 1 MHz simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
- Standby Current: 4 A Max. at +85°C
(SCK) plus separate data in (SI) and data out (SO)
• 8192 x 8-bit Organization lines. Access to the device is controlled through a Chip
• 32-Byte Page Select (CS) input.
• HOLD pin Communication to the device can be paused via the
• Flexible Operating modes: hold pin (HOLD). While the device is paused,
- Byte read and write transitions on its inputs will be ignored, with the
- Page mode (32 Byte Page) exception of Chip Select, allowing the host to service
higher priority interrupts.
- Sequential mode
• Sequential Read/Write The 23X640 is available in standard packages
including 8-lead PDIP and SOIC, and advanced
• High Reliability
packaging including 8-lead TSSOP.
• Temperature Ranges Supported:
- Industrial (I): -40C to +85C
-40C to +125C
Package Types (not to scale)
- Automotive (E):
• Pb-Free and RoHS Compliant, Halogen Free
Pin Function Table
Name Function
PDIP/SOIC/TSSOP
CS Chip Select Input
(P, SN, ST)
SO Serial Data Output
VSS Ground CS 1 8 VCC
SI Serial Data Input
SO 2 7 HOLD
SCK Serial Clock Input
NC 3 6 SCK
HOLD Hold Input
VCC Supply Voltage VSS 4 5 SI
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
CS
16 16
15 15
SCK
17 18
High-Impedance
SO n+2 n+1 n n n-1
Don’t Care 5
SI n+2 n+1 n n n-1
HOLD
CS
2 11
7
8 3
SCK
5 6
SI MSB in LSB in
High-Impedance
SO
CS
9 10 3
SCK
12
13 14
Don’t Care
SI
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
Data Out
High-Impedance
SO 7 6 5 4 3 2 1 0
CS
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction 16-bit Address Data Byte
SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0
High-Impedance
SO
CS
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
CS
32 33 34 35 36 37 38 39
SCK
SI
CS
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction 16-bit Address Page X, Word Y
SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0
Page X, Word Y
CS
32 33 34 35 36 37 38 39
SCK
CS
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction 16-bit Address
SI 0 0 0 0 0 0 1 1 15 14 13 12 2 1 0
Page X, Word Y
SO 7 6 5 4 3 2 1 0
CS
SCK
SI
CS
SCK
SI
CS
0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction 16-bit Address Data Byte 1
SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
Data Byte 2 Data Byte 3 Data Byte n
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
Instruction
SI 0 0 0 0 0 1 0 1
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0
High-Impedance
SO
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Note: For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Revision A (12/2008)
Original Release.
Revision B (01/2009)
Revised Section 2.5: Added a paragraph.
Revision C (04/2009)
Removed Preliminary status; Revised Standby
Current; Revised Table 1-1, Param. No. D009; Revised
TSSOP Package marking information; Revised
Product ID.
Revision D (08/2010)
Revised Table 1-1, Param. No. D009; Revised
Package Drawings.
Revision E (10/2010)
Revised Parameter D003 in Table 1-1: DC Character-
istics.
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ISBN: 978-1-61341-674-7