Computer Organization and Architecture: 2 Marks Question and Answer
Computer Organization and Architecture: 2 Marks Question and Answer
Computer Organization and Architecture: 2 Marks Question and Answer
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2 Marks Question and Answer
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Subject Code & Name: COMPUTER ORGANIZATION AND ARCHITECTURE
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UNIT-I
BASIC STRUCTURE OF COMPUTERS
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Unit In A Computer System And The Flow Of Information Among The Control Of Those Units.
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Computer H/W Is The Electronic Circuit And Electro Mechanical Equipment That
Constitutes The Computer
The memory arithmetic and logic ,and input and output units store and process
information and perform i/p and o/p operation, the operation of these unit must be co ordinate in
some way this is the task of control unit the cu is effectively the nerve center that sends the
control signal to other units and sence their states.
4.What is an interrupt?
An interrupt is an event that causes the execution of one program to be suspended and
another program to be executed.
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COMPUTER ORGANIZATION AND ARCHITECTURE
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7. Name any three of the standard I/O interface.
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• SCSI (small computer system interface),bus standards
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• Back plane bus standards
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• IEEE 796 bus (multibus signals)
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• NUBUS
• IEEE 488 bus standard
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8. Differentiate between RISC and CISC
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RISC CISC
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Simple instructions take one cycle per Complex instruction take multiple
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Fixed format instructions are used. Variable format instructions are used
executed by hardware. Instructions are interpreted by the
Instructions are compiled and then Microprogram and then executed.
RISC machines are multiple register set. CISC machines use single register
Set.
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COMPUTER ORGANIZATION AND ARCHITECTURE
The address of the location of the operand is given explicitly as a part of the instruction.
Eg. Move a , 2000
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• Arithmetic data transfer
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• Logical data transfer
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• Programmed control data transfer
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12. What is the role of MAR and MDR?
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The MAR (memory address register) is used to hold the address of the location to or
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from which data are to be transferred and the MDR(memory data register) contains the data to be
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written into or read out of the addressed location.
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13. What are the various types of operations required for instructions?
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• Data transfers between the main memory and the CPU registers
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Instruction Register (IR) contains the instruction being executed. Its output is available
to the control circuits, which generate the timing signals for controlling the processing circuits
needed to execute the instructions.
The Program Counter (PC) register keeps track of the execution of the program. It
contains the memory address of the instruction currently being executed . During the execution
of the current instruction, the contents of the PC are updated to correspond to the address of the
next instructions to be executed.
• Input unit
• Output unit
• Control unit
• Memory unit
• Arithmetic and logical unit
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COMPUTER ORGANIZATION AND ARCHITECTURE
17.What is a bus?
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A collection of wires that connects several devices is called a bus.
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18.Define word length?
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Each group of n bits is referred to as a word of information and n is called the word
length.
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19.Explain the following the address instruction?
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Operands a,b are called source operand and c is called destination operand.
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It is also possible to use instruction where the location s of all operand are defined
implicitly. This operand of the use of the method for storing the operand in which called push
down stack. Such instructions are sometimes referred to us zero address instruction.
The CPU control circuitry automatically proceed to fetch and execute instruction, one at
a time in the order of the increasing addresses. This is called straight line sequencing.
The CPU contains a register called the program counter, which holds the address of
instruction to be executed next.. to begin the execution of the program the address of its
First instruction must be placed into the pc.
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COMPUTER ORGANIZATION AND ARCHITECTURE
Gates – The manipulation of binary information is done by logic circuits called gates.
Gates are blocks of hardware that produce signals of binary 1 or 0 where input logic
requirements are satisfied.
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Flip flop – The storage elements employed in clocked sequential circuits are called flip
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flops. A flip flop is a binary cell capable of storing 1 bit of information.
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26.State and explain the performance equation?
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Suppose that the average number of basic steps needed to execute one machine instruction
is S, where each basic step is completed in one clock cycle. If the clock cycle rate is R cycles per
second, the program execution time is given byk9
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T = (N x S) / R
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The term ClockCyclesPerInstruction Which is the average number of clock cycles each
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COMPUTER ORGANIZATION AND ARCHITECTURE
1.Draw and explain the block diagram of a simple computer with five functional units.
2.What is RISC ?Explain with proper example.
3. What is CISC ?Explain with proper example.
4.What are the techniques used to measure the performance of a computer?
5.What do you mean by addressing modes? Explain various addressing modes with the help of
examples.
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COMPUTER ORGANIZATION AND ARCHITECTURE
UNIT-II
BASIC PROCESSING UNIT
a)Instruction Fetch
b)Instruction Decode
c)Operand Fetch
d)Execute
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e) Write Back
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2.Define parallel processing.
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Parallel processing is a term used to denote a large class of techniques that are used to
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provide simultaneous data-processing tasks for the purpose of increasing the computational
speed of a computer system. Instead of processing each instruction sequentially as in a
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conventional computer, a parallel processing system is able to perform concurrent data
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processing to achieve faster execution time.
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constitute a combinational circuit, but when included with the flip flops, the overall circuit is
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4.Define interface.
The word interface refers to the boundary between two circuits or devices
Processor clock: Processor circuits are controlled by a timing signal called processor
clock, the clock defines regular time interval called clock cycle.
6. Define latency.
The term memory latency is used to refer to the amount of time it takes to transfer a
word of data to or from the memory. The term latency is used to denote the time it takes to
transfer the first word of data. This time is usually substantially longer than the time needed to
transfer each subsequent word of a block.
7. Define bandwidth.
Bandwidth is a product of the rate at which the data are transferred (and accessed) and
the width of the data bus.
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COMPUTER ORGANIZATION AND ARCHITECTURE
A successful access to data in a cache is called a hit. Number of hits stated as a fraction
of all attempted accesses is called the hit rate.
A miss rate is the number of misses stated as a fraction of attempted accesses. Extra time
needed to bring the desired information into the cache is called the miss penalty.
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10.Define Clock Rate:
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Clock rate, R=1/p cycles/sec(hz)
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Where p is length of one clock cycle
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11.Define Throughput:
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The total amount of work done in a given time
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1.Synchronous bus
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2.Asynchronous bus
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Microprogramming is a method of control unit design in which the control unit selection
and sequencing information are stored in ROM and RAM’s called control store or control
memory. Micro programmed control unit is a general approach used for implementation of
control unit. Here control signals are generated by a program similar to machine language
programs
It is the one that contains control units that use fixed logic circuits to interpret instructions
and generate control signals from them. Here,the fixed logic circuit block includes combinational
circuit that generates the required control outputs for decoding and encoding functions.
If a temporary register assumes the role of the permanent register whose data it is holding
and is given the same name is called as the Register Renaming.
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COMPUTER ORGANIZATION AND ARCHITECTURE
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It is used to reduce the number of the bits in the microinstruction.
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It is used to overcome the draw back of assigning individual bits to each control signal
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results in long microinstructions, because the number of the required signals is usually large,
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moreover only a few bits are used in any given instruction.
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18.List the techniques used for grouping of the control signals?
a) Vertical organization k9
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b) Horizontal organization
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19 List out Various branching technique used in micro program control unit?
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a) Bit-Oring
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They are two possibilities for increasing the clock rate, R. First, improving the IC
technology makes logic circuits faster, which reduces the time needed to complete a basic step.
This allows the clock period P to be reduce and the clock rate R to be increased Second, reducing
the amount of processing done is one basic step makes it possible to reduce the clock period P.
Overflow -In the single precision, if the number requires a exponent greater then +127
or in a double precision, if the number requires an exponent form the overflow occurs.
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COMPUTER ORGANIZATION AND ARCHITECTURE
23.Define Underflow
Underflow-In a single precision ,if the number requires an exponent less than -26 or in
a double precision, if the number requires an exponent less than -1022 to represent its normalized
form the underflow occurs.
24. What are Condition Codes (CC)? Explain the use of them.
Condition Codes are the list of possible conditions that can be tested during conditional
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instructions.CC is used to test the condition (<, =,>).
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Based on this result, Jump instructions move to specified loop.CC flags represent the value of
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processor that keeps the information about the results of various operations for use by
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conditional branches.
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25. What is straight –line sequencing?
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Process of fetching and executing an instruction; one at a time in order of increasing
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address with the help of information in program counter
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2. What is meant by hardwired control? Draw and explain typical hardwire control unit.
3. What is meant by microprogramming? Draw and explain the micro programmed control unit.
4. List the advantages and disadvantages of micro programmed control unit over hardwire
control unit.
5. Explain in detail about nano programming and list out its benefits.
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COMPUTER ORGANIZATION AND ARCHITECTURE
UNIT-III
PIPELINING
1.Define pipelining.
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2.Define parallel processing.
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Parallel processing is a term used to denote a large class of techniques that are used to
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provide simultaneous data-processing tasks for the purpose of increasing the computational
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speed of a computer system. Instead of processing each instruction sequentially as in a
conventional computer, a parallel processing system is able to perform concurrent data
processing to achieve faster execution time. k9
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The transfer of instructions through various stages of the CPU instruction cycle.,
including fetch opcode, decode opcode, compute operand addresses. Fetch operands, execute
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instructions and store results. This amounts to realizing most (or) all of the CPU in the form of
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4. What are the steps required for a pipelinened processor to process the instruction?
A hazard is also called as hurdle .The situation that prevents the next instruction in the
instruction stream from executing during its designated Clock cycle. Stall is introduced by
hazard. (Ideal stage)
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COMPUTER ORGANIZATION AND ARCHITECTURE
A data hazard is any condition in which either the source or the destination operands of
an instruction are not available at the time expected in pipeline. As a result some operation has
to be delayed, and the pipeline stalls.
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The pipeline may be stalled because of a delay in the availability of an instruction. For
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example, this may be a result of miss in cache, requiring the instruction to be fetched from the
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main memory. Such hazards are called as Instruction hazards or Control hazards.
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9.Define Structural hazards?
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The structural hazards is the situation when two instructions require the use of a given
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hardware resource at the same time. The most common case in which this hazard may arise is
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access to memory.
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Classification of data hazard: A pair of instructions can produce data hazard by referring
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reading or writing the same memory location. Assume that i is executed before J. So, the hazards
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1. RAW hazard
2. WAW hazard
3. WAR hazard
Instruction ‘j’ tries to read a source operand before instruction ‘i’ writes it.
Instruction ‘j’ tries to write a source operand before instruction ‘i’ writes it.
Instruction ‘j’ tries to write a source operand before instruction ‘i’ reads it.
Data hazards in the instruction pipelining can prevented by the following techniques.
a)Operand Forwarding
b)Software Approach
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COMPUTER ORGANIZATION AND ARCHITECTURE
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the order in which they appear in the program. The compiler may rearrange program instruction
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to achieve better performance of course, such changes must not affect of the result of the
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computation.
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16. How addressing modes affect the instruction pipelining?
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Degradation of performance is an instruction pipeline may be due to address
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dependency where operand address cannot be calculated without available informatition needed
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by addressing mode for e.g. An instructions with register indirect mode cannot proceed to fetch
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the operand if the previous instructions is loading the address into the register. Hence operand
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Many instruction in localized area of the program are executed repeatedly during some
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time period and the remainder of the program is accessed relatively infrequently .this is referred
as locality of reference.
The time that elapses between the initiation of an operation and completion of that
operation ,for example ,the time between the READ and the MFC signals .This is Referred to as
memory access time.
The minimum time delay required between the initiations of two successive memory
operations, for example, the time between two successive READ operations.
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COMPUTER ORGANIZATION AND ARCHITECTURE
Memories that consist of circuits capable of retaining the state as long as power is applied
are known as static memories.
22. List out Various branching technique used in micro program control unit?
a) Bit-Oring
b) Using Conditional Variable
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c) Wide Branch Addressing
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23. How the interrupt is handled during exception?
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* CPU identifies source of interrupt
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* CPU obtains memory address of interrupt handles
* pc and other CPU status information are saved
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* Pc is loaded with address of interrupt handler and handling program to handle it.
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3.Pipelining
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4.Clock rate
5.Instruction set
6.Compiler
A special control unit may be provided to enable transfer a block of data directly between
an external device and memory without contiguous intervention by the CPU. This approach is
called DMA.
1.State and explain the different types of hazards that can occur in a pipeline.
2.Draw and explain the structure of a superscalar processor. Also explain the flow of instruction
execution in it.
3.what are the two aspects of machine instruction? Explain it .
4.Draw and explain the modified three-bus structure of the processor suitable for four -stage
pipelined execution. How this structure is suitable to provide four-stage pipelined execution?
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COMPUTER ORGANIZATION AND ARCHITECTURE
UNIT-IV
MEMORY SYSTEM
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Multifunction – WORM and Erasable
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2. What is a Mini Disk?
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Minidisk for data (MD-Data) is the data version of the new rewriteable storage format
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developed by Sony Corporation for both business and entertainment as a convenient medium for
carrying music , video and data. MD can be used in three formats to support all potential uses as
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--A premastered optical disk
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A multifunctional drive is a single unit which is capable of reading and writing a variety
of disk media. This type of drive provides the permanence of a read-only device as well as full
flexibility of a rewriteable device along with the powerful intermediate write once capability
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COMPUTER ORGANIZATION AND ARCHITECTURE
The process of moving an object from one level in the storage hierarchy to another
level in that hierarchy is called migration. Migration of Objects to off-line media and removal of
these objects from on-line media is called archiving.
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A juke box is used for storing large volumes of multimedia information in one cost
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effective store . Jukebox – based optical disk libraries can be networked so that multiple users
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can access the information. Opticla disk libraries serve as nearline storage for infrequently used
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ata.
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8. List a few requirements imposed by advanced multimedia applications
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Some of the requirements imposed by multimedia application are
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Cache design use a high-water mark and a low water mark to trigger cache management
operations. When the cache storage fiklls up to the high – water mark , the cache manager starts
creating more space in cache storage. Space is created by discarding objects that have not been
modified and writing back those object that have been modified.
10. What are the various cache usage in a LAN –based system?
In a LAN – based system there can be as many as three stages of caches as follows
1. Disk Cache or System memory cache
2. Hard Disk cache for each object server
3. Shared network cache for all object servers
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COMPUTER ORGANIZATION AND ARCHITECTURE
Techniques that automatically move program and data blocks into the physical memory
when they are required for execution are called virtual memory technique
The binary addresses that the processor issues for either instruction or data are called
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virtual or logical addresses.
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14. Define translation buffer.
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Most commercial virtual memory systems incorporate a mechanism that can avoid the
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bulk of the main memory access called for by the virtual to physical addresses translation buffer.
This may be done with a cache memory called a translation buffer.
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15. What is branch delay slot?
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The location containing an instruction that may be fetched and then discarded because of
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Optical or light based techniques for data storage, such memories usually employ optical
disk which resemble magnetic disk in that they store binary information in concentric tracks on
an electromechanically rotated disks. The information is read as or written optically, however
with a laser replacing the read write arm of a magnetic disk drive. Optical memory offer high
storage capacities but their access rate is are generally less than those of magnetic disk.
Static memory are memories which require periodic no refreshing. Dynamic memories
are memories, which require periodic refreshing.
A facility for dynamic storage relocation that maps logical memory references into
physical memory addresses.
A provision for sharing common programs stored in memory by different users .
The MAR (memory address register) is used to hold the address of the location to or from
which data are to be transferred and the MDR(memory data register) contains the data to be
written into or read out of the addressed location.
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COMPUTER ORGANIZATION AND ARCHITECTURE
Static RAM are fast, but they come at high cost because their cells require several
transistors. Less expensive RAM can be implemented if simpler cells are used. However such
cells do not retain their state indefinitely; Hence they are called Dynamic RAM.
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The specialized memory controller circuit provides the necessary control signals, RAS
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And CAS ,that govern the timing. The processor must take into account the delay in the response
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of the memory. Such memories are referred to as asynchronous DRAMS.The DRAM whose
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operations is directly synchronized with a clock signal. Such Memories are known as
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synchronous DRAM.
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22. What do you mean associative mapping technique?
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The tag of an address received from the CPU is compared to the tag bits of each block of
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the cache to see if the desired block is present. This is called associative mapping technique.
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Small computer system interface can be used for all kinds of devices including RAID
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storage subsystems and optical disks for large- volume storage applications.
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24. What are the two types of latencies associated with storage?
Disk spanning is a method of attaching drives to a single host uadapter. All drives
appear as a single contiguous logical unit. Data is written to the first drive first and when the
drive is full, the controller switches to the second drive, then the second drive writes until its full.
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COMPUTER ORGANIZATION AND ARCHITECTURE
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29. What are the different levels RAID?
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There are six discrete levels of RIAD functionality. They are
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-Level 0 – Disk Striping
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-Level 1 – Disk Mirroring
-Level 2 – Bit Interleaving of Data
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-Level 3 – Bit Interleaving with dedicated parity drives
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- Level 4 – Sector interleaving of data with dedicated parity drive
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1.Primary Memory
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2.Secondary Memory
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1.Define cache memory. Explain the mapping process followed in cache memory. Also discuss
the relative advantages and disadvantages of the mapping techniques used.
2.What is virtual memory? Why is it necessary to implement virtual memory? Explain the virtual
memory address translation.
3.Draw and explain the various types of secondary storage devices.
4.a)Explain about RAM.
b)Explain about ROM.
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COMPUTER ORGANIZATION AND ARCHITECTURE
UNIT-V
I/O ORGANIZATION
ESDI stands for enhanced small device interface was developed by a consortium of
several manufacturers. ESDI converts the data into serial bit streams and uses the RLL encoding
scheme to pack more bits per sector. ESDI drives store a defect map containing the locations of
bad and defective sectors on the drive.
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2. Explain in brief about IDE
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Integrated device electronics contains an integrated controller with the drive as a
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single unit. Interface is a simple 16-bit parallel data interface and requires the data to be written
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and does not need to be told where and how to write the data on the disk. .IDE Interface supports
2 drives – one drive has to be configured as the master and the second as the slave.
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3. What is SCSI?
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Small computer system interface can be used for all kinds of devices including RAID
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storage subsystems and optical disks for large- volume storage applications.
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“Means feature that help to avoid and detect such faults. A realible system does not
silently continue and delivery result that include interrected and corrupted data, instead it
corrects the corruption when possible or else stops
“Means features that follow the systerm to stay operational even offen faults do occur.
A highly available systerm could dis able do the main functioning portion and continue operating
at the reduced capacity”
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COMPUTER ORGANIZATION AND ARCHITECTURE
A memory reference instruction activated the READ M (or)WRITE M control line and
does not affect the IO device. Separate IO instruction are required to activate the READ IOand
WRITE IO lines ,which cause a word to be transferred between the address aio port and the
CPU. The memory and IO address space are kept separate.
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--Single transfer mode(cyclestealing mode)
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--Block Transfer Mode(Brust Mode)
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--Demand Transfer Mode
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--Cascade Mode
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9. What is an interrupt?
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An interrupt is an event that causes the execution of one program to be suspended and
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another program to be executed.
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*Debugging
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In order to reduce the overhead involved in the polling process, a device requesting an
interrupt may identify itself directly to the CPU. Then, the CPU can immediately start executing
the corresponding interrupt-service routine. The term vectored interrupts refers to all interrupt-
handling schemes base on this approach.
An i/o channel is actually a special purpose processor, also called peripheral processor.
The main processor initiates a transfer by passing the required information in the input output
channel. the channel then takes over and controls the actual transfer of data.
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COMPUTER ORGANIZATION AND ARCHITECTURE
14.What is a bus?
Each group of n bits is referred to as a word of information and n is called the word
length.
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16. Why program controlled I/O is unsuitable for high-speed data transfer?
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In program controlled i/o considerable overhead is incurred.. because several program
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instruction have to be executed for each data word transferred between the external devices and
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MM.Many high speed peripheral; devices have a synchronous modes of operation.that is data
transfer are controlled by a clock of fixed frequency, independent of the cpu.
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17.what is the function of i/o interface?
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The function is to coordinate the transfer of data between the cpu and external devices.
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18.what is NUBUS?
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bit micro processor system. It defines a backplane into which upto 16 devices may be
plugged each in the form of circuit board of standard dimensions.
*Video terminals
*Video displays
*Alphanumeric displays
*Graphics displays
* Flat panel displays
*Printers
*Plotters
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COMPUTER ORGANIZATION AND ARCHITECTURE
21.Define interface.
The word interface refers to the boundary between two circuits or devices
Data transfer to and from peripherals may be handled using this mode. Programmed I/O
operations are the result of I/O instructions written in the computer program.
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23.Types of buses.
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-Synchronous bus
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-Asynchronous bus
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24.Define Synchronous bus.
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- Synchronous bus on other hand contains synchronous clock that is used to validate
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each and every signal.
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- Synchronous buses are affected noise only when clock signal occurs.
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- Synchronous bus designers must control with meta stability when attempting different
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- Asynchronous buses can mistake noise pulses at any time for valid handshake signal.
- Asynchronous bus designer must deal with events that like synchronously.
- It must contend with meta stability when events that drive bus transaction.
-When flip flop experiences effects can occur in downstream circurity unless proper
design technique which are used
1.List the different types of interrupts. Explain briefly about mask able interrupt.
2.What is DMA? Explain the block diagram of DMA .Also describe how DMA is used to
transfer data from peripherals.
3.Explain the features of USB,PCI,SCSI bus.
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