Unit 7
Unit 7
Unit 7
UNIT 5
SYSTEM TESTING, INTERACTION TESTING
System Testing, Interaction Testing Threads, Basic concepts for requirements specification,
Finding threads, Structural strategies and functional strategies for thread testing, SATM test
threads, System testing guidelines, ASF (Atomic System Functions) testing example. Context
of interaction, A taxonomy of interactions, Interaction, composition, and determinism,
Client/Server Testing.
Of the three levels of testing (Unit testing, Integration testing, and System testing),
the system level is closest to everyday experience. We test many things: a used car before we
buy it, an on-line network service before we subscribe, and so on. A common pattern in these
familiar forms is that we evaluate a product in terms of our expectations; not with respect to a
specification or a standard. Consequently, the goal is not to find faults, but to demonstrate
performance or correct behavior. Because of this, we tend to approach system testing from a
functional standpoint rather than from a structural one. Since it is so intuitively familiar,
system testing in practice tends to be less formal than it might be, and this is compounded by
the reduced testing interval that usually remains before a delivery deadline.
5.1 Threads
Here are several views of a thread:
A scenario of normal usage
A system level test case
Behavior that results from a sequence of system level inputs
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System Testing
Integration Testing
System level
threads Unit Testing
Integration level
threads Unit level threads
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• Entry of a digit
1
1. Digit entry is a good example of a minimal atomic system function. It begins with a
port input event (the digit keystroke) and ends with a port output event (the screen
digit echo), so it qualifies as a stimulus/response pair. This level of granularity is too
fine for the purposes of system testing. We saw this to be an appropriate level for
integration testing.
2. The second candidate, PIN Entry, is a good example of an upper limit to integration
testing, and at the same time, a starting point of system testing. PIN Entry is a good
example of an atomic system function. It is also a good example of a family of
stimulus/response pairs. PIN Entry entails a sequence of system level inputs and
outputs:
a. A screen requesting PIN digits
b. An interleaved sequence of digit keystrokes and screen responses
c. The possibility of cancellation by the customer before the full PIN is entered
d. A system disposition: A customer has three chances to enter the correct PIN. Once a
correct PIN has been entered, the user sees a screen requesting the transaction
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type; otherwise a screen, a screen advises the customer that the ATM card will
not be returned, and no access to ATM functions is provided.
3. The third candidate, the simple transaction, has a sense of end-to-end completion. A
customer could never execute PIN alone, customer may require to enter even card enter
too, but the simple transaction is commonly executed. This is good example of a system-
level thread; note that it involves the interaction of several ASFs.
4. The fourth and last candidate, session is actually a sequence of threads. This is he part of
system testing.
Thread
Definitions
MM-Path
ASF
Definition 1
A unit thread is a path in the program graph of a unit.
There are two levels of threads used in integration testing: MM-Paths and Atomic
System Functions (ASF). MM-Paths are defined as paths in the directed graph in which
module execution paths are nodes, and edges show execution time sequence.
Definition 2
Given a system defined in terms of atomic system functions, the ASF Graph of the
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system is the directed graph in which nodes are atomic system functions and edges represent
sequential flow.
Definition 3
A source ASF is an atomic system function that appears as a source node in the ASF
graph of a system; similarly, a sink ASF is an atomic system function that appears as a sink
node in the ASF graph.
In the SATM system, the Card Entry ASF is a source ASF, and the session
termination ASF is a sink ASF.
Definition 4
A system thread is a path from a source ASF to a sink ASF in the ASF graph of a
system.
Definition 5
Given a system defined in terms of system threads, the Thread Graph of the system
is the directed graph in which nodes are system threads and edges represent sequential
execution of individual threads.
5.2.1 Data
When a system is described in terms of its data, the focus is on the information used
and created by the system.
We describe data in terms of variables, data structures, fields, records, data stores,
and files.
Entity/relationship models are the most common choice at the highest level, and some
form of a regular expression is used at a more detailed level.
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5.2.2 Actions
Actions have inputs and outputs, and these can be either data or port events. Here are
some methodology- specific synonyms for actions: transform, data transform, control
transform, process, activity, task, method, and service. Actions can also be
decomposed into lower level actions. The input/output view of actions is exactly the
basis of functional testing, and the decomposition (and eventual implementation) of
actions is the basis of structural testing.
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ports in the SATM system include the digit and cancel keys, the function keys, the
display screen, the deposit and withdrawal doors, the card and receipt slots, and
several less obvious devices, such as the rollers that move cards and deposit
envelopes into the machine, the cash dispenser, the receipt printer, and so on.
5.2.4 Events
Events are somewhat schizophrenic: they have some characteristics of data and some
of actions. An event is a system level input (or output) that occurs at a port. Like
data, events can be inputs to or outputs of actions. Events can be discrete (such as
SATM keystrokes) or they can be continuous (such as temperature, altitude, or
pressure). Discrete events necessarily have a time duration, and this can be a critical
factor in real-time systems. We might picture input events as destructive read- out
data, but it's a stretch to imagine output events as destructive write operations.
Events are like actions in the sense that they are the translation point between real-
world physical events and internal logical manifestations of these. Port input events
are physical-to-logical translations, and symmetrically, port output events are
logical-to-physical translations. System testers should focus on the physical side of
events, not the logical side (the focus of integration testers). There are situations
where the context of present data values changes the logical meaning of physical
events. In the SATM system, for example, the port input event of depressing button
B1 means "Balance" when screen 5 is being displayed, "checking" when screen 6 is
being displayed, and "yes" when screens 10, 11, and 14 are being displayed. We
refer to such situations as "context sensitive port events", and we would expect to test
such events in each context.
5.2.5 Threads
Unfortunately for testers, threads are the least frequently used of the five
fundamental constructs. Since we test threads, it usually falls to the tester to find
them in the interactions among the data, events, and actions. About the only place
that threads appear per se in a requirements specification is when rapid prototyping is
used in conjunction with a scenario recorder. It's easy to find threads in control
models, as we will soon see. The problem with this is that control models are just
that — they are models, not the reality of a system.
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Figure 5.1 is an entity/relationship model of our basis concepts. Notice that all relationships
are many-to-many: Data and Events are generalized into an entity; the two relationships to
the Action entity are for inputs and outputs. The same event can occur on several ports, and
typically many events occur on a single port. Finally, an action can occur in several threads,
and a thread is composed of several actions. This diagram demonstrates some of the
difficulty of system testing. Testers must use events and threads to ensure that all the many-
to-many relationships among the five basis concepts are correct.
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The finite state machine models of the SATM system are the best place to look for
system testing threads. We'll start with a hierarchy of state machines; the upper level is
shown in Figure 5.3.
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At this level, states correspond to stages of processing, and transitions are caused by
logical (rather than port) events. The Card Entry "state" for example, would be decomposed
into lower levels that deal with details like jammed cards, cards that are upside-down, stuck
card rollers, and checking the card against the list of cards for which service is offered. Once
the details of a macro-state are tested, we use an easy thread to get to the next macro-state.
The PIN Entry state is decomposed into the more detailed view in Figure 5.4.
At this level, we focus on the PIN retry mechanism; all of the output events are true
port events, but the input events are still logical events. The states and edges are numbered
for reference later when we discuss test coverage.
To start the thread identification process, we first list the port events shown on the
state transitions; they appear in Table 5.1.
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Notice that Correct PIN and Incorrect PIN are really compound port input events. We
can't actually enter an entire PIN, we enter digits, and at any point, we might hit the cancel
key. These more detailed possibilities are shown in Figure 5.5.
The port events in the PIN Try finite state machine are in Table 5.2.
The "x" in the state names in the PIN Try machine refers to which try (first, second,
or third) is passing through the machine.
In addition to the true port events in the PIN Try finite state machine, there are three
logical output events (Correct PIN, Incorrect PIN, and Canceled); these correspond exactly
to the higher level events in Figure 5.4.
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Table 5.2 Port Events in the PIN Entry Finite State Machine
The hierarchy of finite state machines multiplies the number of threads. There are 156
distinct paths form the First PIN Try state to the Await Transaction Choice or Card Entry
states in Figure 5.4. Of these, 31 correspond to eventually correct PIN entries (1 on the first
try, 5 on the second try, and 25 on the third try); the other 125 paths correspond to those
with incorrect digits or with cancel keystrokes.
Tables T3 and T4 follow two paths through the hierarchic state machines. Table 5.3
corresponds to a thread in which a PIN is correctly entered on the first try. Table 5.4 corresponds to
a thread in which a PIN is incorrectly entered on the first try, cancels after the third digit on the
second try, and gets it right on the third try. To make the test case explicit, we assume a pre-condition
that the expected PIN is '1234'.
Table 5.3 Port Event Sequence for Correct PIN on First Try
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Table 5.4 Port Event Sequence for Correct PIN on First Try
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When we organize state machines in a hierarchy, we can work from the bottom up.
There are six paths in the PIN Try state machine. If we traverse these six, we test for three
things: correct recognition and echo of entered digits, response to the cancel keystroke, and
matching expected and entered PINs. These paths are described in Table 5.5 as sequences of
the transitions in Figure 5.5. A thread that traverses the path is described in terms of its input
keystrokes, thus the input sequence 1234 corresponds to the thread described in more detail in
Table 5.3, and here the cancel keystroke is indicated with a 'C'.
Once this portion is tested, we can go up a level to the PIN Entry machine (Figure 5.4),
where there are four paths. These four are concerned with the three try mechanism and the
sequence of screens presented to the user. In Table 5.6, the paths in the PIN Entry state
machine (Figure 5.4) are named as transition sequences.
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What really happens with the '1235' input sequence in Table 5.5? It traverses an
interesting path in the PIN Try machine, and then it "returns" to the PIN Entry machine
where it is seen as a logical event (incorrect PIN), which causes a transition to state 2.2
(Second PIN Try). If no additional keystrokes occur, this machine would remain in state 2.2.
We show how to overcome such situations next.
Because the finite state machines are directed graphs, we can use the same test coverage
metrics that we applied at the unit level. The hierarchic relationship means that the upper level
machine must treat the lower machine as a procedure that is entered and returned.
The two obvious choices are node coverage and edge coverage. Table 5.7 is extended from
Table 5.4 to show the node and edge coverage of the three-try thread.
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Here we have two kinds of incidence tables, one is Thread/State Incidence and another
one is Thread/Transition Incidence as shown in Table 5.8 and Table 5.9.
Input 2.1 2.x.1 2.x.2 2.x.3 2.x.4 2.x.5 2.x.6 2.2 2.3 3 1
Events
1234 X X X X X X X
12351234 X X X X X X X X
C1234 X X X X X X X X X
1C12C1234 X X X X X X X X X X
123C1C1C X X X X X X X X
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Input X X X X X X X X X X1 X1 1 2 3 4 5 6
Events 1 2 3 4 5 6 7 8 9 0 1
1234 X X X X X X
1235123 X X X X X X X X
4
C1234 X X X X X X X X X
1C12C12 X X X X X X X X X X X
34
123C1C1 X X X X X X X X X
C
Consider the space of port input events. There are five port input thread coverage
metrics of interest. Attaining these levels of system test coverage requires a set of threads such
that:
PI1: each port input event occurs
PI2: common sequences of port input events occur
PI3: each port input event occurs in every "relevant" data context
PI4: for a given context, all "inappropriate" input events occur
PI5: for a given context, all possible input events
The PI1 metric is a bare minimum and is inadequate for most systems. PI2 coverage
is the most common, and it corresponds to the intuitive view of system testing because it
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deals with "normal use". It is difficult to quantify, however. What is a "common" sequence of
input events? What is an uncommon one?
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We can identify each of these examples, and many more, by close attention to the
information in the entity/relationship (E/R) model. As we did with event-based
testing, we describe the following sets of threads in terms of data-based coverage
metrics.
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Explanation to DM1:
Cardinality refers of the four possibilities of relationship: one-to-one, one-to-many,
many-to-one, and many-to-many.
In the library example, both the loan and the writes relationships are many-to-many,
meaning that one author can write many books, and one book can have many authors;
and that one book can be loaned to many borrowers and one borrower can borrow
many books. Each of these possibilities results in a useful system testing thread.
Explanation to DM2:
Participation refers to whether or not every instance of an entity participates in a
relationship.
In the writes relationship, both the Book and the Author entities have mandatory
participation i.e., we cannot have a book with no authors, or an author of no books.
In some modeling techniques, participation is expressed in terms of numerical limits;
the Author entity, for example, might be expressed as "at least 1 and at most 12".
Explanation to DM3:
Sometimes transactions determine explicit logical connections among relationships;
these are known as functional dependencies.
For example, we cannot loan a book that is not possessed by the library, and we
would not delete a book that is out on loan. Also, we would not delete a borrower
who still has some books checked out.
These kinds of dependencies are reduced when the database is normalized, but they
still exist, and they lead to interesting system test threads.
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We will express threads in tables in which pairs of rows correspond to port inputs and
expected port outputs at each of the four major stages. We start with three basic threads,
one for each transaction type (balance inquiry, deposit, and withdrawal).
In thread 1, a valid card with PAN = 100 is entered, which causes screen 2 to be
displayed. The PIN digits '1234' are entered, and since they match the expected PIN for
the PAN, screen 5 inviting a transaction selection is displayed. When button B1 is
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touched the first time (requesting a balance inquiry), screen 6 asking which account is
displayed. When B1 is pressed the second time (checking), screen 14 is displayed and
the checking account balance ($1000.00) is printed on the receipt. When B2 is pushed,
screen 15 is displayed, the receipt is printed, the ATM card is ejected, and then screen 1
is displayed.
Thread 2 is a deposit to checking: Same PAN and PIN, but B2 is touched when
screen 5 is displayed, and B1 is touched when screen 6 is displayed. The amount 25.00 is
entered when screen 7 is displayed and then screen 13 is displayed. The deposit door
opens and the deposit envelope is placed in the deposit slot. Screen 14 is displayed, and
when B2 is pushed, screen 15 is displayed, the receipt showing the new checking
account balance of $1025.00 is printed, the ATM card is ejected, and then screen 1 is
displayed.
Thread 3 is a withdrawal from savings: Again the same PAN and PIN, but B3 is
touched when screen 5 is displayed, and B2 is touched when screen 6 is displayed. The
amount 30.00 is entered when screen 7 is displayed and then screen 11 is displayed. The
withdrawal door opens and three $10 notes are dispensed. Screen 14 is displayed, and
when B2 is pushed, screen 15 is displayed, the receipt showing the new savings account
balance of $770.00 is printed, the ATM card is ejected, and then screen 1 is displayed.
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A few of these detailed descriptions are needed to show the pattern; the remaining
threads are described in terms of input and output events that are the objective of the test
thread.
Thread 4 is the shortest thread in the SATM system, it consists of an invalid card,
which is immediately rejected.
Following the macro-states along thread 1, we next perform variations on PIN Entry. We
get four new threads from Table 9, which yield edge coverage in the PIN Entry finite state
machines.
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Moving to the Transaction Request stage, there are variations with respect to the type of
transaction (balance, deposit, or withdraw), the account (checking or savings) and
several that deal with the amount requested. Threads 1, 2, and 3 cover the type and
account variations, so we focus on the amount-driven threads. Thread 9 rejects the
attempt to withdraw an amount not in $10 increments, Thread 10 rejects the attempt to
withdraw more than the account balance, and Thread 11 rejects the attempt to withdraw
more cash than the dispenser contains.
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Decision tables and finite state machines are good choices for ASF testing. If an ASF
is described using a decision table, conditions typically include port input events, and
actions are port output events. We can then devise test cases that cover every condition,
every action, or most completely, every rule. As we saw for finite state machine models, test
cases can cover every state, every transition, or every path.
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Another difference is that because we expect to find more faults with progression
testing, we need to be able to locate the faults. This requires test cases with a diagnostic
capability – that is, tests that can fail only in a few ways.
The ASF graph shows all the ways valid months, days, and years can be entered, but
the transition to ASF-8 (or ASF-9) depends on the history of previous ASFs.
Table 5.14 contains a second set of ASFs.
Event Input Event Description Statement Numbers
e0 Start program event 1
e1 Enter a valid month 67
e2 Enter an invalid month 67
e3 Enter a valid day 69
e4 Enter an invalid day 69
e5 Enter a valid year 71
e6 Enter an invalid year 71
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rest invalid
ASF-7 enter a date with valid day, rest
invalid
ASF-8 enter a date with valid year, rest
invalid
ASF-9 enter a date with invalid month,
day, and year
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What does it mean for location (time and position) to be an attribute of any of the
five basis constructs? This is really a short-coming of nearly all requirements specification
notations and techniques. (This is probably also the reason that interactions are seldom
recognized and tested.) Information about location is usually created when a system is
implemented. Sometimes location is mandated as a requirement — when this happens, the
requirement is really a forced implementation choice. We first clarify the meaning of the
components of location: time and position.
The position aspect is easier. We could take a very tangible, physical view of position
and describe it in terms of some coordinate system. Position can be a three dimensional
Cartesian coordinate system with respect to some origin, or it could be a longitude-latitude-
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elevation geographic point. For most systems, it is more helpful to slightly abstract position
into processor residence. Taken together, time and position tell the tester when and where
something happens, and this is essential to understand interactions.
Before we develop our taxonomy, we need some ground rules about threads and
processors. For now, a processor is something that executes threads or a device where
events occur.
1. Since threads execute, they have strictly positive time duration. We usually speak of
the execution time of a thread, but we might also be interested in when a thread occurs
(executes). Actions are degenerate cases of threads; therefore, actions also have durations
2. In a single processor, two threads cannot execute simultaneously. This resembles a
fundamental precept of physics: no two bodies may occupy the same space at the same
time. Sometimes threads appear to be simultaneous, as in time sharing on a single
processor; in fact, time shared threads are interleaved. Even though threads cannot
execute simultaneously on a single processor, events can be simultaneous. (This is really
problematic for testers.)
3. Events have strictly positive time duration. When we consider events to be actions
that execute on port devices, this reduces to the first ground rule.
4. Two (or more) input events can occur simultaneously, but an event cannot occur
simultaneously in two (or more) processors. This is immediately clear if we consider port
devices to be separate processors.
5. In a single processor, two output events cannot begin simultaneously. This is a
direct consequence of output events being caused by thread executions. We need both the
instantaneous and duration views of time to fully explain this ground rule. Suppose two
output events are such that the duration of one is much greater than the duration of the
other. The durations may overlap (because they occur on separate devices), but the start
times cannot be identical.
6. A thread cannot span more than one processor. This convention helps in the
definition of threads. by confining a thread to a single processor, we create a natural
endpoint for threads; this also results in more simple threads rather than fewer complex
threads. In a multi-processing setting, this choice also results in another form of quiescence
— trans-processor quiescence.
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Threads can only interact in two ways, via events or via data. We will see this more
clearly using EDPNs after we make another definition.
Definition
In an EDPN, the external inputs are the places with indegree = 0, and the external
outputs are the places with outdegree = 0.
In the EDPN in Figure 5.11, p1 and p2 are the only external inputs, and p5, p9 and
p10 are the only external outputs.
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The interaction of these sets contains the events and places at which the composed
threads can interact. This process is illustrated in Figure 5.12 and 5.13.
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The EDPN transitions, places, and events used in Figure 5.17 are summarized in
Table 5.18.
In the lever EDPN (Figure 5.15), transitions to the OFF, LOW, and HIGH states
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require no interaction with the dial EDPN to determine the associated port output
events (p5, p9, and p10).
Also transition to the INT state (s1 and s5) has no output port events.
In the dial EDPN (Figure 5.16), the three dial positions are the three data places, and
the dial events (p3 and p4) are inputs that cause transitions.
The dial EDPN has no port output events, because these are never output of
transitions in the dial EDPN.
Figure 5.17 EDPN for the windshield wiper system. Table 5.18 EDPN windshield wiper
elements.
The interaction between the lever and the dial EDPNs is shown in Figure 5.17. It
shows places d2, d5, d6, and d7 are the INT state, transitions s11, s12 and s13 are the
dial positions states, and port events p6, p7, and p8 are the three intermittent wiper
speeds.
The edges with arrowheads at each end (for example in between d2 and s11) indicate
that the places are inputs to and outputs of the associated transitions.
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1. A system is deterministic if, given its inputs, we can always predict its outputs.
2. A system is deterministic if it always produces the same outputs for a given set of inputs.
Since the second view (repeatable outputs) is less stringent than the first (predictable
outputs), we'll use it as our working definition. Then a non-deterministic system is one in
which there is at least one set of inputs that results in two distinct sets of outputs. It's easy to
devise a non-deterministic finite state machine; Figure 5.18 is one example
When the machine in Figure 5.18 is in state d1, if event e1 occurs, there is a transition
either to state d2 or to d3.
If it is so easy to create a non-deterministic finite state machine, why all the fuss about
determinism in the first place? (It turns out that we can always find a deterministic
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equivalent to any non- deterministic finite state machine anyway.) Finite state machines are
models of reality; they only approximate the behavior of a real system. This is why it is so
important to choose an appropriate model — we would like to use the best approximation.
Roughly speaking, decision tables are the mode I of choice for static interactions, finite state
machines suffice for dynamic interactions in a single processor, and some form of Petri net
is needed for dynamic interactions in multiple processors. Before going on, we should
indicate instances of non-determinism in the other two models. A multiple hit decision table
is one in which the inputs (variables in the condition stub) are such that more than one rule is
selected. In Petri nets, non-determinism occurs when more than one transition is enabled.
The choice of which rule executes or which transition fires is made by an external agent.
(Notice that the choice is actually an input!)
Our question of non-determinism reduces to threads in an OSD net, and this is where
interactions, composition, and determinism come together. To ground our discussion in
something "real", consider the SATM threads we used earlier:
Threads T1, T2, and T3 interact via a data place for the account balance, and they may be executed
in different processors. The initial balance is $50.00.
Begin with thread TI; if no other thread executes, it will execute correctly, leaving a
balance of $10.00. Suppose we began with thread T2; we should really call it "attempt to
withdraw $60.00", because, if no other thread executes, it will result in the insufficient funds
screen. We should really separate T2 into two threads, T2.1 which is a successful
withdrawal that ends with the display of screen 11 (take cash), and T2.2 which is a failed
withdrawal that ends with the display of screen 8 (insufficient funds). Now let's add some
interaction with thread T3. Threads T2 and T3 are 2- connected via the balance data place.
If T3 executes before T2 reads the balance data, then T2.1 occurs, otherwise T2.2 occurs.
The difference between the two views of determinism is visible here: When the OSD net of T2
begins to execute, we cannot predict the outcome (T2.1 or T2.2), so by the first definition, this
is non-deterministic. By the second definition, however, we can recreate the interaction
(including times) between T2 and T2. If we do, and we capture the behavior as a marking of
the composite OSD net, we will satisfy the repeatable definition of determinism.
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Software Testing (10CS842)
Unit V (2016-17) System Testing & Interaction Testing Vishwesh Jayashekar
Client-server systems also include a network to connect the clients with the server,
the network software, and a graphical user interface (GUI) for the clients. To make matters
worse, we can differentiate homogeneous and heterogeneous CS systems in terms of client
processors that are identical or diverse. The multiple terminal version of the SATM system
would be a fat client system, since the central bank does very little of the transaction
processing.
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Software Testing (10CS842)
Unit V (2016-17) System Testing & Interaction Testing Vishwesh Jayashekar
Possible Questions:
1. What is thread? Explain different levels of threads.
2. Explain threads with its different definitions.
3. Explain the basic concepts for requirements specification. (June/July 2016) (10 M)
4. With a neat diagram explain top level, PIN entry and PIN try finite state machine of
SATM system.
5. Explain about structural strategies for thread testing.
6. Explain about functional strategies for thread testing. (June/July 2014) (10M),
(June/July 2015) (10M).
7. Explain different SATM threads.
8. Explain the operational profile of SATM system and mention the difference between
progression and regression testing.
9. What is ASF and explain with testing example.
10. Explain the 6 basic rules of thread taxonomy.
11. Explain static interaction in a single and multiple processors.
12. Explain dynamic interaction in a single and multiple processors.
13. Write a short note on ‘taxonomy of interactions’ and ‘Client/Server testing’.
(June/July 2016) (10 M)
14. Explain about client/server testing. (June/July 2014) (10M), (June/July 2015) (10M).
***
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Software Testing (10CS842)