National University of Sciences & Technology (NUST)

School of Electrical Engineering and Computer Science (SEECS)

Department of Electrical Engineering

Digital Logic Design
Course Code: EE221 Semester: Fall 2016
Credit Hours: 3+1 Pre-requisites: Nil
Instructor: Nasir Mahmood E-mail: nasir.mahmood@seecs.edu.pk
Office: Room A-217, Faculty Block Telephone: +92 (0)51 9085 2106
Students Batch: BEE-8AB Discipline/Year: Electrical Engineering/Second
Lecture/Lab Days: Mon:1100-1150(Sec A/CR-16) Consulting Hours: Wed: 1500-1550 Hrs (Sec A/Off)
1400-1450(Sec B/CR-18) Tue: 1600-1650 Hrs (Sec B/Off)
Tue: 1200-1250(Sec A/CR-16) or
1400-1450(Sec B/CR-18) via email
Wed:1000-1050(Sec A/CR-16)
1100-1150(Sec B/CR-18)
Fri: 1000-1250(Sec A/Digital Lab)
1400-1650(Sec B/Digital Lab)
Lab Engr: Asma Majeed E-mail: asma.majeed@seecs.edu.pk
Knowledge Group: Digital Systems and Signal Processing Updates on LMS: on required basis

Course Description:
Digital Logic Design is a one-semester course taken by Electrical Engineering students during second year of
their engineering program. This course introduces the logic operators and gates to lay the framework for
strengthening the basic understanding of computer building blocks. Both combinational and sequential circuits
are studied in this course along with their constituent elements comprising Arithmetic circuits, Comparators,
Decoders, Encoders, Multiplexers, as well as latches, flip-flops, counters and registers. It lays down foundations
for advanced studies in Microprocessor Systems, Embedded System Design, and Digital System Design.

Course Objectives:
In this course students will learn principles of Digital Logic Design. They will combine classical design
methodologies with a series of laboratory assignments in which they will demonstrate their ability to
successfully design, implement, and debug digital systems using Computer Aided Design tools and physical
prototyping.

Course Learning Outcomes (CLO)

Upon successful completion of this course the students will be able to demonstrate the PLO BT LEVEL*
following:-
1 Describe number systems, base conversions, binary codes, complements and apply 1 C-2
those concepts in computer arithmetic. Explain different simplification methods i.e
Boolean algebra, map method and Quine-McCluskey minimization algorithm and
use them in simplifying functions and optimized logic circuit design.
2 Analyze combinational and sequential circuits of moderate complexity from given 2 C-3
circuit diagram, table, equations or timing waveforms.
3 Design combinational and sequential circuits of moderate complexity within given 3 C-3
hardware constraints.
4 Implement, test, and debug prototype digital systems using standard laboratory 4 P-4
equipment and also demonstrate basic skills in working with hardware description
language (Verilog) in the design and analysis of digital logic circuits.
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 National University of Sciences & Technology (NUST)
School of Electrical Engineering and Computer Science (SEECS)
Department of Electrical Engineering


* BT=Bloom’s Taxonomy, C=Cognitive domain, P=Psychomotor domain, A=Affective domain

Mapping of CLOs TO Program Learning Outcomes

PLOs/ CLOs CLO-1 CLO-2 CLO-3 CLO-4
PLO1 (Engineering Knowledge ) √
PLO2 (Problem Analysis) √
PLO3 (Designing/Development of Solutions) √
PLO4 (Investigation)
PLO5 (Modern tool usage) √
PLO6 (The Engineer and Society)
PLO7 (Environment and Sustainability)
PLO8 (Ethics)
PLO9 (Individual and Team Work)
PLO10 (Communication)
PLO11 (Project Management)

PLO:12 (Lifelong Learning)

Mapping of CLOs to Assessment Modules and Weight ages ( in accordance with NUST
statutes)
To be filled in at the end of the course

CLOs\PLOs CLO-1 CLO-2 CLO-3 CLO-4

Quizzes: (9.0%) √ √ √
Assignments: (4.5%) √ √ √
Class Participation (1.5%) √ √ √
OHT-1: (12%) √
OHT-2: (12%) √ √
Labs: (17.5%) √
Project: (7.5%) √
End Semester Exam: (36%) √ √ √
Total: 100%

Books:
Text Book: Digital Design(Fourth Edition) by M. Morris Mano and Michael Ciletti
Reference 1. Digital Design(Fifth Edition) by M. Morris Mano and Michael Ciletti
Books: 2. Digital Fundamentals (Tenth Edition) by Floyd
3. Logic and Computer Design Fundamentals (Fourth Edition) by M. Morris Mano and Charles R.
Kime
4. Fundamentals of Logic Design (Fifth Edition)by Charles H. Roth Jr
5. Digital Systems: Principles and Applications (Tenth Edition) by Tocci Widmer
6. Contemporary Logic Design (Second Edition) by Randy H. Katz
7. Verilog HDL: A guide to Digital Design and Synthesis (Second Edition) by Samir Palnitkar
8. Fundamentals of Digital Logic with Verilog Design (Second Edition) by Stephen Brown|Zvonko

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 National University of Sciences & Technology (NUST)
School of Electrical Engineering and Computer Science (SEECS)
Department of Electrical Engineering

Main Topics to be Covered:
1. Digital Systems. Binary Numbers. Number Base Conversions. Octal and Hexadecimal Numbers.
Complements. Signed Numbers. Binary Codes.
2. Basic Definitions. Axiomatic Definition of Boolean algebra. Basic Theorems and Properties of
Boolean Algebra
3. Boolean Functions. Canonical and Standard Forms. Other Logic Operations. Digital Logic Gates.
Integrated Circuits
4. The K-Map Method. Four-Variable Map. Product of Sums and Sum of Products simplifications.
Introduction to Five-Variable Map. Quine-McCluskey minimization technique (Tabulation).
5. Don't-Care Conditions. NAND and NOR Implementation. Other Two-Level Implementations
6. Combinational Circuits. Analysis Procedure. Design Procedure. Binary Adder-Subtractor. Decimal
Adder. ALU Design using Combinational Circuits.
7. Binary Multiplier. Magnitude Comparator. Decoders. Encoders. Multiplexers
8. Sequential Circuits. Latches and Flip-flops
9. Analysis of Clocked Sequential Circuits.
10. Mealy and Moore FSM. State Reduction and Assignment. Design of clocked sequential circuits.
11. Registers. Shift Registers. Ripple Counters
12. Synchronous Counters. Other Counters

Lecture Breakdown:

Week Lecture Topics Text Book Other References Remarks
No Reference

1. 1. Introduction: Course introduction 1-1

2 Digital Systems and motivation for study,

Course Policies
3. Number Systems: Binary, Octal, Decimal 1-2,1-3,&1-4 1-2 Ref Book(3)
and Hexadecimal Numbers.
4. Base Conversions. 1-5 .

5 Complements: Subtraction of Unsigned

Numbers using Complements.
2. 6. Signed Binary Numbers Arithmetic: 1-6 2-6 Ref Book(2)
Addition and Subtraction of Signed Binary
Numbers.
7. Binary Codes. 1-7

8. Binary Storage and Registers. 1-8 & 1-9

Binary Logic: Definition of Binary Logic and

Logic gates.

Lab 01 Familiarization of Basic Gates and Digital

ICs , Introduction to Verilog HDL.

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 National University of Sciences & Technology (NUST)
School of Electrical Engineering and Computer Science (SEECS)
Department of Electrical Engineering

Basic language constructs and design entry
using Verilog HDL.
3. 9. Introduction: Boolean Algebra: Basic and 2-1,2-2, &2-3 2-2 Ref Book(3)
Axiomatic Definition of Boolean Algebra;
Two-Valued Boolean Algebra.
10. Basic Theorems and Properties of Boolean 2-4
Algebra.
11. Boolean Functions; Canonical and Standard 2.5 &2-6
Forms.
Lab 02 Derivation of Boolean Functions from given
logic diagram and its Hardware
implementation.
Function implementation using Verilog HDL
Gate-Level modeling.
4. 12. Other Logic Operations. 2-7 8-1 Ref Book (5)
13. Digital Logic Gates and Integrated Circuits. 2-8&2-9

14. Introduction: The K-Map Method; Two, 3-1 & 3-2 5-2 Ref Book(4)
and Three -Variable K-Maps. Sum-of-
Products (SOP) simplification using Three-
Variable K-Map.
Lab 03 Minimization of Boolean Functions and its
Hardware implementation.
5. 15. Sum-of-Products (SOP) simplification using 3-3 5-3 Ref Book(4)
Four-Variable K-Map; Essential and Non- 2.5 Ref Book(3)
essential Prime Implicants.
16. Five-Variable K-Map; Sum-of-Products 3-4 5-4 Ref Book(4)
(SOP) simplification using Map Method.

17. Product- of- Sums (POS) Simplifications and 3.5&3-6

Don’t Care conditions.
Lab 04 Design of Binary-to-Gray/Gray-to-Binary
Code Converter using basic gates.
Gate-Level Modeling of Combinational
Circuits using Verilog HDL.
6. 18. Quine-MacCluskey Minimization algorithm 6-1, 6-2 &6.3 Ref
(Tabulation). Book(4)
19. NAND and NOR implementations. 3-7

20. Other Two-Level implementations. 3-8

Lab 05 BCD-to-Seven Segment Decoder Design.

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 National University of Sciences & Technology (NUST)
School of Electrical Engineering and Computer Science (SEECS)
Department of Electrical Engineering

7. OHT-1

8. 21. Exclusive-OR function: Parity Generation 3-9

and Checking.
22. Introduction: Combinational Circuits: 4-1, 4-2 & 4-4
Design Procedure with Code Conversion
Example.
23. Combinational Circuits: Analysis 4-3
Procedure.
Lab 06 Design of a 2-bit Magnitude Comparator
using Classical design method.
Combinational Logic Design using Verilog
HDL.

9. 24. Half and Full Adders: Design of 4-BIT 4-5

Ripple Carry Adder-Subtractor using Full
Adders.
25. Design of 4-Bit Adder-Subtractor with 4-5
Carry Look-ahead Generator and
Overflow.
26. Decimal Adder. 4-6

Lab 07 Design of a 2-bit Adder/Subtractor Circuit.

Combinational Logic Design using Verilog
HDL.
10. 27. Binary Multiplier. Magnitude Comparator. 4-7&4.8
28. Decoders/De-multiplexers. 4-9
29. Encoders. 4-10
Lab 08 Design of 4-bit ALU.
11. 30. Multiplexers and Tri-State Gates. 4-11 4-2-2, 3, &4 Book (6)
31. Problem Solving Session

32. Introduction: Sequential Circuits and 5-1&5-2

different types of Latches.
Lab 09 Voting Machine Design.
12. 33. Storage Elements: Latches 5-3

34. Storage Elements: Flip-Flops, Other Flip- 5-4 11-4,11-5,11-6 &11-

Flops, Conversion of Flip-Flops. 7 Ref Book (4)
35. Analysis of Clocked-Sequential Circuits; 5-5
State Equations, State Table, State
Diagram, and Flip-Flop input equations.

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 National University of Sciences & Technology (NUST)
School of Electrical Engineering and Computer Science (SEECS)
Department of Electrical Engineering

Lab 10 Memory Elements: Latches and Flip-flops.
Design of a positive-edge triggered D flip-
flop.
13. OHT-2

14. 36. Analysis with D Flip-Flops, JK Flip-Flops, 5-5

and T Flip-Flops.
37. Mealy and Moore Models. Mealy-Moore 5-5
Conversion Procedure.
38. State Reduction using Row Matching and 5-7 15.3 Ref Book(4)
Implication Table Techniques. State
Assignment Method.
Lab 11 Flip-Flop Applications & Proteus
Simulation of Digital Circuits
15. 39. Design Procedure- 5-8
Synthesis using D Flip-Flops.
40. Design Procedure- 5-8
Synthesis using JK Flip-Flops, and T Flip-
Flops.
41. Problem Solving Session

Lab 12 Sequence Detector Design.

Sequential Logic Design using Verilog HDL
16. 42. Introduction: Registers with Parallel Load. 6-1
43. Shift Registers; 4-Bit Shift Register; Serial 6-2
Transfer and Serial Addition.
44. 4-Bit Universal Shift Register. 6-2
Project Work

17. 45. Ripple Counters; Binary and BCD Ripple 6-3

Counters.
46. Synchronous Counters: Binary and BCD 6-4
Counters.
47. Other Counters; Counter with unused 6-5
States.
Project Progress Presentations/Demonstration

18. 48. Other Counters: Counters with unused 6-5

states, Ring Counters and Johnson
Counters.
49. Problem Solving Session

50. Course Revision

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 National University of Sciences & Technology (NUST)
School of Electrical Engineering and Computer Science (SEECS)
Department of Electrical Engineering

Project Final Presentations/Demonstration
19. End Semester Exam

Lab Experiments:
Lab 1: Familiarization of Basic Gates and Digital ICs , Introduction to Verilog HDL. Basic language
constructs and design entry using Verilog HDL.

Lab 2: Derivation of Boolean Functions from given logic diagram and its Hardware
implementation.Function implementation using Verilog HDL Gate-Level modeling.
Lab 3: Minimization of Boolean Functions and its Hardware implementation.
Lab 4: Design of Binary-to-Gray/Gray-to-Binary Code Converter using basic gates.Gate-Level Modeling of
Combinational Circuits using Verilog HDL.

Lab 5: BCD-to-Seven Segment Decoder Design.

Lab 6: Design of a 2-bit Magnitude Comparator using Classical design method. Combinational Logic
Design using Verilog HDL.

Lab 7: Design of a 2-bit Adder/Subtractor Circuit. Combinational Logic Design using Verilog HDL.

Lab 8: Design of 4-bit ALU.

Lab 9: Voting Machine Design.

Lab 10: Memory Elements: Latches and Flip-flops. Design of a positive-edge triggered D flip-flop.
Sequential Logic Design using Verilog HDL

Lab 11: Flip-Flop Applications & Proteus Simulation of Digital Circuits

Lab 12: Sequence Detector Design. Sequential Logic Design using Verilog HDL

Grading Policy:
Quizzes Policy The quizzes are a mandatory component of the overall assessment. The purpose of quizzes
is to keep the students up-to-date with the lecture material and test basic understanding
of the Course concepts. There will be at least 6 unannounced quizzes conducted in the
class any time during the lecture. Each quiz will consist of questions that target specific
topics from the most recent as well as previous week lectures.

Assignments In order to give sufficient practice and comprehensive understanding of the subject, two
types of home assignments will be given. One type will be practice assignments, which
will be given at the end of week for practice. The practice assignments will not be
evaluated, however the discussion forum could be used for suggesting hints for answers.

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 National University of Sciences & Technology (NUST)
School of Electrical Engineering and Computer Science (SEECS)
Department of Electrical Engineering

The students will be evaluated based on participation statistics in discussion forum and
will be given marks in category of class participation.

Second type of assignment will be given on completion of every chapter, on submitting

you have to declare that which questions you attempted yourself. The evaluated
assignment is an individual effort and no hints will be posted on forum. Only declared
questions by individual student will be evaluated. If the declared question done by you is
found a copy of other then you may loose all the marks in assignments and get zero in
assignments. The assignment marks will be taken from Assignment Quizzes.

Conduct of Labs The labs will be conducted for three hours each week. For the conduct of lab the students
will be divided into groups with 2 students per group. A lab handout comprising pre-lab,
in- lab, and post-lab report parts will be provided to students for study and analysis during
the week preceding each lab session. The students are expected to complete pre-lab work
before lab starts and also come prepared for the lab. Any student failing to complete pre-
lab will not be allowed to attend lab session. The students will be evaluated during each
lab on the basis of demonstration, oral viva, and lab report submitted by them individually
on completion of lab work. The students are required to be punctual in the lab; latecomers
will not be allowed in the lab. No make-up provisions for the missed labs. Each lab is
evaluated by Viva and lab report by Lab Engineer.
A comprehensive lab test will be arranged during closing weeks of semester and students
will be individually evaluated accordingly.
Design Projects The students will be allocated course projects during the week preceding mid semester
exam and evaluated before final exams based on parameters spelled out in Project
Reservation form provided to them. The students will be grouped into syndicates with
each syndicate having a maximum strength of 3 students depending upon the complexity
level of design. However, any student desirous of carrying out design work individually will
be encouraged and graded in the same pretext. The students are advised to select project
titles well before their submission schedule.
Other Matters:
Academic Honesty and Plagiarism
Plagiarism is the unacknowledged use of other’s work, including the copying of
assignments and laboratory results from the other students. Plagiarism is considered
a serious offence by the university and severe penalties apply. Therefore, all the
students must display originality of efforts and avoid plagiarism in any form.
Classroom Etiquettes
It is the collective responsibility of all the students to make the class environment
conducive for learning. To create and maintain a friendly atmosphere, the following
standards of class room behavior will be observed: -
1. Students will be punctual for the class. The teacher considers late comers
disrespectful of those who manage to be on time.
2. If a student decides to attend the class, he or she will not disrupt class by
leaving before the lecture has ended.
3. All the cell phones must be switched OFF prior to entering the class room.
Tools / Software Requirement:

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 National University of Sciences & Technology (NUST)
School of Electrical Engineering and Computer Science (SEECS)
Department of Electrical Engineering

1. Verilog Hardware Description Language (Verilog HDL) software and HDL simulator
ModelSim version 5.7f will be used for the design and simulation of logic circuits.
2. Digital and Embedded System lab will be used for hands on practice.

Forum for Communication and Addressing any Questions & Answers:

For online discussions among students and Faculty Piazza forum is used. The students are encouraged to ask
any questions related to the course for better learning value of the subject.

Following link is used for the forum sign up.

https://piazza.com/seecs.edu.pk/fall2017/ee221/home

The students are required to register on above link and use it for addressing any question or discussion or
for polling for an opinion.

Please participate on course discussion forum. Your participation in the forum will be evaluated.

Facebook Group Page for more interactivity

Enable you to give question/answers or share any material with the group members. Following link is
used for the group page. 


https://www.facebook.com/groups/903840203101774/

You may opt to participate on course discussion group.

Online Consultation through Skype and Google Hangout

You can discuss any question related to the course in allocated online consultation hours. Besides the
consultation hours you can take an appointment through email. 


Skype ID : teacher.nasir 


Online Consultation through google hangout 


You may interact and discuss any question or clarify your concepts by hosting a google hangout meeting
with your teacher or class mates. 


Faculty email : nasirm15@gmail.com

BEST OF LUCK FOR INDEPTH LEARNING OF THE SUBJECT KNOWLEDGE 


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 National University of Sciences & Technology (NUST)
School of Electrical Engineering and Computer Science (SEECS)
Department of Electrical Engineering

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