Fpga and HDL: Electronics Club

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Electronics Club

FPGA and HDL


What is an FPGA
FPGA or field programmable gate arrays are integrated circuits similar to CPUs
and other microcontrollers only difference being that the circuit inside the
FPGA can be modified any number of times. The circuit inside FPGA are defined
using Hardware description language or HDL. There are two major HDLs, VHDL and
verilog. We will look into them today.
HOW DOES AN FPGA WORK?
FPGAs consist mainly of three elements: Look up tables
(LUTs), flip-flops, and the routing matrix.

Look up Tables:

A LUT consists of a block of RAM that is indexed by the


LUT's inputs. The output of the LUT is whatever value is in
the indexed location in its RAM.
A 2-input LUT:

Address (In[1:0]) Output (Value Stored at that Address)

00 0

01 0

10 0

11 1
Routing matrix
So why FPGA?
The main reason why FPGAs are used is because of parallel
processing. A microprocessor performs any given task
sequentially, while an FPGA can be reconfigured to perform a
very specific task. This makes it faster than any
microprocessor.
Software programming language
Let us first see how a software programming language works.
A software programming language executes in a sequence i.e.
the code runs from top to bottom unless of course you use
go-to, loop etc. But the important point is in a software
programming language, only one line is executed at a time.
The code that you write is compiled and is converted into
simpler instructions which the processor can understand.
These instructions are then fed into the processor which
then processes them.

The disadvantage of this process is that the processor has


to process all the different types of information. This
means that it can’t be optimised to do a certain process
faster.
Hardware description language
There are two major hardware description languages- Verilog
and VHDL similar to C. But unlike software programming
languages, these do not execute sequentially, but parallely.

We will explain this in more detail.


Verilog
Sample verilog code
Analyzing the code
Module : Modules are simple elements in verilog with inputs
and outputs. Instances of a module can be created in the
main code.

In this case, the module take A and B as inputs and outputs


C.
Analyzing the code
Wires and Registers : There are two new data-types in
Verilog; wires and registers. A wire acts like a physical
wire; it connects two points in the circuit. A register is
an element that is used to store memory. A register is able
to store only one bit

Assign : It creates a connection between wire C and A&B.


Note that since this is not a sequential code, whenever the
inputs A and B are changed, the change will also be
reflected in C.
Creating a simple switch
Analyzing the code
Initializing register value : The register led_reg is
initialized with the value 1’b1. That is, the register is
initialized with a one bit binary number of value 1.

The Always block : The always block is executed when the


statement inside the parenthesis is true. Here, the
statement “posedge button” will be true whenever a positive
edge of the wire button is encountered. In that case, the
register led_reg will flip its state.
.ucf files
Now that we were able to simulate the code for a switch, we
would like to actually implement it on an FPGA.

How do we tell the FPGA that the wire button corresponds to


an actual push-button?

How do we tell the FPGA that the wire led should be


connected to a physical LED present on the board?

The task of connecting the input/outputs of a module to the


GPIO pins/onboard LEDs/pushbuttons is done by the .ucf file.
.ucf files
The syntax is: NET “name” LOC = “pin_number”;

Here, the pin numbers for the onboard LED and pushbutton are
U8 and AF13
Creating a clock
The FPGA board usually has a clock of frequency 100 MHz or
50 MHz. In the following example, we will see how to create
a clock of much lower frequency.
Analyzing the code
Array of registers : We can create an array of registers by
using the following syntax: reg [length - 1 : 0] array_name.

Logic: After every clock pulse of the 100 MHz clock, the
register counter is incremented by one bit. Since the
register is three bits long, after 8 such clock pulses, the
most significant bit of the register gets flipped. This is
connected to the wire clk_12_5. Hence, the frequency of this
clock is 12.5 MHz.
Data structures in Verilog
Random access memory
RAM is a basic data structure which can be configured to
have multiple inputs and outputs. A RAM supports 2
functions, Read and write. A RAM takes an address as one
argument. The data at this address can be read or it can be
overwritten using write enable. Since any address can be
accessed at any point in time, hence the name Random Access
Memory.
VHSIC Hardware Description Language
VHSIC Hardware Description Language


HDLs vs. Software Languages

In VHDL :Concurrent (parallel) Statements


vs.
Sequential Statements
• Two components to the description:

ENTITY: The interface to the design: entity declaration i.e


inputs,outputs,

ARCHITECTURE: The internal behaviour of the


design: architecture construct.
Component (socket mechanism) adder
Process.
The Sensitivity list.
etc.
Signals and variables.

Signal :It is a physical signal (you can think of it like a piece of wire).
A signal assignment takes effect only after a certain delay (the
smallest possible delay is called a “delta time”).

Variable : Assignment to variables are scheduled immediately (the


assignment takes effect immediately)Typically, variables are used
as a local storage mechanism, visible only inside a process
architecture bad of logic is
signal a_or_b : std_logic;
begin
logic_p: process(a,b,c)
begin
a_or_b <= a or b;
z <= a_or_b and c;
end process;
end bad;
architecture good of logic is
variable a_or_b : std_logic;
begin
Use variables for
logic_p: process(a,b,c) immediate operation
begin
a_or_b := a or b;
z <= a_or_b and c;
end process;
end good;
process (a)
variable c;
begin
c:= a or b;
z <= c;
end process;
Incomplete sensitivity list effect

process (a)
variable c;
begin
c:= a or b;
z <= c;
end process;
Do not “read” and “write”
a signal at the same time !!!
Assignment operator

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