F4 : Latches, Flip-Flops, Data buses &

Resolved functions
Latches & Flip-Flops
 SR-Latch

R Q+ Qn+
Q SR =
Q Qn 00 01 11 10
00 11 01 00 10
Q 01 01 01 00 00
S
11 00 00 00 00
10 10 00 00 10
 Gated SR-Latch

R
Q
C
Q
S
 D-latch

D
Q

C
Q

D q

Clk
 Master-Slave Flipflop

D q

Clk

D q

Clk
 Edge-triggered Flipflop

Q
Clk
Q

D
 Latches /MUXES

Mux:
a 1
process(a,b,sel) q
begin
b
if (sel='1') then 0
q<=a;
else
q<=b; Sel
end if;
end process;
 Latches

Latch:
D 1
process(D,clk) q
(a)
begin
if (clk='1') then 0
q<=D;
end if;
end process; Clk
(Sel)
 Flip-flop

D 1 1
q

0 0

Clk
D q

Clk
 Flip-flop

process(clk) -- synthesis might complain that d is not listed

begin
if (clk='1') and clk'event then
q<=d;
end if;
end process;
 Signal Attributes

signal s:bit;
s

s'event =
s'active =
now
s'stable(5 ns) =
activation
s'quiet(5 ns) =
不影响event
s'transaction =
 Signal Attributes

signal s:bit;

s'delayed(5 ns) =
s'last_event =
s'last_active =
s'last_value =
 异步复位
D-latch with asynchronous reset

Latch:
process(D,reset,clk) D 1
begin
q
if (reset=‘0’) then
q<='0'; 0
elsif (clk='1') then Reset
q<=D;
end if; Clk

end process;
 D-latch with synchronous reset
Latch:
process(D,reset,clk)
begin D
1
Reset
if (clk='1') then q
if (reset='0') then
q<='0';
0
else
q<=D;
end if;
Clk
end if;
end process;
 D-flipflop with asynchronous reset

D 1 1
q

0 0

Reset
D q
Clk Clk
Clk

Reset
 Asynchronous reset

process(clk,reset) -- synthesis might complain that d is not

-- listed
begin
if (reset='0') then
q<='0';
elsif (clk='1') and clk'event then
q<= D;
end if;
end process;
 同步复位
D-flipflop with synchronous reset

D 1 1
Reset
q

0 0

D q
Clk Clk
Reset

Clk
 Synchronous reset
process(clk) -- synthesis might complain that neither d nor
-- reset is listed
begin
if (clk='1') and clk'event then
if (reset='0') then
q<='0';
else
q<= D;
end if;
end if;
end process;
 Registers
D(0 to N-1) Q(0 to N-1)

Clk
 Structural description
USE work.all;
ENTITY d_register IS
generic( N:integer );
port( D:IN bit_vector(N-1 DOWNTO 0);
clk:IN bit;
Q:OUT bit_vector(N-1 DOWNTO 0));
END d_register;
ARCHITECTURE structure OF d_register IS
COMPONENT dflipflop -- IS is allowed in VHDL’93 Not very efficient!!!
port( D:IN bit;
clk:IN bit;
Q:OUT bit);
END COMPONENT; -- COMPONENT keyword may be skipped in VHDL’93
BEGIN
U0:FOR i IN 0 TO N-1 GENERATE
R0:dflipflop PORT MAP (D(i),clk,Q(i));
END GENERATE ;
END d_register;
 Sequential description (RTL-style)

ARCHITECTURE behave OF d_register IS

BEGIN
VERY efficient!!!
PROCESS(clk)
BEGIN
IF clk'EVENT AND (clk='1') THEN
q<=D;
END IF;
END PROCESS; The datatype decides the size
END behave;
Synthesis of Latches & Flip-Flops
 顺序执行
Sequential Statements
The statements within a
 During simulation the statements
process are executed are executed one after the other but it
sequentially. does not model the delay of addition.

process(a,b,c,y)
begin
a <= b +c; +
p <= a + y;
end;
+
 Variable as Wire

... a
end process; b
process(a,b)
variable x,y;
begin
+
... 1
x := a + b; x
y := x + 1;
...
end process; +
... y
 Variable as Latch

process(a,b) a
variable x,y,z; b
begin
...
if cond = '1' then +
x := a + b;
end if; cond
y := x + 1;
... Latch (x)
end process;
1
+
y
 Edge Expressions and Clocked
Bodies
Edge Expressions  There is no explicit
signal'event and signal ='1' concept of clock in VHDL.
signal'event and signal ='0' The synthesis tool has to
infer the clock.

 A WAIT or IF statement
Edge Expressions is normally used to make
process (x,y,z); the sequential behavior
begin synchronous.
if x'event and x = '0' then
...
end if;
 Register/Latch Inference Rules

Type of Body

Clocked Body Non Clocked Body

Signals Variables Signals & Variables

Driven in all Not driven in
RBW: Read before write
RBW WBR branches all branches
WBR: Write before read

Flip-flops Wires Latch

Synchronous Behavior: Restrictions

process (clk) process (clk_a, clk_b)

begin begin
if (clk'event and if (clk_a'event and
clk = '1') then clk_a = '1') then
p <= a+b; p <= a + b;
else end if;
q <= a-b; if (clk_b'event and
end if; clk_b = '1') then
end process; q <= a + b;
end if;
end process;

无edge Illegal! Only one clock allowed!

separate two clock stateme
nts in two separate process
 Sensitivity List and Synthesis
• The sensitivity list is very important for
making the simulation efficient but it is
not used by the synthesizer. x
y z
process (x)
begin
z <= x and y; --z is only evaluated
-- when there is a
-- change in value of x
Be careful, when you
end; use a sensitivity list
that does not include
all values!
 Watch out for Latches in your
design!!!
• Latches have unpredictable timing behavior that
makes it very hard to create a functioning design
– Avoid them at all costs
– Use DFF’s instead

– Look for them in the synthesis reports, if there is one

left, there is a high chance that your design will not
work.
 Exercise
• What will be the synthesis result of the following
code?

ENTITY SYNQ IS ARCHITECTURE Alg OF SYNQ IS

SIGNAL x : bit;
PORT ( BEGIN -- Alg
A : IN bit; x <= c(b);
b : IN integer RANGE 0 TO 3; PROCESS(x,a)
c : IN bit_vector(0 TO 3); BEGIN
d : OUT bit); IF a = '1' THEN
d <= x;
END SYNQ; END IF;
END process;
END Alg;
 Tricky Example - 1
• What will be the synthesis result of the following
code?

LIBRARY ieee; Architecture behave of incr is

USE ieee.std_logic_signed; begin
ENTITY incr IS Process(clk,reset)
variable sum:std_logic_vector(3 downto 0);
PORT ( Begin
A : IN std_logic_vector(3 downto 0); if (reset='0') then
Q : OUT std_logic_vector(3 downto 0) q<=(others='0');
); elsif rising_edge(clk) then
sum:=sum+1;
END incr; Q<=sum+A;
end if;
End behave;
 Tricky Example - 2
• What will be the synthesis result of the following
code?

LIBRARY ieee; Architecture behave of incr is

USE ieee.std_logic_signed; signal sum:std_logic_vector(3 downto 0);
ENTITY incr IS begin
Process(clk,reset)
PORT ( Begin
A : IN std_logic_vector(3 downto 0); if (reset='0') then
Q : OUT std_logic_vector(3 downto 0) q<=(others='0');
); elsif rising_edge(clk) then
sum<=sum+1;
END incr; Q<=sum+A;
end if;
Q,q区分 End behave;
Databuses & Resolution
Functions
 Data buses

En(0 to N-1)
How do we model bus-
D(0 to N-1) wires?

Clk
 Bus Resolution in VHDL
• VHDL does not allow multiple concurrent signal assignments to the
same signal
– Multiple sequential signal assignments inside a process are
allowed (last assignment will be kept)
-- this code will generate an error
ENTITY bus IS
PORT (a, b, c : IN bit; z : OUT bit);
END bus;

ARCHITECTURE smoke_generator OF bus IS

SIGNAL circuit_node : bit;
BEGIN
circuit_node <= a;
circuit_node <= b;
circuit_node <= c;
z <= circuit_node;
END smoke_generator;
 Bus Resolution in VHDL (ctd.)
• If a signal has a bus resolution function associated with it, then the
signal may have multiple drivers

USE WORK.my_bus_resolution.ALL;

ENTITY bus IS
PORT (a, b, c : IN bit; z : OUT bit);
END bus;

ARCHITECTURE fixed OF bus IS

SIGNAL circuit_node : wired_and bit;
BEGIN
circuit_node <= a;
circuit_node <= b; a
circuit_node <= c;
z <= circuit_node; b
END fixed; c
Signal Resolution and Buses
Execution phase Signal update phase

Transaction queue

OR

Bus Resolution Function Resolved

signal

AND
 Bus Resolution Functions
• VHDL uses bus resolution functions to resolve the final value of
multiple signal assignments

FUNCTION wired_and (drivers : bit_vector) RETURN bit IS

VARIABLE accumulate : bit := '1';
BEGIN
FOR i IN drivers'RANGE LOOP
accumulate := accumulate AND drivers(i);
END LOOP;
RETURN accumulate;
END wired_and;

 Bus resolution functions may be user defined or

called from a package
Bus resolution effects on Port Modes

• The port mode of the interface describes the direction of the data
flow with respect to the component

• The five types of data flow are

– In - data flows in this port and can only be read
– Out - data flows out of this port and can only be written to
– Buffer - data flow can be in either direction but only one source is
allowed at any one time
– Inout - data flow can be in either direction with any number of sources
allowed (implies a bus)
– Linkage - data flow direction is unknown
 IEEE standard 1164

type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');

'U' - Uninitialized
'X' - Forcing Unknown
'0' - Forcing Zero
'1' - Forcing One
'Z' - High Impedance 高阻抗
'W' - Weak Unknown
'L' - Weak Zero
'H' - Weak One
'-' - Don’t Care
 std_logic

type std_logic is resolved std_ulogic;

type std_logic_vector is array(integer range <>) of std_logic;

type std_logic_LUT is array(std_logic,std_logic) of std_logic;

二重数组
 std_logic Resolved function
Function resolved(input:std_logic_vector) return std_logic is
constant resolve_table:std_logic_LUT:=(…);
variable res:std_logic:='Z';
begin
for i in input'range loop
res:=resolve_table(res,input(i));
end loop;
return res;
end resolved;
 std_logic Resolved function
Function resolved(input:std_logic_vector) return std_logic is
constant resolve_table:std_logic_LUT:=(
-- ‘U’,‘X’, ‘0’, ‘1’, ‘Z’,‘W’,‘L’,‘H’, ‘-’
( ‘U’,’U’,’U’,’U’,’U’,’U’,’U’,’U’,‘U’), -- ‘U’
( ‘U’,’X’,‘X’,‘X’,’X’,’X’, ‘X’,’X’,’-’), -- ‘X’
( ‘U’,’X’, ’0’,’X’, ’0’,’0’, ‘0’, ‘0’, ‘-’), -- ‘0’
( ‘U’,’X’,‘X’, ’1’, ‘1’,’1’, ‘1’, ‘1’, ‘-’), -- ‘1’
( ‘U’,’X’, ‘0’, ‘1’, ‘Z’,’W’,’L’,’H’,’-’), -- ‘Z’
( ‘U’,‘X’, ‘0’, ‘1’,‘W’,’W’,’W’,’W’,’-’), -- ‘W’
( ‘U’,’X’, ‘0’, ‘1’,’L’, ‘W’,’L’,’W’,’-’), -- ‘L’
( ‘U’,’X’, ‘0’, ‘1’,’H’,’W’,’W’,’H’,’-’), -- ‘H’
( ‘U’, ’-’, ‘-’, ‘-’, ‘-’, ‘-’, ‘-’, ‘-’, ‘-’)); -- ‘-’
Example: D-Flipflop with Tri-state
enable

En

D Q

Clk
 Example: I2C (CAN)-bus protocol

0 Single wire used

both for arbitration
and communication
in any direction!!!

1 2 3 4
 How accurate is the
VHDL Resolution model?

VDD
VL
VOH N connected Units
VL
VSS
 高低电平
Voltage levels

VOH VH

Noise Margin
VOL VL

TTL VH>2.4 V, VL<0.8 V, VOH=3.3 V, VOL=0.4V

CMOS VH>90% of VDD -VSS, VL<10% of VDD -VSS

 Representation of 1’s and 0’s

VOH = 3.3V 'H', '1'

VIH = 2.4V
'W', 'X'
VIL = 0.8V
VOL = 0.4V 'L', '0'

Ri
~10 Mohms => 'Z'

Vi Ri = ~10 kOhms => 'L', 'H', 'W'

~10 Ohms => '0', '1', 'X'

Ohms→欧姆Ω
Physical representation of std_ulogic

Vres
<0.8V >0.8V,<2.4V >2.4V - TTL
Rres <10% >10%, <90% >90% - CMOS (% of VDD-VSS)

<1kOhm '0' 'X' '1'

>1kOhm, <1MOhm 'L' 'W' 'H'

>1 MOhm (TTL)

'Z' 'Z' 'Z'
>1 GOhm (CMOS)
Equivalent Two-pole of output stage

VDD R
VL
VOH V=VOH
V
R=ROH
VL
VSS
Equivalent Two-pole of output stage

VDD R
VH
VOL V=VOL
V
R=ROL
VH
VSS
 '0' - Forcing Zero
R
VDD
VH
VH
VOL V
VL V VH
VSS

'0' '1'
V<VL '1'
R~10 Ohms
 'H' - Weak High (Open Drain)
R
VDD
VH V

VOH V
VL VL

VSS

VDD
'0'
VH<V 'H'
R~10 kOhms
 'Z' - High Impedance
R
VDD
VH
VH
V=?
V=?
VL VL

VSS

'0' '0'
'Z'
V=?
R~10 MOhms (TTL)
10 GOhms (CMOS)
 Two-pole equivalent

Vres

R1 R2

V1 V2

Rres = R1||R2

Vres = V1*R2/(R1+R2)+V2*R1/(R1+R2)
 Example: 'X' - Forcing Unknown
R
VH

V V
VL

'X' '1'
VL<V<VH '0'
R~10 Ohms
 'X' - Forcing Unknown

VDD VDD
VH VL
VOL VOH
VH VL
VSS VSS
 'X' - Forcing Unknown

Vres
VDD
R1 R2
VL
V=? V1 V2
VH
VSS

V1 = VDD = 5 (V), V2 = VSS = 0 (V), R1 = R2 = RON = 10 (Ohm)

V = (VDD-VSS)*RON/(RON+RON) = VDD/2 = 2.5 (V)
R = RON//RON = RON/2 = 5 (Ohm)
 A ”Real” Resolution Algorithm...

Apply Voltage-division repeatedly until you get final voltage & resistance:
Vres0 = 0 (V), Rres0 = 1 (GOhm)
Vres := Vi *Rres-1/(Ri+Rres-1)+Vres-1*Ri/(Ri+Rres-1)
Rres := Ri*Rres-1/(Ri+Rres-1)
Final check:
if Rres> 1 (MOhm) then return 'Z';
elsif Vres> 0.9*VDD then
if Rres> 1 (kOhm) then return 'H'; else return '1'; end if;
elsif Vres> 0.1*VDD then
if Rres> 1 (kOhm) then return 'W'; else return 'X'; end if;
else
if Rres> 1 (kOhm) then return 'L'; else return '0'; end if;
end if;
 Final Result table

Vres
<0.8V >0.8V,<2.4V >2.4V - TTL
Rres <10% >10%, <90% >90% - CMOS (% of VDD-VSS)

<1kOhm '0' 'X' '1'

>1kOhm, <1MOhm 'L' 'W' 'H'

>1 MOhm (TTL)

'Z' 'Z' 'Z'
>1 GOhm (CMOS)
 Example – ”Real” Resolution
functions 扇入/扇出
• How many Open Drains ('H') can be connected to
a Forcing Zero ('0') before the Forcing Zero goes
into the unknown region?

• How many Open Source ('L') can be connected to

a Forcing One ('1') before the Forcing One goes
into the unknown region?
Appendix
Dataflow Modeling of Tri-state
functionality
 Dataflow modeling

Concurrent statements:

U0: q0 <= a and b ;

U1: q1 <= f(a,b);
U2: and_gate port map(q0,q1,q2);
Concurrent If-statements

q <= '1' when sel="00"

else d(0) when sel="01"
else d(2) when sel="10"
else '0';
Concurrent Case-statement

with sel select

q<='1' when "00",
d(0) when "01",
d(2) when "10",
'0' when others;
 Data flow Modeling of Latches &
Flipflops

-- D-latch
q<=D when clk='1' else q;

-- D-flipflop
q <= D when clk'event and (clk='1') else q;
q <= D when (NOT(clk'STABLE) AND (clk='1') AND

(clk'LAST_VALUE='0')) else q;
 Tristate Modeling - Null Transaction

• How can a driver be disconnected (i.e., not influencing the output at

all)?
– Use the null waveform element
• Example
bus_out <= null after 17 ns;
 Bus & Register construct

• What happens if all drivers of a resolved signal are disconnected?

– Use register kind in signal declaration to keep most recently determined
value
– Use bus kind in signal declaration if resolution function must determine
the value
• Example
signal t : wired_bus bus;
signal u : bit register;
 Blocks and Guards
• Blocks partition the concurrent statements in an architecture such
that conditional activities unique to each block can occur
• A guarded signal assignment statement generates a value only if the
block guard expression is true. If false, the assignment is
disconnected
• Example
ARCHITECTURE guarded_assignments OF n_1_mux IS
BEGIN
bi: FOR j IN i’range GENERATE
bj: BLOCK (s(j)=‘1’ or s(j)=‘Z’)
BEGIN
x <= guarded i(j);
END BLOCK;
END GENERATE;
END guarded_assignments
 The Implicit Guard-signal
• The Guard can also be used as an implicit signal
• Example

ARCHITECTURE guarded_assignments OF n_1_regs IS

BEGIN
bi: FOR j IN regs’range GENERATE
bj: BLOCK (enable=‘1’ and read=‘1’)
BEGIN
x <= regs(j) when guard else “ZZZZZZZZ”;
END BLOCK;
END GENERATE;
END guarded_assignments;
 Modeling Latches using Guarded
Dataflow Style

-- Latch, dataflow style with synchronous reset

U0 : BLOCK(clk=’1’)
signal q_temp:bit;
BEGIN
q_temp<=guarded ’0’ when (reset=’1’) else d;
q<=q_temp;
qbar<=not(q_temp);
END BLOCK;
 Modeling Flipflops using Guarded
Dataflow Style

-- Flipflop, dataflow style with asynchronous reset

U0:BLOCK((NOT(clk’STABLE) AND (clk=’1’) AND (clk’LAST_VALUE=’0’))
OR reset=’1’)
signal q_temp:bit;
BEGIN
q_temp<=guarded ’0’ when (reset=’1’) else d;
q<=q_temp;
qbar<=not(q_temp);
END BLOCK;
 Disconnect statement
entity tristate is
port(a0,a1,a2,a3,en:IN bit;
q0,q1,q2,q3:OUT bit);
end tristate;
architecture data_flow of tristate is
disconnect q0:bit after 1 ns;
disconnect others:bit after 2 ns;
-- disconnect all:bit after 2 ns;
begin
U0:block(en=1)
begin
q0 <= guarded a;
...
end block;
end data_flow;
 Block syntax

block_label: block [ (Guard_expression)] [ is ]

[ generic ( generic_interface_list );
[ generic map ( generic_association_list ); ] ]
[ port ( port_interface_list );
[ port map ( port_association_list ); ] ]
{ block_declarative_item }
begin
{ concurrent_statements }
end block [ block_label ] ;
Electrical Equivalents to
std_logic
 ‘X’ - Forcing Unknown
R
VDD
VH
VL
V V
V=?
VL VH
VSS

‘X’
VL<V<VH ‘0’ ‘1’
R~10 Ohms
 ‘0’ - Forcing Zero
R
VDD
VH
VH
VOL V
VL V VH
VSS

‘0’
V<VL ‘1’ ‘1’
R~10 Ohms
 ‘1’ - Forcing One
R
VDD
VH V
VL
VOH V
VL VL
VSS

‘1’
VH<V ‘0’ ‘0’
R~10 Ohms
 ‘Z’ - High Impedance
R
VDD
VH
VH
V=?
V=?
VL VL

VSS

‘0’ ‘0’
‘Z’
V=?
R~10 MOhms (TTL)
10 GOhms (CMOS)
 ‘W’ - Weak Unknown
R
VDD
VH

V V
V=?
VL

VSS

VDD
‘0’
VL<V<VH ‘W’

R~10 kOhms
VSS
 ‘L’ - Weak Zero (Open Source)
R
VDD
VH
VH
VOL V
VL V

VSS

‘0’
V<VL ‘L’
R~10 kOhms
VSS
 ‘H’ - Weak High (Open Drain)
R
VDD
VH V

VOH V
VL VL

VSS

VDD
‘0’
VH<V ‘H’
R~10 kOhms