International Journal of Applied Engineering Research, ISSN 0973-4562 Vol. 10 No.

68 (2015)
© Research India Publications; httpwww.ripublication.comijaer.htm

REVIEW ON WORD LENGTH OPTIMIZATION

Pandi G Sabareeswari, Bhuvaneswari S Dr Manivannan S
EEE. Dr. M.G.R. Educational & Research Institute EEE, Dr. M.G.R. Educational & Research Institute
University. University
Dr. M.G.R. Educational & Research Institute University Dr. M.G.R. Educational & Research Institute University
Chennai, India. Chennai, India.
Pandieswari@yahoo.co.in

Abstract—This paper proposes the word length optimization Field-Programmable Gate Arrays[FPGA] and Application
for Digital Signal Processor required for real-time applications Specific Integrated Circuits[ASICs] optimizes the bit-width[2]
such as Communication, Signal Processing, design of filter banks reduction results in precision which in turn reduces the cost,
etc. Various algorithms and techniques are discussed for bit- range analysis is useful in finding datapath and reduces
width optimization and allocation of bit-width. The main arithmetic circuits cost. Dynamic analysis based on simulation
objective of this paper is to develop an algorithm which suits for method is helpful in finding numerical range and its analysis.
various applications by achieving area reduction, enhanced speed Data range values were analyzed and optimized by data flow
and minimum power consumption during its operation. Various
graph [DFG].
techniques are also involved in achieving the better performance
of the DSP systems. It can be implemented using suitable Algorithm based on memory packaging were developed
processor. The digital filters plays a significant role in estimating for hardware. Hardware resources requirement was computed
speed, area, power, SQNR values and computational time. Digital based on perturbation theory. Simulink tool was used for
filters should be less prone to filter coefficient changes. The floating-point to fixed-point. It Optimized the data types of
algorithm can also be tested for different sized problems. This fixed-point. Static analysis neglects simulation method.
can be done using software packages such as MATLAB, Verilog Interval arithmetic[IA] method was used for range analysis.
Hardware Description Languages for good precision. The derivative of IA is Affine Arithmetic[AA].Modeling of
AA, computed the range analysis and precision.
Keywords—Bit-Width,SQNR,Optimization.
LTI system used synoptix which is one of the optimization
techniques for optimizing bit-width. SMT and SAT-Modulo
I.  Introduction   theory techniques for allocation of bit-width provides exact
FPGA replaced the conventional method of results compares to IA and AA. More execution time to
implementing digital filters on Digital Signal Processor. The complete each loop is the drawback. Arithmetic
microelectronic techniques finds applications in Transform[AT] is a modern method produces smallest bit-
width as a response[2].Definitive integer part is the first step
Communication Signal Processing, Mobile Communication,
of IA or AA. The second step is to find out the fractional part.
Military Communication, Consumer Electronics etc. Digital
Filters helps to enhance the operating speed, low power The optimization problem should be operated within its
consumption, occupies less area [1,2].Digital filter is a LTI limitations. The choice of optimization algorithm doesnot
filter which is used widely based on linear convolution. Linear depend on the cost function. If the wordlength size is large, the
convolution is mathematically defined as time also increases. Signal grouping techniques reduces the
time significantly[3].Optimization algorithms were proposed
Y[n] = x[n]*h[n] such as GRASP,GRASP-a, Accuracy/Cost based GRASP
n=∞ produced good results and had complexity when compared to
= ∑ x[n]* h[n-k] (1) other methods.
n=-∞ Multiple Constant Multiplication [MCM] operation
Where x[n] is the input sequence, h[n] is the impulse multiplies the variable with a constants. It finds applications in
response of a signal, y[n] is the output. error correcting codes, linear DSP transforms and FIR filters.
MCM performs addition, subtraction and shift operations.
Infinite Impulse Response [IIR] and Finite Impulse
Algorithms were developed to overcome MCM problem [4].
Response[FIR] are the types of LTI filters. The IIR filter
involves more time for calculation and was carried out using The algorithm used less number of addition, subtraction
software tools. The design of FIR filter and its analysis is done and shift operation at gate-level[4]. FIR filter is used
using the FDA and MATLAB tools. FIR filter design should commonly for stabilizing to approach linear phase response.
be incorporated in an architecture by quantizing the filter The transfer function of FIR filter is
coefficients into fixed point representation. The solution is to
round-off the coefficients to b-bit numbers[1]. H(Z)=∑ h[n] z-n (2)
n=-∞

851
 International Journal of Applied Engineering Research, ISSN 0973-4562 Vol. 10 No.68 (2015)
© Research India Publications; httpwww.ripublication.comijaer.htm
The number of multiplication reduction is under The paper sequence is as follows: Basic definitions are
investigation by using sparse filters or frequency response given in Section II. Section III Contribution of previous work
masking filters. Two’s complement method is generally used is discussed. Section IV describes conclusion. Future scope is
to represent the data in DSP systems. Logarithmic Number included in Section V.
System[LNS] replaced the arithmetic operations such as
multiplications, divisions, roots and powers to additions,
multiplication. LNS enhances its properties in low power II. DEFINITIONS 
signal processing system.60% of power can be saved. Most of The paper is focused with basic definitions .The word
the research work is carried out with low power design of high length set[MWS] of a vector is minimum if bmin=(b1
speed multipliers. min
,b2min,……..bnmin) where each bkmin is the minimum
Many algorithms and architectures are proposed to wordlength of kth operator.The process of finding the feasible
improve the multiplication operation. Compared to CPA, solution among the different existing solutions is called as
Wallace Tree Compressor [WTC] were used for area Word length optimization.
reduction and consuming less power by minimizing full
adders and half adders during its operation. As a result, WTC
produces accurate output without the requirement of error
III. CONTRIBUTION OF PREVIOUS 
compensation circuits. WORK 
Linear Phase FIR filters for even symmetry(even order)and In [1], optimization results in low area and better
odd symmetry is quite important in choosing frequency- speed with different quantization values on FPGA using
selective filters such as bank of filters. Choosing of h(k) Xilinx ISE 14.2 version simulator were achieved. The area
determines the shape of Ho(Ω) even function[7].The filter reduction enables the chip to perform for other applications.
coefficients can be symmetric or anti-symmetric[7,8].Direct This in turn reduces the requirement of hardware, The
form and transposed form are the classification of FIR filters. development of C++ algorithm results in overflow error and
They are designed depending upon multiplierless based and
can be minimized with the help of AT compared to IA and AA
memory based. Transposed structure was used in former
which originates from IA. Hence, bit-width minimization,
method and seems to be faster.
correlation of polynomial, faster execution were proposed in
The area reduction is achieved by using Integer Linear [2].
Programming, LUT and distributed arithmetic[DA] are the The optimization for medium and larger sized
methods of memory based type. LUT method helps to realize problems were discussed and its performance were tested in
constant multiplications in MCM and DA methods were used FFT,NLMS,IIR filters using different algorithm such as
to obtain the partial products required for FIR filtering. FIR deterministic, Tabu Search, Greedy, branch and bound
filters should be able to produce rounded outputs[8]. algorithm [5],MILP,MOGA does not results in optimal
IIR filters needs less number of multiplications in solution. The performance of GRASP-a performed better in
comparison with FIR digital filters. IIR filter works faster and comparison with above said algorithm and applicable for
enables to implement the practical applications. Evolutionary small and average sized problems.
optimization is the recent technique used in continuous and Direction of word length and minimization of bit
discrete optimization for non-standard amplitude width were achieved in [5].Digit serial architecture provides
characteristics. an alternative solution to the complex circuits at gate level and
The digital filter was designed to withstand the rounding improves efficiency. Multiple constant multiplication
errors because IIR filters are prone to change the filter MCM]reduces the difficulties of DSP system. It was
coefficients by changing its amplitude characteristics after performed for VLSI architecture using Xilinx simulator. The
implementation. The computational time of minimal phase architecture were tested using test bench for transposed FIR
digital filter was lesser than linear phase filter with respect to structure[6].
memory, filter length and group delay. Logarithmic number system [LNS]replaced the linear
coefficients. Branch and bound algorithm were developed
Yule-Walker method arose the complexity of filter design using LNS domain and results in better approximation error
in programmable fixed point DSP processors. Filter
were described in [7].In[8], significant reduction in area,
coefficients has to be scaled, quantized to the fixed point in
real time. Hence, the above said method does not produce optimized speed were achieved using MCMAT to truncate
appropriate results. The EA-MP-FWL-FD eliminates the and compress the least significant bit value. It was
disadvantage of YULE-Walker method and can be applicable implemented using Verilog HDL code. Discrete-
for real time without altering the filter coefficients[9]. reoptimization were discussed in odd order system .This re-
optimization were tested in single channel-system and can be
The selection of word length optimization[WLO] explores extended to filter-banks[9].
the area reduction, increased speed and less power In[10],MCMA were performed on FPGA based on
consumption using fixed point arithmetic[1,2,3].SQNR is the memory type FIR filters [i.e.]using LUT refers to look-up
analytical method to estimate the design time in a rapid table. Direct FIR structure using MCMA produces good area
manner. A Novel Method of SQNR estimator were proposed
minimization and power reduction than conventional FIR
for with and without feedbacks which improves the WLO[10].

852
 International Journal of Applied Engineering Research, ISSN 0973-4562 Vol. 10 No.68 (2015)
© Research India Publications; httpwww.ripublication.comijaer.htm
filters. In [4],evolutionary algorithm were developed using
mutation and crossover operators and can be implemented in
V. FUTURE SCOPE 
DSP system by analyzing linearly falling, growing, non- GRASP algorithm can be done in multi-core
linearly falling and growing without altering the filter processor .Replacing LNS by other number representation can
coefficients. also be a further studies. MSB values can also be discussed.
Even-Order system can be extended in FIR Filter banks. Noise
parameter can be analyzed in non-linear fixed point algorithm
Frequency Response Specification in presence of loops. Randomized-selection strategy can be
performed in bank of filters. Algorithm can be developed in
digit-serial MCM operations at gate-level. Odd-Order system
can be implemented in MCMA.

Determination of Filter Acknowledgment 

Coefficients The author extends thankfulness to the Supervisor for
And guidance and support in completing this paper.
Filter Order
References 
[1] Nilesh B. Bosmiya,R.C.Patel, “Reduced Area Fully Parallel and Fully
Serial FIR Filters on Field-Programmable Gate Array,”vol.1,Issue-2,Oct
-2013.
[2] Yu Pang,Yafeng Yan, Junchao Wang, Zhilong He, Ting Liu,”Using
Arithmetic Transform to Calculate Ranges of Arithmetic Datapaths,”
Quantization vol.7,NO.12,December 2012.
[3] H.-N. Nguyen, D. Menard and O. Sentieys,”Novel algorithms for word-
length Optimization,”EURASIP,2011-ISSN 2076-1465.
[4] Samidha Shirish Pusegaonkar, Vipin S Bhure, Amol Y Deshmukh,”
VLSI Architecture for Optimized Low Power Digit Serial FIR,” Volume
10, Issue 7 (July 2014), PP.41-45.
[5] Syed Asad Alam and Oscar Gustafsson,” Design of Finite Word Length
Linear-Phase FIR Filters in the Logarithmic Number System domain
Filter using MCM,” Volume 2014, Article ID 217495, 14 pages.
Digital Filter
[6] V. Bindhya, R. Guru Deepthi, S. Tamilselvi, Dr. C. N. Marimuthu, R.
implementation in DSP Nicole, “ Optimized FIR filter design using Truncated Multiplier
Processor Technique,” | Vol. 4 | Iss. 3 | Mar. 2014 | 31 |.
[7] U.Heute,A.Srivastav,V.Sauerland andj.Kliewer,“Fixed-point-Coefficient
FIR Filters and Filter Banks:Improved Design by Randomized
Quantizations,” Unpublished.
Fig.1. Digital Filter Design Flow [8] U. Sudha Rani,S.P. Suresh Naik,” LUT based FIR Filter Design &
implementation on FPGA using Faithfully Rounded Truncated Multiple
Constant Multiplication/Accumulation,” Volume No.3 Issue No: Special
Finally in [3], AA were proposed to measure the 2, pp: 97-102 22 March 2014.
SQNR values based on perturbation theory. These techniques [9] A.SŁOWIK,” Application of evolutionary algorithm to design minimal
Can be incorporated for range analysis, analysis of limit cycle phase digital filters with non-standard amplitude characteristics and
etc. finite bit word length.
[10] Gabriel Caffarena, Juan A. L´opez, Angel Fern´andez-Herrero and
Carreras,” SQNR Estimation Of Non-Linear Fixed-Point Algorithms,”
IV. CONCLUSION  © EURASIP, 2010 ISSN 2076-1465.

This paper concludes with the inclusion of the

parallel architecture which occupies larger area compared to
serial architecture due to requirement of multipliers and adders
etc. Range analysis can be analyzed using AA for bit-width
optimization. The GRASP algorithm can be implemented in
multicore processor which yields better results. Further, the
algorithm should be developed at the gate-level
implementation using suitable techniques for area reduction,
improved speed and low power consumption etc. which results
in good precision.

853
International Journal of Applied Engineering Research, ISSN 0973-4562 Vol. 10 No.68 (2015)
© Research India Publications; httpwww.ripublication.comijaer.htm

854