Ic HDL Lab Manual

Lab Manual IC Applications & HDL Simulation Lab Autonomous -R–01 Regulation
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
IC Applications & HDL Simulation Lab

Lab Manual
(As per Autonomous – R-15 Regulation)
B. Tech (ECE) - V Sem.
Prepared by
Mr. M. Vedachary, Associate Professor, ECE
Ms. T. Swapna Rani, Assistant Professor, ECE
CMR COLLEGE OF ENGINEERING & TECHNOLOGY

(An Autonomous Institution)
KANDLAKOYA, MEDCHAL ROAD, HYDERABAD – 501401
List of the Experiments

Part – I: Linear IC Experiments
Department of ECE, CMRCET - Hyderabad Page 1

S. No. Name of the experiment Page

No.
Introduction 3
1 Adder, Subtractor, Comparator Using IC 741 Op-Amp. 7
2 Integrator And Differentiator Using IC741 Op-Amp. 13
3 Active Low Pass & High Pass Butterworth (Second Order) 18
4 RC Phase Shift And Wein Bridge Oscillators Using IC 741 OP-Amp 24
5 IC 555 Timer In Monostable And Astable Multivibrator Circuits 30
6 Voltage Regulators IC 723, Three Terminal Voltage Regulators -7805, 34

7809, 7912.
7 3-8 decoder – 74LS138 39
8 4 bit comparator 74LS85. 42
9 D Flip-Flop (74LS74) and JK Master –Slave Flip-Flop (74LS73). 45
10 Universal Shift registers-74LS194/195. 49
Part – II: HDL Simulation Programs
S. No. Name of the experiment Page No.
Introduction
1 HDL code to simulate basic gates
2 Full adder using 3 modelling Styles

3 Design of 4 bit Binary to Gray &Gray to Binary Converter
4 Design of 3x8 Decoder and 8x3 Encoder

5 Design of 8x1 Mux using 4x1 Mux and 8x1 Demux
6 Design of SR & D Flip flop
7 Design of JK & T Flip flop
8 Decade counter & Up down counter
9 Universal Shift register
10 Binary Multiplier

Part – I: Linear IC Experiments

Introduction
STUDY OF OP-AMPs IC 741, IC 555, IC 565 FUNCTIONING, PARAMETERS &
SPECIFICATIONS
AIM: To Study about IC741 (Op-Amp), IC555 (Timer), IC565 (PLL).
COMPONENTS: IC741, IC555, IC565.
IC741 : (Operational Amplifier)
Symbol
Fig.a
Pin Configuration
Fig.b
Maximum Ratings:
Supply Voltage  18V
Internal Power Dissipation 310mw

Differential input voltage  30V
Input Voltage  15V
Operating temperature range 0ºC to 70ºC
Applications:
Non-inverting amplifier
Inverting amplifier
Integrator
Differentiator
Low Pass, High Pass, Band pass and Band Reject Filters
Features:
No External frequency compensation is required
Short circuit Protection
Off Set Null Capability
Large Common mode and differential Voltage ranges
Low Power Dissipation
No-Latch up Problem
741 is available in three packages :- 8-pin metal can, 10-pin flat pack and 8 or 14-pin DIP
IC 555 : (Timer ) Pin Configuration
Fig.(c) Fig(d)

Functional block diagram:
Fig(e)
Specifications:
Supply Voltage 5V to 18V

Maximum Current rating 200mA
Minimum Triggering Voltage -(1/3) VCC
Operating temperature range 0ºC to 70ºC
Applications:
1. Astable Multivibrator : Schmitt trigger, Free running ramp Generator, etc.,
2. Monostable Multivibrator: Frequency divider, Pulse structure
3. Bi stable multivibrator
Features :
555 timers are reliable, easy to use and low cost. The device is available as an 8 pin metal can, an
8 –pin mini DIP or a 14 Pin DIP
IC565 : ( Phase locked loop):

Pin configuration:
Fig.(f) Fig(g)
Specifications:
Minimum input for lock 1 mV
VCO Frequency 0.5MHz
Lock range 60%
VCC Minimum 10V
VCC Maximum 26 Volts
Applications:
Frequency multiplier,
Frequency Shift Keying (FSK) Demodulator
Frequency Translation or shifting
Frequency demodulation.
Features:
Extreme Stability of Center frequency
Very high linearity of De modulated output
TTL Compatible square wave output
Highly Linear tri angular output
Loop can be broken to insert digital frequency divider

EXPERIMENT NO : 1
OPAMP APPLICATIONS – ADDER, SUBTRACTOR & COMPARATOR CIRCUITS
AIM : To design an adder, Subtractor & comparator circuits using OP- AMP 741 IC.
APPARATUS : Bread Board.

741IC.
Resistors – R1 =10KΩ - 5No’s.
Connecting wires.
Dc Supply.
Signal Generator.
Multimeter.
CRO, Probes. Connecting Wires.
CIRCUIT DIAGRAM :
Adder :
Fig.(a)
Subtractor :

Fig.(b)
Comparator :
Fig.(c)
THEORY :
Adder : Adder circuit is a Summing Amplifier. Op-amp can be used to design a circuit whose
output is the sum of several input signals. Such a circuit is called a summing amplifier or a
summer. Summing amplifier can be classified as inverting & non-inverting summer depending
on the input applied to inverting & non-inverting terminals respectively. Fig shows an inverting
summer with two inputs. Here the output will be the linear summation of input voltages. Here the
feedback forces a virtual ground to exist at the inverting input . The output is equal to the
negative weighted sum of the input voltages. The summing operation depends exclusively on the
sum of the resistor ratios. Fig . shows the inverting configuration with three inputs Va, Vb, Vc
depending on the relationship between the feedback resistor RF and the input resistors Ra ,Rb and
Rc , the circuit can be used as either a summing amplifier, scaling amplifier, or averaging
amplifier. By connecting more than one input voltages to the inverting input, the resulting circuit
is the Adder.
Va Vb Vc
I =------ + -------+ -------
Ra Rb Rc
V0 = - Rf.I
Va Vb Vc
V0 = -Rf ( ------+ ------+ --------- )

Ra Rb Rc
If Ra = Rb = Rc = R
V0 = - (Rf/R) (Va +Vb + Vc)
This means that the output voltage is equal to the negative sum of all the inputs
times the gain of the circuit is called a summing amplifier. Obviously, when the gain of the
circuit is 1, that is , Ra = Rb = Rc = RF , the output voltage is equal to the negative sum of all
input voltages. Thus
V0 = - (Va + Vb + Vc)
Subtractor : A subtractor is a circuit that gives the difference of the two inputs. Vo =V1-V2 ,
Where V1 and V2 are the inputs.
By connecting one input voltage V1 to inverting terminal and another input voltage V2 to the non
– inverting terminal then the resulting circuit is the Subtractor.
Output of a differential amplifier (subtractor) is given as
Vo=(-Rf/R1)(V1-V2)
If all external resistors are equal in value, then the gain of the amplifier is equal to 1. The output
voltage of the differential amplifier with a gain of 1 is
V0 = (V2-V1)
Thus the output voltage V0 is equal to the voltage V2 applied to the non – inverting
terminal minus the voltage V1 applied to the inverting terminal. Hence the circuit is called a
Subtractor.
Comparator : A Comparator is a non-linear signal processor. It is an open loop mode

application of Op-amp operated in saturation mode. Comparator compares a signal voltage at one
input with a reference voltage at the other input. Here the Op-amp is operated in open loop mode
and hence the input is ± Vsat. It is basically classified as inverting and non-inverting comparator.
In a non inverting comparator Vin is given to +ve terminal and Vref to –ve terminal. When Vin <
Vref, the output is –Vsat and when Vin > Vref, the output is + Vsat. In an inverting comparator
input is given to the inverting terminal and referenceis given to the non inverting terminal. The
comparator can be used as a zero crossing detector , window detector, time marker, phase meter.

Fig.(d)
PROCEDURE :
Adder :
1. Connect the adder circuit as shown in fig.(a) by connecting the appropriate resistors to 741 IC.
2. Switch on the trainer.
3. Apply dc voltages at each input terminals for V1 and V2 from the dc supply and check the
output voltage Vo at the output terminal.
4. Tabulate the readings.
5. Compare practical Vo with the theoretical output voltage Vo=-Rf[(V1/R1)+(V2/R2)].
Subtractor :
1. Connect the subtractor circuit as shown in fig.(b) by connecting the appropriate resistors to
741 IC.
2. Switch on the trainer.
3. Apply dc voltages at each input terminals for V1 and V2 from the dc supply and check the
output voltage Vo at the output terminal.
4. Tabulate the readings.
5. Compare the practical Vo with the theoretical output voltage Vo=(-Rf/R1)(V2-V1) value.
Comparator :
1. connect the comparator circuit as shown in fig.(c)

2. Apply 1 KHz sine wave with 5 Vp-p at the inverting input terminal of 741 IC using a function
generator.
3. Apply 3V dc voltage as reference voltage at the non-inverting terminal of 741 IC.
3. Connect channel -1 of CRO at the input terminals and channel-2 of CRO at the output
terminals.
4. Observe the input sinusoidal signal in ch-1 and the corresponding output square wave in ch-2
of CRO.
5. Note the amplitude and timeperiods of Vin and Vo.
6. Plot the output square wave corresponding to sine input with Vref = 3V
TABULAR COLUMN;

Adder :
R1 = 10 K R2 = 10K Rf =10K
S.No V1 V2 Theoretical Practical Vo
Volts Volts Vo=-Rf[(V1/R1)+(V2/R2)] Volts
Subtractor :
R1 = R2 = Rf= 10K
S.No V1 V2 Theoretical Practical Vo
Volts Volts Vo=(-Rf/R1)(V2-V1) Volts
EXPECTED WAVEFORMS:
COMPARATOR INPUT & OUTPUT WAVEFORMS

Fig.(e)
Fig.(f)
RESULT :
Adder: Adder circuit is implemented as per the circuit. The practical values are differs slightly
with theoretical values due to the offset voltage
Substractor: Substractor circuit is implemented as per the circuit. The practical values are differs
slightly with theoretical values due to the offset voltage
Comparator: The circuit to compare the input signal with the reference voltages and then found
the output wave forms
VIVA VOCE:
1. What is an Op-Amp.
2. What are the different Linear IC Packages.
3.List five characteristics of an idal Op-Amp.
4.Define Commom Mode Rejection Ratio.
5.What are the various DC Characteristics of an Op-Amp.

EXPERIMENT NO :2
INTEGRATOR AND DIFFERENTIATOR CIRCUITS USING IC741

AIM: To study the operation of the differentiator & Integrator and trace the output wave forms
for sine and square inputs.
APPARATUS: IC741 Op-Amp .

Resistors- 5.6K, 10K, 100K
Capacitors- 0.1 µF
Signal Generator.
CRO, Probes, Connecting wires
CIRCUIT DIAGRAM :
Differentiator:
Fig.(a)
Integrator :

Fig(b)
THEORY:
Integrator.
In the practical integrator to reduce the error voltage at the output, a resistor R F is connected
across the feedback capacitor CF. Thus, RF limits the low-frequency gain and hence minimizes
the variations in the output voltage.
Fig.(c)
The frequency response of the basic integrator is shown in the fig(c) fb is the frequency at
which the gain is 0 dB and is given by
fb = 1/2 R1Cf.
In this fig(c) is some relative operating frequency, and for frequencies f to fa the gain
RF/R1 is constant. However, after fa the gain decreases at a rate of 20 dB/decade. In other words,
between fa and fb the circuit of fig(b), acts as an integrator. The gain-limiting frequency fa is
given by
fa = 1/2 RfCf.
Generally, the value of fa and in turn R1Cf and RfCf values should be selected such that fa
< fb. For example, if fa = fb / 10, then Rf = 10R1. In fact, the fig(c), frequency response of basic
and practical integrators.
fa =1 / (2 RfCf ) and fb = /(2 RfCf).

The input signal will be integrated properly if the time period T of the signal is larger
than or equal to RfCf. i.e., T > RfCf
where RfCf = 1 / 2 fa.
Integrator has wide applications in

1. Analog computers used for solving differential equations in simulation arrangements.
2. A/D Converters
3. Signal wave shaping
4. Function Generators.
Differentiator:
The frequency response of the basic differentiator is shown in fig(c), in this fig(c), fa is
the frequency at which the gain is 0 dB and is given by
fa = 1/2 RfC1
Both the stability and the high-frequency noise problems can be corrected by the addition
of two components: R1 and Cf, as shown in fig(a), This circuit is a practical differentiator, the
frequency response of which is shown in fig(c) by a dashed line.
From frequency f and fb, the gain increases at 20 dB/decade. However, after fb the gain
decreases at 20 dB/decade. This 40-dB/decade change in gain is caused by the R1C1 and RfCf
combinations. The gain-limiting frequency fb is given by
fb = 1 / 2 R1C1.
Where R1C1 = RfCf.
Thus R1C1 and RfCf help to reduce significantly the effect of high-frequency input,
amplifier noise, and offsets. Above all, it makes the circuit more stable by preventing the
increase in gain with frequency. Generally, the value of fb and in turn R1C1and RFCF values
should be selected such that fa<fb<fc
Where fa = 1 / 2 RfC1
fb = 1 / 2 R1C1 = 1 / 2 RfCf
fc = unity gain-bandwidth
The input signal will be differentiated properly if the time period T of the input signal is
larger than or equal to RfCf. That is, T> RfC1
Differentiator can be designed by implementing the following steps.

1. Select fa equal to the highest frequency of the input signal to be differentiated.
Then, assuming a value of C1<1 F, calculate the value of Rf
2. choose fb = 20fa and calculate the values of R1and Cf so that R1C1=RfCf.

PROCEDURE:
Differentiator:
1. Connect the Differentiator circuit as shown in fig(a).

2.Apply 1 KHz sine wave with Vp-p = 5 V at the input terminals of the differentiator circuit
using function Generator.
3. Connect channel-1 of CRO at the input terminals and channel-2 at the output terminals.
4. Switch ON the kit, observe cosine wave at the output of the circuit on the CRO and record the
amplitude & timeperiod of Vin and Vo.
5. Now Apply square wave as input signal .
6. Observe the spike output voltage wave form on the CRO and note down the corresponding
values of amplitude and timeperiod of Vin & Vo.
7. Plot the output voltages corresponding to sine and square wave inputs.
Integrator:
1. Connect the integartor circuit as shown in fig(b).

2.Apply 1 KHz sine wave with Vp-p = 5 V at the input terminals of the differentiator circuit
using function Generator.
3. Connect channel-1 of CRO at the input terminals and channel-2 at the output terminals.
4. Switch ON the kit, observe cosine wave at the output of the circuit on the CRO and record the
amplitude & timeperiod of Vin and Vo.
5. Now Apply square wave as input signal .
6. Observe the triangular output voltage wave form on the CRO and note down the
corresponding values of amplitude and timeperiod of Vin & Vo.
7. Plot the output voltages corresponding to sine and square wave inputs.
EXPECTED WAVEFORMS:
Differentiator:

Integrator :
RESULT: Studied about the Operation of Integrator and Differentiator using Op-Amp 741 and
output waveforms are observed on CRO for sine and square inputs.
VIVA VOCE:
1.List various Operational Amplifier parameters.
2.Define Slew Rate.
3. What are the various specifications of Op-Amp 741.
4. What are the various factors effecting the parameters of Op-Amp.
5.Define input offset voltage.

EXPERIMENT NO : 3
ACTIVE FILTER APPLICATIONS- FREQUENCY RESPONSE OF LPF & HPF
(a) SECOND ORDER LOW PASS BUTTERWORTH FILTER
AIM : To plot the frequency response characteristics of a second order Butterworth low pass
filter.
APPARATUS: IC 741 -- 1 No.
Resistor 10K  --- 2 No.
Capacitor 0.022 F --- 2No.
Function Generator, CRO, Dual Regulated Power Supply.
Connecting wires.
CIRCUIT DIAGRAM:
THEORY :
In case of Low Pass Filter, it is always desirable that the gain rolls off very fast after the
cut-off frequency i.e. in the Stop Band. In case of first order filter, it rolls off at a rate of 20 dB
/decade. In case of second order filter, the gain rolls off at a rate of 40 dB/ decade. Thus, the
slope of the frequency response after f = fH is -40dB/ decade, for a second order low pass filter.

A first order filter can be converted to second order type by using an additional
RC network as Shown in the fig. The cut-off frequency fH for the filter is decided by R2, C1, R3,
and C2. The gain of the filter is as usual decided by op-amp i.e. the resistance R1 and Rf.
1
Higher Cut off Frequency f H =
2π√(R2 R3 C1 C2)
Af
A = |V /V |=
Gain of the Second Order Filter 0 in
1  ( f / fH )4
Where Af = Pass band gain of the Filter (1 + RF/ R1)
f = frequency of the Input Signal
f H = Higher Cut off frequency
DESIGN PROCEDURE: f H = 723Hz
Choose the value of ‘C ‘less than or equal to 1 f ; let C = 0.022 f
1
Then calculate R using the f H =
2π√(R2 R3 C1 C2)
R2 = R3 = R
C1 = C2 = C
So f H = 1/ 2 RC
723 = 1/ 2 . R. 0.022
R2 = R3 = R = 10KΩ .
PROCEDURE :
1. Make Connections as per the Circuit diagram

2. Set Vin(p-p) = 1V vary frequency from 5 Hz to 1 MHz and note down the
Amplitude of output wave form (Vo).
3. Calculate Gain and Gain in db.
4. Plot the frequency response curve and determine FH.
Also mark the pass band and stop band.

EXPECTED GRAPH:
Theoretical fH=
Practical fH=
RESULT : The frequency response of 1st order Low Pass Filter is plotted. The cut off
frequency is calculated and is verified with the theoretical value.

ACTIVE FILTER APPLICATIONS- FREQUENCY RESPONSE OF LPF & HPF
(b ) SECOND ORDER HIGH PASS BUTTER WORTH FILTER
AIM : To plot the frequency response characteristics of a Butterworth second order

high pass filter using op-amp.
APPARATUS: IC 741 -- 1 No.
Resistors : 10K  -1
20K  -1.
Capacitor 0,01 F --- 2No.
Function Generator, CRO, Dual Regulated Power Supply.
CIRCUIT DIAGRAM:
THEORY : In case of High Pass Filter, it is always desirable that the gain rolls off
very fast before the cut-off frequency i.e. in the Stop Band. In case of first order filter, it rolls off
at a rate of 20 dB /decade. In case of second order filter, the gain rolls off at a rate of 40 dB/
decade. Thus, the slope of the frequency response before f = fL is +40dB/ decade, for a second
order high pass filter.
A Second order Low pass filter can be converted to second order High pass Filter
type by interchanging the positions of Capacitors and Resistors as given in fig. The cut-off

frequency fL for the filter is decided by R2, C1, R3, and C2. The gain of the filter is as usual
decided by op-amp i.e. the resistance R1 and Rf
1
Lower Cut off Frequency f L =
2π√R2 R3 C1 C2
Af
= |V /V |=
Gain of the Second Order Filter A 0 in
1  ( fL / f )4
Where AF = Pass band gain of the Filter (1 + RF/ R1)

f = frequency of the Input Signal
f L = Lower Cut off frequency.
PROCEDURE:
1. Make Connections as per the Circuit diagram

2. Set Vin = 1V(P-P) vary frequency from 5Hz to 1 MHz and note down the Amplitude of
output wave form (Vo).
3. Calculate gain, gain in db.
4. Plot the frequency response curve and determine fL.
Also mark the pass band and stop band.
TABULAR COLUMN: Vin(p-p)=
Input Frequency(f) Vo Gain in dB

Gain ( )
Vin Vo
20 log ( )
in Hz Vo(in Volts) 10
Vin
EXPECTED GRAPH:

THEORITICAL PRACTICAL
Lower cutoff frequency fL
RESULT : The frequency response of 1st order High Pass Filter is plotted. The cut off
frequency is calculated and is verified with the theoretical value.
Viva Voice : 1. Draw the Circuit of Third Order Low Pass Filter.
2. Draw the Frequency Response of Band Pass Filter.
3. Draw the Ideal Frequency Response of All types of Filers.

EXPERIMENT NO :4
IC-741 OSCILLATOR CIRCUITS – RC PHASE SHIFT OSCILLATOR & WEIN –

BRIDGE OSCILLATOR
a) RC Phase Shift Oscillator
AIM : To compare theoretical and practical frequency of oscillation of RC Phase Shift

Oscillator.
APPARATUS : CRO Probes

Connecting wires
R1=10KΩ,
Rf=10 KΩ,
Rcomp=5 KΩ
R=10 KΩ,C=.01µf
CIRCUIT DIAGRAM :
Fig(a)
THEORY :
Oscillator is a circuit which generates output without any input. Oscillator can be defined
as a device that converts dc to ac.
Oscillators can be classified as

Based on the components used.

RC Oscillators - RC Phase shift, Wein Bridge Oscillator

LC oscillators - Colpitts, Hartley, Clapp Oscillator
Crystal Oscillators
Based on the type of waveform
Sinusoidal Oscillators – RC Phase shift, Wein Bridge, Colpitts, Hartley….
Non-Sinusoidal Oscillators- UJT relaxation Oscillators
Based on frequency range
Audio frequency oscillator – RC oscillators
Radio frequency oscillator – LC oscillators
Barkhausen ‘s criterion for oscillations:

1) For sustained oscillations the phase shift around the circuit( amplifier and feedback
circuit) should be 360o or 0o.
2) The gain of the amplifier should greater than or equal to unity
A Phase shift oscillator consists of an Op-Amp as the amplifying stage and three
cascaded networks as the feedback circuit. The feedback circuit provides feedback voltage from
the output back to the input of the amplifier. The Op-Amp is used in the inverting mode,
therefore any signal that appears at the inverting terminal is shifted by 180o at the output. An
additional 180o phaseshift is provided by the 3 RC sections – each section providing a Phase shift
of 60o. There fore feedback circuit ( 3 RC-sections) provide additional around the loop 180o,
totally giving 360o phaseshift around the loop. A specific frequency when the phaseshift of the
cascaded RC sections is 180o and the gain of the amplifier is sufficiently large, the circuit will
oscillate at that frequency which is called the frequency of oscillation fo and is given by
fo = 1/2πRC√6 = 0.065/ RC
At this frequency, the gain Av must be atleast 29
i.e., Rf/R = 29.
The circuit will produce a sinusoidal waveform of frequency fo if the gain is 29 and the total
Phase shift around the circuit is exactly 360o or 0o. For desired frequency of oscillation. Choose a
capacitor C, and then calculate the value of R.
PROCEDURE :
1. Connect the circuit as shown in fig(a).

2. Connect the output of the circuit to CRO through probes.
3. Calculate the practical frequency of oscillation f = 1/T by observing the timeperiod of the
output sinusoidal waveform on the CRO and compare it with theoretical frequency of Oscillation
f = 1/2πRC√6
4. Sketch the output waveform by noting the timeperiod and peak to peak voltage of the output
waveform

TABULAR COLUMN:
S.No R C Theoretical Timeperiod Practical
Ω µF fo= 1/2πRC√6 T fo = 1/T
EXPECTED WAVEFORMS :
Fig(b)
RESULT: Practical frequency of oscillation of RC Phase Shift Oscillator is compared with the
theoretical value.
VIVA VOCE:
1. Define Oscillator
2. What is the frequency of oscillation i.e f0 for RC Phase shift Oscillator.
3.What is the minimum gain required in RC Phase shift Oscillator.
4. What is the phase shift provided by each RC section at the frequency of oscillation.
5. What is Barkhusen’s criteria for oscillations

IC-741 OSCILLATOR CIRCUITS –RC PHASE SHIFT OSCILLATOR & WEIN –

BRIDGE OSCILLATOR
b) Wein Bridge Oscillator.
AIM : To compare theoretical and practical frequency of oscillation of Wein Bridge Oscillator.
APPARATUS : CRO
Probes
Connecting wires
Rf=100 KΩ (pot),R1=10 KΩ
R=4.7 KΩ,C=0.047µf
CIRCUIT DIAGRAM :
Fig.(a)
THEORY :
Many electronic devices require a source of energy at a specific frequency which may
range a few Hz to several MHz. This is achieved by an electronic device called an oscillator.
Oscillator is a circuit which generates output without any input. Oscillator can be defined as a
device that converts dc to ac. Oscillators can be classified as
Based on the components used.

RC Oscillators - RC Phase shift, Wein Bridge Oscillator
LC oscillators - Colpitts, Hartley, Clapp Oscillator
Crystal Oscillators
Based on the type of waveform
Sinusoidal Oscillators – RC Phase shift, Wein Bridge, Colpitts, Hartley….
Non-Sinusoidal Oscillators- UJT relaxation Oscillators
Based on frequency range
Audio frequency oscillator – RC oscillators
Radio frequency oscillator – LC oscillators
This wein Bridge Oscillator is the standard oscillator circuit for low to moderate
frequencies, in the range of 5 Hz to about 1 MHz . This oscillator is preferred for commercial
audio generators and other low frequency applications. To avoid the damped oscillations at the
output the Wein Bridge oscillator it uses a feedback circuit called a lead – lag network. To
generate un damped oscillations, the positive feedback must be used because the output must
generate itself.
Barkhausen ‘s criterion for oscillations:
1) For sustained oscillations the phase shift around the circuit( amplifier and feedback
circuit) should be 360o or 0o.
2) The gain of the amplifier should greater than or equal to unity.
This type of RC oscillator’s is used for frequencies from 1 Hz to 5 MHz,
The commonly used audio frequency oscillator is Wein Bridge oscillator as shown in the
circuit. The feedback signal in this circuit is connected to the non-inverting terminal, therefore
the Op-Amp is working in non-inverting mode. Hence this amplifier doesn’t provide any phase
shift. There fore the feedback network need not provide any phase shift. The condition of zero
Phase shift around the circuit is achieved by balancing the bridge.
For sustained oscillations, the amplifier must have a gain of precisely 3. but practically
Av may be slightly less or greater than 3.
For Av < 3, the oscillations will either die down or fail to start.
For Av > 3, the oscillations will be growing.

PROCEDURE :
1. Connect the circuit as shown in Fig(a)
2. Switch ON the power supply.
3. Connect the output of the circuit to CRO through probes.
4. Calculate the practical frequency of oscillation f = 1/T by observing the timeperiod of the
output sinusoidal waveform on the CRO and compare it with theoretical frequency of Oscillation
f = 1/2πRC
5. Sketch the output waveform by noting the timeperiod and peak to peak voltage of the output
waveform
TABULAR COLUMN:
S.No R C Theoretical Timeperiod Practical
Ω µF fo= 1/2πRC T fo = 1/T
EXPECTED WAVEFORMS :
Fig(b)
RESULT: Practical frequency of oscillation of Wein Bridge Oscillator is compared with the
theoretical value.

VIVA VOCE:
1.What is the resonant frequency of the balanced wein bridge oscillator.
2.What is the relationship between RF and R1 in Wein bridge Oscillator.
3.What are the two requirements for oscillation.
4. Why RC oscillators are called low frequency oscillators
5.What is the advantage by using IC 741 op-amp in the oscillator circuit

EXPERIMENT NO :5
MONOSTABLE MULTIVIBRATOR USING IC555
AIM : To generate a pulse waveform of required pulse width by using 555 timer.
APPARATUS : Monostable Multivibrator Kit

CRO Probes
Connecting wires
C1=C2=0.01µF,C=0.1 µF
R=3.9KΩ.
CIRCUIT DIAGRAM :
Fig(a)
Fig(b)
THEORY:
Monostable can also called as One – shot Multivibrator. when the output is low, the
circuit is in stable state, Transistor Q1 is ON and Capacitor C is shorted out to ground. However,
upon application of a negative trigger pulse to Pin – 2, transistor Q1 is turned OFF , which
releases short circuit across the external capacitor and drives the output High. The capacitor C

now starts charging up toward VCC through RA . However when the voltage across the external
capacitor equals 2/ 3 VCC comparator – 1’s (C1 ) output switches from low to high, which is
turn derives the output to its low state via the output of the flip flop turns transistor Q1 ON, and
hence, capacitor C rapidly discharges through the transistor. The output of the Monostable
remains low until a trigger pulse is again applied. Then the cycle repeats. The time during which
the output remains high is given by Tp = 1.1 R C
Fig.(c)

Waveforms for IC555 Monostable Multivibrator
Fig.(d)
Once triggered, the circuit ‘s output will remain in the high state until the set time tp
elapses. The output will not change its state even if an input trigger is applied again during this
time interval tp.
PROCEDURE:
1. Connect the circuit as shown in fig(b).

2. Connect function generator at Pin 2 and Ch-1 of CRO at Pin 2 and ch-2of CRO at Pin 3.
3. Apply square wave from function generator and observe the output voltage Vo with respect to
input.
4. Now connect ch-2 of CRO across capacitor and observe the voltage across the capacitor Vc.
5. Note the timeperiod and amplitude of output voltage Vo and capacitor voltage Vc.
6. Find out the practical pulse width.
TABLE:
Theoretical value Practical value
tp =1.1RC tp
Pulse width

EXPECTED WAVEFORMS:
Fig (e)
RESULT: Theoretical and Practical frequency of oscillation of monostable multivibrator is

calculated and compared.
VIVA VOCE:
1.List various applications of 555 timer.
2.Explain the function of RESET in 555 timer.
3.What are the modes of operation of a timer.
4.What is supply voltage of 555 timer.
5.What are the various applications in Monostable mode.

EXPERIMENT NO : 6
VOLTAGE REGULATOR USING 723. THREE TERMINAL VOLTAGE

REGULATORS-7805, 7809,7912.
AIM : To verify the action of IC723 as a voltage regulator and to find the values of load
regulation and line regulation.
APPARATUS : IC723 Voltage regulator

Connecting wires.
Multimeter.
DRB.
RPS.
CRO
Probes
CIRCUIT DIAGRAM :
Fig(a)
THEORY:
IC723 device is most versatile of monolithic regulators. It can be used to provide high
and low positive regulated voltages, negative regulated voltages and can be used as positive and
negative switching regulator.

IC 723 by itself can supply output current upto 120mA. External resistors can be
added to provide higher load currents. It takes input voltage upto 40 V. The output voltage is
adjustable from 2V to 35 V. This can be either a linear or switching regulator. This can be also
used as shunt regulator, a current regulator or a temperature controller.
PROCEDURE:
1. Connect the circuit as shown in figure(a)by connecting appropriate resistors and capacitors.
2. Measure the reference voltage at Pin 6(it should be greater than 7V)
3. The internal reference voltage are applied to the potential divider R1 & R2.
4. Keeping R1 constant, vary R 2 and R3 . The output voltage Vo is measured .
5. Compare this output voltage with the theoretical value
6. Tabulate the result for different values of R2 ,R3.
7. Calculate load Regulation & line regulation
Load Regulation : VNL –VFL X 100

VFL
Line Regulation : VO1 –VO2 X 100

VO1
VO1 =Ouput Voltage when Vcc = 25 V

CALCULATIONS:
VNL = VFL =
VO1 = VO2 =
Load Regulation = VNL –VFL X 100

VFL
Line Regulation = VO1 –VO2 X 100

VO1
=
Where VO1 =Ouput Voltage when Vcc = 25 V

RESULT: Load Regulation & Line Regulation of IC 723 are calculated.

THREE TERMINAL VOLTAGE REGULATORS-7805, 7809,7812,7912.
AIM :To study about 3 pin regulators IC 78XX & 79XX.
APPARATUS : 3 Pin Regulator IC trainer.

Digital Multimeter.
Connecting wires.
CIRCUIT DIAGRAM :
78XX voltage Regulator
Fig(a)
79XX voltage Regulator
Fig(b)
THEORY :
A three terminal voltage regulator is a regulator in which the output voltage is set at some
predetermined value. Such regulator does not require any external feedback connections. Hence
only three terminals are required for device of such type :

input Vin,
Output Vo &
a ground terminal.
The main advantage of three terminal regulators are :
1. Simplicity of connections to the external circuit and

2. Minimum pF external components ( in some cases no external components are required)
78XX THREE TERMINAL POSITIVE VOLTAGE REGULATORS.
The 78XX series of three terminal voltage regulators are available with output voltage of 5, 6, 8,
12, 15, 18 & 24V with the designation of the 5V regulator being the 7805, the 6V being the 7806
and so on
The voltage regulators of 78XX series all have the same internal circuitry, expect for
different values of one resistor, which determines the output voltage level.
Fig represents the circuit connections for 78XX series. Pin 1 represents the input, Pin 2
represents ground and Pin3 represents the output terminal.
79XX THREE TERMINAL NEGATIVE VOLTAGE REGULATOR
The 79XX series of fixed output negative voltage regulators are complements to the 78XX series
devices. The negative regulators are available in the output voltage options -2, -5, -5.2, -6, -8, -
12, -15, -18 and -24 V. The maximum input voltage for Vo=24v is 40V, while for the remaining
options is -35V
PROCEDURE:
1. Connect the circuit as shown in fig.
2. Switch ON the 3 Pin regulator IC trainer.

3. Observe the o/p voltages for 78XX &79XX IC regulators at Pin 2 by applying input at Pin 1.
4. Tabulate the reading for different IC’s.
TABULAR COLUMN:
S.No Voltage Input Vin Output Vo
Regulator (volts) (volts)
1 7805
2 7806
3 7812
4 7905
5 7912
6 7924
RESULT: 78XX and 79XX 3 pin IC voltage regulators output voltages are observed.

EXPERIMENT NO: 7
3-8 DECODER – 74LS138
1. AIM:
To verify the truth table of 3 to 8 decoder by using ic 74IC138.
2. HARDWARE:
i. IC 74LS138.
ii. Connecting probes.
3. PIN DIAGRAM
4. DECODER LOGIC DIAGRAM:

5. TRUTH TABLE:
6. THEORY:
In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic
circuit that converts coded inputs into coded outputs, where the input and output codes are
different e.g. n-to-2n , binary-coded decimal decoders. Decoding is necessary in applications
such as data multiplexing, 7 segment display and memory address decoding.
The example decoder circuit would be an AND gate because the output of an AND gate is
"High" (1) only when all its inputs are "High." Such output is called as "active High output". If
instead of AND gate, the NAND gate is connected the output will be "Low" (0) only when all its
inputs are "High". Such output is called as "active low output".
A slightly more complex decoder would be the n-to-2n type binary decoders. These types of
decoders are combinational circuits that convert binary information from 'n' coded inputs to a
maximum of 2n unique outputs. In case the 'n' bit coded information has unused bit
combinations, the decoder may have less than 2n outputs. 2-to-4 decoder, 3-to-8 decoder or 4-to-
16 decoder are other examples.
The input to a decoder is parallel binary number and it is used to detect the presence of a
particular binary number at the input. The output indicates presence or absence of specific
number at the decoder input.
3:8 decoder
It uses all AND gates, and therefore, the outputs are active- high. For active- low outputs, NAND
gates are used. It has 3 input lines and 8 output lines. It is also called as binary to octal decoder it
takes a 3-bit binary input code and activates one of the 8(octal) outputs corresponding to that
code.

7. PROCEDURE:
I. Connect The Probes As Per Diagram (SWITCHES)

2. Apply The Input As Per The Truth Table (LEDS).
3. Verify The Out Puts As Per The Table.
8. RESULT: Truth table of 3 to 8 decoder by using IC 74IC138 is verified.
9. VIVA QUESTIONS:
1. A device that converts from decimal to binary numbered is called?
2. What is a Combinational circuit?
3. What is a Decoder?
4. In 3: 8 decoder the no. of inputs are how many?
5. Which circuit can be used as parallel to series converter?

EXPERIMENT NO : 8
4 BIT COMPARATOR 74LS85.
1. AIM:
To verify the truth table of 4 bit comparator by using IC 74LS85.
2. HARDWARE:
i.IC74LS85
ii. Connecting probes
3. PIN DIAGRAM
4. LOGIC DIAGRAM:

5.TRUTH TABLE:
6. THEORY :
Another common and very useful combinational logic circuit is that of the Digital Comparator
circuit. Digital or Binary Comparators are made up from standard AND, NOR and NOT gates
that compare the digital signals present at their input terminals and produce an output depending
upon the condition of those inputs.
For example, along with being able to add and subtract binary numbers we need to be able to
compare them and determine whether the value of input A is greater than, smaller than or equal
to the value at input B etc. The digital comparator accomplishes this using several logic gates
that operate on the principles of Boolean Algebra. There are two main types of Digital
Comparator available and these are.
 1. Identity Comparator – an Identity Comparator is a digital comparator that has only one
output terminal for when A = B either “HIGH” A = B = 1 or “LOW” A = B = 0
 2. Magnitude Comparator – a Magnitude Comparator is a digital comparator which has
three output terminals, one each for equality, A = B greater than, A > B and less than
A<B
The purpose of a Digital Comparator is to compare a set of variables or unknown numbers, for
example A (A1, A2, A3, …. An, etc) against that of a constant or unknown value such as B (B1,
B2, B3, …. Bn, etc) and produce an output condition or flag depending upon the result of the
comparison. For example, a magnitude comparator of two 1-bits, (A and B) inputs would
produce the following three output conditions when compared to each other.
Which means: A is greater than B, A is equal to B, and A is less than B
This is useful if we want to compare two variables and want to produce an output when any of
the above three conditions are achieved. For example, produce an output from a counter when a
certain count number is reached. Consider the simple 1-bit comparator below.

7. PROCEDURE
I. Connect the Probes As Per Diagram (SWITCHES)
8. RESULT: Truth table of 4 bit comparator by using IC 74LS85 is verified.
9. VIVA QUESTIONS:
1. A circuit which converts some binary code into a singular active output representing its
numerical value is ?
2. A logic circuit which determines if one input is equal to another is called?
3. Comparator requires which type of gate?
4. Why clamp diodes are used in comparator?
5. How to obtain high rate of accuracy in comparator

EXPERIMENT NO : 9
D FLIP-FLOP (74LS74) AND JK MASTER –SLAVE FLIP-FLOP (74LS73).
1. AIM:
To verify the truth table of D flip flop and JK master Slave Flip flop by using ICs 74LS74,
74LS73.
2. HARDWARE:
i.IC74L74, 74LS73
3. PIN DIAGRAM
4. LOGIC DIAGRAM:

5.TRUTH TABLE:
6.THEORY :
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store
state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state
by signals applied to one or more control inputs and will have one or two outputs. It is the basic

storage element in sequential logic. Flip-flops and latches are fundamental building blocks of
digital electronics systems used in computers, communications, and many other types of
systems.
Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary
digit) of data; one of its two states represents a "one" and the other represents a "zero". Such data
storage can be used for storage of state, and such a circuit is described as sequential logic. When
used in a finite-state machine, the output and next state depend not only on its current input, but
also on its current state (and hence, previous inputs). It can also be used for counting of pulses,
and for synchronizing variably-timed input signals to some reference timing signal.
Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-

triggered). Although the term flip-flop has historically referred generically to both simple and
clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for
discussing clocked circuits; the simple ones are commonly called latches.[1][2]
Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is,
when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single
type (positive going or negative going) of clock edge.
Flip-flops can be either simple (transparent or asynchronous) or clocked (synchronous). The

simple ones are commonly described as latches,[1] while the clocked ones are described as flip-
flops.[2]
Simple flip-flops can be built around a single pair of cross-coupled inverting elements: vacuum
tubes, bipolar transistors, field effect transistors, inverters, and inverting logic gates have all been
used in practical circuits.
Clocked devices are specially designed for synchronous systems; such devices ignore their inputs
except at the transition of a dedicated clock signal (known as clocking, pulsing, or strobing).
Clocking causes the flip-flop either to change or to retain its output signal based upon the values
of the input signals at the transition. Some flip-flops change output on the rising edge of the
clock, others on the falling edge.
Since the elementary amplifying stages are inverting, two stages can be connected in succession
(as a cascade) to form the needed non-inverting amplifier. In this configuration, each amplifier
may be considered as an active inverting feedback network for the other inverting amplifier.
Thus the two stages are connected in a non-inverting loop although the circuit diagram is usually
drawn as a symmetric cross-coupled pair (both the drawings are initially introduced in the
Eccles–Jordan patent).
The D ﬂip-ﬂop is widely used. It is also known as a "data" or "delay" flip-flop.
The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as
the rising edge of the clock). That captured value becomes the Q output. At other times, the
output Q does not change
The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the J
= K = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a
command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop;

and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the
logical complement of its current value. Setting J = K = 0 maintains the current state. To
synthesize a D flip-flop, simply set K equal to the complement of J. Similarly, to synthesize a T
flip-flop, set K equal to J. The JK flip-flop is therefore a universal flip-flop, because it can be
configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop.
7. PROCEDURE
8. RESULT: Truth table of D flip flop and JK master Slave Flip flop by using ICs
74LS74,74LS73 is verified.
9. VIVA QUESTIONS:
1. How many flip-flops are required to make a MOD-32 binary counter?

2. How is a J-K flip-flop made to toggle?
3. How many flip-flops are in the 7475 IC?
4. How many flip-flops are required to produce a divide-by-128 device?
5. On a master-slave flip-flop, when is the master enabled?

EXPERIMENT NO : 10
UNIVERSAL SHIFT REGISTERS-74LS194/195.
1. AIM:
To verify the truth table of universal shift register by using IC 74L194/195.
2. HARDWARE:
i. IC74LS194/195
3. PIN DIAGRAM

5. THEORY:
Universal Shift Register is a register which can be configured to load and/or retrieve the data in
any mode (either serial or parallel) by shifting it either towards right or towards left. In other
words, a combined design of unidirectional (either right- or left-shift of data bits as in case of
SISO, SIPO, PISO, PIPO) and bidirectional shift register along with parallel load provision is
referred to as universal shift register. Such a shift register capable of storing n input bits is
shown by Figure 1. The design shown by Figure 1 uses n 4×1 multiplexers to drive the
input pins of n flip-flops in the register which are also connected to clock and clear inputs. All of
the multiplexers in the circuit share the same select lines, S1 and S0 (pink lines in the figure), in

order to select the mode in which the shift registers operates. It is also seen that the MUX driving
a particular flip-flop has its
1. First input (Pin Number 0) connected to the output pin of the same flip-flop i.e. zeroth pin
of MUX1 is connected to Q1, zeroth pin of MUX2 is connected to Q2, … zeroth pin of
MUXn is connected to Qn.
2. Second input (Pin Number 1) connected to the output of the very-previous flip-flop
(except the first flip-flop FF1 where it acts like an serial-input to the input data bits which
are to be shifted towards right) i.e. first pin of MUX2 is connected to Q1, first pin of
MUX3 is connected to Q2, … first pin of MUXn is connected to Qn-1.
3. Third input (Pin Number 2) connected to the output of the very-next flip-flop (except the
first flip-flop FFn where it acts like an serial-input to the input data bits which are to be
shifted towards left) i.e. second pin of MUX1 is connected to Q2, second pin of MUX2 is
connected to Q3,… second pin of MUXn-1 is connected to Qn.
4. Fourth input (Pin Number 3) connected to the individual bits of the input data word
which is to be stored into the register, thus providing the facility for parallel loading.
7. PROCEDURE
8. RESULT: Truth table of universal shift register by using IC 74L194/195 is verified.
9. VIVA QUESTIONS:
1. On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = 1. On the
sixth clock pulse, the sequence is..
2. What is a shift register that will accept a parallel input, or a bidirectional serial load and
internal shift features, called?
3. How can parallel data be taken out of a shift register simultaneously?

4.What is meant by parallel load of a shift register?
5. In a 6-bit Johnson counter sequence there are a total of how many states, or bit patterns?

Part – II: HDL Simulation Programs

Introduction
Xilinx ISE : Is a software tool produced by Xilinx for synthesis and analysis of HDL designs
Which enables the developer to synthesize ("compile") their designs, perform timing analysis
examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the
Target device with the programmer.
In our Lab, the scope is limited to design and analyze the design using test benches
&Simulation.
The following is the step by step procedure to design in the Xilinx ISE
1. New Project Creation
Once the Xilinx ISE Design suite is started, open a new project & enter your design
Name and the location path. By default HDL is selected as the top-level source type. (If
Not, please select Top-level source type as HDL)

2. Continue to the next window and check if the Preferred Language is selected as Verilog
3 Proceed by clicking „Next and create a New Source using the Create New Source Window

4. Select the source type as Verilog Module and input a filename and proceed to Next. In the
next window Define Module enter the ports.
5. Finish with the new project setup with the Summary window.

6. Once Finish is selected a pop-up appears to create the directory. Select yes
7. Then proceed to Next in the “New Project Wizard to Add Existing Sources Add source if
an existing source is available, If not proceed to Next and finish with the Project Summary
window

8. Design Entry and Syntax Check
The ports defined during the Project Creation are defined as a module in the filename File
9. Input your design (verilog code) within the module definition

10. Select the design from the Hierarchy window. In the below window of Processes Implement
Design would be orange (in color) ready for implementation
11. Double click on implement design, it turns green (in color) once the design is
implemented successfully and the Summary report is displayed.

12. Test-Bench creation, Simulation & Verification
To add a test-bench to the existing design, right click on the v file from the
HierarchyWindow and select New Source
13. Select Verilog Text Fixture from the Select Source Type and name the Test-Bench

14. Continue toFinish and a test bench is added in the project area
15. Edit the test bench as per your simulation requirements and select Behavioral
Simulation in the Design Window. In the Processes window Simulator would be displayed. First
Proceed with the Behavior al Check Syntax.

EXPERIMENT 1
REALIZATION OF LOGIC GATES
AIM: To develop the source code for logic gates by using VERILOG and obtain the
simulation, synthesis, place and route and implement into FPGA.
SOFTWARE & HARDWARE REQUIREMENTS:
PC, Xilinx ISE 9.2i, FPGA-SPARTAN-3
THEORY:
TYPE DISTINCTIVE SHAPE BOOLEAN EXPRESSION
B/W A & B
AND A.B
OR A+B
NOT
NAND
NOR
XOR
XNOR OR

TRUTH TABLES OF ALL LOGIC GATES
AND gate
OR gate
NOT gate
NAND gate
NOR gate
EX-OR gate

EX-NOR gate
SOURCE CODE:
//VERILOG CODE FOR LOGIC GATES
Module logicgates(
input A,
input B,
output notA,
output andAB,
output orAB,
output nandAB,
output norAB,
output xorAB,
output xnorAB
);
/*seven different logic gates acting on four bits buses*/
assign notA=~A;
assign andAB = A&B;
assign orAB = A|B;
assign nandAB = ~(A&B);
assign norAB = ~(A|B);
assign xorAB = A^B;

assign xnorAB = ~(A^B);
endmodule
OBSERVATION:
EXPECTED OUTPUT WAVEFORMS:
RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC
RESULT: Thus the Output’s of All Logic Gate are verified by synthesizing and
simulating the VERILOG code.

EXPERIMENT 2
FULL ADDER USING THREE MODELLING STYLES
AIM: To develop the source code for full adder in three modelling styles by using VERILOG and
obtain the simulation, synthesis, place and route and implement into FPGA.
SOFTWARE & HARDWARE REQUIREMENTS: PC, Xilinx ISE 9.2i,FPGA-SPARTAN-3
THEORY: FULL ADDER CIRCUIT
SUM=A^B^C
CARRY=AB+BC+CA
SOURCE CODE:
A) DATA FLOW MODEL:

module fulladder(
input A,
input B,
input Ci,
output S,
output Co
);

assign S= A^B^Ci;
assign Co= (A&B)|(B&Ci)|(A&Ci);
endmodule
B) STRUCTURAL MODEL
module fulladder(
input A,
input B,
inputCi,
output S,
output Co
);
wire z1,z2,z3,z4;
and AND1(z1,A,B);
and AND2(z2,B,Ci);
and AND3(z3,A,Ci);
or OR1(Co,z1,z2,z3);
xor XOR1(z4,A,B);
xor XOR2(S,z4,Ci);
endmodule
C) BEHAVIORAL ARRANGEMENT
module fulladder(
input A,
input B,
inputCi,
output reg S,
output reg Co
);
always @(Ci,A,B)
begin
Case({Ci,A,B})
3’b000:{Co,S}= 2’b00;
3’b001:{Co,S}= 2’b01;
3’b010:{Co,S}= 2’b01;
3’b011:{Co,S}= 2’b10;
3’b100:{Co,S}= 2’b01;
3’b101:{Co,S}= 2’b10;
3’b110:{Co,S}= 2’b10;
3’b111:{Co,S}= 2’b11;
endcase
end
endmodule

OBSERVATION:
LUT3_96

LUT-E8
RESULT: Thus the Outputs of Full Adder are verified by synthesizing and simulating the
VERILOG code
EXPERIMENT 3

BINARY TO GRAY & GRAY TO BINARY CONVERTERS
AIM:To develop the source code for Binary to Gray and Gray to Binary Converters by using
VERILOG and obtain the simulation, synthesis, place and route and implement into FPGA.
THEORY: BINARY TO GRAY CONVERSION
GRAY TO BINARY CODE CONVERSION

SOURCE CODE:

BINARY TO GRAY CODE CONVERSION
A) Data flow
module converter(
input B3,
input B2,
input B1,
input B0,
output G3,
output G2,
output G1,
output G0);
assign G3= B3;
assign G2= B3^B2;
assign G1=B2^B1;
assign G0= B1^B0;
endmodule
GRAY TO BINARY CONVERSION
module converter(
input [3:0] G,
output [3:0] B);
assign B[3]= G[3];
assign B[2]= B[3]^G[2];
assign B[1]=B[2]^G[1];
assign B[0]= B[1]^G[0];
endmodule

OBSERVATION:

RESULT: Thus the Outputs of Binary to Gray and Gray to Binary Converters are verified by
synthesizing and simulating the VERILOG code.

EXPERIMENT 4
3X8 DECODER and 8X3 ENCODER
AIM:To develop the source code for 3X8 DECODER and 8x3 ENCODER by using VERILOG
and obtain the simulation, synthesis, place and route and implement into FPGA.
THEORY:
An encoder is a digital circuit which performs the inverse of decoder. An encoder has
2^N input lines and N output lines. In encoder the output lines generate the binary code
corresponding to input value. The decimal to bcd encoder usually has 10 input lines and 4 output
lines. The decoder decimal data as an input for decoder an encoded bcd output is available at 4
output lines.
Y2 = w7 + w6 + w5 + w4
Y1 = w7 + w6 + w3 + w2
Y0 = w7 + w5 + w3 + w1
3 TO 8 DECODER:
8 TO 3 ENCODER:

SOURCE CODE:
Verilog program for 8x3 encoder:
module encoder (din, dout);
input [7:0] din; output [2:0] dout; reg [2:0] dout;
always @(din)
begin
if (din ==8'b00000001) dout=3'b000;
else if (din==8'b00000010) dout=3'b001;
else if (din ==8'b00100000) dout=3'b101;
else dout=3'bX;
end
endmodule

OBSERVATION:
EXPECTED WAVEFORMS
RTL SCHEMATIC:
3 TO 8 DECODER
module decoder_3to8(Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0, A, B, C, en);
output Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0;
input A, B, C;
input en;
assign {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} = ( {en,A,B,C} == 4'b1000) ? 8'b1111_1110 :

( {en,A,B,C} == 4'b1001) ? 8'b1111_1101 :
( {en,A,B,C} == 4'b1010) ? 8'b1111_1011 :
( {en,A,B,C} == 4'b1011) ? 8'b1111_0111 :
( {en,A,B,C} == 4'b1100) ? 8'b1110_1111 :
( {en,A,B,C} == 4'b1101) ? 8'b1101_1111 :
( {en,A,B,C} == 4'b1110) ? 8'b1011_1111 :
( {en,A,B,C} == 4'b1111) ? 8'b0111_1111 :
8'b1111_1111;
endmodule
OBSERVATION:
EXPECTED WAVEFORMS
RTL SCHEMATIC:

RESULT: Thus the Outputs of 3X8 DECODER and 8x3 ENCODER are verified by

EXPERIMENT 5
8X1 MULTIPLEXER and 1X8 DEMULTIPLEXER
Aim:To develop the source code for 8X1 Multiplexer using 4x1 MUX and 1X8
DEMULTIPLEXER by using VERILOG and obtain the simulation, synthesis, place and route
and implement into FPGA.
Software & Hardware Requirements: PC, Xilinx ISE 9.2i,FPGA-SPARTAN-3
THEORY:
input S2 S1 S0 Output
L0 0 0 0 L0
L1 0 0 1 L1
L2 0 1 0 L2
L3 0 1 1 L3
L4 1 0 0 L4
L5 1 0 1 L5
L6 1 1 0 L6
L7 1 1 1 L7

SOUR CE CODE:
8X1 MULTIPLEXER:
module mux2to1(a,b,sel,out);
input a,b,sel;
output out;
tri out;
bufif1 (out,a,sel);
bufif0 (out,b,sel);
endmodule
module mux4to1(a,sel,out);
input [3:0] a;
input [1:0] sel;
output out;

wire mux[2:0];
mux2to1 m1 (a[3],a[2],sel[0],mux_1),
m2 (a[1],a[3],sel[0],mux_2),
m3 (mux_1,mux_2,sel[1],out);
endmodule
module mux8to1(a,sel,out);
input [7:0] a;
input [2:0] sel;
output out;
wire mux[2:0];
mux4to1 m1 (a[7:4],sel[1:0],mux_1),
m2 (a[3:0],sel[1:0],mux_2);
mux2to1 m3 (mux_1,mux_2,sel[2],out);
endmodule
DEMULTIPLEXER
moduledemux(
input [2:0] s,
input x,
output [7:0] y
);
wire z1,z2,z3,z4;
not NOT1(z1,s[0]);
not NOT2(z2,s[1]);
not NOT3(z3,s[2]);
and AND1(y[0],z3,z2,z1);
and AND2(y[1],z3,z2,s[0]);
and AND3(y[2],z3,s[1],z1);

and AND4(y[3],z3,s[1],s[0]);
and AND5(y[4],s[2],z2,z1);
and AND6(y[5],s[2],z2,s[0]);
and AND7(y[6],s[2],s[1],z1);
and AND8(y[0],s[2],s[1],s[0]);
end module
OBSERVATION:

RTL SCHEMATIC:
8X1 MUX:
DEMUX TECHNOLOGY SCHEMATIC

RESULT: Thus the Outputs of 8x1 Multiplexer and 1x8 Demultiplexer are verified by

EXPERIMENT 6
DESIGN OF SR and D FLIP -FLOPS
Aim:To develop the source code for SR and D Flip –Flops By using VERILOG and obtain the
THEORY: D FLIP FLOP

SOUR CE CODE:
module DFF(
input wire D,
input wire CLK,
outputreg Q=0,
outputregQbar=1
);
always @(posedge CLK)
begin
Q=D;
Qbar= ~Q;
end
endmodule
OBSERVATION:

SR FLIP FLOP
THEORY:

SOUR CE CODE:
module SR(
input S,
input R,
inputClk,
outputregQa=1’b0,
outputregQb=1’b1
);
wireS,R,Clk;
rega,b;
always @(S,R,Clk)
begin
a=Qa;
b=Qb;
if(Clk==1’b1)
case({S,R})
‘b00:{Qa,Qb}={a,b};
‘b01:{Qa,Qb}=’b01;
‘b10:{Qa,Qb}=’b10;
endcase
elseif(Clk==1’b0)
{Qa,Qb}={a,b};
end
endmodule

OBSERVATION:
TEST BENCH WAVEFORM
RESULT: Thus the Outputs of all the SR and D FLIP-FLOPs are verified by synthesizing and

EXPERIMENT 6
DESIGN OF JK and T FLIP -FLOPS
Aim:To develop the source code for JK and T Flip –Flops By using VERILOG and obtain the
THEORY:
T FLIP FLOP
THEORY:
PROGRAM CODE:
module TFF(
input T,
inputClk,
outputreg Q=0,
outputregQbar=1,
outputreg Di
);
always @(posedgeClk)

Begin
Di=T;
Q=Di;
Qbar=~Q;
end
endcase
OBSERVATION:
TEST BENCH WAVEFORM

JK FLIP FLOP
THEORY:

SOURCE CODE:
module JKFF(
input wire J,
input wire K,
input wire Clk,
outputreg Q=0,
outputregQbar=1
);
rega,b;
always @(posedgeClk)
begin
a=Q;
b=~Q;
case({J,K})
‘b00:{Q,Qbar}={a,b};
‘b01:
begin
Q=0;
a=Q;
b=~Q;
Qbar=b;
end
‘b10:
begin
Q=1; a=Q; b=~Q;Qbar=b;
end
‘b11:{Q,Qbar}={b,a};

endcase
end
endmodule
OBSERVATION:
RESULT: Thus the Outputs of all the SR and D FLIP-FLOPs are verified by synthesizing and

EXPERIMENT 8
DECADE COUNTER & UP-DOWN COUNTER
Aim:To develop the source code for Decade Counter By using VERILOG and obtain the
Theory
A binary counter can be constructed from J-K flip-flops by taking the output of one cell to the
clock input of the next. The J and K inputs of each flip-flop are set to 1 to produce a toggle at
each cycle of the clock input. For each two toggles of the first cell, a toggle is produced in the
second cell, and so on down to the fourth cell. This produces a binary number equal to the
number of cycles of the input clock signal. This device is sometimes called a "ripple through"
counter. The same device is useful as a frequency divider.
DECADE COUNTER:
PROGRAM:
module decade_counter(
input clock,
input reset,
output reg [3:0] q );
always@(posedge clock)
begin
if(reset)
q <=4'b0000;
else if(q<=4'b1000)
q <= q+1'b1;
else
q <= 4'b0000;
end
endmodule

OBSERVATION:
RTL SCHEMATIC:
WAVE FORMS:
UP-DOWN COUNTER:
PROGRAM:
module up_down_counter (
out , data, // Output of the counter
up_down , // up_down control for counter
clk , // clock input
reset // reset input
);
//----------Output Ports--------------

output [7:0] out;
//------------Input Ports--------------
input [7:0] data;
input up_down, clk, reset;
//------------Internal Variables--------
reg [7:0] out;
//-------------Code Starts Here-------
always @(posedge clk)
if (reset) begin // active high reset
out <= 8'b0 ;
end else if (up_down) begin
out <= out + 1;
end else begin
out <= out - 1;
end
endmodule

OBSERVATION:
RTL SCHEMATIC:
WAVE FORMS:
RESULT: Thus the Outputs of Counter is verified by synthesizing and simulating the VERILOG
code.

EXPERIMENT 9
UNIVERSAL SHIFT REGISTER
Aim: To Design and Implement Universal Shift Register using verilog.
Software & Hardware Requirements: pc, xilinx ise 9.2i,fpga-spartan-3
THEORY:
Universal shift registers are very useful digital devices. They can be configured to
respond to operations that require some form of temporary memory, delay information such as
the SISO or PIPO configuration modes or transfer data from one point to another in either a
serial or parallel format. Universal shift registers are frequently used in arithmetic operations to
shift data to the left or right for multiplication or division.

PROGRAM:
module Universal_shift_reg (data_out, msb_out, lsb_out, data_in, msb_in, lasb_in, s1, s0, clk,
rst);
output [3:0] data_out; // Hold
output msb_out, lsb_out; // Serial shift from msb
input [3:0] data_in; // Serial shift from lsb
input msb_in, lsb_in; // Parallel load
input s1, s0, clk, rst;
reg data_out;
assign msb_out= data_out[3];
assign lsb_out= data-out[0];
always @ (posedge clk)
begin
if (rst) data_out<=0;
else case ({s1, s0})
0 : data_out <= data_out;
1 : data_out <= {msb_in, data_out[3:1]};
2 : data_out <= {data_out[2:0], lsb_in};
3 : data_out <= data_in;
endcase
end
endmodule
SIMULATION OUTPUT:
RESULT: The Design of Universal Shift Register is implemented and verified.

EXPERIMENT 10
BINARY MULTIPLIER
Aim:To develop the source code for Binary Multiplier by using VERILOG and obtain the
Theory

Program
module mult8(p,x,y);
output [15:0]p;
input [7:0]x,y;
reg [15:0]p=0;
reg [7:0]a;
integer i;
always @(x , y)
begin
a=x;
for(i=0;i<8;i=i+1)
begin
if(y[i])
begin
p<=p+a;
a=a<<1;
end
else
a=a<<1;
end
end
endmodule

OBSERVATIONS:
RESULT: Thus the Outputs of Binary Multiplier is verified by synthesizing and simulating the
VERILOG code.

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Lab Manual IC Applications & HDL Simulation Lab Autonomous -R–01 Regulation

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

IC Applications & HDL Simulation Lab

B. Tech (ECE) - V Sem.

CMR COLLEGE OF ENGINEERING & TECHNOLOGY

List of the Experiments

Department of ECE, CMRCET - Hyderabad Page 1

S. No. Name of the experiment Page

1 Adder, Subtractor, Comparator Using IC 741 Op-Amp. 7

2 Integrator And Differentiator Using IC741 Op-Amp. 13

3 Active Low Pass & High Pass Butterworth (Second Order) 18

4 RC Phase Shift And Wein Bridge Oscillators Using IC 741 OP-Amp 24

5 IC 555 Timer In Monostable And Astable Multivibrator Circuits 30

6 Voltage Regulators IC 723, Three Terminal Voltage Regulators -7805, 34

8 4 bit comparator 74LS85. 42

9 D Flip-Flop (74LS74) and JK Master –Slave Flip-Flop (74LS73). 45

10 Universal Shift registers-74LS194/195. 49

Part – II: HDL Simulation Programs

S. No. Name of the experiment Page No.

1 HDL code to simulate basic gates

2 Full adder using 3 modelling Styles

4 Design of 3x8 Decoder and 8x3 Encoder

8 Decade counter & Up down counter

9 Universal Shift register

Department of ECE, CMRCET - Hyderabad Page 2

Part – I: Linear IC Experiments

AIM: To Study about IC741 (Op-Amp), IC555 (Timer), IC565 (PLL).

COMPONENTS: IC741, IC555, IC565.

IC741 : (Operational Amplifier)

Supply Voltage  18V

Internal Power Dissipation 310mw

Department of ECE, CMRCET - Hyderabad Page 3

Differential input voltage  30V

Input Voltage  15V

Operating temperature range 0ºC to 70ºC

Short circuit Protection

Off Set Null Capability

Large Common mode and differential Voltage ranges

Low Power Dissipation

IC 555 : (Timer ) Pin Configuration

Department of ECE, CMRCET - Hyderabad Page 4

Functional block diagram:

Supply Voltage 5V to 18V

IC565 : ( Phase locked loop):

Department of ECE, CMRCET - Hyderabad Page 5

Department of ECE, CMRCET - Hyderabad Page 6

OPAMP APPLICATIONS – ADDER, SUBTRACTOR & COMPARATOR CIRCUITS

APPARATUS : Bread Board.

Department of ECE, CMRCET - Hyderabad Page 7

I =------ + -------+ -------

V0 = -Rf ( ------+ ------+ --------- )

Department of ECE, CMRCET - Hyderabad Page 8

V0 = - (Rf/R) (Va +Vb + Vc)

Output of a differential amplifier (subtractor) is given as

Comparator : A Comparator is a non-linear signal processor. It is an open loop mode

Department of ECE, CMRCET - Hyderabad Page 9

1. connect the comparator circuit as shown in fig.(c)

Department of ECE, CMRCET - Hyderabad Page 10