In 

digital logic and computing, a counter is a device which stores (and sometimes displays) the number
of times a particular event or process has occurred, often in relationship to a clock signal. In practice,
there are two types of counters:

 Up counters, which increase (increment) in value

 Down counters, which decrease (decrement) in value
Contents
 [hide]

1 In electronics

o 1.1 Asynchronous

(ripple) counter

o 1.2 Synchronous

counter

o 1.3 Ring counter

o 1.4 Johnson counter

o 1.5 Decade counter

o 1.6 Up–down counter

2 In computer science

3 Mechanical counters

4 References

5 See also

[edit]In electronics
In electronics, counters can be implemented quite easily using register-type circuits such as the flip-flop,
and a wide variety of designs exist, e.g.:

 Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state flip-
flops
 Synchronous counter – all state bits change under control of a single clock
 Decade counter – counts through ten states per stage
 Up–down counter – counts both up and down, under command of a control input
 Ring counter – formed by a shift register with feedback connection in a ring
 Johnson counter – a twisted ring counter
 Cascaded counter
Each is useful for different applications. Usually, counter circuits are digital in nature, and count in natural
binary. Many types of counter circuit are available as digital building blocks, for example a number of
chips in the 4000 series implement different counters.

Occasionally there are advantages to using a counting sequence other than the natural binary sequence
—such as the binary coded decimal counter, a linear feedback shift register counter, or a Gray-
code counter.

Counters are useful for digital clocks and timers, and in oven timers, VCR clocks, etc.[1]

[edit]Asynchronous (ripple) counter

Asynchronous counter created from two JK flip-flops

An asynchronous (ripple) counter is a single D-type flip-flop, with its D (data) input fed from its own
inverted output. This circuit can store one bit, and hence can count from zero to one before it overflows
(starts over from 0). This counter will increment once for every clock cycle and takes two clock cycles to
overflow, so every cycle it will alternate between a transition from 0 to 1 and a transition from 1 to 0.
Notice that this creates a new clock with a 50% duty cycle at exactly half the frequency of the input clock.
If this output is then used as the clock signal for a similarly arranged D flip-flop (remembering to invert the
output to the input), you will get another 1 bit counter that counts half as fast. Putting them together yields
a two bit counter:

Cycl
Q1 Q0 (Q1:Q0)dec
e

0 0 0 0

1 0 1 1

2 1 0 2
 3 1 1 3

4 0 0 0

You can continue to add additional flip-flops, always inverting the output to its own input, and using the
output from the previous flip-flop as the clock signal. The result is called a ripple counter, which can count
to 2n-1 where n is the number of bits (flip-flop stages) in the counter. Ripple counters suffer from unstable
outputs as the overflows "ripple" from stage to stage, but they do find frequent application as dividers for
clock signals, where the instantaneous count is unimportant, but the division ratio overall is. (To clarify
this, a 1-bit counter is exactly equivalent to a divide by two circuit; the output frequency is exactly half that
of the input when fed with a regular train of clock pulses).

The use of flip-flop outputs as clocks leads to timing skew between the count data bits, making this ripple
technique incompatible with normal synchronous circuit design styles.

[edit]Synchronous counter

A 4-bit synchronous counter using JK flip-flops

A simple way of implementing the logic for each bit of an ascending counter (which is what is depicted in
the image to the right) is for each bit to toggle when all of the less significant bits are at a logic high state.
For example, bit 1 toggles when bit 0 is logic high; bit 2 toggles when both bit 1 and bit 0 are logic high; bit
3 toggles when bit 2, bit 1 and bit 0 are all high; and so on.

Synchronous counters can also be implemented with hardware finite state machines, which are more
complex but allow for smoother, more stable transitions.

Hardware based counters are of this type.

[edit]Ring counter
Main article:  Ring counter

A ring counter is a shift register (a cascade connection of flip-flops) with the output of the last one
connected to the input of the first, that is, in a ring. Typically a pattern consisting of a single 1 bit is
circulated, so the state repeats every N clock cycles if N flip-flops are used. It can be used as a cycle
counter of N states.

[edit]Johnson counter
Main article:  Ring counter

A Johnson counter (or switchtail ring counter, twisted-ring counter, walking-ring counter, or Moebius
counter) is a modified ring counter, where the output from the last stage is inverted and fed back as input
to the first stage.[2][3][4] A pattern of bits equal in length to twice the length of the shift register thus
circulates indefinitely. These counters find specialist applications, including those similar to the decade
counter, digital to analog conversion, etc.

[edit]Decade counter
A decade counter is one that counts in decimal digits, rather than binary. A decade counter may have
each digit binary encoded (that is, it may count in binary-coded decimal, as the 7490 integrated circuit did)
or other binary encodings (such as the bi-quinary encoding of the 7490 integrated circuit). Alternatively, it
may have a "fully decoded" or one-hot output code in which each output goes high in turn; the 4017 was
such a circuit. The latter type of circuit finds applications in multiplexers and demultiplexers, or wherever a
scanning type of behavior is useful. Similar counters with different numbers of outputs are also common.

The decade counter is also known as a mod-counter.

[edit]Up–down counter
A counter that can change state in either direction, under the control of an up–down selector input, is
known as an up–down counter. When the selector is in the up state, the counter increments its value;
when the selector is in the down state, the counter decrements the count.

[edit]In computer science

Main article:  Register machine

In computability theory, a counter is considered a type of memory. A counter stores a single natural

number (initially zero) and can be arbitrarily many digits long. A counter is usually considered in
conjunction with a finite-state machine (FSM), which can perform the following operations on the counter:

 Check whether the counter is zero

 Increment the counter by one
 Decrement the counter by one (if it's already zero, this leaves it unchanged).
The following machines are listed in order of power, with each one being strictly more powerful than the
one below it:

1. Deterministic or non-deterministic FSM plus two counters

2. Non-deterministic FSM plus one stack
3. Non-deterministic FSM plus one counter
4. Deterministic FSM plus one counter
5. Deterministic or non-deterministic FSM

For the first and last, it doesn't matter whether the FSM is a deterministic finite-state machine or
a nondeterministic finite-state machine. They have equivalent power. The first two and the last one are
levels of the Chomsky hierarchy.

The first machine, an FSM plus two counters, is equivalent in power to a Turing machine. See the article
on register machines for a proof.

Introduction

Circuits for counting events are frequently used in computers and other digital
systems.  Since a counter circuit must remember its past states, it has to possess
memory.  The chapter about flip-flops introduced how flip-flops are connected to
make a counter.  The number of flip-flops used and how they are connected
determine the number of states and the sequence of the states that the counter
goes through in each complete cycle.

Counters can be classified into two broad categories according to the way they
are clocked:

1. Asynchronous (Ripple) Counters - the first flip-flop is clocked by the

external clock pulse, and then each successive flip-flop is clocked by the Q
or Q' output of the previous flip-flop.

2. Synchronous Counters - all memory elements are simultaneously triggered

by the same clock.

In this tutorial, pure binary, decade and up-down counters within the two
categories will be introduced.
 Asynchronous
(Ripple) Counters

A two-bit asynchronous counter is shown on the left.

The external clock is connected to the clock input of
the first flip-flop (FF0) only.  So, FF0 changes state at
the falling edge of each clock pulse, but FF1 changes
only when triggered by the falling edge of the Q
output of FF0.  Because of the inherent propagation
delay through a flip-flop, the transition of the input
clock pulse and a transition of the Q output of FF0
can never occur at exactly the same time.
Therefore, the flip-flops cannot be triggered
simultaneously, producing an asynchronous
operation.

Note that for simplicity, the transitions of Q0, Q1 and CLK in the timing diagram
above are shown as simultaneous even though this is an asynchronous counter.
Actually, there is some small delay between the CLK, Q0 and Q1 transitions.    

Usually, all the CLEAR inputs are connected together, so that a single pulse can
clear all the flip-flops before counting starts.  The clock pulse fed into FF0 is
rippled through the other counters after propagation delays, like a ripple on
water, hence the name Ripple Counter.

The 2-bit ripple counter circuit above has four different states, each one
corresponding to a count value.  Similarly, a counter with n flip-flops can have 2
to the power n states.  The number of states in a counter is known as its mod
(modulo) number.  Thus a 2-bit counter is a mod-4 counter.

A mod-n counter may also described as a divide-by-n counter.  This is because

the most significant flip-flop (the furthest flip-flop from the original clock pulse)
produces one pulse for everyn pulses at the clock input of the least significant
flip-flop (the one triggers by the clock pulse).  Thus, the above counter is an
example of a divide-by-4 counter. 
The following is a three-bit asynchronous binary counter   and its timing
diagram for one cycle.  It works exactly the same way as a two-bit asynchronous
binary counter mentioned above, except it has eight states due to the third flip-
flop.

Asynchronous
Decade Counters
The binary counters previously introduced have two to the power n states.  But
counters with states less than this number are also possible.  They are designed to
have the number of states in their sequences, which are called truncated
sequences.  These sequences are achieved by forcing the counter to recycle before
going through all of its normal states.

A common modulus for counters with truncated sequences is ten.  A counter with
ten states in its sequence is called a decade counter.  The circuit below is an
implementation of a decade counter.
Once the counter counts to ten (1010), all the flip-flops are being cleared.  Notice
that only Q1 and Q3 are used to decode the count of ten.  This is called partial
decoding, as none of the other states (zero to nine) have both Q1 and Q3 HIGH at
the same time.

The sequence of the decade counter is shown in the table below:

Asynchronous
Up-Down Counters
In certain applications a counter must be able to count both up and down.  The
circuit below is a 3-bit up-down counter.  It counts up or down depending on the
status of the control signals UP and DOWN.  When the UP input is at 1 and the
DOWN input is at 0, the NAND network between FF0 and FF1 will gate the non-
inverted output (Q) of FF0 into the clock input of FF1.  Similarly, Q of FF1 will be
gated through the other NAND network into the clock input of FF2.  Thus the
counter will count up.
When the control input UP is at 0 and DOWN is at 1, the inverted outputs of FF0
and FF1 are gated into the clock inputs of FF1 and FF2 respectively.  If the flip-
flops are initially reset to 0's, then the counter will go through the following
sequence as input pulses are applied.

Notice that an asynchronous up-down counter is slower than an up counter

or a down counter because of the additional propagation delay introduced by
the NAND networks.

Synchronous Counters
In synchronous counters, the clock inputs of all the flip-flops are connected
together and are triggered by the input pulses.  Thus, all the flip-flops change state
simultaneously (in parallel).  The circuit below is a 3-bit synchronous counter.  The J
and K inputs of FF0 are connected to HIGH.  FF1 has its J and K inputs connected to
the output of FF0, and the J and K inputs of FF2 are connected to the output of an
AND gate that is fed by the outputs of FF0 and FF1.
Pay attention to what happens after the 3rd clock pulse.  Both outputs of FF0
and FF1 are HIGH.  The positive edge of the 4th clock pulse will cause FF2 to
change its state due to the AND gate.

The count sequence for the 3-bit counter is shown on the right.

The most important advantage of synchronous counters is that there

is no cumulative time delay because all flip-flops are triggered in
parallel.  Thus, the maximum operating frequency for this counter
will be significantly higher than for the corresponding ripple
counter.

Synchronous
Decade Counters
Similar to an asynchronous decade counter, a synchronous decade
counter  counts from 0 to 9 and then recycles to 0 again.  This is done by forcing
the 1010 state back to the 0000 state.  This so called truncated sequence can be
constructed by the following circuit.
 From the sequence on the left, we notice that:

 Q0 toggles on each clock pulse.

 Q1 changes on the next clock pulse each time Q0=1
and Q3=0.
 Q2 changes on the next clock pulse each time
Q0=Q1=1.
 Q3 changes on the next clock pulse each time Q0=1,
Q1=1 and Q2=1 (count 7), or when Q0=1 and Q3=1
(count 9).

These characteristics are implemented with the AND/OR logic connected as shown
in the logic diagram above.

Synchronous
Up-Down Counters
A circuit of a 3-bit synchronous up-down counter and a table of its sequence are
shown below.  Similar to an asynchronous up-down counter, a synchronous up-
down counter also has an up-down control input.  It is used to control the direction
of the counter through a certain sequence.

An examination of the sequence table shows:

 for both the UP and DOWN sequences, Q0 toggles on each

clock pulse.
 for the UP sequence, Q1 changes state on the next clock
pulse when Q0=1.
 for the DOWN sequence, Q1 changes state on the next clock
pulse when Q0=0.
 for the UP sequence, Q2 changes state on the next clock
pulse when Q0=Q1=1.
  for the DOWN sequence, Q2 changes state on the next clock
pulse when Q0=Q1=0.

These characteristics are implemented with the AND, OR & NOT logic connected as
shown in the logic diagram above.

Applications
Digital counters are very useful in many applications.  They can be easily found in
digital clocks and parallel-to-serial data conversion (multiplexing).  In this section,
we will use the later as an example on how counters are being used.

A group of bits appearing simultaneously on parallel lines is called parallel data.

A group of bits appearing on a single line in a time sequence is called serial data.
Parallel-to-serial conversion is normally accomplished by the use of a counter to
provide a binary sequence for the data-select inputs of a multiplexer, as
illustrated in the circuit below.

The Q outputs of the modulus-8 counter are

connected to the data-select inputs of an eight-bit
multiplexer.  The first byte (eight-bit group) of parallel
data is applied to the multiplexer inputs.  As the
counter goes through a binary sequence from 0 to 7,
each bit beginning with D0, is sequentially selected
and passed through the multiplexer to the output
line. 

After eight clock pulses, the data byte has been

converted to a serial format and sent out on the
transmission line.  Then, the counter recycles back to
0 and converts another parallel byte sequentially
again by the same process.