Pulse and Digital Circuits laboratory, Department Of ECE 1

CIRCUIT DIAGRAM:

MODEL WAVE FORMS:

Pulse and Digital Circuits laboratory, Department Of ECE 2

EX NO: LINEAR WAVESHAPING - RC INTEGRATOR DATE:

AIM: To observe the response of the low pass RC circuit for

the given square waveform for T<<RC,T=RC and T>>RC

APPARATUS:

Resistors:1kΩ,10kΩ,100kΩ 1 No’s
Capacitors:0.1µF 1 No
Function Generator 1 No.
Connecting wires Required no.
Bread Board 1 No
CRO 1 No
CRO Probes 2 No’s

THEORY:

When time constant RC is chosen very large in comparisons with the time
interval t of the i/p waveform. This circuit may be called an Integrator. When time
constant is very large, R must be large. Therefore, voltage across capacitor C, will
be very small and it may be consider that all the i/p voltage appears across resistor
R only. Since Vin= Vc+Vr.

Vr is very large as resistance R is large and V C is very small. And thus Vin = Vr.
Under this condition, current I, in the circuit is totally determined by resistance R
only, which is given by I=Vin/Vr.
But o/p is taken across capacitor C therefore, o/p voltage Vo is given by

VO= Vc = 1/c ∫idt ; ∴ Vo = 1/c ∫ (Vin/R)dt

∴ Vo =1/RC ∫ Vin dt

Hence o/p of low pass RC circuit is proportional to the integral of the i/p
voltage, when time constant is very large. Raise time ( t r ) may be defined as the time
taken by an RC circuit to raise its o/p voltage from 0.1v to 0.9v of its maximum value
(V). Where V is the amplitude of the applied voltage. It gives an indication of how fast
the circuit can respond to a discontinuation of applied voltage.
Calculations:
Given
C = 0.1 µF
R = 10 KΩ T= 1ms

Pulse and Digital Circuits laboratory, Department Of ECE 3

Pulse and Digital Circuits laboratory, Department Of ECE 4
PROCEDURE:

1. All the connections are made as per the circuit diagram.

2. The i/p signal voltage is fixed to 10v p-p and 1 KHz frequency.
3. Change the value of the resistor to 1k,10k and 100k
4. Now, the i/p signal is applied to the integrator and the o/p waveforms are
observed on CRO at 3 different time constants. I.e. RC>>T, RC =T and
RC<<T

PRECAUTIONS:

1. Connections should be tight.

2. Take care when biasing the supply.

RESULT:

VIVA QUESTIONS:

1. What is high pass circuit under what condition it acts as a differentiator?

2. What is low pass circuit under what condition it acts as a integrator?
3. What happens when a sine wave is applied to a differentiator or integrator
circuit?
4. What are different applications of a differentiator?
5. What are different applications of a integrator?

Pulse and Digital Circuits laboratory, Department Of ECE 5

CIRCUIT DIAGRAM:

MODEL WAVE FORMS:

Pulse and Digital Circuits laboratory, Department Of ECE 6

EX NO: LINEAR WAVESHAPING- RC DIFFERENTIATOR DATE:

AIM: To observe the response of the high pass RC circuit for the given
square waveform for T<<RC,T=RC and T>>RC

APPARATUS:
Resistors:1kΩ,10kΩ,100kΩ 1 No’s
Capacitors:0.1µF 1 No
Function Generator 1 No.
Connecting wires Required no.
Bread Board 1 No
CRO 1 No
CRO Probes 2 No’s

THEORY:

When time constant RC is chosen very small in comparison with the time
interval t of the i/p waveform the circuit is called a differentiator. When time constant
is very small, R must be very small total i/p may be considered as appearing across
capacitor c only.

Vin = Vc+Vr
Since Vr is very small, Vin = Vc
Under this condition current I in the circuit is determined by capacitor only.
This is given by
I = C (dVi/dt)
But o/p is taken across resistor R. Therefore
Vo = I R.
= C* (dVi/dt) * R
= RC * (dVi/dt)
Hence o/p of high pass circuit is proportional to the derivative of i/p voltage, when
time constant is very small.

Pulse and Digital Circuits laboratory, Department Of ECE 7

Calculations:

Pulse and Digital Circuits laboratory, Department Of ECE 8

PROCEDURE:
1. Connections are made as per the circuit diagram.
2. The i/p signal which is given from signal generator to the high pass RC circuit
is fixed to 10V P-P and 1KHz.
3. The i/p signal is applied to differentiator circuit and taken the graphs.
4. Change the value of the resistor to 1k,10k and 100k
5. Draw the waveforms with p-p amplitude for the cases RC>>T, RC<<T and
RC=T.

PRECAUTIONS:

1. Connections should be tight.

2. Take care when biasing the supply.

RESULT:

VIVA QUESTIONS:

1. What is high pass circuit under what condition it acts as a differentiator?

2. What is low pass circuit under what condition it acts as a integrator?

3. What happens when a sine wave is applied to a differentiator or integrator

circuit?

4. What are different applications of a differentiator?

5. What are different applications of a integrator?

Pulse and Digital Circuits laboratory, Department Of ECE 9

CIRCUIT DIAGRAMS:

1. Shunt diode positive clipper

i) Input signal ii) Output signal

2. Shunt diode negative clipper

i)Input signal ii) Output signal

3.Series diode positive clipper

i)Input signal ii) Output signal

Pulse and Digital Circuits laboratory, Department Of ECE 10

EX NO: NON-LINEAR WAVESHAPING CLIPPERS DATE:

AIM: To obtain the response of different clipping circuits and to draw the output
waveforms of each clipping circuit.

APPARATUS:

Resistors:1kΩ 2 No’s
Diodes 1N4001 2 No’s
Function Generator 1 No.
Connecting wires Required No.
Bread Board 1 No
CRO 1 No
CRO Probes 2 No’s
RPS 1 No

THEORY:

When sinusoidal or non-sinusoidal waveforms are applied to non linear

networks consisting one nonlinear device such as diode or transistor the resultant
output waveform may be different from the i/p waveform. Hence the nonlinear circuit
said to shape the i/p voltage waveform. This is called non linear wave shaping.

The clipping circuit may be defined as a circuit that limits the amplitude of a
voltage by removing the signal above or below the reference voltage. Either +ve side
or –ve side or both sides of the waveform may be clipped. Clipping circuits are also
known as voltage or current limiters.

The diode clipper circuits are classified according to the placement of the
diode in the circuit as a series diode clipper or shunt diode clipper.

SHUNT DIODE CLIPPERS:

i) WITH POSITIVE BIAS CLIPPERS:

During the +ve half cycle Vi>Vr the diode acts as a short circuit and o/p
voltage is equals to the reference voltage Vr. When Vi <Vr the diode is reverse bias
and the total i/p voltage Vi appears across the open circuit o/p terminals as shown in
the figure.

ii) WITH NEGATIVE BIAS CLIPPERS:

During complete +ve half cycle as well as during –ve half cycle when Vi > Vr
the diode is reverse biased and it acts as a open circuit. Therefore Vi appears across
open circuit terminals of the o/p circuit.

Pulse and Digital Circuits laboratory, Department Of ECE 11

 4.Series diode negative clipper

i)Input signal ii) Output signal

5.Two level clipper

i)Input signal ii) Output signal

Pulse and Digital Circuits laboratory, Department Of ECE 12

SERIES DIODE CLIPPERS:

Assuming the diode used is an ideal the series diode clippers with +ve bias as
shown in the figure, The diode conducts during –ve half cycle as well as during +ve
half cycle when Vi<Vr as the anode of the diode is at the potential Vr. During this
conduction the current flows through the resistor when an o/p voltage appears
across the open circuited o/p terminals which is equal to Vi . During +ve half cycle
when Vi >Vr the diode is reverse biased no current flows through the resistor and the
o/p voltage equal to the reference voltage Vr.

Assuming the diode used is an ideal one the series diode clipper with +ve bias
is shown in the figure. The diode conducts only when Vi >Vr as the cathode is at the
potential of Vr. To make diode forward bias anode potential must be greater than Vr.
During +ve half cycle when Vi > Vr the diode is forward bias and the current flows
through the diode as well as resistor. An o/p voltage appears across the open circuit
output terminals which are equal to Vi. During –ve half cycle as well as during +ve
half cycle when Vi<Vr the diode is reverse bias and no current flows through the
diode , hence through the resistor . Thus o/p voltage equals to the reference voltage
Vr.

UNBIASED SHUNT CLIPPERS:

During the +ve half cycle the diode is forward biased and diode acts as a
short circuit for the i/p signal. Therefore o/p voltage is zero. During –ve half cycle the
diode is reverse biased and the diode acts as an open circuit. Thus Vi=Vr . During –
ve half cycle the diode is forward bias and acts as a short circuit for the i/p signal.
Therefore o/p is equal to zero. During +ve half cycle the diode is reverse biased and
the diode acts as an open circuit thus the o/p voltage = i/p voltage.

DOUBLE DIODE CLIPPERS:

This type of clippers is to clip at two independent levels. When both diodes
are not conducting o/p follows the i/p.

Diode D1 conducts during +ve half cycle when Vi>Vr1. Where as Diode D2
conducts during the –ve half cycle when Vi> Vr2. Thus during the period Vi<Vr1 and
Vi>Vr2 both diodes are reverse biased and the o/p voltage follows the i/p as shown
in the figure.

PROCEDURE:
1. Connections are made as per the circuit diagram.
2. The sinusoidal i/p signal which is given from signal generator to the various
clipper circuits.
3. Observe the output wave forms in the CRO and note down the amplitude at
which clipping occurs.
4. Draw the observed waveforms in the graph.

Pulse and Digital Circuits laboratory, Department Of ECE 13

Pulse and Digital Circuits laboratory, Department Of ECE 14
PRECAUTIONS:

1. Connections should be tight.

2. Take care when applying proper supply.

RESULT:

VIVA QUESTIONS:

1. Define clipping?

2. What are the other names for the clipper?

3. Define peak inverse voltage of diode?

4. What is slicer?

5. What are the applications of clippers?

6. Explain the clipping process?

Pulse and Digital Circuits laboratory, Department Of ECE 15

CIRCUIT DIAGRAMS-Negative Clamper

I) 0v reference voltage
i)input voltage ii).Output signal

II) +ve reference voltage

iii) -ve reference voltage

Pulse and Digital Circuits laboratory, Department Of ECE 16

EX NO: NON-LINEAR WAVESHAPING CLAMPERS DATE:

AIM: To understand the working of clamping circuits.

APPARATUS:
Resistors:1kΩ ,100KΩ 2 No’s
Diodes 1N4001 2 No’s
Function Generator 1 No.
Connecting wires =====
Bread Board 1 No
CRO 1 No
CRO Probes 2 No’s
RPS 1 No

THEORY:

Clamping circuits are circuits, which are used to clamp or fix the extremity of a
periodic wave form to some constant reference level. Clamping circuits may be one
way clamps or two way clamps.

The clamping circuits only changes the dc level of the input signal .It does not
affect its shape. Clamping circuits may be positive voltage clamping circuits or
negative voltage clamping circuits. In positive clamping, the negative extremity of the
wave form is at the reference level and the entire wave form appears above the
reference level. i.e. the output wave form is positively clamped with reference to the
reference level. In negative clamping the positive extremity of the wave form is fixed
at the reference level and the entire wave form appears below the reference voltage.
i.e. the output wave form is negatively clamped with reference to the reference level.

The capacitors are essential in the clamping circuits. The difference between
the clipping and clamping circuits is that while the clipper clips off an unwanted
portion of the input wave form, the clipper simply clamps the maximum positive or
negative peak of the wave form to a desired level.

Pulse and Digital Circuits laboratory, Department Of ECE 17

 2.POSITIVE CLAMPER

a). With 0v reference voltage i)input voltage ii).Output voltage

b). With -2V reference voltage

c). With+2Vreference voltage

Pulse and Digital Circuits laboratory, Department Of ECE 18

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. I/P signal is applied to the circuit with the amplitude of 10 v p-p and 1 KHz
frequency.
3. The AC / DC push button switch of CRO is to be kept in DC mode.
4. Note down the o/p amplitude for each and every circuit.
5. The O/P waveforms are to be drawn on the graph sheet.

RESULT:

VIVA QUESTIONS:

1. Define clamping?

2. Define peak inverse voltage of diode?

3. What are the other names for the clamper?

4. What are the applications of clampers?

5. Explain the clamping process?

Pulse and Digital Circuits laboratory, Department Of ECE 19

CIRCUIT DIAGRAMS:

MODEL WAVE FORMS:

i) In put signal

Pulse and Digital Circuits laboratory, Department Of ECE 20

EX NO: TRANSISTOR AS A SWITCH DATE:

AIM: To study the operation of Transistor as a switch.

APPARATUS:

Resistors:1kΩ,8.2K (15k,330k) 2 No’s

TransistorBC107 or 2N269 1 No’s
Function Generator 1 No.
Connecting wires Required No.
Bread Board 1 No
CRO 1 No
CRO Probes 2 No’s
RPS 1 No

THEORY:

A transistor can work in 3 regions i.e., Active region Saturation region and
Cut-off region. When the transistor is connected in CE configuration the conditions
for active region is base-emitter junction forward bias and collector-emitter junction
reverse bias.In this region transistor can act as an amplifier.
When emitter to base junction and collector emitter junction both are forward
bias the transistor is said to be in ‘Saturation Region’.
When emitter to base junction and collector to emitter junction are reverse
bias the transistor is said to be in ‘Cut-off region’.
To operate transistor as a switch it is made to operate in saturation or cut-off
region. If the switch is ON it is saturation region. If the switch is OFF it is in cut-off
region.
A pulse train with sufficient amplitude is applied to the transistor base. When
pulse is at high the emitter -base and collector-base junctions are forward bias.
Thus transistor enters into saturation or is ON. When pulse is at low both the
junctions are reverse biased and the transistor is cut-off or open circuited.
Depending up on the base control voltage the switch may be ON or OFF.

Pulse and Digital Circuits laboratory, Department Of ECE 21

Pulse and Digital Circuits laboratory, Department Of ECE 22
PROCEDURE:

1. All the connections are made as per the circuit diagram.

2. The square wave with p-p amplitude of 4v, and 1KHz frequency was given as i/p
to the circuit from function generator.
3. Observe and note down the o/p waveforms those appeared on the CRO with p-p
amplitude and time period.

RESULT:

VIVA QUESTIONS:

1. What are the different switching times of a transistor?

2. What is the Vbe of a ON transistor?

3. Define OFF time of a transistor?

4. Explain how transistor acts as a switch?

Pulse and Digital Circuits laboratory, Department Of ECE 23

GATE SYMBOLS:

TRUTH TABLES:

AND GATE NAND GATE

INPUTSOUTPUT
INPUTS INPUTS OUTPUT
A B Y A B Y
0 0 0 0 0 1
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0

OR GATE NOR GATE

INPUTS OUTPUT INPUTS OUTPUT
A B Y A B Y
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 1 1 1 0
NOT GATE EX-ORGATE

INPUT OUTPUT INPUTS OUTPUT

A Y A B Y
0 1 0 0 0
1 0 0 1 1
1 0 1
1 1 0

Pulse and Digital Circuits laboratory, Department Of ECE 24

EX NO: STUDY OF LOGIC GATES DATE:

AIM: To verify the truth tables of AND, OR, NOT, NAND and NOR gates.

APPARATUS:

Resistors:100k,4.7k,4.7kΩ Each 1 No
Diodes 1N4007 2 No’s
Connecting wires Required No.
Transistor BC107 1 No
RPS 1 No
Bread Board IC Trainer 1 No

THEORY:

In digital electronic circuits two discrete levels are recognized as two logic
levels logic ‘1’ and logic ‘0’. These are also known as high and low logic levels
depending up on the actual voltages. There are two logic circuits
1. Positive logic – in which higher voltage level corresponds to 1 (high) and the lower
level corresponds to 0(low)

2. Negative logic - in which the lower voltage level corresponds to logic 1 and the
higher voltage level corresponds to logic 0.

In digital circuits there are only 4 basic operations which are required to be
performed. These are AND, OR, NOT, and EX-OR. There are two types of digital
circuits.

1. Combinational circuits
2. Sequential circuits.

1. COMBINATIONAL CIRCUITS:

In combinational circuits the o/p at any 4 instances of time depend completely

on the i/p’s present at the instance of time. In such circuits only AND, OR, NOT
operations are required.

SEQUENTIAL CIRCUITS:

In sequential circuits the o/p at any instant of time depend up on the past o/p’s
as well as the present i/p’s at that instant of time. Here in addition to AND, OR, NOT
operations, Flip-Flops are also defined which can be used to realizes AND, OR,
NOT, operations.

Pulse and Digital Circuits laboratory, Department Of ECE 25

1.OR gate 4.NOT GATE

2.AND GATE 5.NAND GATE

3. NOR GATE:

Pulse and Digital Circuits laboratory, Department Of ECE 26

The function, logic diagram and truth table for each of the gates are given. These
tables illustrates AND, OR, NAND, and NOR gates with two i/p’s only. But the
number of i/p’s can be more than also.

These functions can be realized by using discrete devices such as Diodes,

BJT and FET’s. However since the gates are available in the form of ICs.

BASIC OPERATIONS:

AND GATE:

IC4LS08 is quad 2-i/p AND gate: It requires 5v between VCC and ground
terminals. The o/p of AND gate is HIGH when both the two i/p’s of AND gate are
HIGH. Otherwise the o/p always LOW.

IC74LS32 is quad 2-i/p OR gate: It requires 5v between VCC and ground

terminals. The o/p of OR gate is LOW when both the i/p’s are LOW. Other wise the
o/p always remains at “HIGH”.

IC4LS04 is hex NOT gate: It requires 5v between VCC and GND terminals. The o/p
of NOT gate is always the complement of i/p.

IC74LS00 is quad 2-i/p NAND gate: It requires 5v between VCC and ground
terminals. It is the series connection of AND and NOT gates. The o/p of NAND gate
is LOW when both the i/p’s of NAND gates are HIGH. Otherwise the o/p is HIGH.

IC74LS02 is quad 2-i/p NOR gate: It requires 5v between VCC and ground
terminals. It is the series connection of OR and NOT Gates. The o/p of NOR gate is
HIGH only when both the i/p’s of the NOR gate are at LOW. Other wise the o/p
remains at LOW.

IC74LS86 is quad 2-i/p EX-OR gate: It requires 5v between VCC and ground
terminals. The o/p of EX-OR gate is HIGH when two different i/p’s are applied .
Otherwise the o/p is LOW.

Pulse and Digital Circuits laboratory, Department Of ECE 27

Pulse and Digital Circuits laboratory, Department Of ECE 28
PROCEDURE:

1. +5V DC is applied at VCC (pin no:14) of each IC w..t. ground(pin no:7).

2. I/p’s are applied (at pin no’s 1 &2) and o/p is taken from (pin no:3).

3. I/p’s are applied from toggle switches and o/p is observed at o/p indicators.

PRECAUTIONS:

1. Avoid loose connections on Breadboard.

2. Take care while making connections with NOT and NOR gates.

RESULT:

VIVA QUESTIONS:

1. Which gate is called an ALL OR NOTHING gate?

2. Differentiate b/w Positive logic & Negative logic.

3. Why NAND , NOR gates are called Universal gates?

4. Differentiate b/w Combinational & Sequential circuits.

5. Define Logic gate & Logic circuit.

Pulse and Digital Circuits laboratory, Department Of ECE 29

CIRCUIT DIAGRAMS:

i)S-R FLIP-FLOP using NAND gate TRUTH TABLES:

S-R FLIP-FLOP:

ii)S-R FLIP-FLOP using NOR gate

iii)J-K FLIP- FLOP

Pulse and Digital Circuits laboratory, Department Of ECE 30

EX NO: STUDY OF FLIP FLOPS & SOME DATE:
APPLICATIONS

AIM: To construct and verify the truth tables of SR flip flop, JK flip flop, D and T flip -
flop.
APPRATUS:
Resistors:100k,4.7k,4.7kΩ Each 1 No
Connecting wires Required No.
IC74LS08 (AND) Each 1 No
IC74LS32 (OR)
IC 74LS04 (NOT)
IC74LS00 (NAND)
IC74LS02 (NOR)
IC74LS86 (EX-OR)
RPS 1 No
Bread Board IC Trainer 1 No

THEORY: A flip-flop can be constructed from two NAND gates or two NOR gates.
The cross coupled connection from the output of one gate to the input of the other
gate constitute a feedback path. Each flip flop has two out put Q and Q ─and two
inputs Set and Reset .This types of flip flop is sometimes called direct coupled flip
flop or SR latch

A JK Flip flop is a refinement of the RS flip-flop in that the intermediate state

of the RS type is defined in the JK type. Inputs J and K behave like inputs S and R to
set and clear the flip flop. The inputs J and K for set and the input marked k is for
reset. When both inputs J and K are equal to 1, the flip-flop switches to its
complement state, i.e. if Q=1, it switches to Q=0, and vice versa. A KJ flip-flop
constructed with two cross neither coupled NOR gates and two AND gates.

The T- flip-flop is a single input version of the JK flip-flop. The T flip-flop is

obtained from the JK Flip-flop when inputs are tied together. The designation T
comes from the ability of the ability of the flip-flop to “toggle” or complement, its state.

Pulse and Digital Circuits laboratory, Department Of ECE 31

 iv)D FLIP- FLOP TRUTH TABLES

D Qn+1 NOT(Qn+1)
0 0 1
1 1 0

v)T FLIP- FLOP

T Qn+1 NOT(Qn+1)
0 Qn 0
1 1

PIN DIAGRAM:

Pulse and Digital Circuits laboratory, Department Of ECE 32

 The D flip flop has two inputs D and CP. The D input goes directly to the
S input and its complement is applied to the R input. If D is 1, the output goes to 1,
placing the circuit in the Set state. If D is 0, the output Q goes to 0 and the circuit
switches to the clear state

PROCEDURE:

1. The input S, R is given to NAND gates and clock pulse is applied between
the other two terminals and NAND gates.
2. The input of the one NAND gate is connected to the other gate and vice
versa to form SR latch.
3. The output of the NAND gate whose input is S, is connected to the input of
the other NAND gate.
4. The output of the NAND gate whose input is R, is connected to the input of
the other NAND gate whose output is ‘Q1’.

J K flip-flop:

1. Connections are made as per the circuit diagram.

2. The inputs J1 and K1 are given to the pin numbers 14 and 3 of IC 7473.
3. Clock pulse CP1 is applied at the pin 1.
4. Vcc and ground connections are given to the pin 4 and 11.
5. The outputs Q1 and Q1 bar are connected to pin 12 and 13.
D flip-flop
1. Connections are made per the circuit diagram.
2. A NOT gate is connected between the inputs J and K.
3. From JK flip flop we can obtain the D flip flop.
T flip-flop
1. Connections are made as per the circuit diagram.
2. From J K flip flop, we can obtain the T flip-flop by shorting the two inputs J
and K.

Pulse and Digital Circuits laboratory, Department Of ECE 33

Pulse and Digital Circuits laboratory, Department Of ECE 34
RESULT:

VIVA QUESTIONS:

1. Differentiate b/w Flipflop & Latch.?

2. What is Race around condition in JK-flipflop?

3. Compare RS & JK Flipflop.?

4. Does Flipflop can act like Register.?

5 .What is the other name for Flipflop?

Pulse and Digital Circuits laboratory, Department Of ECE 35

 CIRCUIT DIAGRAM:

MODEL WAVEFORMS:

Pulse and Digital Circuits laboratory, Department Of ECE 36

EX NO: STUDY OF SAMPLING GATES DATE:

AIM: To construct and verify the response of sampling gate by using diode.

APPARATUS:

Resistors-1K,10K 1 No
Function Generator 1 No.
Connecting wires Required No.
Bread Board 1 No
CRO 1 No
CRO Probes 2 No’s
RPS 1 No
Diode 1N4007 1 No.

THEORY:

An ideal sampling gate is a transmission circuit that produces an output signal

identical to the input signal during a selected time interval. The output of the
sampling gate is zero outside this selected time interval. The sampling gate is open
during the sampling interval and it is closed at all other times. The time interval for
transmission is monitored by a control input signal, which is usually rectangular in
shape. In practice, the idealized transmission gate is not realized. As long as the
output is produced at the correct time the performance of the practical sampling
gates available is treated to be quite satisfactory.

PROCEDURE:

1. Connect the circuit as per circuit diagram

2. Apply sinusoidal input signal 1.2kHZ,10 Vp-p and square wave control signal
269HZ,15 Vp-p simultaneously to the circuit.
3. Note down the output waveforms.
PRECAUTIONS:
1. Connections should be tight.
2. Take care when applying the control signal.
RESULT:

VIVA QUESTIONS:
1. What is sampling gate?
2. What is the other name for the control signal?
3. What is the difference between logic gates and sampling gates?
4. What is the necessity of the sampling gate?

Pulse and Digital Circuits laboratory, Department Of ECE 37

CIRCUIT DIAGRAM:

MODEL WAVEFORMS:

.
\

Pulse and Digital Circuits laboratory, Department Of ECE 38

EX NO: ASTABLE MULTIVIBRATOR DATE:

AIM: To understand the response at base and collector points of the Astable
multivibrator.
APPARATUS:
Resistors: 4.7K,47K Each 2 No’s
Diodes 1N4001 2 No’s
Capacitor 0.01 µF 2 No’s.
Connecting wires Required No.
CRO 1 No
CRO Probes 2 No’s
RPS 1 No
Bread Board 1 No
Transistors BC107 2 No’s

THEORY:
Multivibrators are electronics circuits are used to generate waveform of type
non-sinusoidal. A multivibrator have two states if these states are semi stable states
it is called an astable multivibrator.
Astable multivabrator is called free running multivibrator. This vibrator
changes its state from one to another on its own without any application of external
trigger .The duration of each of the two semi stable state is dependent upon two RC
times constants within the multivibrator circuitDepending upon the β value we con
conform which transistor is in ON position. Higher value of β first switched ON, here
consider T2 enter into saturation and T1 is in cut-off when T2 is conducting, C2
changes to Vcc as T1 is off C2 cannot force its voltage on to the base of the T2.
Base of T2 gets sufficient bias voltage to operate in saturation through Rb2.
Therefore, T2 continues to conduct even though C2 is charged to Vcc. but when T2
is conducting +ve plate of the C1 is grounded though short circuited T2 . C1 is
already charged to VCC thus –ve plate is connected to base of T1, which reverse
biases NPN transistor and therefore T1 remains in cut-off. Now capacitor starts
charging through Rb1 and short circuited T2 from –VCC to +VCC. When charged
voltage on C1 becomes 0v, the base T1 starts getting +ve potential from C1 and it
enters into saturation.

Pulse and Digital Circuits laboratory, Department Of ECE 39

Pulse and Digital Circuits laboratory, Department Of ECE 40
 When T1 is short circuited as it is ON, +ve plate of the C2 is effectively
grounded and its –ve plate is connected to the base of T2. Therefore T2 comes out
of saturation and it becomes OFF. When T2 is OFF, C1 which is at this time charged
to +ve VCC is not connected to the base of T1 and required base drive for T1 be in
saturation is obtained from Rb1. Capacitor C2 which starts charging from –VCC to
+VCC through Rb2 and short circuited T1 When charge on C2 becomes 0v, T2
starts conducting and therefore –ve plate of C1 is connected to the base of T1, so T1
comes out of saturation.\
T1 = 0.69Rb1*C1
T2 = 0.69Rb2*C2
When Rb1 =Rb2 and C1=C2 (for square wave)
T = T1 + T2.

PROCEDURE:

1. All the connections are made as per the circuit diagram.

2. Different voltages are measured at base and collector points of two transistors
w.r.t ground as VC1, VC2, VB1 and VB2.
3. All the waveforms are plotted on the graph sheet, the amplitudes and time
periods are noted down.
4. Theoretical values of amplitudes and time periods are compared with practical
values.

PRECAUTIONS:

1. Connections should be tight.

2. Should take care when applying proper supply.

RESULT:

VIVA QUESTIONS:

1. Define stable state of a transistor?

2. Define semi-stable state of transistor?
3. What are the other names of Astable Multivibrator?
4. Explain the operation of a Astable Multivibrator?
5. How many stable states and semi-stable states present in the Astable
Multivibrator?
6. Draw the waveforms of VC1 and VC2 of a Astable Multivibrator?
7. What is the formula for the theoretical value of T in Astable Multivibrator?

Pulse and Digital Circuits laboratory, Department Of ECE 41

CIRCUIT DIAGRAM:

MODEL WAVEFORMS:

Pulse and Digital Circuits laboratory, Department Of ECE 42

EX NO: MONOSTABLE MULTIVIBRATOR DATE:

AIM: To construct and study the operation of monostable multivibrator using

transistors and to observe the response at base and collector points of the
transistors.
APPARATUS:
Resistors:
100kΩ, 4.7 kΩ,22 kΩ Each 3 No’s
220Ω 1 No
Transistors– BC107 2 No’s
Capacitor 0.01 µF,0.1µF 2 No’s.
Connecting wires Required No.
CRO 1 No
CRO Probes 2 No’s
RPS 1 No
Bread Board 1 No
Diode IN4007 1 No

THEORY:
In the monostable multivibrator one state is stable and the other is semi or
quasi stable state. So it is called Monostable multivibrator. It requires an external
force to change from stable state to semi stable state. Where as on its own after a
small duration it changes its state from semi stable state to stable state. This
duration of staying in semi stable state completely depends upon timing elements
resistor and capacitor with in the circuit.
When no trigger pulse is applied to the base of T2 transistor T1 is OFF and
transistor T2 is ON. During this stable state of this circuit capacitor C charges
through resistor R to VCC. This charging will not affect the base drive of T2 as T1 is
opened and the charged voltage as T1 is open and the charged voltage Vcc is not
w.r.t ground. Due to T2 is conducting, the collector voltage T2 is very small , which is
applied through potential R1&Rb1 can not drive T1into saturation, Thus T1 remains
in cut-off during stable state.
When a negative triggering pulse is applied to the base of ON transistor T2,
which decreases base drive and T2 becomes OFF. Due to this collector voltage of
T2 rises to VCC in turn this increases base drive of T1. Now T1 becomes ON. Due

Pulse and Digital Circuits laboratory, Department Of ECE 43

THEORITICAL CALCULATIONS:

T1 = 0.69R1C1` T2 = 0.69R2C2

Where R1 =R2 C1 = C 2

T= T1+T2

f=1/T

Pulse and Digital Circuits laboratory, Department Of ECE 44

toT1 becomes short circuit, the +ve plate of charged capacitor C is effectively
connected to the ground. The –ve plate is connected to the base of T2. Charged
capacitor C provided the –ve voltage to the base of T2. To turn on T2 it requires a
+ve drive as it is an NPN transistor.
When a negative triggering pulse is applied to the base of ON transistor T2,
which decreases base drive and T2 becomes OFF. Due to this collector voltage of
T2 rises to VCC in turn this increases base drive of T1. Now T1 becomes ON. Due to
T1 becomes short circuit, the +ve plate of charged capacitor C is effectively
connected to the ground. The –ve plate is connected to the base of T2. Charged
capacitor C provided the –ve voltage to the base of T2. To turn on T2 it requires a
+ve drive as it is an NPN transistor.
The capacitor C starts charging from –VCC to +VCC through resistor R. When
the charging on capacitor reaches ‘0’ volts base of T2 starts getting +ve base drive
and it turns ON the T2. Depending upon RC constant, circuit returns to its stable
state. When T2 is ON, the collector voltage of it falls to Vce(sat) and there by
T1becomes OFF.
PROCEDURE:
1. Connections are made as per the circuit diagram.
2. The voltages are measured at collector and base terminals w.r.t ground by
giving the VBB of –1.5v through the 100k Ω resistor and the wave forms are
drawn as VC1, VC2, VB1, VB2.
3. The amplitudes and time periods of all the waveforms are noted down.
RESULT:

VIVA QUESTIONS:

1. What are the other names of Monostable Multivibrator?

2. How many stable and semi stable states present in the Monostable
Multivibrator?
3. Explain the operation of Monostable Multivibrator?
4. What is the theoretical value of T ?
5. What is the name of base capacitor and what is the purpose of base
capacitor?

Pulse and Digital Circuits laboratory, Department Of ECE 45

CIRCUIT DIAGRAM:

MODEL WAVEFORMS:

Pulse and Digital Circuits laboratory, Department Of ECE 46

EX NO: BISTABLE MULTIVIBRATOR DATE:

AIM: To understand the working of Bistable Multivibrator using transistors.

APPARATUS:

Resistors:
1kΩ,2.2kΩ,15kΩ, Each 2 No’s
100kΩ 1 No
Transistors– BC107 2 No’s
Capacitor 0.047 µF 2 No’s.
Connecting wires Required No.
CRO 1 No
CRO Probes 2 No’s
RPS 1 No
Bread Board 1 No

THEORY:
If the circuit stays at one state may be at high state or at low state until unless
a disturbance comes extremely to change the state from high to low or from low to
high, then we can say the state of the circuit is stable. The multivibrator in which the
two states are stable is called the Bistable Multivibrator. This Multivibrator needs an
external voltage to change from unstable state to another stable state.

Assume that when the circuit is switched ON the transistor T1 is switched

OFF and Transistor T2 is ON in the absence of triggering pulse. When T2 is ON the
collector voltage at point A is VCE (sat). The small voltage is not sufficient to drive
T1 to saturation. Therefore it remains OFF. Due to T1 OFF its collector voltage at
point B is coupled to VCC. This high voltage through R1 and C1 parallel combination
is applied to base of T2, which is sufficient to drive T2 into saturation. For saturation
emitter base junction and collector base junction must be forward biased. Here base
is P-type gets greater potential than collector it is driven into saturation. This state of
operation remains stable until an external pulse is applied to the base of transistor
T2, so that its base drive is reduced to a voltage for it which it comes out of
saturation becomes OFF, raising its collector voltage to VCC from VCE sat.
This high voltage connected to the base of T1 makes it ON from
OFF and thus collector voltage VCC fall to VCE sat. This small voltage applied to

Pulse and Digital Circuits laboratory, Department Of ECE 47

Theoretical Calculations:

Pulse and Digital Circuits laboratory, Department Of ECE 48

base of T2 is not sufficient to drive T2, I.e., T2 will OFF and T1 will ON. This stable
condition exists as long as another triggering pulse is applied. Here capacitors C1
and C2 are called speed up capacitors, which turns transistors ON and OFF quickly
by supplying sufficient charge flow to the base of the transistor. The circuit consisting
RB1, RB2 and -VBB is used to empty the charge flow quickly when transistor is
made OFF from conduction.

PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Without keeping the base resistances and with base resistances measure the
voltages at base and collector points of the two transistors T1 and T2 as VC1,
VB1 and VC2, VB2 respectively.
3. By applying the triggering voltage of –1.5V at the base terminals measure the
time period and amplitude of the waveform.
4. All the graphs are drawn on the graph sheet.

RESULT:

VIVA QUESTIONS:

1. What are the other names of Bistable Multivibrator?

2. How many stable and semi stable states present in the Bistable Multivibrator?
3. Explain the operation of Bistable Multivibrator?
4. What is the theoretical value of T?
5. What is the name of base capacitor and what is the purpose of base
capacitor?

Pulse and Digital Circuits laboratory, Department Of ECE 49

CIRCUIT DIAGRAM:

MODEL WAVE FORMS:

Pulse and Digital Circuits laboratory, Department Of ECE 50

EX NO: SCHMITT TRIGGER DATE:

AIM: To construct and study the operation of Schmitt trigger using transistors.

APPARATUS:

Resistors:
1K 2 No’s
3.9K,6.8K,47Ω,100K 1 No Each
Transistors– BC107 2 No’s
Connecting wires Required No.
CRO 1 No
CRO Probes 2 No’s
Function Generator 1 No
RPS 1 No
Bread Board 1 No

THEORY:

Schmitt trigger is an electronic circuit which is a special form of bistable

multivibrator in which one stable state to the other is changed by changing the
amplitude of i/p applied voltage. When the circuit is switched on without any i/p
voltage T1 will be in cut off and T2 will be in saturation. As there is no base drive to
T1 it will be off. Collector voltage of T1 will be coupled to VCC through RC1. The
voltage is connected through the potential divider to the base of T2 which is sufficient
to drive T2 in to saturation. Now saturation current starts flowing through the RC2,
T2 and RE.
Therefore a voltage is developed across which is o/p voltage. This emitter
resistance Re also connected to the emitter of T1. To drive T1, to saturation from
cut-off, it required i/p voltage of voltage across Re plus VBE of T1. As the i/p voltage
reaches the voltage T1 starts conducting there by its collector voltage falls and base
drive to the transistor T2 is stop. Due to this the collector voltage of T2 raises to VCC
which is the o/p voltage.
Voltage across Re now is due to current flow through T1. Suppose RC1 >
RC2 voltage across Re due to current flow through T1 is smaller than voltage across
Re due to current flow through T2. To stop conduction in T1 i/p voltage has to be

Pulse and Digital Circuits laboratory, Department Of ECE 51

THEORITICAL CALCULATIONS:

UTP = (VCC.RE/(RC2+RE))+VBE1

LTP = VCE (sat) +VBE

HYSTERISIS = UTP – LTP

Pulse and Digital Circuits laboratory, Department Of ECE 52

reduced to lower value than to make it to conduct. Thus by increasing & decreasing
the i/p amplitude one stable state is changed to another. The greater amplitude for
which T1 becomes ON from OFF is called Upper Trigger Point (UTP) , the lower
amplitude for which T1 becomes OFF from ON is called Lower Trigger Point (LTP).

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. Fixed the i/p voltage 5v p-p at 1 KHz frequency.
3. The o/p voltage was taken at the collector point of transistor T2. w.r.t the
ground applying the bias voltage 5V.
4. The magnitudes of UTP and LTP are noted. By observing waveform on CRO.

PRECAUTIONS:

1. Connections should be tight.

2. Should take care when biasing proper supply.

RESULT:

VIVA QUESTIONS:

1. Define UTP AND LTP?

2. Define hysterisis?
3. What are the other names of Schmitt trigger?
4. For any type of i/p what is the o/p of a Schmitt trigger?
5. Explain the operation of a Schmitt trigger?

Pulse and Digital Circuits laboratory, Department Of ECE 53

Circuit Diagram

MODEL WAVE FORMS:

Pulse and Digital Circuits laboratory, Department Of ECE 54

EX NO: UJT RELAXATION OSCILLATOR DATE:

AIM: To construct and study the operation of UJT as Relaxation Oscillator.

APPARATUS:

Resistors:

UJT 2N2646 1 No’s

Capacitor 100 nF 1 No’s.
Connecting wires =====
CRO 1 No
CRO Probes 2 No’s
RPS 1 No
Bread Board 1 No
DRB 1 No

THEORY:

The Uni junction transistor is a efficient switch, its switching time is in range of
nano seconds. As UJT is exhibits Negative resistance characteristics it can be used
as a relaxation Oscillator. Relaxation circuits are circuits in which the timing interval
is established through the gradual charging of a capacitor, the timing interval being
terminated by the sudden discharge of a capacitor. The multivibrator, the sweep
generator, the blocking oscillator all these circuits have in common a timing interval
and a relaxation interval and each exists in an astable or monostable form the
mechanism of synchronization and frequency division is the same for all these
devices.

In the pulse synchronization of a sweep generator using UJT, in the absence

of an external synchronous signal, the capacitor stops charging when the capacitor
voltage reaches peak or break down voltage V p of the negative resistance device.
There after, the capacitor discharges abruptly through the negative resistance device
UJT. When the capacitor voltage falls to the valley voltage, the UJT goes off and the
capacitor begins to recharge. A negative pulse is applied at the base B 2 of the UJT
will lower Vp.

Pulse and Digital Circuits laboratory, Department Of ECE 55

THEORITICAL CALCULATIONS:

Pulse and Digital Circuits laboratory, Department Of ECE 56

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. The Output Vo is noted, time period is also noted.
3. The theoretical time period should be calculated.
4. T=RTCT ln(1/1-n)
5. The Output at base 1 and base 2 should note.
6. Graph should be plotted and waveforms are drawn for V 0, VB1,VB2.

Design Procedure:

Assume the capacitor value is 0.1micro farads.

Sweep time=Ts =

Peak Value Vp=

The Base VoltageVbb =

PRECAUTIONS:

1. Connections should be tight.

2. UJT terminals are identified properly.
3. Readings can not be exceeding the limits.

RESULT:

VIVA QUESTIONS:

1. Draw the circuit symbol of double sided diode?

2. Define intrinsic-standoff ratio?
3. Define peak voltage?
4. Define valley voltage?

Pulse and Digital Circuits laboratory, Department Of ECE 57

CIRCUIT DIAGRAM:

MODEL WAVEFORMS:

Pulse and Digital Circuits laboratory, Department Of ECE 58

EX NO: DATE:
BOOTSTRAP SWEEP CIRCUIT
AIM: To construct and study the working of Bootstrap sweep circuit to generate
a ramp signal

APPARATUS:
Resistors: 22K,100K,4.7K 1 No EACH
Transistor BC548 2 No’s
Capacitor 4.nF,10Uf,100nF 1 No EACH
Connecting wires Required No.
CRO 1 No
CRO Probes 2 No’s
Function Generator 1 No
Bread Board 1 No

THEORY:

Bootstrap circuit of the transistor connected in the mode of emitter follower,

i.e., what ever applied at the base of transistor appears at the base of transistor

appears at the emitter thus emitter follows the input applied signal.

Initially switch is kept open, capacitor C, starts charging to voltage V through

the resistor R. Now if the switch is closed, capacitor starts discharging through the

switch. Since the capacitor voltage is the base input signal for the transistor, the o/p

follows the capacitor charging voltage Vo is given by

Vo =V+Vc.

Where V is charging battery voltage which is also connected to the emitter,

where the o/p is taken and Vc is voltage across capacitor.

When the capacitor is charging the o/p voltage increases from the voltage V

exponentially. If the exponential increase is approximated to linear by allowing the

capacitor to charge only up to a small portion of V, discharging is very fast through

the switch as it is a short circuit. The waveform generated is bootstrap waveform.

Pulse and Digital Circuits laboratory, Department Of ECE 59

CALCULATIONS:

Pulse and Digital Circuits laboratory, Department Of ECE 60

PROCEDURE:

1. All the connections are made as per the circuit diagram.

2. Fixed the i/p voltage constant at 4v p-p and 1 KHz frequency.
3. Apply Vcc=12v to the circuit.
4. The o/p voltage was taken at the emitter point.
5. The waveforms are plotted on the graph sheet.

RESULT:

VIVA QUESTIONS:

1. What is a sweep circuit?

2. What are the different types of sweep circuits?

3. What is the basic principle of Boot strap sweep circuit?

Pulse and Digital Circuits laboratory, Department Of ECE 61

Pulse and Digital Circuits laboratory, Department Of ECE 62
Pulse and Digital Circuits laboratory, Department Of ECE 63