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Assingment 2

The document contains an assignment for a real time embedded systems class. It includes 8 questions covering topics like NAND and NOR gates, building an XOR gate, synchronous vs asynchronous circuits, comparing a custom GCD processor to a software implementation using metrics like performance and gate count, designing an FSM diagram and logic for a subway turnstile system, illustrating how program and data memory can be overlapped in a Harvard architecture, analyzing the features of various microcontrollers, and writing an instruction set simulator.

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274 views2 pages

Assingment 2

The document contains an assignment for a real time embedded systems class. It includes 8 questions covering topics like NAND and NOR gates, building an XOR gate, synchronous vs asynchronous circuits, comparing a custom GCD processor to a software implementation using metrics like performance and gate count, designing an FSM diagram and logic for a subway turnstile system, illustrating how program and data memory can be overlapped in a Harvard architecture, analyzing the features of various microcontrollers, and writing an instruction set simulator.

Uploaded by

Rizwan_Ali_6773
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Assignment # 2

Subject: Real Time Embedded Systems Teacher: Ahsan Malik


Class: BCE 8th Submission Date: November 12, 2010

Q-1 Explain why NAND and NOR gates are more common than AND and OR Gates.

Q-2 Build a 2-input XOR gate using minimum number of CMOS transistors.

Q-3 What is the difference between a synchronous and asynchronous circuit?

Q-4 Compare the GCD custom-processor implementation to a software implementation

a) Compare the performance. Assume a 100-ns clock for the microcontroller, and a 20-ns
clock for the custom processor. Assume the microcontroller uses two operand
instructions, and each instruction requires four clock cycles. Estimates for the
microcontroller are fine.
b) Estimate the number of gates for the custom design, and compare this to 10,000 gates for
a simple 8-bit microcontroller.
c) Compare the custom GCD with the GCD running on a 300-MHz processor with 2-
operand instructions and one clock cycle per instruction (advanced processors use
parallelism to meet or exceed one cycle per instruction).
d) Compare the estimated gates with 200,000 gates, a typical number of gates for a modern
32-bit processor.

Q-5 A subway has an embedded system controlling the turnstile, which releases when two
tokens are deposited.

a) Draw the FSMD state diagram for this system.


b) Separate the FSMD into and an FSM+D.
c) Derive the FSM logic using truth tables and K-maps to minimize logic.
d) Draw your FSM and datapath connections.

Q-6 Illustrate how program and data memory fetches can be overlapped in Harvard architecture.

Q-7 Acquire data-sheet for PPC 403GCX, AT91SAM, 68HC16, C2000, TLCS-900 and ARM9. List the
features of the basic version of that microcontroller, including key characteristics of the
instruction set (number of instructions of each type, length per instruction, etc), memory
architecture and available memory, general purpose registers, special function registers, I/O
facilities, interrupt facilities, and other salient features and explicitly mention the applications
where they are mostly used. Create a table and mention all the features.
Q-8 Write the instruction set simulator for the given instruction set for some processor.

0) ADC Rd, Rr Add with Carry Rd ← Rd + Rr + C


1) ADD Rd, Rr Add without Carry Rd ← Rd + Rr
2) ADIW(1) Rd, K Add Immediate to Word Rd ← Rd + 1:Rd + K
3) SUB Rd, Rr Subtract without Carry Rd ← Rd - Rr
4) SUBI Rd, K Subtract Immediate Rd ← Rd - K
5) SBC Rd, Rr Subtract with Carry Rd ← Rd - Rr - C
6) SBCI Rd, K Subtract Immediate with Carry Rd ← Rd - K - C
7) SBIW(1) Rd, K Subtract Immediate from Word Rd + 1:Rd ← Rd + 1:Rd - K
8) AND Rd, Rr Logical AND Rd ← Rd • Rr
9) ANDI Rd, K Logical AND with Immediate Rd ← Rd • K
10) OR Rd, Rr Logical OR Rd ← Rd v Rr
11) ORI Rd, K Logical OR with Immediate Rd ← Rd v K
12) EOR Rd, Rr Exclusive OR Rd ← Rd ْ Rr
13) COM Rd One’s Complement Rd ← $FF - Rd
14) NEG Rd Two’s Complement Rd ← $00 - Rd
15) SBR Rd,K Set Bit(s) in Register Rd ← Rd v K
16) CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FFh - K)
17) INC Rd Increment Rd ← Rd + 1
18) DEC Rd Decrement Rd ← Rd - 1
19) TST Rd Test for Zero or Minus Rd ← Rd • Rd
20) CLR Rd Clear Register Rd ← Rd ْ Rd
21) SER Rd Set Register Rd ← $FF
22) MUL(1) Rd,Rr Multiply Unsigned R1:R0 ← Rd x Rr (UU)

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