1

An Isolated Power Factor Corrected Power Supply

Utilizing the Transformer Leakage Inductance.
Thomas Conway

Abstract—The widespread use of electronic devices increases A. Brief Review of Published Isolated PFC Converters
arXiv:1808.06699v1 [eess.SP] 20 Aug 2018

the need for compact power factor corrected power supplies. This
paper describes an isolated power factor corrected power supply For lower power levels, flyback type architectures, often us-
that utilizes the leakage inductance of the isolation transformer to ing a single switching element can provide PFC functionality,
provide boost inductor functionality. The bulk capacitor is in the and use an output bulk capacitor for energy storage. A range
isolated part of the power supply allowing for controlled startup
without dedicated surge limiting components. A control method of flyback based power factor corrected power supplies have
based on switch timing and input/output voltage measurements is been developed and are described in the literature. Ref. [5]
developed to jointly achieve voltage regulation and input power describes a 60W flyback PFC supply to achieve IEC61000
factor control. A prototype design is implemented with detailed THD requirements. A 10W to 30W LED lighting supply is
measurements and waveforms shown to confirm the desired described in [6] and another 60W supply described in [7]. A
functionality.
72W flyback design is shown in [8] and a 100W flyback PFC
Index Terms—AC-DC Power Conversion, Power Factor Cor- design in described in [9]. In these architectures, the flyback
rection, Transformer Leakage Inductance. transformer initially stores energy from the input source and
then releases it to the output bulk capacitor. The transformer
thus provides the PFC input current control and galvanic
I. I NTRODUCTION
isolation. However, the need to store all the energy in the
The widespread use of electronic devices from single phase flyback transformer, the unidirectional core excitation [4], high
AC supplies necessitates the increasing use of power factor voltage stresses in the switching device and difficulties with
corrected (PFC) power supplies in many applications including the transformer leakage inductance, limit the usage of such
electronic equipment, computer servers and consumer prod- power supplies to lower power levels.
ucts. PFC power supplies provide low total harmonic distortion At higher power levels, two stage supplies with a separate
(THD) in the current drawn from the line and this is an boost PFC stage and isolated DC to DC stage are widespread.
increasingly important requirement. They typically consist of a power factor correction stage, based
Power factor correction techniques have been researched around a boost converter with large bulk storage capacitor
widely in the literature [1][2] and active PFC using high fre- to control the input line current, followed by an inverter
quency switching techniques [3] are now commonly used. The driving a high frequency isolation transformer and finally an
overarching principle involves controlling the input current output stage with at least some filtering components. Such
drawn from the mains input to achieve the required current designs work well, especially when there is a need to supply
shape for low THD and high power factor. The power supply a number of different voltage rails and a long holdup time
must provide a regulated DC output voltage and for many is required. Most of these architectures use one (or more)
applications, galvanic isolation is also required. boost inductors in the active PFC stage [3], and such inductors
The basic boost or step-up converter [4] forms the core of need to handle the full supply power levels resulting in a
most architectures as it has an input inductor that allows input significantly sized component. The design of such front end
current control to be readily achieved. The well known flyback PFC converters is a tradeoff between boost inductor size and
converter can be derived from the buck-boost converter, but high frequency losses [10]. Also, cascading multiple power
with a transformer for output voltage isolation [4]. stages leads to reduced overall efficiencies. The front end
Traditionally for PFC supplies, flyback converters have been boost PFC stage typically has high in-rush current on startup,
used for lower power levels (≤ 100W ). For higher power or needs additional components to limit the in-rush current
levels (≥ 500W), a separate boost converter for PFC and [11][12].
separate DC to DC converter with transformer isolation for Therefore, there has been considerable research published
output DC voltage regulation is used. on other architectures that attempt to eliminate or mitigate
some of the disadvantages of both the flyback and two stage
Thomas Conway is a lecturer in the ECE dept. of the University of PFC AC/DC power supplies.
Limerick, Limerick, Ireland
Contact: Dr. Thomas Conway Lecturer, ECE Dept University of Limerick A quasi-active PFC converter in [14] delivers 100W using
National Technology Park Limerick, Ireland. Tel +353 61 202628, Email a combined PFC cell with two transformers, one operating as
thomas.conway@ul.ie a flyback converter and one operating as a forward converter.
This work has been submitted to the IEEE for possible publication.
Copyright may be transferred without notice, after which this version may This allows parallel power transfer and avoids lossy snubber
no longer be accessible. networks, all with a single controlled switch, but at the expense
 2

of a number of magnetic cores and inductor elements. II. P ROPOSED A RCHITECTURE

A combination of a separate boost stage cascaded with a
The circuit diagram of the proposed power supply is shown
lossless snubber network is presented in [15], delivering 96W.
in Fig. 1. A conventional 4 diode full wave rectifier rectifies the
Again only a single controlled switch is used but a number of
input AC source voltage producing a voltage VR . This voltage
separate magnetic cores and inductor elements are required.
is inverted to the high frequency fs with a half bridge inverter
For higher power levels, modified two stage structures have
before being applied to a high frequency transformer Txf r . The
been proposed. An architecture to improve on the existing
half bridge inverter consists of the two switches M1 and M2
two stage PFC is described in [10] which moves the boost
operated out of phase with a 50% duty cycle at the switching
inductor and bulk capacitor to the isolated side of a resonant
frequency fs and the capacitive divider formed by C1 and C2.
LLC converter with the effect of improving the voltage stresses
The capacitors C1 and C2 prevent DC current flowing through
on the switching devices and providing an output power of
the transformer primary and causing saturation problems. The
250W.
values of C1 and C2 are chosen sufficiently small such that at
A two stage structure proposed in [16] uses a boost con- the mains frequency fAC and low power level, they allow the
verter PFC with a resonant LLC converter. The design uses rectifier output voltage VR to follow the input mains waveform
transformer coupled power transfer from the boost inductor to envelope. However, at the switching frequency, their values
the output. Using two transformers (one providing the boost are sufficiently large to act as fixed voltage sources and not
inductor functionality), a power output of 480W is provided. resonate with the transformer inductances or load.
Fig. 2 and Fig. 3 show qualitative voltage and current
waveforms for√the circuit of Fig. 1. The mains input voltage
B. Proposed PFC Architecture
is VM (t) = 2VAC sin(2πfAC t), with VAC being the rms
In this paper an active power factor corrected power supply input voltage and VR (t) being the input voltage fully rectified.
is described, whereby the leakage inductance of the high The transformer primary voltage VP (t) switches at the high
frequency isolation transformer is used to provide the func- frequency rate fs , but with an amplitude of half VR (t), due to
tionality of the boost inductor. Minimization of the leakage in- the half bridge configuration.
ductance in high frequency isolation transformers is normally The symbol for the transformer in Fig. 1 is drawn to
desirable in most DC to DC converters, although resonant and emphasize that the transformer leakage inductance is used
soft switching architectures do use a controlled amount of in the circuit rather than the usual case whereby leakage
leakage inductance [17] for the purpose of reducing switching inductance is minimized as much as possible. The key to the
losses. operation of the circuit is the bidirectional secondary shorting
The use of a controlled amount of leakage inductance is switch shown in Fig. 1 [21].
proposed in this paper to eliminate the need for two separate By turning on this switch at the beginning of the high
magnetic components in the two stage PFC converter and frequency cycle, the current in the leakage inductance of the
instead uses one magnetic component to achieve both the transformer is controlled by the input voltage level and the
power factor correction and galvanic isolation. period that the switch is on for (denoted T1 ).
In-rush current on startup can also be controlled by imple- When the shorting switch opens, the leakage inductance
menting a soft start strategy whereby the large bulk capacitor current is forced through the output rectifier into the bulk
is initially charged up in a controlled manner. capacitor CB and output load. The bulk capacitor CB stores
Bidirectional core excitation is used, with part of the energy sufficient energy over the input AC half cycle to provide a low
transferred via transformer action, and part stored in the ripple output voltage VO (t).
transformer leakage inductance. The described architecture The output voltage VO (t), should not be less than the
NS NS
provides a useful technique at power levels above those maximum value of VP N P
where N P
is the transformer turns
suitable for single stage flyback type converters. ratio. In Fig. 3, the current waveforms labeled IL∗ and IX ∗

The technique lends itself to the adoption of wide band- represent the currents IL (t) and IX (t) (as in Fig. 1), multiplied
gap semiconductor devices [18] with hard switching [19][20]. by the sign of the primary voltage VP (t) and averaged over
Typically applications might include LED lighting, electronic each high frequency period T . The value of IL∗ is the same
equipment, server power supplies and on-board chargers for shape as the mains input voltage and thus the magnitude of
NS
electric vehicles. the filtered line input current IM (t) equals 12 IL∗ (t) N P
.
In this paper, section II describes the proposed architecture. Provided the DC output voltage VO is larger than the
A simplified system model for the power electronics is out- maximum secondary output voltage, the leakage inductance
lined in section III, from which the basic operating modes current is controlled by the input voltage level, the output DC
of the circuit are identified and characterized. The dynamic voltage level and the secondary shorting switch timing period
selection of the operating modes and their control parameters T1 . With measurement of the voltage levels, the timing period
to achieve power factor correction are presented in section IV. T1 is used to control the input current IM (t) drawn from the
An example design for a 300W 50V power supply is shown AC source and thus power factor correction can be achieved.
in section V with an experimental prototype constructed, In practice, this current control functionality operates at a
its operation confirmed, and waveforms and measurements high switching frequency fs and controls the average input
presented in section V-B. current over the switching period T = f1s . Output voltage
 3

Secondary
Shorting Switch IO
D5 D6 M1 C1
IM D1 D2

IX
VM VR IL CB
VP VO

M2 T xfr
D7 D8 C2
D3 D4
Input Half Bridge Output
Rectifer Inverter Rectifer

Fig. 1. Circuit diagram of the proposed power supply architecture.

400 30

300
20 IL ∗ IL
200 VP VR IX
VO
∗

10
100
Voltage (V)

Current (A)
0 0
IO
−100
IM
−10
−200

−300 VM −20

−400 −30
0 5 10 15 20 0 5 10 15 20
Time (ms) Time (ms)

Fig. 2. Qualitative voltage waveforms for the circuit of Fig. 1 over a full AC Fig. 3. Qualitative current waveforms for the circuit of Fig. 1 over a full AC
cycle. cycle.

regulation is achieved by controlling the ratio of instantaneous at time t = kT .

current drawn to the instantaneous voltage applied and this The operation of the circuit is based on the assumption
control functionality operates at a slow rate comparable with that the transformer magnetizing inductance LM has little
the input source frequency, denoted fAC . effect on the operation of the circuit other than to add a
In effect, the transformer leakage inductance and secondary magnetizing current to the input source. Simulations show that
shorting switch act as a step up or boost converter with magnetizing currents significantly less (a factor of 51 × or less),
the output rectifier and bulk capacitor CB . However, the than the currents being transferred, have little impact on the
input voltage polarity reverses once each cycle and the boost circuit overall functionality. This is verified in the experimental
operation is carried out in two T /2 time periods, each with prototype waveforms of section V-B.
opposite polarity voltage and current waveforms. The total leakage inductance of the transformer is denoted
LL and the current flowing out of the transformer secondary
III. T HEORY OF O PERATION winding is denoted IL (t).
Fig. 4 shows a simplified circuit model for the proposed IY
LL
power supply. Assuming the switching frequency of the con- IL
verter is very high compared to to the AC source frequency, the D1 D2
input to the transformer can be considered to be essentially a Vi VS IX
S1 CB
50% duty cycle square wave with period T and peak amplitude +
− VI
LM Vo

±VI . The model in Fig. 4 is referenced to the secondary side of

D3 D4 Load
the transformer and the voltage amplitude into the transformer T/2
model is the primary voltage VP (t) multiplied by the turns
ratio of the transformer, or
T1
 
 Ns 
VI [kT ] = VP (kT ) 
 (1) Fig. 4. Simplified circuit model for the proposed power supply.
Np
 4

The operation of the system is essentially that of a step up V S (t) +VO

or boost converter and is based around the timing of shorting
switch S1 in Fig. 4. At the beginning of a switching cycle, VP N
NP
S
V i (t)
the input voltage switches to +VI (dropping the [kT ] for
notation for clarity) and simultaneously the shorting switch t
S1 is turned on. The current IL (t) in the leakage inductance
LL rises linearly while the switch S1 is on. When the switch
T
S1 is turned off, the current in the leakage inductance is forced −VO
through the rectifier diode bridge formed by D1 , D2 , D3 , +IP
I L (t)
and D4 , and into the capacitor CB and system load, and the I*L
current in the leakage inductance falls. After a period of T2 ,
the input voltage changes sign to −VI and the same operation t
occurs, except for a change in the sign of the inductor current. T2
Two distinct operation modes of the circuit can be identified T1
+IP −IP
depending on whether the leakage inductance current starts
at zero and returns to zero before time T2 , denoted as the
discontinuous conduction mode (DCM), or when the leakage
inductance current starts the cycle with a non zero (negative) I X (t)
value, retains a non zero (positive value) at time T2 and returns
to a non zero (negative) value at the end of the cycle (time −IP
T ), denoted as the continuous conduction mode (CCM). +IP
To achieve unity power factor, the circuit needs to be
operated in such a manner as to control the input current drawn
from the supply. The two operating modes are now discussed I Y (t)
in detail to relate the input current drawn to the timing period
Fig. 5. Idealized discontinuous conduction mode waveforms.
T1 .

A. Discontinuous Conduction Mode (DCM) with any contribution from the magnetizing inductance aver-
Fig. 5 shows the input voltage Vi (t), the secondary voltage aging to zero over each T period.
VS (t), the leakage inductor current IL (t) and the current into It is apparent by considering eqn. 1 and eqn. 7, that
and out of the output rectifier IX (t) and IY (t), for the circuit achieving unity power factor in the input source is equivalent
operating in discontinuous conduction mode. With the shorting to controlling the current value IL∗ to be directly proportional
switch S1 closed, the leakage inductor current IL (t) rises from to VI . Denoting the constant of proportionality as GM , or
zero to the value +IP over the set period T1 , thus: IL∗ = GM VI , then substituting in eqn. 6 and rearranging yields
the equation:
IP = VI T1 /LL (2) s  
VO − VI
When the shorting switch S1 opens, the inductor current falls T1 = GM T LL . (8)
back to zero over a period T2 with the relationship: VO

IP = (VO − VI )T2 /LL (3) The equation shows that given a constant of proportionality
as GM , the required time period T1 can be calculated by
The sum of the periods must be less than the half period knowledge of the system parameters LL and T , measurement
T /2 to ensure operation in the discontinuous conduction mode of the output voltage VO and calculating VI by measurement
or: of the rectified input source voltage and scaling by a factor of
T 1 Ns
T1 + T2 ≤ . (4) 2 Np .
2
The average input current to the transformer model (ignoring
B. Continuous Conduction Mode (CCM)
the magnetizing inductance) over the period T /2 can then be
calculated as: Fig. 6 shows the input voltage Vi (t), the secondary voltage
1 T1 + T2 VS (t), the leakage inductor current IL (t) and the current into
IL∗ = IP T
(5)
2 2
and out of the output rectifier IX (t) and IY (t), for the circuit
and combining with eqn. 2 and eqn. 3, the average input operating in continuous conduction mode. With the shorting
current is: switch S1 closed, the leakage inductor current IL (t) rises from
T12 the value −IE to the value +IP over the set period T1 thus:
 
∗ VI VO
IL = (6)
T LL VO − VI IP + IE = VI T1 /LL (9)
The actual input current from the AC source is a scaled version
When the shorting switch S1 opens, the inductor current falls
of this current and is:
back to +IE over a period T2 = T2 − T1 with the relationship:
1 Ns ∗
IM = I (7) IP − IE = (VO − VI )T2 /LL (10)
2 Np L
 5

√ Ns
The average input current to the transformer model (ignoring and with a maximum input voltage VImax = 2VAC 12 N p
,
1 2
yields a power capability Pmax = 2 GMmax VImax of:
+VO
V S (t) VP N S Ns
NP VAC N VO
Pmax ≤ √ p (14)
V i (t)
32 2fs LL
This equation can be used as a basis for converter design
t as demonstrated by the prototype example in section V. The
maximum peak current in the leakage inductor during the
+IP
T CCM can be calculated as:
−VO VO T
IP max = (15)
+IE I*L
8LL
I L (t)
and the transformer must be designed to handle this peak
t
−IE current without saturation.

T1 +IP −IP IV. P OWER S UPPLY C ONTROL

The control objective for the power supply is to provide
+IE a constant output voltage and unity input power factor. This
I X (t) requires measurement of the output voltage and adjustment
of the input current through the GM factor defined in sec-
−IP −IE tion III-A. However, calculating the time parameter T1 in
+IP section III-A and III-B also requires knowledge of the
parameter LL , the leakage inductance, which may not be
+IE
accurately known. Therefore a new control parameter K is
I Y (t) defined as:
GM LL
K= (16)
Fig. 6. Idealized continuous conduction mode waveforms. T
and K is used for control rather than GM . Substituting into
the magnetizing inductance) over the period T /2 can then be eqn. 8 and eqn. 13 results in the required calculations for DCM
calculated as: as: s  
1
− IE )T1 + 21 (IP + IE )T2 VO − VI
2 (IP T1 = T K . (17)
IL∗ = T
(11) VO
2
and CCM as:
and combining with eqn. 9 and eqn. 10, the average input r !
current can be shown to be: T 16KVI
T1 = 1− 1− . (18)
  4 VO
T VO
IL∗ = T1 − T12 (12)
2 T LL It can further be shown that the boundary condition of eqn. 4
can be written as:
With IL∗ = GM VI , then substituting in eqn. 12 and rearranging
yields the equation: VO (1 − 4K) ≥ VI (19)
!
The feedback loop of Fig. 7 can then be used to control the
r
T 16GM LL VI
T1 = 1− 1− (13) power supply. In Fig. 7, the power supply output voltage VO
4 T VO
is measured and compared to a reference voltage VREF to
Similar to section III-A, this equation shows that given a produce an output voltage error VERR = VO − VREF . This
constant of proportionality GM , the required time period T1 error voltage is used by a PID controller with dynamics below
can be calculated from LL , T , VO and VI . the input AC frequency fAC to adjust the variable K to control
the output voltage VO .
The variable K, is used in the timing generator to generate
C. Power Handling Capability the inverter timing and the secondary shorting period T1 twice
per sample period T . The timing generator uses the measured
The power capability of converter is determined by the
power supply output voltage VO , and a scaled version of the
maximum value of GM supported which is limited by the Ns
input rectifier voltage VR as VI = 12 N VR . Using K, VI and
requirement for equation 13 to result in a real number. This p

requires the argument under the square root to be non-negative VO , the timing generator evaluates the condition in eqn. 19
and hence and if the result is true, the DCM is selected and eqn. 17 is
16GMmax LL VI used to calculate the time period T1 . Otherwise, the CCM is
≤1 selected and eqn. 18 is used to calculate the time period T1 .
T VO
 6

T
T/2 input voltage VAC is based on selecting a desired switching
frequency fs , calculating the maximum transformer turns ratio
Ns
Np , and using eqn. 14 to determine the maximum allowed
T1 value of leakage inductance.
V
o
Consider the design of a 300W 50V power supply with a
VR α VI Vo
240Vrms AC 50Hz source or P = 300W , VO = 50V and
Timing
Generator VAC ≤ 240V rms. A switching frequency of fs = 50kHz is
K chosen for this example.
Operation in boost mode requires the peak transformer
PID V ERR +
output voltage to be not greater than the desired output voltage
Controller Σ
and thus
− Ns 2VO
≤√
Np 2VAC
V REF Ns Ns 6
or N p
≤ 0.295. Choosing Np = 22 , then rearranging eqn. 14
Fig. 7. Feedback control for the power supply. to:
Ns
VAC N VO
LL ≤ √ p
32 2fs P
Fig. 8 shows a plot of the T1 time as a fraction of the
switching period T for the first quarter of the input sine wave, imposes the requirement that LL ≤ 4.82uH. With these
under a range of load conditions from 20% to full load. Under parameters, the maximum transformer peak current can be
full load (GM at its maximum value), the circuit operates in calculated from eqn. 15 as 26.0 A.
discontinuous conduction mode for just over half the time,
with the calculated shorting period T1 reducing from an initial
A. Transformer Design
value of T /4. However, after switching to the continuous
operating mode, the calculated shorting period T1 rises again. The transformer design for the prototype is based on using
The fraction of time spent in the continuous conduction mode two E-Cores with the primary winding on one core and the
reduces as the load level drops. secondary winding on the other core as in Fig. 9(a). This
results in a transformer with good magnetizing inductance and
a usable amount of leakage inductance. The transformer design
0.25 requirements are to provide the specified leakage inductance
and maximum magnetizing inductance, while preventing core
CCM saturation under peak operating currents. Fig. 9(b) shows
0.20
a magnetic reluctance model for the transformer with the
leakage being modeled by the air gap reluctance Rg between
0.15 the central core and the outer legs. The central core reluctance
is RC and the reluctance of each top and side halves is RO
T1 /T

The final reluctance model, Fig. 9(c) can then be used with
0.10
the equations:

0.05 (RC + R2O )2

RM = 2RC + RO + 2 ,
DCM Rg
0.00
0 10 20 30 40 50 60 70 80 90 RO
Input phase angle (deg) RK = RC + + Rg .
2
Fig. 8. Required timing for T1 /T over one quarter cycle of input sinewave The resulting magnetizing inductance (from the primary side)
2
with GM = 0.2, 0.4, 0.6, 0.8, 1.0 times the maximum GM . NP
is LP = RM and total leakage inductance (from the secondary
side) is LL = 2NS2 /RK .
The calculations for shorting period T1 need to be calculated
The peak core magnetic flux ΦMAX is then the sum of the
in real-time by the controller at a rate considerably higher than
magnetizing flux NRP M
IM
and the leakage flux IPRSKNS , with IM
the input frequency fAC , though not necessarily at the full fS
being the peak primary magnetizing current and IP S being the
rate. Eqn. 19, eqn. 17 and eqn. 18 can be readily implemented
peak secondary current. The peak core magnetic flux density
in a modern microcontroller, DSP or FPGA at the required data
with a core effective area of Ae is then:
rates.
NP IM IP S NS
BMAX = + (20)
V. E XAMPLE P ROTOTYPE D ESIGN RM Ae RK Ae
Design of a converter using the proposed technique for a The prototype transformer consists of a pair of E42/21/15
given power level P , an output voltage VO and a maximum cores, 3C90 ferrite material, with 22 turns on the primary and
 7

NP I P TABLE I
P ROTOTYPE COMPONENT VALUES AND SPECIFICATION .
Ro Ro
Rc Component/Parameter Specified/Measured
Rg RK EMC filter 3× 100nF Capacitor
RM
RK 2× 5A 7mH Common Mode Choke
Rg
Rc
Ro Ro Rectifier Br1 BU15065S-E3/45, 15A 600V
Bridge Rectifier
NS I S MOSFETS M1, M2 C3M0280090D SiC, 11.5 A, 900 V

Capacitors C1, C2 1uF 250V Film Capacitor (PET)

(a) (b) (c)
Transformer 2× Ecore 42mm/21mm/15mm, 3C90
Fig. 9. Ecore transformer construction with flux paths for the leakage (solid) Turns Ratio 22:6
and magnetizing (dashed) inductances and corresponding magnetic models. Primary Inductance 2.0 mH
Secondary Inductance 150 uH
Secondary Leakage 4.0 uH
Inductance
6 turns on the secondary. The corresponding magnetizing in-
ductance (from the primary side) and total leakage inductance Schottky Diodes D1, D2 MBR4060 60V 40A
(from the secondary side) is calculated as: MOSFETS M3, M4 IRFB4110 100V 120A

LM = 1800µH and LL = 4.7µH Bulk Capacitor 6000uF (6×1000uF) 63V

and the actual measured values are listed in Table I. With a Control Processor LPC1114 ARM M0
240Vrms AC input, the magnetizing current is ≈ ±0.47A and
with a peak secondary current of 26A, the peak core magnetic
flux density based on equation 20 is Table II. Measured waveforms of the line input voltage and
current and transformer primary voltage and current are shown
BMAX = 0.211T + 0.0562T ≈ 0.27T.
in Fig. 12 over a full line cycle. Zoomed in waveforms of the
This value is less than the saturation magnetic flux density transformer primary voltage and current and secondary voltage
of 0.32T , and only occurs at the peak of the input AC and current are shown in Fig. 13 (DCM) and Fig. 14 (CCM)
waveform. Notice that the contribution from the leakage flux and confirm the desired operation. The effect of finite values
is small due to the high reluctance of the leakage flux path of bus capacitors C1 and C2 can be seen in the primary voltage
as it passes through the air gap. This example shows that the waveform of Fig. 14 as a droop in the voltage rather than an
addition of the leakage inductance does not severely impact ideal square wave.
on the size of transformer in terms of core saturation. The measured efficiency, power factor and total harmonic
distortion are plotted against output power in Fig. 15.
B. Prototype Construction and Measurements
TABLE II
The power electronics schematic of the prototype power M EASURED PERFORMANCE FOR THE EXPERIMENTAL PROTOTYPE .
supply is shown in Fig. 10. A bridge rectifier Br1 is used to
rectify the input AC voltage and a half bridge inverter based on Parameter Measured Value
MOSFETs M1 and M2 drive the transformer. The prototype is Switching Frequency 50 kHz
Input Voltage 237.1Vrms
based on a semi synchronous rectifier for the output rectifier Input Current 1.375Arms
[21]. In this case, two MOSFET transistors M3 and M4 are Input Power 320W
used to perform the secondary shorting during the T1 period Power Factor 0.98
by turning on both transistors. During the remaining time, Output Voltage 49.8V
only one of the transistors is left switched on to perform the Output Voltage Ripple 3.8Vpp (i.e ±3.8%)
rectification function in conjunction with one of the Schottky Output Current 6.02A
Output Power 300W
diodes, D1 or D2.
The measured parameters of the constructed prototype trans- Efficiency 93.7 %
former are listed in Table I, together with the other power
THD 4.1%,
components used in the prototype power supply.
Control of the prototype is implemented in firmware on
a modern 32bit microcontroller. An internal 10 bit ADC The efficiency of the converter is determined by the com-
measures the input rectified voltage and bulk capacitor output ponent losses and an analytical model of the relative contribu-
voltage. The microcontroller performs the calculations for the tions results in the distribution shown in Fig. 16. The largest
PID output voltage control and the timing calculations as per contributions are given by the Schottky diodes conduction
section IV with the timing signals generated with on-chip losses and the transformer core and winding losses. Fig. 17
PWM generators. shows an infra red thermal image of the prototype showing
Fig. 11 shows an image of the prototype power supply and the highest spot temperature on the windings of the trans-
its measured performance at 300W output power is given in former. Switching losses dominate in the secondary MOSFET
 8

M1 C1 D1 D2
~
V out
− +
~
CB
Br 1

M2 T1
C2
M3 M4

Fig. 10. Prototype power electronics schematic.

Fig. 11. Prototype power supply.

Fig. 13. Measured waveforms at 300W operation, 1.5ms from zero crossing
and operating in DCM mode. Transformer primary voltage (VP) and current
(IP) and secondary voltage (VS) and current (IS).

leakage inductance value as per equation 14. For a given

power level, universal input voltage support could be addressed
by adopting variable frequency operation with lower input
voltages supported by reducing the switching frequency.

C. Comparison with existing designs

A key motivation for the work reported in this paper is
the reduction of size and weight of the converter with a key
component of these being the magnetic elements. Table III
provides a comparison of the prototype developed with a
Fig. 12. Measured waveforms at 300W operation over a complete line cycle, range of PFC isolated supplies described in the literature.
input AC voltage (VAC) and current (IAC) and transformer primary voltage Flyback type architectures dominate at lower power levels
(VP) and current (IP).
(below 100W) with two stage architectures accounting for
higher power levels. The prototype based on the proposed
architecture in this paper compares well with the other designs
switches and the use of faster switches such as GAN devices
and industry expectations [22], and should provide a useful
or soft switching techniques might be useful here particularly
topology for PFC converter designers.
if a higher frequency of operation is adopted.
The prototype design is based on a fixed line input voltage
and a fixed switching frequency of 50kHz. Further work VI. C ONCLUSIONS
could involve extending the architecture to operate as an This paper describes an isolated AC/DC power supply using
universal supply over wide input voltage operation. While the leakage inductance of the isolation transformer to achieve
the existing design will work at lower input voltages, the active power factor correction. The proposed architecture
output power is limited by the fixed switching frequency and allows for a compact lightweight power supply for power
 9

TABLE III
C OMPARISON WITH OTHER ISOLATED PFC TOPOLOGIES .

Ref: Topology Switching Peak Universal Weight of No. Switches (S) Peak Power per
Frequency Power Voltage Magnetic Cores No. Diodes (D) Efficiency Core Weight
[5] Flyback 65kHz 60W Yes 31g 1 S, 5 D 89.5% 1.94 W/g
[7] Flyback ( ≥ 44kHz) 60W Yes 36g 1 S, 5 D 91% 1.67 W/g
[8] Flyback 40kHz 72W No 36g 2 S, 2 D 90% 2.00 W/g
[15] Boost-Flyback 50kHz 96W Yes 120g 1 S, 7 D 90.6% 0.80 W/g
[14] Quasi-Active Flyback 75kHz 100W Yes 57g 1 S, 10 D 93% 1.75 W/g
[10] Resonant LLC / Boost 90-450kHz 250W Yes 92g 8S,4D 94.5% 2.72 W/g
[16] Boost / Resonant LLC 100kHz 480W No 122g 5 S, 4 D 93.58% 3.93 W/g
This work 50kHz 300W No 88g 4 S, 6 D 93.7% 3.41 W/g

Schottky
Diodes

EMI filter
27.1%
Secondary
Bridge 0.9% MOSFET
Rectifier Switching
11.0% 12.9%

2.2% Secondary
6.2% MOSFET
16.4% Conduction
Transformer Core
Loss
Half Bridge 2.0% 21.2%
Conduction

Half Bridge Transformer Winding Loss

Switching

Fig. 16. Calculated loss contributions from the circuit elements.

Fig. 14. Measured waveforms at 300W operation, 5ms from zero crossing
and operating in CCM mode. Transformer primary voltage (VP) and current
(IP) and secondary voltage (VS) and current (IS).

1.00 50

0.95 40
Power Factor, Efficiency

0.90 Power Factor PF 30

THD (%)

Efficiency η
0.85 20
THD
0.80 10

Fig. 17. Thermal Image of prototype at 300W output power (Spot temperature
0.75 0
0 50 100 150 200 250 300 62.1 deg C).
POUT (W)

Fig. 15. Measured efficiency and power factor for the prototype. R EFERENCES
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 25

20

15
IP , IA (A)

10

5 IP
IA
0
0 10 20 30 40 50 60 70 80 90
Input phase angle (deg)