SN74LVC1G02-EP

SINGLE 2-INPUT POSITIVE-NOR GATE

www.ti.com SGLS370 – AUGUST 2006

FEATURES • Supports 5-V VCC Operation

• Controlled Baseline • Inputs Accept Voltages to 5.5 V
– One Assembly • Max tpd of 3.6 ns at 3.3 V
– One Test Site • Low Power Consumption, 10-µA Max ICC
– One Fabrication Site • ±24-mA Output Drive at 3.3 V
• Extended Temperature Performance of –55°C • Ioff Supports Partial-Power-Down Mode
to 125°C Operation
• Enhanced Diminishing Manufacturing • Latch-Up Performance Exceeds 100 mA Per
Sources (DMS) Support JESD 78, Class II
• Enhanced Product-Change Notification • ESD Protection Exceeds JESD 22
• Qualification Pedigree (1) – 2000-V Human-Body Model (A114-A)
• Available in the Texas Instruments – 200-V Machine Model (A115-A)
NanoStar™ and NanoFree™ Packages – 1000-V Charged-Device Model (C101)
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
(A) (A) (A)
YEA , YEP , YZA ,
(A) (A) (A)
DBV PACKAGE DCK PACKAGE DRL PACKAGE OR YZP PACKAGE
(TOP VIEW) (TOP VIEW) (TOP VIEW) (BOTTOM VIEW)

A 1 5 VCC A 1 5 VCC GND 3 4

Y
A 1 5 VCC
B 2 B 2

B 2
A 1 5
VCC
2 GND 3 4 Y
B GND 3 4 Y

GND 3 4 Y

See mechanical drawings for dimensions.

A. Product Preview

DESCRIPTION/ORDERING INFORMATION
This single 2-input positive-NOR gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G02 performs the Boolean function Y = A + B or Y = A × B in positive logic.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC1G02-EP
SINGLE 2-INPUT POSITIVE-NOR GATE www.ti.com
SGLS370 – AUGUST 2006

ORDERING INFORMATION
TOP-SIDE
TA PACKAGE (1) ORDERABLE PART NUMBER
MARKING (2)
NanoStar™ – WCSP (DSBGA)
SN74LVC1G02NYEAREP (3)
0,17-mm Small Bump – YEA
NanoFree™ – WCSP (DSBGA)
SN74LVC1G02NYZAREP (3)
0,17-mm Small Bump – YZA (Pb-free)
Reel of 3000 _ _ _CB_
NanoStar™ – WCSP (DSBGA)
SN74LVC1G02MYEPREP (3)
0,23-mm Large Bump – YEP
–55°C to 125°C
NanoFree™ – WCSP (DSBGA)
SN74LVC1G02MYZPREP (3)
0,23-mm Large Bump – YZP (Pb-free)
SOT (SOT-23) – DBV Reel of 3000 SN74LVC1G02MDBVREP (3) C02_
SOT (SC-70) – DCK Reel of 3000 SN74LVC1G02MDCKREP BUF
SOT (SOT-553) – DRL Reel of 4000 SN74LVC1G02MDRLREP (3) CB_

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA,YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition(1 = SnPb, • = Pb-free).
(3) Product Preview

FUNCTION TABLE
INPUTS OUTPUT
A B Y
H X L
X H L
L L H

LOGIC DIAGRAM (POSITIVE LOGIC)

1
A 4
2 Y
B

2 Submit Documentation Feedback

 SN74LVC1G02-EP
www.ti.com
SINGLE 2-INPUT POSITIVE-NOR GATE
SGLS370 – AUGUST 2006
(1)
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
VI Input voltage range (2) –0.5 6.5 V
VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V
VO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
DBV package 206
DCK package 252
θJA Package thermal impedance (4) DRL package 142 °C/W
YEA/YZA package 154
YEP/YZP package 132
Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.

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SN74LVC1G02-EP
SINGLE 2-INPUT POSITIVE-NOR GATE www.ti.com
SGLS370 – AUGUST 2006

Recommended Operating Conditions (1)

MIN MAX UNIT
Operating 1.65 5.5
VCC Supply voltage V
Data retention only 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC
VCC = 2.3 V to 2.7 V 1.7
VIH High-level input voltage V
VCC = 3 V to 3.6 V 2
VCC = 4.5 V to 5.5 V 0.7 × VCC
VCC = 1.65 V to 1.95 V 0.35 × VCC
VCC = 2.3 V to 2.7 V 0.7
VIL Low-level input voltage V
VCC = 3 V to 3.6 V 0.8
VCC = 4.5 V to 5.5 V 0.3 × VCC
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V
–24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V
24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
∆t/∆v Input transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ± 0.5 V 5
TA Operating free-air temperature –55 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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 SN74LVC1G02-EP
www.ti.com
SINGLE 2-INPUT POSITIVE-NOR GATE
SGLS370 – AUGUST 2006

Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP (1) MAX UNIT
IOH = –100 µA 1.65 V to 5.5 V VCC – 0.1
IOH = –4 mA 1.65 V 1.2
IOH = –8 mA 2.3 V 1.9
VOH V
IOH = –16 mA 3V 2.4
IOH = –24 mA 2.3
IOH = –32 mA 4.5 V 3.8
IOL = 100 µA 1.65 V to 5.5 V 0.1
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
VOL V
IOL = 16 mA 3V 0.4
IOL = 24 mA 0.55
IOL = 32 mA 4.5 V 0.6
II A or B inputs VI = 5.5 V or GND 0 to 5.5 V ±5 µA
Ioff VI or VO = 5.5 V 0 ±10 µA
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 µA
∆ICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 µA
Ci VI = VCC or GND 3.3 V 4 pF

(1) All typical values are at VCC 3.3 V, TA = 25°C.

Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
PARAMETER UNIT
(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A or B Y 2.8 10.7 1.2 7.3 1 6 1 5 ns

Operating Characteristics
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER TEST CONDITIONS UNIT
TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 23 23 23 25 pF

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SN74LVC1G02-EP
SINGLE 2-INPUT POSITIVE-NOR GATE www.ti.com
SGLS370 – AUGUST 2006

PARAMETER MEASUREMENT INFORMATION

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
(see Note A) RL tPLZ/tPZL VLOAD
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 15 pF 1 MΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 15 pF 1 MΩ 0.15 V
3.3 V ± 0.3 V 3V ≤2.5 ns 1.5 V 6V 15 pF 1 MΩ 0.3 V
5 V ± 0.5 V VCC ≤2.5 ns VCC/2 2 × VCC 15 pF 1 MΩ 0.3 V

VI
Timing Input VM
0V
tW

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
VOL S1 at VLOAD VOL + V∆
(see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – V∆
Output VM VM VM
VOL S1 at GND ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators have the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

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 SN74LVC1G02-EP
www.ti.com
SINGLE 2-INPUT POSITIVE-NOR GATE
SGLS370 – AUGUST 2006

PARAMETER MEASUREMENT INFORMATION (continued)

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
(see Note A) RL tPLZ/tPZL VLOAD
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
3.3 V ± 0.3 V 3V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
5 V ± 0.5 V VCC ≤2.5 ns VCC/2 2 × VCC 50 pF 500 Ω 0.3 V

VI
Timing Input VM
0V
tW

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
VOL S1 at VLOAD VOL + V∆
(see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – V∆
Output VM VM VM
VOL S1 at GND ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators have the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

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 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74LVC1G02MDCKREP ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 BUF
& no Sb/Br)
V62/06631-01XE ACTIVE SC70 DCK 5 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 BUF
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

OTHER QUALIFIED VERSIONS OF SN74LVC1G02-EP :

• Catalog: SN74LVC1G02

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G02MDCKREP SC70 DCK 5 3000 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1G02MDCKREP SC70 DCK 5 3000 202.0 201.0 28.0

Pack Materials-Page 2
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