William Stallings ENIAC - background

Computer Organization • Electronic Numerical Integrator And

and Architecture Computer
7th Edition • Eckert and Mauchly
• University of Pennsylvania
Chapter 2 • Trajectory tables for weapons
Computer Evolution and • Started 1943
Performance
• Finished 1946
—Too late for war effort
• Used until 1955

ENIAC - details von Neumann/Turing

• Decimal (not binary) • Stored Program concept
• 20 accumulators of 10 digits • Main memory storing programs and data
• Programmed manually by switches • ALU operating on binary data
• 18,000 vacuum tubes • Control unit interpreting instructions from
• 30 tons memory and executing
• 15,000 square feet • Input and output equipment operated by
• 140 kW power consumption control unit
• 5,000 additions per second • Princeton Institute for Advanced Studies
—IAS
• Completed 1952
Structure of von Neumann machine IAS - details
• 1000 x 40 bit words
—Binary number
—2 x 20 bit instructions
• Set of registers (storage in CPU)
—Memory Buffer Register
—Memory Address Register
—Instruction Register
—Instruction Buffer Register
—Program Counter
—Accumulator
—Multiplier Quotient

Structure of IAS –
detail Commercial Computers
• 1947 - Eckert-Mauchly Computer
Corporation
• UNIVAC I (Universal Automatic Computer)
• US Bureau of Census 1950 calculations
• Became part of Sperry-Rand Corporation
• Late 1950s - UNIVAC II
—Faster
—More memory
IBM Transistors
• Punched-card processing equipment • Replaced vacuum tubes
• 1953 - the 701 • Smaller
—IBM’s first stored program computer • Cheaper
—Scientific calculations • Less heat dissipation
• 1955 - the 702 • Solid State device
—Business applications
• Made from Silicon (Sand)
• Lead to 700/7000 series
• Invented 1947 at Bell Labs
• William Shockley et al.

Transistor Based Computers Microelectronics

• Second generation machines • Literally - “small electronics”
• NCR & RCA produced small transistor • A computer is made up of gates, memory
machines cells and interconnections
• IBM 7000 • These can be manufactured on a
• DEC - 1957 semiconductor
—Produced PDP-1 • e.g. silicon wafer
Generations of Computer Moore’s Law
• Vacuum tube - 1946-1957 • Increased density of components on chip
• Transistor - 1958-1964 • Gordon Moore – co-founder of Intel
• Small scale integration - 1965 on • Number of transistors on a chip will double every
—Up to 100 devices on a chip year
• Medium scale integration - to 1971 • Since 1970’s development has slowed a little
— Number of transistors doubles every 18 months
—100-3,000 devices on a chip
• Cost of a chip has remained almost unchanged
• Large scale integration - 1971-1977
• Higher packing density means shorter electrical
—3,000 - 100,000 devices on a chip
paths, giving higher performance
• Very large scale integration - 1978 -1991 • Smaller size gives increased flexibility
—100,000 - 100,000,000 devices on a chip
• Reduced power and cooling requirements
• Ultra large scale integration – 1991 - • Fewer interconnections increases reliability
—Over 100,000,000 devices on a chip

Growth in CPU Transistor Count IBM 360 series

• 1964
• Replaced (& not compatible with) 7000
series
• First planned “family” of computers
—Similar or identical instruction sets
—Similar or identical O/S
—Increasing speed
—Increasing number of I/O ports (i.e. more
terminals)
—Increased memory size
—Increased cost
• Multiplexed switch structure
DEC PDP-8 DEC - PDP-8 Bus Structure
• 1964
• First minicomputer (after miniskirt!)
• Did not need air conditioned room
• Small enough to sit on a lab bench
• $16,000
—$100k+ for IBM 360
• Embedded applications & OEM
• BUS STRUCTURE

Semiconductor Memory Intel

• 1970 • 1971 - 4004
• Fairchild —First microprocessor
• Size of a single core —All CPU components on a single chip
—i.e. 1 bit of magnetic core storage —4 bit

• Holds 256 bits • Followed in 1972 by 8008

—8 bit
• Non-destructive read
—Both designed for specific applications
• Much faster than core
• 1974 - 8080
• Capacity approximately doubles each year —Intel’s first general purpose microprocessor
Speeding it up Performance Balance
• Pipelining • Processor speed increased
• On board cache • Memory capacity increased
• On board L1 & L2 cache • Memory speed lags behind processor
• Branch prediction speed
• Data flow analysis
• Speculative execution

Login and Memory Performance Gap Solutions

• Increase number of bits retrieved at one
time
—Make DRAM “wider” rather than “deeper”
• Change DRAM interface
—Cache
• Reduce frequency of memory access
—More complex cache and cache on chip
• Increase interconnection bandwidth
—High speed buses
—Hierarchy of buses
I/O Devices Typical I/O Device Data Rates
• Peripherals with intensive I/O demands
• Large data throughput demands
• Processors can handle this
• Problem moving data
• Solutions:
—Caching
—Buffering
—Higher-speed interconnection buses
—More elaborate bus structures
—Multiple-processor configurations

Improvements in Chip Organization and

Key is Balance Architecture
• Processor components • Increase hardware speed of processor
• Main memory —Fundamentally due to shrinking logic gate size
– More gates, packed more tightly, increasing clock
• I/O devices rate
• Interconnection structures – Propagation time for signals reduced
• Increase size and speed of caches
—Dedicating part of processor chip
– Cache access times drop significantly
• Change processor organization and
architecture
—Increase effective speed of execution
—Parallelism
Problems with Clock Speed and Login
Density Intel Microprocessor Performance
• Power
— Power density increases with density of logic and clock
speed
— Dissipating heat
• RC delay
— Speed at which electrons flow limited by resistance and
capacitance of metal wires connecting them
— Delay increases as RC product increases
— Wire interconnects thinner, increasing resistance
— Wires closer together, increasing capacitance
• Memory latency
— Memory speeds lag processor speeds
• Solution:
— More emphasis on organizational and architectural
approaches

Increased Cache Capacity More Complex Execution Logic

• Typically two or three levels of cache • Enable parallel execution of instructions
between processor and main memory • Pipeline works like assembly line
• Chip density increased —Different stages of execution of different
—More cache memory on chip instructions at same time along pipeline
– Faster cache access • Superscalar allows multiple pipelines
• Pentium chip devoted about 10% of chip within single processor
area to cache —Instructions that do not depend on one
• Pentium 4 devotes about 50% another can be executed in parallel
Diminishing Returns New Approach – Multiple Cores
• Internal organization of processors • Multiple processors on single chip
— Large shared cache
complex
• Within a processor, increase in performance
—Can get a great deal of parallelism proportional to square root of increase in
—Further significant increases likely to be complexity
relatively modest • If software can use multiple processors, doubling
• Benefits from cache are reaching limit number of processors almost doubles
performance
• Increasing clock rate runs into power • So, use two simpler processors on the chip
dissipation problem rather than one more complex processor
—Some fundamental physical limits are being • With two processors, larger caches are justified
reached — Power consumption of memory logic less than
processing logic
• Example: IBM POWER4
— Two cores based on PowerPC

POWER4 Chip Organization Pentium Evolution (1)

• 8080
— first general purpose microprocessor
— 8 bit data path
— Used in first personal computer – Altair
• 8086
— much more powerful
— 16 bit
— instruction cache, prefetch few instructions
— 8088 (8 bit external bus) used in first IBM PC
• 80286
— 16 Mbyte memory addressable
— up from 1Mb
• 80386
— 32 bit
— Support for multitasking
Pentium Evolution (2) Pentium Evolution (3)
• 80486 • Pentium II
—sophisticated powerful cache and instruction — MMX technology
pipelining — graphics, video & audio processing

—built in maths co-processor • Pentium III

— Additional floating point instructions for 3D graphics
• Pentium • Pentium 4
—Superscalar — Note Arabic rather than Roman numerals
—Multiple instructions executed in parallel — Further floating point and multimedia enhancements
• Pentium Pro • Itanium
—Increased superscalar organization — 64 bit
— see chapter 15
—Aggressive register renaming
• Itanium 2
—branch prediction
— Hardware enhancements to increase speed
—data flow analysis
• See Intel web pages for detailed information on
—speculative execution processors

PowerPC PowerPC Family (1)

• 1975, 801 minicomputer project (IBM) RISC • 601:
• Berkeley RISC I processor — Quickly to market. 32-bit machine
• 1986, IBM commercial RISC workstation product, RT PC. • 603:
— Not commercial success — Low-end desktop and portable
— Many rivals with comparable or better performance — 32-bit
• 1990, IBM RISC System/6000 — Comparable performance with 601
— RISC-like superscalar machine — Lower cost and more efficient implementation
— POWER architecture • 604:
• IBM alliance with Motorola (68000 microprocessors), and — Desktop and low-end servers
Apple, (used 68000 in Macintosh) — 32-bit machine
• Result is PowerPC architecture — Much more advanced superscalar design
— Derived from the POWER architecture — Greater performance
— Superscalar RISC
• 620:
— Apple Macintosh
— High-end servers
— Embedded chip applications
— 64-bit architecture
PowerPC Family (2) Internet Resources
• 740/750: • http://www.intel.com/
—Also known as G3 —Search for the Intel Museum
—Two levels of cache on chip • http://www.ibm.com
• G4: • http://www.dec.com
—Increases parallelism and internal speed • Charles Babbage Institute
• G5: • PowerPC
—Improvements in parallelism and internal
speed
• Intel Developer Home
—64-bit organization