Baier VNWA2 QEX
Baier VNWA2 QEX
Baier VNWA2 QEX
Baier, DG8SAQ
University of Applied Sciences, Prittwitzstrasse 10, 89075 Ulm, Germany; baier@hs-ulm.de
Summary
Since I had published my ideas for a
simple and low cost vector network analyzer
(VNWA) in QEX in 2007, I have received
lots of feedback, showing, that there is a great
interest in this field.1 The original design
(VNWA1.0) had a few shortcomings. It only
covered a fundamental frequency range up
to 160 MHz. On the other hand, it could
measure at some limited higher frequency
bands up to 500 MHz, with reduced accu-
racy, by using higher DDS alias frequen-
cies.2 Another drawback was that it was a
veroboard design. This made it very tough
to duplicate. So, I have thought about how to
make the VNWA design even simpler, better,
and last but not least easier to build. In this
article, I describe the very satisfactory result
of this development process, which is a small
single printed circuit board VNWA covering
1 kHz to 1.3 GHz in one continuous fre-
quency band, which can be powered directly
from a computer USB interface.
VNWA Design Figure 1 — A block diagram showing the fundamental design of the VNWA2.1.
Figure 1 shows the fundamental design
of the new VNWA2.1. Like the original
VNWA1.0, it consists of two digitally tun- to the Editor in QEX (see Note 2), it is crucial experimental approach, but pushing the DDS
able Direct Digital Synthesizers (DDSs), that the two DDS cores are clocked with dif- clock frequency means pushing the usable
now realized by two fast Analog Devices ferent frequencies, if one wants to omit anti- fundamental frequency range of the VNWA,
AD9859 chips.3 Here, the clock genera- aliasing filters and make use of higher order which spans to 600 MHz under the selected
tion could be realized in a very simple way, alias frequencies. This is simply achieved by operating conditions.
because the AD9859 contains an on-chip setting the clock multipliers of the two DDS Like in the VNWA1.0 design, the RF
clock multiplier PLL circuit. Both DDSs are chips to two different values — for example, DDS output signal is fed into an SWR-
clocked from the same crystal oscillator, real- 20 and 19 — leading to clock frequencies of bridge, now formed by 50 Ω resistors in
ized with a low cost standard 12.3 MHz crys- 703 MHz and 740 MHz respectively. Note, order to simplify power level adaptations by
tal, which is oscillating on the third overtone that in this frequency scheme, the DDSs an optional 50 Ω attenuator pad between the
at about 37 MHz. The exact crystal frequency operate well beyond their specification lim- DDS and the bridge. The balanced bridge
is of no importance, since it can be accounted its of 400 MHz maximum core clock. Quite output signal is fed into the balanced inputs
for in the software. As described in my letter remarkably, all tested DDS chips (about 30 of the Gilbert cell mixer, M1, followed by an
pieces so far), work nicely without getting operational amplifier. The amplifier output
Notes appear on page 36.
1 hot under these conditions. This is a very signal is guided through a CMOS switch into
Hardware
Figure 2 shows the VNWA2.1 board
mounted into a small metal sheet box as
seen from top. The left SMA connector is Figure 2 — Top view of the VNWA2.1 board. Board size is 100 × 60 mm².
the TX port output. It is directly connected to
the internal SWR bridge. The bridge is sur-
rounded by the mixers M1, M2 (left) and the
RF-DDS (right). The right SMA connector is
the RX port input. Above, the mixer M3 and
to the left the LO DDS are found.
The SubD9 connector on the upper side
of Figure 2 is the digital control port, which
is directly connected to the computer parallel
printer port. Also, the power supply is pro-
vided through this connector.
The 3.5 mm audio connector on the upper
right of Figure 2 is the stereo audio output
to be connected to the computer sound card
line-in.
The digital part of the board runs on 1.8 V
dc and 3.3 V dc. These voltages can directly
be obtained with low drop regulators by tap-
ping 5 V dc from a computer USB port.
The analog circuitry requires a low noise
6 V dc power supply. Fortunately, it only con-
sumes 10 mA of current. In order to power
the whole board from 5 V dc, a low power
step up switching regulator was added on the
upper left corner of the board. It translates Figure 3 — Frequency dependent available signal amplitudes: Trace 1/S21: clock multipliers
5 V input voltage to 8.5 V on output, which are 14/13; trace 2/Mem1: clock multipliers are 20/19; trace 3/Mem2: clock multipliers are
is then reduced to 6 V dc with a dissipative dynamically switched during the frequency sweep. Also shown is the noise floor of the
voltage regulator. This way, a very low noise system with TX output and RX input isolated (bottom trace, Mem4). Note that traces 2 and 3
6 V power supply could be obtained and no exactly match from the starting point up to their first crossing of trace 1.