DECODER

A decoder is a combinational circuit that converts binary information from ‘n’ input lines
to a maximum of 2n output lines i.e. if we have 2 input lines, there will be 22=4 output lines, if
there are 3 inputs we have 8 output lines and so on…

In order to construct the decoder, we need to consider the truth table first. Here we are going
to design a 3 –to-8 decoder. As discussed now, if we have 3 inputs we will have 23 =8 outputs.

Now let us see how do we write the truth table. Just look at the table below.

We can consider D0 at 20 , D1 at 21 and so on… i.e we will enable the corresponding

Note that Enable input is always equal to 1, if it is 0 irrespective of the inputs all the
outputs will be zero

E X Y Z D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 0 0 0 0 0 0 0 1

1 0 0 1 0 0 0 0 0 0 1 0

1 0 1 0 0 0 0 0 0 1 0 0

1 0 1 1 0 0 0 0 1 0 0 0

1 1 0 0 0 0 0 1 0 0 0 0

1 1 0 1 0 0 1 0 0 0 0 0

1 1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 1 0 0 0 0 0 0 0

0 x x x 0 0 0 0 0 0 0 0

Mahija Dandanayakula
From the above table we can write the equations for all the outputs i.e D0 to D7. Generally we use
K-maps to obtain equations, but here we have only one high output so we can directly write
equations as follows

D0 =x|y|z| D1 =x|y|z D2 =x|yz| D3 =x|yz

D4 =xy|z| D5 =xy|z D6 =xyz| D7 =xyz

By using the above equations we can draw the circuit as below. Here we have included Enable
input too which is always high

x y z E=1

x| y| z|

x|y|z| =D0

x|y|z =D1

x|yz| =D2

x|yz=D3

xy|z| =D4

xy|z =D5

xyz| =D6

xyz =D7

Mahija Dandanayakula
 The three inputs are decoded into eight outputs, each representing one of the minterms of
the three input variables. The three inverters provide the complement of the inputs and each one of
the eight AND gates generates on of the minterms.

A particular application of this decoder is binary-to-octal conversion. The input variables

The operation can be clarified by the above truth table. Consider the case when x=1,y=0,
z=1. In this case only D5=1 and all others are zero

The output whose value is equal to 1 represents the minterm equivalent of the binary
number currently available in the input lines.

Design with NAND Gates:

Since a NAND gate produces the AND operation with an inverted output it becomes more
economical to generate the decoder minterms in their complemented form. Furthermore, decoders
include one or more enable inputs to control the circuit operation. Consider the following truth
table

E A B D0 D1 D2 D3

1 X X 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

Mahija Dandanayakula
A two-to-four line decoder with an enable input constructed with NAND gates is shown below

A B

A| B|

A|B| =D0

A|B=D1

AB| =D2

AB=D3

Mahija Dandanayakula
 The circuit operates with complemented outputs and a complement enable input. The
decoder is enabled when E is equal to 0 ( i.e active low enable). You can see from the truth table
that only one input can be equal to ‘0’ at any given time, all other outputs are equal to 1. The
output whose value is equal to zero represents the minterm selected by inputs A and B. The circuit
is disabled when E is equal to ‘1’ regardless of the values of the other two inputs.

Combinational Logic implementation

A decoder provides the 2n minterms of n input variables. Since any Boolean function can
be expressed in sum-of-minterms form, a decoder that generates the minterms of the function
together with an external OR gate that forms their logical sum, provides a hardware
implementation of the function.

For example, let us consider the implementation of full adder. From the truth table of the
full adder below, we obtain functions as

S(x,y,z) = ∑(1,2,4,7) C(x,y,z) =∑(3,5,6,7)

Truth table for full adder

x y z Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Mahija Dandanayakula
 Since there are three inputs and a total of eight minterms we need a three-to-eight line
decoder. The implementation can be realised as shown in the below circuit

S(x,y,z) = ∑(1,2,4,7) C(x,y,z) =∑(3,5,6,7)

2
x SUM
3

4
y
5

7
z CARRY

Mahija Dandanayakula