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    D Flip-Flop Using 6 NAND Gates

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    Asadullah Jamalov
    This document describes a D flip-flop circuit design using 6 NAND gates. It consists of 3 S'R' latches that store the current values of Q and Q' when the clock is low. When the clock transitions high, the values of D and its complement pass through and update Q and Q' accordingly. The timing diagrams from both ModelSim and MultiSim simulations show that the output only changes on the positive edge of the clock, consistent with the behavior of a D flip-flop.

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    D Flip-Flop Using 6 NAND Gates

    Uploaded by

    Asadullah Jamalov
    110 views3 pages
    This document describes a D flip-flop circuit design using 6 NAND gates. It consists of 3 S'R' latches that store the current values of Q and Q' when the clock is low. When the clock transitions high, the values of D and its complement pass through and update Q and Q' accordingly. The timing diagrams from both ModelSim and MultiSim simulations show that the output only changes on the positive edge of the clock, consistent with the behavior of a D flip-flop.

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    d_flip-flop_report

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    This document describes a D flip-flop circuit design using 6 NAND gates. It consists of 3 S'R' latches that store the current values of Q and Q' when the clock is low. When the clock transitions high, the values of D and its complement pass through and update Q and Q' accordingly. The timing diagrams from both ModelSim and MultiSim simulations show that the output only changes on the positive edge of the clock, consistent with the behavior of a D flip-flop.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    110 views3 pages

    D Flip-Flop Using 6 NAND Gates

    Uploaded by

    Asadullah Jamalov
    This document describes a D flip-flop circuit design using 6 NAND gates. It consists of 3 S'R' latches that store the current values of Q and Q' when the clock is low. When the clock transitions high, the values of D and its complement pass through and update Q and Q' accordingly. The timing diagrams from both ModelSim and MultiSim simulations show that the output only changes on the positive edge of the clock, consistent with the behavior of a D flip-flop.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3

    D Flip-Flop using 6 NAND gates

    Written by Asadullah Jamalov 26.04.2020

    P3

    P1

    P2

    P4

    Above circuit is efficient design (with fewer transistors) of positive edge D flip-flop. In
    this report, I will introduce the working principals and the Timing Diagrams (in both
    ModelSim and MultiSim) of this circuit. Firstly, I would say that, this scheme consists
    of 3 S’R’ latches.
    Let’s explain “how the above circuit works?” (look at the first picture):
    • When Clk=0, P1 and P2 are high (P1=P2=1). That is why it is keeping the values
    of Q and Q' intact (look at the table of S’R’ latch).
    • Now when Clk=1 (at positive edge), the values of P4 (complement of D) and P3
    (equal D) passes through P1 and P2.
    • Now P1=P4=D' and P2=P3=D which means Q=D and Q'=D' (look at the
    table of S’R’ latch).
    • When D=0, P2=0 which will keep the value of P4=1 regardless of
    the value of D.
    • When D=1, P1=0 which will keep the value of P2=1 regardless of
    the value of D.
    • This implies that the above circuit ignores the changes in D when
    Clk=1 after positive edge of the clock.

    Let’s look at the timing diagrams of positive edge D flip-flop in ModelSim & MultiSim:

    The figure above is the timing diagram of this circuit in ModelSim Software. As seen
    from the graph, the value of “out” updates (according to value of “in”) only in the
    positive edges of “clk”.
    Above diagram is the oscilloscope output of this circuit in MultiSim Software.

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