High Performance FSK/ASK Transceiver IC: Data Sheet

High Performance
FSK/ASK Transceiver IC
Data Sheet ADF7020-1
FEATURES On-chip VCO and fractional-N PLL
Low power, low IF transceiver On-chip 7-bit ADC and temperature sensor
Frequency bands Fully automatic frequency control loop (AFC) compensates
135 MHz to 650 MHz, direct output for lower tolerance crystals
80 MHz to 325 MHz, divide-by-2 mode Digital RSSI
Data rates supported Integrated TRx switch
0.15 kbps to 200 kbps, FSK Leakage current <1 µA in power-down mode
0.15 kbps to 64 kbps, ASK
2.3 V to 3.6 V power supply APPLICATIONS
Programmable output power
Low cost wireless data transfer
−20 dBm to +13 dBm in 63 steps
Wireless medical applications
Receiver sensitivity
Remote control/security systems
−119 dBm at 1 kbps, FSK, 315 MHz
Wireless metering
−114 dBm at 9.6 kbps, FSK, 315 MHz
Keyless entry
−111.8 dBm at 9.6 kbps, ASK, 315 MHz
Home automation
Low power consumption
Process and building control
17.6 mA in receive mode
21 mA in transmit mode (10 dBm output)
FUNCTIONAL BLOCK DIAGRAM

RSET CREG(1:4) ADCIN MUXOUT
RLNA POLARIZATION LDO(1:4) TEMP TEST MUX

OFFSET
SENSOR
CORRECTION
LNA
RFIN FSK/ASK DATA
IF FILTER RSSI MUX 7-BIT ADC DEMODULATOR SYNCHRONIZER
RFINB
GAIN
OFFSET
CORRECTION CE
AGC
DATA CLK
CONTROL
Tx/Rx
CONTROL DATA I/O
FSK MOD GAUSSIAN Σ-∆
CONTROL FILTER MODULATOR AFC
CONTROL INT/LOCK
DIVIDERS/
RFOUT DIV P N/N+1
MUXING
SLE
SERIAL SDATA
PORT SREAD
VCO
SCLK
CP PFD
CLK
DIV R
RING OSC DIV
05669-001
L1 L2 VCOIN CPOUT OSC1 OSC2 CLKOUT
Figure 1.
Rev. A Document Feedback

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ADF7020-1 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Transmit Protocol and Coding Considerations ..................... 26
Applications ....................................................................................... 1 Device Programming after Initial Power-Up ......................... 26
Functional Block Diagram .............................................................. 1 Interfacing to Microcontroller/DSP ........................................ 26
Revision History ............................................................................... 2 Serial Interface ................................................................................ 29
General Description ......................................................................... 3 Readback Format........................................................................ 29
Specifications..................................................................................... 4 Register 0—N Register............................................................... 30
Timing Characteristics ................................................................ 8 Register 1—Oscillator/Filter Register ...................................... 31
Absolute Maximum Ratings .......................................................... 10 Register 2—Transmit Modulation Register (ASK/OOK
ESD Caution ................................................................................ 10 Mode) ........................................................................................... 32
Pin Configuration and Function Descriptions ........................... 11 Register 2—Transmit Modulation Register (FSK Mode) ..... 33
Typical Performance Characteristics ........................................... 13 Register 2—Transmit Modulation Register (GFSK/GOOK

Mode) ........................................................................................... 34
Frequency Synthesizer ................................................................... 15
Register 3—Receiver Clock Register ....................................... 35
Reference Input ........................................................................... 15
Register 4—Demodulator Set-up Register.............................. 36
Choosing Channels for Best System Performance ................. 17
Register 5—Sync Byte Register ................................................. 37
Transmitter ...................................................................................... 18
Register 6—Correlator/Demodulator Register ...................... 38
RF Output Stage .......................................................................... 18
Register 7—Readback Set-up Register .................................... 39
Modulation Schemes.................................................................. 18
Register 8—Power-Down Test Register .................................. 40
Receiver Section .............................................................................. 20
Register 9—AGC Register ......................................................... 41
RF Front End ............................................................................... 20
Register 10—AGC 2 Register.................................................... 42
RSSI/AGC .................................................................................... 21
Register 11—AFC Register ....................................................... 42
FSK Demodulators on the ADF7020-1 ................................... 21
Register 12—Test Register......................................................... 43
FSK Correlator/Demodulator ................................................... 21
Register 13—Offset Removal and Signal Gain Register ....... 44
Linear FSK Demodulator .......................................................... 23
Outline Dimensions ....................................................................... 45
AFC Section ................................................................................ 23
Ordering Guide .......................................................................... 45
Automatic Sync Word Recognition ......................................... 24
Applications ..................................................................................... 25
LNA/PA Matching ...................................................................... 25
REVISION HISTORY
1/2018—Rev. 0 to Rev. A
Changed CP-48-3 to CP-48-5 ...................................... Throughout
Changes to Figure 6 and Table 4 ................................................... 11
Updated Outline Dimensions ....................................................... 45
Changes to Ordering Guide .......................................................... 45
12/2005—Revision 0: Initial Version
Rev. A | Page 2 of 45
GENERAL DESCRIPTION
The ADF7020-1 is a low power, highly integrated FSK/GFSK/ A low IF architecture is used in the receiver (200 kHz),
ASK/OOK/GOOK transceiver designed for operation in the minimizing power consumption and the external component
low UHF and VHF bands. The ADF7020-1 uses an external count and avoiding interference problems at low frequencies.
VCO inductor that allows users to set the operating frequency The ADF7020-1 supports a wide variety of programmable
anywhere between 135 MHz and 650 MHz. Using the divide- features, including Rx linearity, sensitivity, and IF bandwidth,
by-2 circuit allows users to operate the device as low as 80 MHz. allowing the user to trade off receiver sensitivity and selectivity
The typical range of the VCO is about 10% of the operating for current consumption, depending on the application. The
frequency. A complete transceiver can be built using a small receiver also features a patent-pending automatic frequency
number of external discrete components, making the ADF7020- control (AFC) loop, allowing the PLL to compensate for
1 very suitable for price-sensitive and area-sensitive frequency error in the incoming signal.
applications. An on-chip ADC provides readback of an integrated tempera-
The transmit section contains a VCO and low noise ture sensor, an external analog input, the battery voltage, or the
fractional-N PLL with output resolution of <1 ppm. This RSSI signal, which provides savings on an ADC in some
frequency agile PLL allows the ADF7020-1 to be used in applications. The temperature sensor is accurate to ±10°C over
frequency-hopping spread spectrum (FHSS) systems. The VCO the full operating temperature range of −40°C to +85°C. This
operates at twice the fundamental frequency to reduce spurious accuracy can be improved by doing a 1-point calibration at
emissions and frequency pulling problems. room temperature and storing the result in memory.
The transmitter output power is programmable in 63 steps from
−20 dBm to +13 dBm. The transceiver RF frequency, channel
spacing, and modulation are programmable using a simple 3-
wire interface. The device operates with a power supply range of
2.3 V to 3.6 V and can be powered down when not in use.
SPECIFICATIONS
VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C.
All measurements are performed using the EVAL-ADF7020-1-DBX and PN9 data sequence, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions
RF CHARACTERISTICS
Frequency Ranges (Direct Output) 135 650 MHz See Table 5 for VCO bias settings at different
frequencies
Frequency Ranges 80 325 MHz
(Divide-by-2 Mode)
VCO Frequency Range 1.1 1.2 Ratio FMAX/FMIN, using VCO bias settings in Table 5
Phase Frequency Detector Frequency RF/256 20.96 MHz PFD must be less than direct output
frequency/31
TRANSMISSION PARAMETERS
Data Rate
FSK/GFSK 0.15 200 kbps
OOK/ASK 0.15 64 1 kbps
OOK/ASK 0.3 100 kbaud Using Manchester biphase-L encoding
Frequency Shift Keying
GFSK/FSK Frequency Deviation 2, 3 1 110 kHz PFD = 3.625 MHz
4.88 620 kHz PFD = 20 MHz
Deviation Frequency Resolution 100 Hz PFD = 3.625 MHz
Gaussian Filter BT 0.5
Amplitude Shift Keying
ASK Modulation Depth 30 dB
OOK-PA Off Feedthrough −50 dBm
Transmit Power 4 −20 +13 dBm VDD = 3.0 V, TA = 25°C, FRF > 200 MHz
Transmit Power −20 +11 dBm VDD = 3.0 V, TA = 25°C, FRF < 200 MHz
Transmit Power Variation vs. Temp. ±1 dB From −40°C to +85°C
Transmit Power Variation vs. VDD ±1 dB From 2.3 V to 3.6 V at 315 MHz, TA = 25°C
Programmable Step Size

−20 dBm to +13 dBm 0.3125 dB See Figure 13 for how output power varies
with PA setting
Integer Boundary −55 dBc 50 kHz loop BW
Reference −65 dBc
Harmonics
Second Harmonic −27 dBc Unfiltered conductive
Third Harmonic −21 dBc
All Other Harmonics −35 dBc
VCO Frequency Pulling, OOK Mode 30 kHz rms DR = 9.6 kbps
Optimum PA Load Impedance 5 79.4 + j64 FRF = 140 MHz
109 + j64 FRF = 320 MHz
40 + j47.5 FRF = 590 MHz
RECEIVER PARAMETERS
FSK/GFSK Input Sensitivity At BER = 1E − 3, FRF = 315 MHz,
LNA and PA matched separately 6
Sensitivity at 1 kbps −119.2 dBm FDEV= 5 kHz, high sensitivity mode 7
Sensitivity at 9.6 kbps −114.2 dBm FDEV = 10 kHz, high sensitivity mode
OOK Input Sensitivity At BER = 1E − 3, FRF = 315 MHz
Sensitivity at 1 kbps −118.2 dBm High sensitivity mode
Sensitivity at 9.6 kbps −111.8 dBm High sensitivity mode
LNA and Mixer, Input IP37
Enhanced Linearity Mode 6.8 dBm Pin = −20 dBm, 2 CW interferers,
Low Current Mode −3.2 dBm FRF = 315 MHz, F1 = FRF + 3 MHz,
High Sensitivity Mode −35 dBm F2 = FRF + 6 MHz, maximum gain
Rx Spurious Emissions 8 −57 dBm <1 GHz at antenna input
−47 dBm >1 GHz at antenna input
AFC
Pull-In Range ±50 kHz IF_BW = 200 kHz
Response Time 48 Bits Modulation index = 0.875
Accuracy 1 kHz
CHANNEL FILTERING
Adjacent Channel Rejection 27 dB IF filter BW settings = 100 kHz, 150 kHz,
(Offset = ±1 × IF Filter BW 200 kHz; desired signal 3 dB above the input
Setting) sensitivity level; CW interferer power level
Second Adjacent Channel Rejection 50 dB increased until BER = 10−3; image channel
(Offset = ±2 × IF Filter BW excluded
Setting)
Third Adjacent Channel Rejection 55 dB
(Offset = ±3 × IF Filter BW
Setting)
Image Channel Rejection 35 dB Image at FRF − 400 kHz
CO-CHANNEL REJECTION −2 dB
Wideband Interference Rejection 70 dB Swept from 100 MHz to 2 GHz, measured as
channel rejection
BLOCKING Desired signal 3 dB above the input sensitivity
±1 MHz 60 dB level, CW interferer power level increased
until BER = 10−2
±5 MHz 68 dB
±10 MHz 65 dB
±10 MHz (High Linearity Mode) 72 dB
Saturation (Maximum Input Level) 12 dBm FSK mode, BER = 10−3
LNA Input Impedance 237 − j193 Ω FRF = 130 MHz, RFIN to GND
101.4 − j161.6 Ω FRF = 310 MHz
49.3 − j104.6 Ω FRF = 610 MHz
RSSI
Range at Input −100 to −36 dBm
Linearity ±2 dB
Absolute Accuracy ±3 dB
Response Time 150 µs See the RSSI/AGC section
PHASE-LOCKED LOOP
VCO Gain 40 MHz/V 433 MHz, VCO adjust = 0,
VCO_BIAS_SETTING = 2
35 MHz/V 315 MHz, VCO adjust = 0,
16.5 MHz/V 135 MHz, VCO adjust = 0,
Phase Noise (In-Band) −89 dBc/Hz PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz,
FRF = 315 MHz, VCO_BIAS_SETTING = 2
Normalized In-Band Phase Noise −198 dBc/Hz
Floor 9
Phase Noise (Out-of-Band) −110 dBc/Hz 1 MHz offset
Residual FM 128 Hz From 200 Hz to 20 kHz, FRF = 315 MHz
PLL Settling 40 µs Measured for a 10 MHz frequency step to
within 5 ppm accuracy, PFD = 20 MHz,
LBW = 50 kHz
REFERENCE INPUT
Crystal Reference 3.625 24 MHz Must ensure PFD maximum is not exceeded
External Oscillator 3.625 24 MHz
Load Capacitance 33 pF Refer to the crystal’s data sheet
Crystal Start-Up Time 2.1 ms 11.0592 MHz crystal, using 33 pF load
capacitors
1.0 ms Using 16 pF load capacitors
Input Level CMOS See the Reference Input section
levels
ADC PARAMETERS
INL ±1 LSB From 2.3 V to 3.6 V, TA = 25°C
DNL ±1 LSB From 2.3 V to 3.6 V, TA = 25°C
TIMING INFORMATION
Chip Enabled to Regulator Ready 10 µs CREG = 100 nF
Chip Enabled to RSSI Ready 3.0 ms See Table 13 for more details
Tx-to-Rx Turnaround Time 150 µs + Time to synchronized data out, includes
(5 × TBIT) AGC settling. See AGC Information and
Timing section for more details.
LOGIC INPUTS
Input High Voltage, VINH 0.7 × V DD V
Input Low Voltage, VINL 0.2 × V DD V
Input Current, IINH/IINL ±1 µA
Input Capacitance, CIN 10 pF
Control Clock Input 50 MHz
LOGIC OUTPUTS
Output High Voltage, VOH DVDD − 0.4 V IOH = 500 µA
Output Low Voltage, VOL 0.4 V IOL = 500 µA
CLKOUT Rise/Fall 5 ns
CLKOUT Load 10 pF
TEMPERATURE RANGE—TA −40 +85 °C
POWER SUPPLIES
Voltage Supply
VDD 2.3 3.6 V All VDD pins must be tied together
Transmit Current Consumption FRF = 315 MHz, VDD = 3.0 V, PA is matched
to 50 Ω
433 MHz, 0 dBm/5 dBm/10 dBm 13/16/21 mA VCO_BIAS_SETTING = 2
Receive Current Consumption
Low Current Mode 17.6 mA VCO_BIAS_SETTING = 2
High Sensitivity Mode 20.1 mA VCO_BIAS_SETTING = 2
Power-Down Mode
Low Power Sleep Mode 0.1 1 μA
1
Higher data rates are achievable, depending on local regulations.
2
For definition of frequency deviation, see the Register 2—Transmit Modulation Register (FSK Mode) section.
3
For definition of GFSK frequency deviation, see the Register 2—Transmit Modulation Register (GFSK/GOOK Mode) section.
4
Measured as maximum unmodulated power. Output power varies with both supply and temperature.
5
For matching details, see the LNA/PA Matching section.
6
Sensitivity for combined matching network case is typically 2 dB less than separate matching networks. See Table 11 for sensitivity values at various data rates and
frequencies.
7
See Table 6 for a description of different receiver modes.
8
Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.
9 This figure can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise
performance as seen at the PA output: –198 + 10 log(fPFD) + 20 log N.
TIMING CHARACTERISTICS
VDD = 3 V ± 10%, VGND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design, but not production tested.
Table 2.
Parameter Limit at TMIN to TMAX Unit Test Conditions/Comments
t1 <10 ns SDATA-to-SCLK set-up time
t2 <10 ns SDATA-to-SCLK hold time
t3 <25 ns SCLK high duration
t4 <25 ns SCLK low duration
t5 <10 ns SCLK-to-SLE set-up time
t6 <20 ns SLE pulse width
t8 <25 ns SCLK-to-SREAD data valid, readback
t9 <25 ns SREAD hold time after SCLK, readback
t10 <10 ns SCLK-to-SLE disable time, readback
t3 t4
SCLK
t1 t2
DB1 DB0 (LSB)

SDATA DB31 (MSB) DB30 DB2
(CONTROL BIT C2) (CONTROL BIT C1)
t6
SLE
05669-002
t5
Figure 2. Serial Interface Timing Diagram
t1 t2
SCLK
SDATA
REG7 DB0
(CONTROL BIT C1)
SLE
t3
t10
SREAD X RV16 RV15 RV2 RV1

05669-003
t9
t8
Figure 3. Readback Timing Diagram
±1 × DATA RATE/32 1/DATA RATE
RxCLK
RxDATA DATA
05669-004
Figure 4. RxData/RxCLK Timing Diagram
1/DATA RATE
TxCLK
TxDATA DATA
FETCH SAMPLE
05669-005
NOTES
1. TxCLK ONLY AVAILABLE IN GFSK MODE.
Figure 5. TxData/TxCLK Timing Diagram
ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum
Table 3. Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
Parameter Rating
or any other conditions above those indicated in the operational
VDD to GND 1 −0.3 V to +5 V
section of this specification is not implied. Operation beyond
Analog I/O Voltage to GND −0.3 V to AVDD + 0.3 V
the maximum operating conditions for extended periods may
Digital I/O Voltage to GND −0.3 V to DVDD + 0.3 V
affect product reliability.
Operating Temperature Range
Industrial (B Version) −40°C to +85°C This device is a high performance RF-integrated circuit with an
Storage Temperature Range −65°C to +125°C ESD rating of <2 kV. It is ESD sensitive; proper precautions
Maximum Junction Temperature 150°C should be taken for handling and assembly.
MLF θJA Thermal Impedance 26°C/W ESD CAUTION
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
1
GND = CPGND = RFGND = DGND = AGND = 0 V.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
37 MUXOUT
42 CPOUT
41 CREG3
48 CVCO
47 GND1
39 OSC1
38 OSC2
40 VDD3
45 GND
43 VDD
46 L1
44 L2
VCOIN 1 36 CLKOUT
CREG1 2 35 DATA CLK
VDD1 3 34 DATA I/O
RFOUT 4 33 INT/LOCK
RFGND 5 32 VDD2
ADF7020-1
RFIN 6 31 CREG2
TOP VIEW
RFINB 7 (Not to Scale) 30 ADCIN
RLNA 8 29 GND2
VDD4 9 28 SCLK
RSET 10 27 SREAD
CREG4 11 26 SDATA
GND4 12 25 SLE
MIX_I 13
MIX_I 14
MIX_Q 15
MIX_Q 16
FILT_I 17
FILT_I 18
GND4 19
FILT_Q 20
FILT_Q 21
GND4 22
TEST_A 23
CE 24
05669-006
NOTES
1. CONNECT EXPOSED PAD TO GND.
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1 VCOIN VCO Input Pin. The tuning voltage on this pin determines the output frequency of the voltage controlled
oscillator (VCO). The higher the tuning voltage, the higher the output frequency.
2 CREG1 Regulator Voltage for PA Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin
and ground for regulator stability and noise rejection.
3 VDD1 Voltage Supply for PA Block. Decoupling capacitors of 0.1 μF and 10 pF should be placed as close as possible to
this pin. All VDD pins should be tied together.
4 RFOUT PA Output Pin. The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm.
The output should be impedance matched to the desired load using suitable components. See the Transmitter
section.
5 RFGND Ground for Output Stage of Transmitter. All GND pins should be tied together.
6 RFIN LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA input
to ensure maximum power transfer. See the LNA/PA Matching section.
7 RFINB Complementary LNA Input. See the LNA/PA Matching section.
8 RLNA External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.
9 VDD4 Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor.
10 RSET External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5% tolerance.
11 CREG4 Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND for
regulator stability and noise rejection.
12 GND4 Ground for LNA/MIXER Block.
13 to 18 MIX/FILT Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
19, 22 GND4 Ground for LNA/MIXER Block.
20, 21, FILT/TEST_A Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
23 unconnected.
24 CE Chip Enable. Bringing CE low puts the ADF7020-1 into complete power-down. Register values are lost when CE
is low, and the part must be reprogrammed once CE is brought high.
25 SLE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches. A latch is selected using the control bits.
26 SDATA Serial Data Input. The serial data is loaded MSB first, with the 2 LSBs as the control bits. This pin is a high
impedance CMOS input.
Pin No. Mnemonic Description
27 SREAD Serial Data Output. This pin is used to feed readback data from the ADF7020-1 to the microcontroller. The SCLK
input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin.
28 SCLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.
29 GND2 Ground for Digital Section.
30 ADCIN Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 to 1.9 V.
Readback is made using the SREAD pin.
31 CREG2 Regulator Voltage for Digital Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this
pin and ground for regulator stability and noise rejection.
32 VDD2 Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to this pin.
33 INT/LOCK Bidirectional Pin. In output mode (interrupt mode), the ADF7020-1 asserts the INT/LOCK pin when it has found
a match for the preamble sequence. In input mode (lock mode), the microcontroller can be used to lock the
demodulator threshold when a valid preamble has been detected. Once the threshold is locked, NRZ data can
be reliably received. In this mode, a demodulator lock can be asserted with minimum delay.
34 DATA I/O Transmit Data Input/Received Data Output. This is a digital pin and normal CMOS levels apply.
35 DATA CLK Transmit/Receive Clock Pin. In receive mode, the pin outputs the synchronized data clock. The positive clock
edge is matched to the center of the received data. In GFSK transmit mode, the pin outputs an accurate clock to
latch the data from the microcontroller into the transmit section at the exact required data rate. See the
Gaussian Frequency Shift Keying (GFSK) section.
36 CLKOUT A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to
drive several other CMOS inputs such as a microcontroller clock. The output has a 50:50 mark-space ratio.
37 MUXOUT Multiplexer Output Pin. This pin provides the Lock_Detect signal, which is used to determine if the PLL is locked
to the correct frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial
interface regulator.
38 OSC2 Oscillator Output Pin. The reference crystal should be connected between this pin and OSC1. A TCXO reference
can be used by driving this pin with CMOS levels and disabling the crystal oscillator.
39 OSC1 Oscillator Input Pin. The reference crystal should be connected between this pin and OSC2.
40 VDD3 Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a 0.01 μF
capacitor.
41 CREG3 Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor should be
placed between this pin and ground for regulator stability and noise rejection.
42 CPOUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated
current changes the control voltage on the input to the VCO.
43 VDD Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 μF capacitor.
44, 46 L2, L1 External VCO Inductor Pins. A chip inductor should be connected across these pins to set the VCO operating
frequency. See the Voltage Controlled Oscillator (VCO) section for details on choosing the appropriate value.
45, 47 GND, GND1 Grounds for VCO Block.
48 CVCO VCO Noise Compensation Node. A 22 nF capacitor should be placed between this pin and CREG1 to reduce
VCO noise.
EP EPAD Exposed Pad. Connect the exposed pad to GND.
TYPICAL PERFORMANCE CHARACTERISTICS

MKR4 3.482GHz
REF 10dBm ATTEN 20dB SWEEP 16.52ms (601pts)
CARRIER POWER –0.28dBm ATTEN 0.00dB MKR1 10.0000kHz PEAK 1
REF –70.00dBc/Hz –87.80dBc/Hz LOG
10.00 10dB/
dB/
1
3
REF LEVEL
10.00dBm
05669-010
05669-007
START 100MHz STOP 10.000GHz
1kHz FREQUENCY OFFSET 10MHz RES BW 3MHz VBW 3MHz SWEEP 16.52ms (601pts)
Figure 7. Phase Noise Response at 315 MHz, VDD = 3.0 V, ICP = 1.5 mA Figure 10. Harmonic Response, RFOUT Matched to 50 Ω, No Filter
∆ Mkr1 1.834GHz
REF 15dBm ATTEN 30dB –62.57dB
REF 20dBm ATTEN 30dB NORM 1R
NORM
LOG LOG
10 10dB/
dB/
MARKER ∆
1.834000000GHz
FSK –62.57dB
LgAv
LgAv
W1 S2 1
V1 V2 S3 FC
S3 FC GFSK
AA AA
£(f): £(f):
f>50k FTun
SWP Swp
05669-058
05669-011
CENTER 415.000 0 MHz SPAN 400 kHz START 800MHz STOP 5.000GHz
#RES BW 300 Hz VBW 300 Hz SWEEP 5.359 s (601pts) #RES BW 30kHz VBW 30kHz SWEEP 5.627s (601pts)
Figure 8. Output Spectrum in FSK and GFSK Modulation Figure 11. Harmonic Response, Murata Dielectric Filter
0
–5 200kHz FILTER BW REF 20dBm ATTEN 30dB
NORM
–10 LOG
10
–15 dB/
ATTENUATION LEVEL (dB)
–20
–25
–30 OOK
–35
–40 ASK
–45 150kHz FILTER BW LgAv

–50 V1 V2
S3 FC GOOK
–55
100kHz FILTER BW AA
–60 £(f):
f>50k
–65 SWP
–70
–400 –300 –200 –100 0 100 200 300 400 500 600
05669-059
05669-009
–350 –250 –150 –50 50 150 250 350 450 550

CENTER 415.000 0 MHz SPAN 300 kHz
IF FREQ (kHz) #RES BW 360 Hz VBW 360 Hz SWEEP 2.791 s (601pts)
Figure 9. IF Filter Response Figure 12. Output Spectrum in ASK, OOK, and GOOK Modes, DR = 10 kbps
0
20 +2.3V,+85°C
+2.3V,+25°C
9µA –1
15 +3.6V,+85°C
11µA –2
10 +2.3V,–40°C
5 –3 +3.6V,–40°C
PA OUTPUT POWER
LOG (BER)
5µA +3.6V,+25°C +3.0V,–40°C
0 –4
7µA
–5
–5
–10
–6
–15
–7
–20
–8
–25
05669-016
–127 –126 –125 –124 –123 –122 –121 –120 –119 –118 –117 –116 –115
05669-013
1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61
PA SETTING INPUT POWER (dBm)
Figure 13. PA Output Power vs. Setting Figure 16. Sensitivity vs. VDD and Temperature,
RF = 315 MHz, DR = 1 kBPS, Correlator Demod
0
CARRIER POWER 10.75dBm ATTEN 6.00dB MKR1 10.0000kHz
REF –70.00dBc/Hz –86.20dBc/Hz
10.00 –1
200.8k
dB/
DATA RATE
–2
–3
1.002k 9.760k
DATA RATE DATA RATE
–4
BER
–5
–6
–7
–8
–122
–121
–120
–119
–118
–117
–116
–115
–114
–113
–112
–111
–110
–109
–108
–107
–106
–105
–104
–103
–102
–101
–100
–99
–98
–97
–96
–95
–94
–93
–92
–91
–90
05669-017
05669-057
1kHz FREQUENCY OFFSET 10MHz RF I/P LEVEL (dBm)
Figure 14. Wideband Interference Rejection. Wanted Signal (880 MHz) at 3 dB Figure 17. BER vs. Data-Rate (Combined Matching Network) Separate LNA
above Sensitivity Point Interferer = FM Jammer (9.76 kbps, 10k Deviation) and PA Matching Paths Typically Improve Performance by 2 dB
–60
20
–65
0 –70
ACTUAL INPUT LEVEL
LINEAR AFC OFF
–75
–20
RF I/P LEVEL (dBm)
–80
RSSI LEVEL (dB)
–40 CORRELATION
–85
RSSI READBACK LEVEL AFC ON
–60 –90
–95 CORRELATION LINEAR AFC ON

–80 AFC OFF
–100
–100 –105
–110
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
110
05669-018
05669-015
–120 –100 –80 –60 –40 –20 0 20

RF I/P (dB) FREQUENCY ERROR (kHz)
Figure 15. Digital RSSI Readback Linearity Figure 18. Sensitivity vs. Frequency Error with AFC On/Off
FREQUENCY SYNTHESIZER
REFERENCE INPUT R Counter
The on-board crystal oscillator circuitry (see Figure 19) can use The 3-bit R counter divides the reference input frequency by an
an inexpensive quartz crystal as the PLL reference. The oscil- integer from 1 to 7. The divided-down signal is presented as the
lator circuit is enabled by setting R1_DB12 high. It is enabled by reference clock to the phase frequency detector (PFD). The
default on power-up and is disabled by bringing CE low. Errors divide ratio is set in Register 1. Maximizing the PFD frequency
in the crystal can be corrected using the automatic frequency reduces the N value. This reduces the noise multiplied at a rate
control (see the AFC Section) feature or by adjusting the of 20 log(N) to the output, as well as reducing occurrences of
fractional-N value (see the N Counter section). A single-ended spurious components. The R Register defaults to R = 1 on
reference (TCXO, CXO) can also be used. The CMOS levels power-up:
should be applied to OSC2 with R1_DB12 set low. PFD [Hz] = XTAL/R
MUXOUT and Lock Detect
The MUXOUT pin allows the user to access various digital
OSC1 OSC2
points in the ADF7020-1. The state of MUXOUT is controlled
by Bits R0_DB (29:31).
5669-019
CP2 CP1
Regulator Ready
Figure 19. Oscillator Circuit on the ADF7020-1
Regulator ready is the default setting on MUXOUT after the
Two parallel resonant capacitors are required for oscillation at transceiver has been powered up. The power-up time of the
the correct frequency; their values are dependent on the crystal regulator is typically 50 µs. Because the serial interface is
specification. They should be chosen so that the series value of powered from the regulator, the regulator must be at its
capacitance added to the PCB track capacitance adds up to the nominal voltage before the ADF7020-1 can be programmed.
load capacitance of the crystal, usually 20 pF. Track capacitance The status of the regulator can be monitored at MUXOUT.
values vary from 2 pF to 5 pF, depending on board layout. When the regulator ready signal on MUXOUT is high,
Where possible, choose capacitors that have a very low programming of the ADF7020-1 can begin.
temperature coefficient to ensure stable frequency operation DVDD
over all conditions.
CLKOUT Divider and Buffer
REGULATOR READY
The CLKOUT circuit takes the reference clock signal from the
DIGITAL LOCK DETECT
oscillator section (see Figure 19) and supplies a divided-down
ANALOG LOCK DETECT
50:50 mark-space signal to the CLKOUT pin. An even divide MUX CONTROL MUXOUT
R COUNTER OUTPUT
from 2 to 30 is available. This divide number is set in R1_DB N COUNTER OUTPUT
(8:11). On power-up, the CLKOUT defaults to the divide-by-8 PLL TEST MODES
block. Σ-∆ TEST MODES
DVDD
CLKOUT
05669-021
ENABLE BIT
DGND
DIVIDER Figure 21. MUXOUT Circuit

OSC1 ÷2 CLKOUT
1 TO 15
05669-020
Digital Lock Detect

Figure 20. CLKOUT Stage Digital lock detect is active high. The lock detect circuit is
located at the PFD. When the phase error on five consecutive
To disable CLKOUT, set the divide number to 0. The output cycles is less than 15 ns, lock detect is set high. Lock detect
buffer can drive up to a 20 pF load with a 10% rise time at remains high until 25 ns phase error is detected at the PFD.
4.8 MHz. Faster edges can result in some spurious feedthrough Because no external components are needed for digital lock
to the output. A small series resistor (50 Ω) can be used to slow detect, it is more widely used than analog lock detect.
the clock edges to reduce these spurs at FCLK.
Analog Lock Detect For GFSK, it is recommended that an LBW of 2.0 to 2.5 times
This N-channel, open-drain lock detect should be operated the data rate be used to ensure that sufficient samples are
with an external pull-up resistor of 10 kΩ nominal. When a lock taken of the input data while filtering system noise. The free
has been detected, this output is high with narrow low-going design tool ADIsimPLL can be used to design loop filters for
pulses. the ADF7020-1.
Voltage Regulators N Counter

The ADF7020-1 contains four regulators to supply stable The feedback divider in the ADF7020-1 PLL consists of an 8-bit
voltages to the part. The nominal regulator voltage is 2.3 V. integer counter and a 15-bit Σ-Δ fractional-N divider. The
Each regulator should have a 100 nF capacitor connected integer counter is the standard pulse-swallow type common in
between CREG and GND. When CE is high, the regulators and PLLs. This sets the minimum integer divide value to 31. The
other associated circuitry are powered on, drawing a total fractional divide value gives very fine resolution at the output,
supply current of 2 mA. Bringing the chip-enable pin low where the output frequency of the PLL is calculated as
disables the regulators, reduces the supply current to less than XTAL Fractional − N
1 µA, and erases all values held in the registers. The serial FOUT = × (Integer − N + )
R 215
interface operates from a regulator supply; therefore, to write to
the part, the user must have CE high and the regulator voltage
must be stabilized. Regulator status (CREG4) can be monitored REFERENCE IN
PFD/
using the regulator ready signal from muxout. 4\R
CHARGE VCO
PUMP
Loop Filter
The loop filter integrates the current pulses from the charge
4\N
pump to form a voltage that tunes the output of the VCO to the
desired frequency. It also attenuates spurious levels generated by
THIRD-ORDER
the PLL. A typical loop-filter design is shown in Figure 22. Σ-∆ MODULATOR
05669-023
FRACTIONAL-N INTEGER-N
CHARGE VCO
PUMP OUT Figure 23. Fractional-N PLL
05669-022
The combination of the integer-N (maximum = 255) and the

fractional-N (maximum = 16,383/16,384) give a maximum N
Figure 22. Typical Loop-Filter Configuration divider of 255 + 1. Therefore, the minimum usable PFD is
In FSK, the loop should be designed so that the loop bandwidth PFDMIN [Hz] = Maximum Required Output Frequency/(255 + 1)
(LBW) is approximately 5 times the data rate. Widening the
For example, when operating at 620 MHz, PFDMIN equals
LBW excessively reduces the time spent jumping between
2.42 MHz.
frequencies, but can cause insufficient spurious attenuation.
Voltage Controlled Oscillator (VCO)
For ASK systems, a wider LBW is recommended. The sudden
large transition between two power levels might result in VCO The ADF7020-1 features an on-chip VCO with external tank
pulling and can cause a wider output spectrum than is desired. inductor, which is used to set the frequency range. The center
By widening the LBW to more than 10 times the data rate, the frequency of the VCO is set by the internal varactor capacitance
amount of VCO pulling is reduced, because the loop settles and the combined inductance of the external chip inductor,
quickly back to the correct frequency. The wider LBW might bond wire, and PCB track. A plot of VCO operating range vs.
restrict the output power and data rate of ASK-based systems total external inductance (chip inductor + PCB track) is shown
more than it would that of FSK-based systems. in Figure 24. The inductance for a PCB track using FR4
material is approximately 0.57 nH/mm. This should be
Narrow-loop bandwidths can result in the loop taking long
subtracted from the total value to determine the correct chip
periods of time to attain lock. Careful design of the loop filter is
inductor value.
critical to obtaining accurate FSK/GFSK modulation.
An additional frequency divide-by-2 block is included to allow
operation from 80 MHz to 325 MHz. To enable the divide-by-2
block, set R1_DB13 to 1.
The VCO can be recentered, depending on the required CHOOSING CHANNELS FOR BEST SYSTEM
frequency of operation, by programming the VCO adjust bits PERFORMANCE
R1_DB (20:21).
The fractional-N PLL allows the selection of any channel within
The VCO is enabled as part of the PLL by the PLL-enable bit, 80 MHz to 650 MHz to a resolution of <300 Hz. This also
R0_DB28. facilitates frequency-hopping systems.
The VCO needs an external 22 nF between the VCO and the Careful selection of the RF transmit channels must be made
regulator to reduce internal noise. to achieve best spurious performance. The architecture of
fractional-N results in some level of the nearest integer channel
750
moving through the loop to the RF output. These beat-note
700
spurs are not attenuated by the loop if the desired RF channel
650
FMAX (MHz)
and the nearest integer channel are separated by a frequency of
600
FREQUENCY (MHz)
less than the LBW.

550
500 The occurrence of beat-note spurs is rare, because the integer

450 frequencies are at multiples of the reference, which is typically
400 >10 MHz.
350 The amplitude of beat-note spurs can be significantly reduced
300 FMIN (MHz) by using the frequency doubler to avoid very small or very large
05669-024
250 values in the fractional register. By having a channel 1 MHz

200 away from an integer frequency, a 100 kHz loop filter can
0 5 10 15 20 25 30
TOTAL EXTERNAL INDUCTANCE (nH) reduce the level to <−45 dBc.
Figure 24. External Inductance vs. Frequency
VCO Bias Current

VCO bias current can be adjusted using Bits R1_DB19 to
R1_DB16. To minimize current consumption, the bias current
setting should be as indicated in Table 5.
Table 5. Recommended VCO Bias Currents

Direct Frequency Output (f) VCO Bias R1_DB(19:16)
f < 200 MHz 0001
200 MHz < f < 450 MHz 0010
f > 450 MHz 0011
VCO BIAS
R1_DB (16:19) TO N
DIVIDER
LOOP FILTER VCO ÷2 MUX TO PA

÷2
220µF
CVCO PIN
05669-025
VCO SELECT BIT
Figure 25. Voltage Controlled Oscillator (VCO)
TRANSMITTER
RF OUTPUT STAGE The PA is equipped with overvoltage protection, which makes it
robust in severely mismatched conditions. Depending on the
The PA of the ADF7020-1 is based on a single-ended, application, users can design a matching network for the PA to
controlled current, open-drain amplifier that has been designed exhibit optimum efficiency at the desired radiated output power
to deliver up to 13 dBm into a 50 Ω load at a maximum level for a wide range of different antennas, such as loop or mono-
frequency of 650 MHz. pole antennas. See the LNA/PA Matching section for details.
The PA output current and, consequently, the output power are
PA Bias Currents
programmable over a wide range. The PA configurations in
FSK/GFSK and ASK/OOK modulation modes are shown in Control Bits R2_DB (30:31) facilitate an adjustment of the PA
Figure 26 and Figure 27, respectively. In FSK/GFSK modulation bias current to further extend the output power control range, if
mode, the output power is independent of the state of the necessary. If this feature is not required, the default value of
DATA_IO pin. In ASK/OOK modulation mode, it is dependent 9 μA is recommended. The output stage is powered down by
on the state of the DATA_IO pin and Bit R2_DB29, which resetting Bit R2_DB4. To reduce the level of undesired spurious
selects the polarity of the TxData input. For each transmission emissions, the PA can be muted during the PLL lock phase by
mode, the output power can be adjusted as follows: toggling this bit.
 FSK/GFSK: The output power is set using bits MODULATION SCHEMES

R2_DB (9:14). Frequency Shift Keying (FSK)
 ASK: The output power for the inactive state of the TxData Frequency shift keying is implemented by setting the N value
input is set by Bits R2_DB (15:20). The output power for the for the center frequency and then toggling this with the TxData
active state of the TxData input is set by Bits R2_DB (9:14). line. The deviation from the center frequency is set using Bits
 OOK: The output power for the active state of the TxData R2_DB (15:23). The deviation from the center frequency in
input is set by Bits R2_DB (9:14). The PA is muted when hertz is
the TxData input is inactive. PFD ModulationNumber
R2_DB(30:31) FSKDEVIATION [Hz]
2
214
where Modulation Number is a number from 1 to 511
6
IDAC R2_DB(9:14) (R2_DB (15:23)).
Select FSK using Bits R2_DB (6:8).
RFOUT
R2_DB4
+ R2_DB5
DIGITAL
RFGND LOCK DETECT
05669-026
4R PFD/ PA STAGE
FROM VCO CHARGE VCO
PUMP
Figure 26. PA Configuration in FSK/GFSK Mode
FSK DEVIATION
DATA I/O ASK/OOK MODE FREQUENCY
R2_DB29 N
–FDEV
R2_DB(30:31) THIRD-ORDER
+FDEV - MODULATOR
6
05669-028
6 R2_DB(9:14)
IDAC TxDATA
FRACTIONAL-N INTEGER-N
6
R2_DB(15:23)
Figure 28. FSK Implementation
RFOUT 0
R2_DB4
+ R2_DB5
DIGITAL
RFGND LOCK DETECT
05669-027
FROM VCO
Figure 27. PA Configuration in ASK/OOK Mode
Gaussian Frequency Shift Keying (GFSK) Amplitude Shift Keying (ASK)
Gaussian frequency shift keying reduces the bandwidth Amplitude shift keying is implemented by switching the output
occupied by the transmitted spectrum by digitally prefiltering stage between two discrete power levels. This is accomplished by
the TxData. A TxCLK output line is provided from the toggling the DAC, which controls the output level between two
ADF7020-1 for synchronization of TxData from the micro- 6-bit values set up in Register 2. A 0 TxData bit sends Bits R2_DB
controller. The TxCLK line can be connected to the clock input (15:20) to the DAC. A high TxData bit sends Bits R2_DB (9:14)
of a shift register that clocks data to the transmitter at the exact to the DAC. A maximum modulation depth of 30 dB is possible.
data rate. On-Off Keying (OOK)
Setting Up the ADF7020-1 for GFSK On-off keying is implemented by switching the output stage to a
To set up the frequency deviation, set the PFD and the certain power level for a high TxData bit and switching the
modulator control bits according to the following equation: output stage off for a low TxData bit. For OOK, the transmitted
power for a high input is programmed using Bits R2_DB (9:14).
PFD × 2 m
GFSK DEVIATION [Hz] = Gaussian On-Off Keying (GOOK)
212
Gaussian on-off keying represents a prefiltered form of OOK
where m is GFSK_MOD_CONTROL set using R2_DB (24:26).
modulation. The usually sharp symbol transitions are replaced
To set up the GFSK data rate, set the PFD and the modulator with smooth Gaussian filtered transitions, the result being a
control bits according to the following equation: reduction in frequency pulling of the VCO. Frequency pulling
PFD of the VCO in OOK mode can lead to a wider than desired BW,
DR [bps] = especially if it is not possible to increase the loop-filter BW >
DIVIDER _ FACTOR × INDEX _ COUNTER
300 kHz. The GOOK sampling clock samples data at the data
where DIVIDER_FACTOR and INDEX_COUNTER are rate. (See the Setting Up the ADF7020-1 for GFSK section.)
programmed in Bits R2_DB (15:21) and R2_DB (27:28),
respectively. For further information, see the Using GFSK on
the ADF7010 section in the EVAL-ADF7010EB1 data sheet.
RECEIVER SECTION
RF FRONT END The LNA has two basic operating modes: high gain/low noise
The ADF7020-1 is based on a fully integrated, low IF receiver mode and low gain/low power mode. To switch between these
architecture. The low IF architecture facilitates a very low two modes, use the LNA_mode bit, R6_DB15. The mixer is also
external component count and does not suffer from power-line- configurable between a low current and an enhanced linearity
induced interference problems. mode using the mixer_linearity bit, R6_DB18.
Figure 29 shows the structure of the receiver front end. The Based on the specific sensitivity and linearity requirements of
many programming options allow users to trade off sensitivity, the application, it is recommended to adjust control bits
linearity, and current consumption for each other in the most LNA_mode (R6_DB15) and mixer_linearity (R6_DB18) as
suitable way for their applications. To achieve a high level of outlined in Table 6.
resilience against spurious reception, the LNA features a The gain of the LNA is configured by the LNA_gain field,
differential input. Switch SW2 shorts the LNA input when R9_DB (20:21), and can be set by either the user or the
transmit mode is selected (R0_DB27 = 0). This feature facili- automatic gain control (AGC) logic.
tates the design of a combined LNA/PA matching network, IF Filter Settings/Calibration
avoiding the need for an external Rx/Tx switch. See the
Out-of-band interference is rejected by means of a fourth-order
LNA/PA Matching section for details on the design of the
Butterworth polyphase IF filter centered around a frequency of
matching network.
200 kHz. The bandwidth of the IF filter can be programmed
I (TO FILTER)
between 100 kHz and 200 kHz by means of Control Bits R1_DB
RFIN
Tx/Rx SELECT
SW2 LNA
(22:23); it should be chosen as a compromise between inter-
LO
[R0_DB27]
RFINB
ference rejection, attenuation of the desired signal, and the AFC
Q (TO FILTER) pull-in range.
LNA MODE
[R6_DB15]
MIXER LINEARITY
To compensate for manufacturing tolerances, the IF filter
LNA CURRENT [R6_DB18] should be calibrated once after power-up. The IF filter
[R6_DB(16:17)]
calibration logic requires that the IF filter divider in
LNA GAIN
[R9_DB(20:21)] Bits R6_DB (20:28) be set dependent on the crystal frequency.
05669-029
LNA/MIXER ENABLE Once initiated by setting Bit R6_DB19, the calibration is

[R8_DB6]
performed automatically without any user intervention. The
Figure 29. ADF7020-1 RF Front End
calibration time is 200 μs, during which the ADF7020-1 should
The LNA is followed by a quadrature down conversion mixer, not be accessed. It is important not to initiate the calibration
which converts the RF signal to the IF frequency of 200 kHz. It cycle before the crystal oscillator has fully settled. If the AGC
is important to consider that the output frequency of the syn- loop is disabled, the gain of IF filter can be set to three levels
thesizer must be programmed to a value 200 kHz below the using the filter_gain field, R9_DB (22:23). The filter gain is
center frequency of the received channel. adjusted automatically, if the AGC loop is enabled.
Table 6. LNA/Mixer Modes

LNA Gain Mixer Sensitivity Rx Current
LNA Mode Value Linearity (DR = 9.6 kbps, Consumption Input IP3
Receiver Mode (R6_DB15) R9_DB (21:20) (R6_DB18) fDEV = 10 kHz) (mA) (dBm)
High Sensitivity Mode (default) 0 30 0 −112.5 20.1 −35
RxMode2 1 10 0 −105.8 19.0 −15.9
Low Current Mode 1 3 0 −92.2 17.6 −3.2
Enhanced Linearity Mode 1 3 1 −102.5 17.6 +6.8
RxMode5 1 10 1 −99 19.0 −8.25
RxMode6 0 30 1 −105 20.1 −28.8
RSSI/AGC AGC Settling = AGC_Wait_Time × Number of Gain
The RSSI is implemented as a successive compression log amp Changes
following the base-band channel filtering. The log amp achieves Thus, in the worst case, if the AGC loop has to go through all five
±3 dB log linearity. It also doubles as a limiter to convert the gain changes, AGC delay = 10, and SEQ_CLK = 200 kHz, then
signal-to-digital levels for the FSK demodulator. The RSSI itself AGC settling = 10 × 5 µs × 5 = 250 µs. Minimum AGC_Wait_Time
is used for amplitude shift keying (ASK) demodulation. In ASK must be at least 25 µs.
mode, extra digital filtering is performed on the RSSI value. RSSI Formula (Converting to dBm)
Offset correction is achieved using a switched capacitor integra-
Input_Power [dBm] = −120 dBm + (Readback_Code +
tor in feedback around the log amp. This uses the BB offset
Gain_Mode_Correction) × 0.5
clock divide. The RSSI level is converted for user readback and
digitally controlled AGC by an 80-level (7-bit) flash ADC. This where:
level can be converted to input power in dBm. Readback_Code is given by Bits RV7 to RV1 in the readback
OFFSET
register (see Readback Format section).
CORRECTION Gain_Mode_Correction is given by the values in Table 7.
FSK LNA gain and filter gain (LG2/LG1, FG2/FG1) are also
1 A A A LATCH DEMOD
obtained from the readback register.
IFWR IFWR IFWR IFWR CLK RSSI Table 7. Gain Mode Correction
ASK
DEMOD LNA Gain Filter Gain
ADC
(LG2, LG1) (FG2, FG1) Gain Mode Correction
05669-030
R
H (1, 1) H (1, 0) 0
Figure 30. RSSI Block Diagram M (1, 0) H (1, 0) 24
M (1, 0) M (0, 1) 45
RSSI Thresholds
M (1, 0) L (0, 0) 63
When the RSSI is above AGC_HIGH_THRESHOLD, the gain is L (0, 1) L (0, 0) 90
reduced. When the RSSI is below AGC_LOW_THRESHOLD, the EL (0, 0) L (0, 0) 105
gain is increased. A delay (AGC_DELAY) is programmed to allow
An additional factor should be introduced to account for losses
for settling of the loop. The user programs the two threshold values
in the front-end matching network/antenna.
(recommended defaults, 30 and 70) and the delay (default, 10).
The default AGC set-up values should be adequate for most FSK DEMODULATORS ON THE ADF7020-1
applications. The threshold values must be more than 30 settings The two FSK demodulators on the ADF7020-1 are
apart for the AGC to operate correctly.
• FSK correlator/demodulator
Offset Correction Clock • Linear demodulator
In Register 3, the user should set the BB offset clock divide bits
Select these using the demodulator select bits, R4_DB (4:5).
R3_DB (4:5) to give an offset clock between 1 MHz and 2 MHz,
where: FSK CORRELATOR/DEMODULATOR
BBOS_CLK (Hz) = XTAL/(BBOS_CLK_DIVIDE) The quadrature outputs of the IF filter are first limited and then
BBOS_CLK_DIVIDE can be set to 4, 8, or 16. fed to a pair of digital frequency correlators that perform band-
pass filtering of the binary FSK frequencies at (IF + FDEV) and
AGC Information and Timing (IF − FDEV). Data is recovered by comparing the output levels
AGC is selected by default, and operates by selecting the appro- from each of the two correlators. The performance of this
priate LNA and filter gain settings for the measured RSSI level. frequency discriminator approximates that of a matched filter
It is possible to disable AGC by writing to Register 9 if you want detector, which is known to provide optimum detection in the
to enter one of the modes listed in Table 6, for example. The presence of AWGN.
time for the AGC circuit to settle and hence the time it takes to FREQUENCY CORRELATOR SLICER
take an accurate RSSI measurement is typically 150 µs, although I IF Rx DATA

SYNCHRONIZER
DEMOD FILTER
this depends on how many gain settings the AGC circuit has to
DATA
POST
LIMITERS
cycle through. After each gain change, the AGC loop waits for a Rx CLK
Q
programmed time to allow transients to settle. This wait time IF – FDEV IF + FDEV
can be adjusted to speed up this settling by adjusting the 0
05669-031
appropriate parameters. DB(8:15)

DB(4:13) DB(14)
AGC _ DELAY × SEQ _ CLK _ DIVIDE Figure 31. FSK Correlator/Demodulator Block Diagram
AGC _ Wait _ Time =
XTAL
Postdemodulator Filter Table 8. When K Is Even
A second-order digital low-pass filter removes excess noise from K K/2 R6_DB14 R6_DB29
the demodulated bit stream at the output of the discriminator. Even Even 0 0
The bandwidth of this postdemodulator filter is programmable Even Odd 0 1
and must be optimized for the user’s data rate. If the bandwidth
is set too narrow, performance is degraded due to intersymbol Table 9. When K Is Odd
interference (ISI). If the bandwidth is set too wide, excess noise K (K + 1)/2 R6_DB14 R6_DB29
degrades the receiver’s performance. Typically, the 3 dB bandwidth Odd Even 1 0
of this filter is set at approximately 0.75 times the user’s data Odd Odd 1 1
rate, using Bits R4_DB (6:15).
Bit Slicer Postdemodulator Bandwidth Register Settings
The received data is recovered by the threshold detecting the The 3 dB bandwidth of the postdemodulator filter is controlled
output of the postdemodulator low-pass filter. In the correlator/ by Bits R4_ DB (6:15) and is given by
demodulator, the binary output signal levels of the frequency
2 10 × 2π × FCUTOFF
discriminator are always centered on zero. Therefore, the slicer Post _ Demod _ BW _ Setting =
threshold level can be fixed at zero, and the demodulator DEMOD _ CLK
performance is independent of the run-length constraints of the where FCUTOFF is the target 3 dB bandwidth in hertz of the post-
transmit data bit stream. This results in robust data recovery, demodulator filter. This should typically be set to 0.75 times the
which does not suffer from the classic baseline wander prob- data rate (DR).
lems that exist in the more traditional FSK demodulators.
Some sample settings for the FSK correlator/demodulator are
Frequency errors are removed by an internal AFC loop that
DEMOD_CLK = 5 MHz
measures the average IF frequency at the limiter output and
DR = 9.6 kbps
applies a frequency correction value to the fractional-N
FDEV = 20 kHz
synthesizer. This loop should be activated when the frequency
errors are greater than approximately 40% of the transmit Therefore
frequency deviation (see the AFC Section). FCUTOFF = 0.75 × 9.6 × 103 Hz
Data Synchronizer Post_Demod_BW = 211 π 7.2 × 103 Hz/(5 MHz)
Post_Demod_BW = Round(9.26) = 9
An oversampled digital PLL is used to resynchronize the received
bit stream to a local clock. The oversampled clock rate of the and
PLL (CDR_CLK) must be set at 32 times the data rate. See the K = Round(200 kHz)/20 kHz) = 10
notes for the Register 3—Receiver Clock Register section for a Discriminator_BW = (5 MHz × 10)/(800 × 103) = 62.5 =
definition of how to program the various on-chip clocks. The clock 63 (rounded to nearest integer)
recovery PLL can accommodate frequency errors of up to ±2%.
Table 10. Register Settings
FSK Correlator Register Settings
Setting Name Register Address Value
To enable the FSK correlator/demodulator, Bits R4_DB (5:4) Post_Demod_BW R4_DB (6:15) 0x09
should be set to [01]. To achieve best performance, the bandwidth Discriminator_BW R6_DB (4:13) 0x3F
of the FSK correlator must be optimized for the specific deviation Dot Product R6_DB14 0
frequency that is used by the FSK transmitter. Rx Data Invert R6_DB29 1
The discriminator BW is controlled in Register 6 by R6_DB
(4:13) and is defined as
Discriminator _ BW = (DEMOD _ CLK × K ) /(800 × 10 3 )
where:
DEMOD_CLK is as defined in the Register 3—Receiver Clock
Register section, Note 2.
K = round(200e3/FSK deviation)
To optimize the coefficients of the FSK correlator, two
additional bits, R6_DB14 and R6_DB29, must be assigned.
The value of these bits depends on whether K (as defined
above) is odd or even. These bits are assigned according to the
conditions listed in Table 8 and Table 9.
LINEAR FSK DEMODULATOR postdemodulator filter.
Figure 32 shows a block diagram of the linear FSK demodulator. It is also recommended to use Manchester encoding in ASK/OOK
MUX 1 SLICER
mode to ensure the data run length limit (RLL) is 2 bits. If a longer
ADC RSSI OUTPUT 7 RLL, up to a maximum of 4 bits, is required, users should disable
the extra-low gain setting by writing 0x3C00C to the test mode
LEVEL Rx DATA
I register.
AVERAGING
IF
FILTER
LIMITER
AFC SECTION
DETECTOR
ENVELOPE
Q The ADF7020-1 supports a real-time AFC loop, which is used
FREQUENCY
FREQUENCY
READBACK
to remove frequency errors that can arise due to mismatches
LINEAR DISCRIMINATOR AND between the transmit and receive crystals. The AFC loop uses the
05669-032
AFC LOOP
frequency discriminator block as described in the Linear FSK
DB(6:15)
Demodulator section (see Figure 32). The discriminator output
Figure 32. Block Diagram of Frequency Measurement System and
ASK/OOK/Linear FSK Demodulator is filtered and averaged to remove the FSK frequency
modulation using a combined averaging filter and envelope
This method of frequency demodulation is useful when very detector. In FSK mode, the output of the envelope detector
short preamble length is required and the system protocol provides an estimate of the average IF frequency. Two methods
cannot support the overhead of the settling time of the internal of AFC, external and internal, are supported on the ADF7020-1
feedback AFC loop settling. (in FSK mode only).
A digital frequency discriminator provides an output signal that External AFC
is linearly proportional to the frequency of the limiter outputs.
The user reads back the frequency information through the
The discriminator output is then filtered and averaged using a
ADF7020-1 serial port and applies a frequency correction value
combined averaging filter and envelope detector. The demodu-
to the fractional-N synthesizer’s N divider.
lated FSK data is recovered by comparing the filter output with
its average value, as shown in Figure 32. In this mode, the slicer The frequency information is obtained by reading the 16-bit
output shown in Figure 32 is routed to the data synchronizer signed AFC_readback, as described in the Readback Format
PLL for clock synchronization. To enable the linear FSK section, and applying the following formula:
demodulator, set Bits R4_DB (4:5) to [00]. FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/215
The 3 dB bandwidth of the postdemodulation filter is set in the Note that while the AFC_READBACK value is a signed number,
same way as the FSK correlator/demodulator, which is set in under normal operating conditions it is positive. In the absence
R4_DB (6:15) and is defined as of frequency errors, the FREQ_RB value is equal to the IF
210  2  FCUTOFF frequency of 200 kHz.
Post _ Demod _ BW _ Setting 
DEMOD _ CLK Internal AFC
where: The ADF7020-1 supports a real-time internal automatic fre-
FCUTOFF is the target 3 dB bandwidth in hertz of the quency control loop. In this mode, an internal control loop
postdemodulator filter. DEMOD_CLK is as defined in the automatically monitors the frequency error and adjusts the
Register 3—Receiver Clock Register section, Note 2. synthesizer N divider using an internal PI control loop.
ASK/OOK Operation The internal AFC control loop parameters are controlled in
Register 11. The internal AFC loop is activated by setting
ASK/OOK demodulation is activated by setting Bits R4_DB (4:5)
R11_DB20 to 1. A scaling coefficient must also be entered,
to [10].
based on the crystal frequency in use. This is set up in R11_DB
ASK/OOK demodulation is performed by digitally filtering the (4:19) and should be calculated using
RSSI output, and then comparing the filter output with its average
AFC_Scaling_Coefficient = (500 × 224)/XTAL
value in a similar manner to FSK demodulation. The bandwidth
of the digital filter must be optimized to remove any excess Therefore, using a 10 MHz XTAL yields an AFC scaling
noise without causing ISI in the received ASK/OOK signal. coefficient of 839.
The 3 dB bandwidth of this filter is typically set at approximately AFC Performance
0.75 times the user data rate and is assigned by R4 _DB (6:15) as The improved sensitivity performance of the Rx when AFC is
2  2  FCUTOFF
10 enabled and in the presence of frequency errors is shown in
Post_Demod_BW_Setting = Figure 18. The maximum AFC pull-in range is ±50 kHz, which
DEMOD_CLK
corresponds to ±58 ppm at 868 MHz. This is the total error
where FCUTOFF is the target 3 dB bandwidth in hertz of the tolerance allowed in the link. For example, in a point-to-point
system, AFC can compensate for two ±29 ppm crystals or one This feature can be used to alert the microprocessor that a valid
±50 ppm crystal and one ±8 ppm TCXO. channel has been detected. It relaxes the computational require-
AFC settling typically takes 48 bits to settle within ±1 kHz. This ments of the microprocessor and reduces the overall power
can be improved by increasing the postdemodulator bandwidth consumption. The INT/LOCK is automatically deasserted again
in Register 4 at the expense of Rx sensitivity. after nine data clock cycles.
When AFC errors have been removed using either the internal The automatic sync/ID word detection feature is enabled by
or external AFC, further improvement in the receiver’s sensitivity selecting Demodulator Mode 2 or 3 in the demodulator set-up
can be obtained by reducing the IF filter bandwidth using register. Do this by setting R4_DB (25:23) = [010] or [011].
Bits R1_DB (22:23). Bits R5_DB (4:5) are used to set the length of the sync/ID
word, which can be 12, 16, 20, or 24 bits long. The transmitter
AUTOMATIC SYNC WORD RECOGNITION must transmit the MSB of the sync byte first and the LSB last to
The ADF7020-1 also supports automatic detection of the sync ensure proper alignment in the receiver sync byte detection
or ID fields. To activate this mode, the sync (or ID) word must hardware.
be preprogrammed in the ADF7020-1. In receive mode, this For systems using FEC, an error tolerance parameter can also
preprogrammed word is compared to the received bit stream, be programmed that accepts a valid match when up to three bits
and the external pin INT/LOCK is asserted by the ADF7020-1 of the word are incorrect. The error tolerance value is assigned
when a valid match is identified. in R5_DB (6:7).
Table 11. Sensitivity Values for Varying RF Frequency and Data Rates
FSK Sensitivity FSK Sensitivity
Deviation in at BER = 1E-3, at BER = 1E-3, ASK Sensitivity
Frequency Data Rate (NRZ) FSK Mode Correlator Demodulator Linear Demodulator at BER = 1E-3
135 MHz 9.6 kbps ±10 kHz −113.2 dBm −106.2 dBm −110.8
135 MHz 1.0 kbps ±5 kHz −119.5 dBm −109.2 dBm −116.8 dBm
315 MHz 1.0 kbps ±5 kHz −120 dBm −110.1 dBm −118 dBm
APPLICATIONS
LNA/PA MATCHING network with respect to ground, a compromise between the input
reflection coefficient and the maximum differential signal swing
The ADF7020-1 exhibits optimum performance in terms of at the LNA input must be established. The use of appropriate
sensitivity, transmit power, and current consumption only if its CAD software is strongly recommended for this optimization.
RF input and output ports are properly matched to the antenna
impedance. For cost-sensitive applications, the ADF7020-1 is Depending on the antenna configuration, the user might
equipped with an internal Rx/Tx switch, which facilitates the need a harmonic filter at the PA output to satisfy the spurious
use of a simple combined passive PA/LNA matching network. emission requirement of the applicable government regulations.
Alternatively, an external Rx/Tx switch, such as the Analog The harmonic filter can be implemented in various ways, such
Devices ADG919, can be used, which yields a slightly improved as a discrete LC pi or T-stage filter. The immunity of the
receiver sensitivity and lower transmitter power consumption. ADF7020-1 to strong out-of-band interference can be improved
by adding a band-pass filter in the Rx path, or alternatively by
External Rx/Tx Switch selecting one of the high linearity modes outlined in Table 6.
Figure 33 shows a configuration using an external Rx/Tx switch.
Internal Rx/Tx Switch
This configuration allows an independent optimization of the
matching and filter network in the transmit and receive path Figure 34 shows the ADF7020-1 in a configuration where the
and is therefore more flexible and less difficult to design than internal Rx/Tx switch is used with a combined LNA/PA
the configuration using the internal Rx/Tx switch. The PA is matching network. This is the configuration used in the
biased through Inductor L1, and C1 blocks the dc current. Both ADF7020-1DBX Evaluation boards. For most applications, the
elements, L1 and C1, also form the matching network, which slight performance degradation of 1 dB to 2 dB caused by the
transforms the source impedance into the optimum PA load internal Rx/Tx switch is acceptable, allowing the user to take
impedance, ZOPT_PA. advantage of the cost saving potential of this solution. The
VBAT
design of the combined matching network must compensate for
the reactance presented by the networks in the Tx and the Rx
L1
PA_OUT
paths, taking the state of the Rx/Tx switch into consideration.
OPTIONAL
PA VBAT
LPF
ANTENNA ZOPT_PA L1
C1 PA_OUT
ZIN_RFIN
PA
OPTIONAL CA RFIN
BPF
(SAW) ANTENNA OPTIONAL ZOPT_PA
LA LNA BPF OR LPF ZIN_RFIN
RFINB
CA RFIN
ADG919
ZIN_RFIN
LA LNA
05669-033
CB RFINB
Rx/Tx – SELECT ADF7020-1
Figure 33. ADF7020-1 with External Rx/Tx Switch ZIN_RFIN
05669-034
CB
ZOPT_PA depends on various factors, such as the required ADF7020-1
output power, the frequency range, the supply voltage range, Figure 34. ADF7020-1 with Internal Rx/Tx Switch
and the temperature range. Selecting an appropriate ZOPT_PA
helps to minimize the Tx current consumption in the The procedure typically requires several iterations until an
application. The Specifications section lists a number of acceptable compromise is reached. The successful implementation
ZOPT_PA values for representative conditions. Under certain of a combined LNA/PA matching network for the ADF7020-1 is
conditions, however, it is recommended to obtain a suitable critically dependent on the availability of an accurate electrical
ZOPT_PA value by means of a load-pull measurement. model for the PC board. In this context, the use of a suitable CAD
package is strongly recommended. To avoid this effort, however, a
Due to the differential LNA input, the LNA matching network small form-factor reference design for the ADF7020-1 is provided,
must be designed to provide both a single-ended to differential including matching and harmonic filter components. The design
conversion and a complex conjugate impedance match. The is on a 2-layer PCB to minimize cost. Gerber files are available
network with the lowest component count that can satisfy these on the www.analog.com website.
requirements is the configuration shown in Figure 33, which
consists of two capacitors and one inductor. A first-order
implementation of the matching network can be obtained by
understanding the arrangement as two L type matching networks
in a back-to-back configuration. Due to the asymmetry of the
TRANSMIT PROTOCOL AND CODING INTERFACING TO MICROCONTROLLER/DSP
CONSIDERATIONS Low level device drivers are available for interfacing to the
SYNC ID
ADF7020-1, the ADI ADuC84x microcontroller parts, or the
05669-035
PREAMBLE WORD FIELD DATA FIELD CRC Blackfin ADSP-BF53x DSPs using the hardware connections
shown in Figure 36 and Figure 37.
Figure 35. Typical Format of a Transmit Protocol
ADuC84x ADF7020-1
A dc-free preamble pattern is recommended for FSK/ASK/
MISO TxRxDATA
OOK demodulation. The recommended preamble pattern is a MOSI
dc-free pattern such as a 10101010 … pattern. Preamble SCLOCK RxCLK
patterns with longer run-length constraints, such as SS
P3.7 CE
11001100…, can also be used. However, this results in a longer
P3.2/INT0 INT/LOCK
synchronization time of the received bit stream in the receiver. P2.4 SREAD
P2.5 SLE
Manchester coding can be used for the entire transmit protocol. GPIO
05669-036
P2.6 SDATA
However, the remaining fields that follow the preamble header P2.7 SCLK
do not have to use dc-free coding. For these fields, the Figure 36.ADuC84x to ADF7020-1 Connection Diagram
ADF7020-1 can accommodate coding schemes with a run-
ADSP-BF533 ADF7020-1
length of up to 6 bits without any performance degradation.
SCK SCLK
If longer run-length coding must be supported, the ADF7020-1 MOSI SDATA
MISO SREAD
has several other features that can be activated. These involve a PF5 SLE
range of programmable options that allow the envelope detector RSCLK1 TxRxCLK
output to be frozen after preamble acquisition. DT1PRI TxRxDATA
DR1PRI
DEVICE PROGRAMMING AFTER INITIAL RFS1 INT/LOCK
POWER-UP PF6 CE
05669-037
VCC VCC
Table 12 lists the minimum number of writes needed to set up GND GND
the ADF7020-1 in either Tx or Rx mode after CE is brought Figure 37.ADSP-BF533 to ADF7020-1 Connection Diagram
high. Additional registers can also be written to tailor the part
to a particular application, such as setting up sync byte
detection or enabling AFC. When going from Tx to Rx or vice
versa, the user needs to write only to the N register to alter the
LO by 200 kHz and to toggle the Tx/Rx bit.
Table 12. Minimum Register Writes Required for Tx/Rx Setup

Mode Registers
Tx Reg 0 Reg 1 Reg 2
Rx Reg 0 Reg 1 Reg 2 Reg 4 Reg 6
(OOK)
Rx Reg 0 Reg 1 Reg 2 Reg 4 Reg 6
(G/FSK)
Tx <-> Reg 0
Rx
Figure 38 and Figure 39 show the recommended programming
sequence and associated timing for power-up from
standby mode.
ADF7020-1 IDD
17.6mA TO
20.1mA
14mA
_XTAL
T0
3.65mA
2.0mA
AFC
T10
REG. WR3 WR4 WR6 AGC/ CDR
READY WR0 WR1 RxDATA TIME
VCO T5 T6 T7 RSSI
T9
T1 T2 T3 T4 T8 T11
05669-038
TON TOFF
Figure 38. Rx Programming Sequence and Timing Diagram
Table 13. Power-Up Sequence Description

Parameter Value Description/Notes Signal to Monitor
T0 2 ms Crystal starts power-up after CE is brought high. This typically depends CLKOUT pin
on the crystal type and the load capacitance specified.
T1 10 μs Time for regulator to power up. The serial interface can be written to after MUXOUT pin
this time.
T2, T3, T5, T6, T7 32 × 1/SPI_CLK Time to write to a single register. Maximum SPI_CLK is 25 MHz.
T4 1 ms The VCO can power-up in parallel with the crystal. This depends on the CVCO pin
CVCO capacitance value used. A value of 22 nF is recommended as a
trade-off between phase noise performance and power-up time.
T8 150 μs This depends on the number of gain changes the AGC loop needs to cycle Analog RSSI on TEST_A
through and AGC settings programmed. This is described in more detail pin (available by writing
in the AGC Information and Timing section. 0x3800 000C)
T9 5 × Bit_Period This is the time for the clock and data recovery circuit to settle. This typically
requires 5-bit transitions to acquire sync and is usually covered by the
preamble.
T10 16 × Bit_Period This is the time for the automatic frequency control circuit to settle. This
typically requires 16-bit transitions to acquire lock and is usually covered
by an appropriate length preamble.
T11 Packet Length Number of bits in payload by the bit period.
ADF7020-1 IDD
15mA TO
30mA
14mA
3.65mA
2.0mA
REG. WR0 WR1 WR2 TxDATA TIME

READY
T2 T3 XTAL + VCO T5
T1 T4 T12
05669-039
TON TOFF
Figure 39. Tx Programming Sequence and Timing Diagram
SERIAL INTERFACE
The serial interface allows the user to program the eleven 32-bit RSSI Readback
registers using a 3-wire interface (SCLK, SDATA, and SLE). It The RSSI readback operation yields valid results in Rx mode
consists of a voltage level shifter, a 32-bit shift register, and with ASK or FSK signals. The format of the readback word is
11 latches. Signals should be CMOS compatible. The serial shown in Figure 40. It is comprised of the RSSI level informa-
interface is powered by the regulator and therefore is inactive tion (Bits RV1 to RV7), the current filter gain (FG1, FG2), and
when CE is low. the current LNA gain (LG1, LG2) setting. The filter and LNA
Data is clocked into the register MSB first on the rising edge of gain are coded in accordance with the definitions in Register 9.
each clock (SCLK). Data is transferred to one of the 11 latches With the reception of ASK modulated signals, averaging of the
on the rising edge of SLE. The destination latch is determined measured RSSI values improves accuracy. The input power can
by the value of the four control bits (C4 to C1). These are the be calculated from the RSSI readback value as outlined in the
bottom 4 LSB, DB3 to DB0, as shown in the timing diagram in RSSI/AGC.
Figure 2. Data can also be read back on the SREAD pin. Battery Voltage ADCIN/Temperature Sensor Readback
READBACK FORMAT The battery voltage is measured at Pin VDD4. The readback
The readback operation is initiated by writing a valid control information is contained in Bits RV1 to RV7. This also applies
word to the readback register and setting the readback-enable for the readback of the voltage at the ADCIN pin and the
bit (R7_DB8 = 1). The readback can begin after the control temperature sensor. From the readback information, the battery
word has been latched with the SLE signal. SLE must be kept or ADCIN voltage can be determined using
high while the data is read out. Each active edge at the SCLK VBATTERY = (Battery_Voltage_Readback)/21.1
pin clocks the readback word out successively at the SREAD VADCIN = (ADCIN_Voltage_Readback)/42.1
pin, as shown in Figure 3, starting with the MSB first. The data
Silicon Revision Readback
appearing at the first clock cycle following the latch operation
must be ignored. The silicon revision readback word is valid without setting any
other registers, especially directly after power-up. The silicon
AFC Readback
revision word is coded with four quartets in BCD format. The
The AFC readback is valid only during the reception of FSK product code (PC) is coded with three quartets extending
signals with either the linear or correlator demodulator active. from Bits RV5 to RV16. The revision code (RV) is coded with
The AFC readback value is formatted as a signed 16-bit integer one quartet extending from Bits RV1 to RV4. The product code
comprised of Bits RV1 to RV16 and is scaled according to the for the ADF7020-1 should read back as PC = 0x200. The
following formula: current revision code should read back as RC = 0x6.
FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/215 Filter Calibration Readback
In the absence of frequency errors, the FREQ_RB value is equal The filter calibration readback word is contained in Bits RV1 to
to the IF frequency of 200 kHz. Note that the down-converted RV8 and is for diagnostic purposes only. Using the automatic
input signal must not fall outside the bandwidth of the analogue filter calibration function, accessible through Register 6, is
IF filter for the AFC readback to yield a valid result. At low- recommended. Before filter calibration is initiated Decimal 32
input signal levels, the variation in the readback value can be should be read back.
improved by averaging.
READBACK MODE READBACK VALUE
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
AFC READBACK RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1
RSSI READBACK X X X X X LG2 LG1 FG2 FG1 RV7 RV6 RV5 RV4 RV3 RV2 RV1
BATTERY VOLTAGE/ADCIN/
TEMP. SENSOR READBACK X X X X X X X X X RV7 RV6 RV5 RV4 RV3 RV2 RV1
SILICON REVISION RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1
05669-040
FILTER CAL READBACK 0 0 0 0 0 0 0 0 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1
Figure 40. Readback Value Table
REGISTER 0—N REGISTER
ENABLE
Tx/Rx
ADDRESS
PLL
MUXOUT 8-BIT INTEGER-N 15-BIT FRACTIONAL-N BITS
DB11
DB31
DB30
DB29
PLE1 DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB9
DB8
DB7
DB6
DB5
DB4
C4 (0) DB3
C3 (0) DB2
C2 (0) DB1
C1 (0) DB0
M11
M15
M14
M13
M12
M10
TR1
M3
M2
M1
M9
M8
M7
M6
M5
M4
M3
M2
M1
N8
N7
N6
N5
N4
N3
N2
N1
TRANSMIT/ FRACTIONAL
TR1 RECEIVE M15 M14 M13 ... M3 M2 M1 DIVIDE RATIO
0 TRANSMIT 0 0 0 ... 0 0 0 0
1 RECEIVE 0 0 0 ... 0 0 1 1
0 0 0 ... 0 1 0 2
PLE1 PLL ENABLE
. . . ... . . . .
0 PLL OFF . . . ... . . . .
1 PLL ON . . . ... . . . .
1 1 1 ... 1 0 0 32764
M3 M2 M1 MUXOUT
1 1 1 ... 1 0 1 32765
0 0 0 REGULATOR READY (DEFAULT) 1 1 1 ... 1 1 0 32766
0 0 1 R DIVIDER OUTPUT 1 1 1 ... 1 1 1 32767
0 1 0 N DIVIDER OUTPUT
0 1 1 DIGITAL LOCK DETECT
1 0 0 ANALOG LOCK DETECT
1 0 1 THREE-STATE
1 1 0 PLL TEST MODES
1 1 1 Σ-∆ TEST MODES
N COUNTER
N8 N7 N6 N5 N4 N3 N2 N1 DIVIDE RATIO
0 0 0 1 1 1 1 1 31
0 0 1 0 0 0 0 0 32
. . . . . . . . .
. . . . . . . . .
. . . . . . . . .
1 1 1 1 1 1 0 1 253
1 1 1 1 1 1 1 0 254
05669-041
1 1 1 1 1 1 1 1 255
Figure 41.
Notes
1. The Tx/Rx bit (R0_DB27) configures the part in Tx or Rx mode and also controls the state of the internal Tx/Rx switch.
XTAL Fractional-N
FOUT = × (Integer-N + )
2. R 215 .
REGISTER 1—OSCILLATOR/FILTER REGISTER
IF FILTER BW
VCO BAND
CURRENT
DOUBLER
ENABLE
ADJUST
XOSC
XTAL
VCO
CLOCKOUT ADDRESS
CP
VCO BIAS DIVIDE R COUNTER BITS
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
C4 (0) DB3
C3 (0) DB2
C2 (0) DB1
C1 (1) DB0
DD2
DD1
VA2
VA1
VB4
VB3
VB2
VB1
CL4
CL3
CL2
CL1
IR2
IR1
D1
R3
R2
R1
V1
X1
FREQUENCY X1 XTAL OSC RF R COUNTER
VA2 VA1 OF OPERATION 0 OFF R3 R2 R1 DIVIDE RATIO
0 0 850–920 1 ON 0 0 1 1
0 1 860–930 0 1 0 2
1 0 870–940 . . . .
1 1 880–950 VCO . . . .
V1 DIV-BY-2
. . . .
0 DIRECT OUTPUT 1 1 1 7
VCO BIAS 1 DIVIDE-BY-2
VB4 VB3 VB2 VB1 CURRENT OUTPUT
0 0 0 1 0.375mA XTAL
0 0 1 0 0.625mA D1 DOUBLER
. . . . 0 DISABLE
1 1 1 1 3.875mA 1 ENABLED
CLKOUT
FILTER ICP(MA) CL4 CL3 CL2 CL1 DIVIDE RATIO
IR2 IR1 BANDWIDTH CP1
CP2 RSET 3.6k 0 0 0 0 OFF
0 0 100kHz
0 0 0.3 0 0 0 1 2
0 1 150kHz
0 1 0.9 0 0 1 0 4
1 0 200kHz
1 0 1.5 . . . . .
1 1 NOT USED
1 1 2.1 . . . . .
05669-042
. . . . .
1 1 1 1 30
Figure 42.
Notes
1. Set the VCO adjust bits R1_DB (20:21) to 0 for normal operation.
2. See Table 5 for the recommended VCO bias settings.
3. The divide-by-2 block is enabled by setting R1_DB13. As this divide block is outside the PLL loop, users must program an N-value
that corresponds to twice the divide-by-2 output frequency. The deviation frequency is also halved when divide-by-2 is enabled.
REGISTER 2—TRANSMIT MODULATION REGISTER (ASK/OOK MODE)
UNTIL LOCK
COUNTER
MUTE PA
ENABLE
TxDATA
INVERT
INDEX
GFSK MOD MODULATION ADDRESS
PA
PA BIAS CONTROL MODULATION PARAMETER POWER AMPLIFIER SCHEME BITS
DB11
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB9
DB8
DB7
DB6
DB5
DB4
C4 (0) DB3
C3 (0) DB2
C2 (1) DB1
C1 (0) DB0
MC3
MC2
MC1
MP1
PA2
PA1
PE1
DI1
IC2
IC1
D9
D8
D7
D6
D5
D4
D3
D2
D1
P6
P5
P4
P3
P2
P1
S3
S2
S1
PE1 POWER AMPLIFIER
IC2 IC1 MC3 MC2 MC1 0 OFF

1 ON
X X X X X
MUTE PA UNTIL
DI1 MP1 LOCK DETECT HIGH
0 TxDATA 0 OFF
1 TxDATA 1 ON
PA2 PA1 PA BIAS S3 S2 S1 MODULATION SCHEME

0 0 5µA 0 0 0 FSK
0 1 7µA 0 0 1 GFSK
1 0 9µA 0 1 0 ASK
1 1 11µA 0 1 1 OOK
1 1 1 GOOK
POWER AMPLIFIER OUTPUT LOW LEVEL POWER AMPLIFIER OUTPUT HIGH LEVEL
D6 D5 . D2 D1 P6 . . P2 P1
X X . X X OOK MODE 0 . . X X PA OFF
0 X . X X PA OFF 0 . . 0 0 –16.0dBm
0 0 . 0 0 –16.0dBm 0 . . 0 1 –16 + 0.45dBm
0 0 . 0 1 –16 + 0.45dBm 0 . . 1 0 –16 + 0.90dBm
0 . . 1 0 –16 + 0.90dBm . . . . . .
. . . . . . . . . . . .
05669-043
. . . . . . 1 1 . 1 1 13dBm
1 1 . 1 1 13dBm
Figure 43.
Notes
1. Figure 13 shows how the PA bias affects the power amplifier level. The default level is 9 µA. If you need maximum power, program
this value to 11 µA.
2. In ASK/OOK, Manchester encoding is recommended to keep the data run length limit to 2 bits. See the ASK/OOK Operation
section for more details on dealing with longer run lengths.
3. D7, D8, and D9 are don’t care bits.
REGISTER 2—TRANSMIT MODULATION REGISTER (FSK MODE)
UNTIL LOCK
COUNTER
MUTE PA
ENABLE
TxDATA
INVERT
INDEX
GFSK MOD MODULATION ADDRESS
PA
DB11
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB9
DB8
DB7
DB6
DB5
DB4
C4 (0) DB3
C3 (0) DB2
C2 (1) DB1
C1 (0) DB0
MC3
MC2
MC1
MP1
PA2
PA1
PE1
DI1
IC2
IC1
D9
D8
D7
D6
D5
D4
D3
D2
D1
P6
P5
P4
P3
P2
P1
S3
S2
S1
PE1 POWER AMPLIFIER
IC2 IC1 MC3 MC2 MC1 0 OFF

1 ON
X X X X X
MUTE PA UNTIL
DI1 FOR FSK MODE, MP1 LOCK DETECT HIGH
0 TxDATA D9 .... D3 D2 D1 F DEVIATION
0 OFF
1 TxDATA 0 .... 0 0 0 PLL MODE 1 ON
0 .... 0 0 1 1 × FSTEP
0 .... 0 1 0 2 × FSTEP
PA2 PA1 PA BIAS 0 .... 0 1 1 3 × FSTEP
. .... . . . . S3 S2 S1 MODULATION SCHEME
0 0 5µA 1 .... 1 1 1 511 × FSTEP 0 0 0 FSK
0 1 7µA 0 0 1 GFSK
1 0 9µA 0 1 0 ASK
1 1 11µA 0 1 1 OOK
1 1 1 GOOK
POWER AMPLIFIER OUTPUT LEVEL

P6 . . P2 P1
0 . . X X PA OFF
0 . . 0 0 –16.0dBm
0 . . 0 1 –16 + 0.45dBm
0 . . 1 0 –16 + 0.90dBm
. . . . . .
05669-044
. . . . . .
1 1 . 1 1 13dBm
Figure 44.
Notes
1. FSTEP = PFD/214.
2. PA bias default = 9 µA.
REGISTER 2—TRANSMIT MODULATION REGISTER (GFSK/GOOK MODE)
UNTIL LOCK
COUNTER
MUTE PA
ENABLE
TxDATA
INVERT
INDEX GFSK MOD MODULATION ADDRESS
PA
DB11
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB9
DB8
DB7
DB6
DB5
DB4
C4 (0) DB3
C3 (0) DB2
C2 (1) DB1
C1 (0) DB0
MC3
MC2
MC1
MP1
PA2
PA1
PE1
DI1
IC2
IC1
D9
D8
D7
D6
D5
D4
D3
D2
D1
P6
P5
P4
P3
P2
P1
S3
S2
S1
D7 ... D3 D2 D1 DIVIDER_FACTOR PE1 POWER AMPLIFIER
0 ... 0 0 0 INVALID 0 OFF
0 ... 0 0 1 1 1 ON
0 ... 0 1 0 2
0 ... 0 1 1 3
. ... . . . .
MUTE PA UNTIL
DI1 1 ... 1 1 1 127
MP1 LOCK DETECT HIGH
0 TxDATA 0 OFF
1 TxDATA 1 ON
PA2 PA1 PA BIAS GAUSSIAN – OOK S3 S2 S1 MODULATION SCHEME

D9 D8 MODE
0 0 5µA 0 0 0 FSK
0 1 7µA 0 0 NORMAL MODE 0 0 1 GFSK
1 0 9µA 0 1 OUTPUT BUFFER ON 0 1 0 ASK
1 1 11µA 1 0 BLEED CURRENT ON 0 1 1 OOK
1 1 BLEED/BUFFER ON 1 1 1 GOOK
IC2 IC1 INDEX_COUNTER

0 0 16 POWER AMPLIFIER OUTPUT LEVEL
0 1 32 P6 . . P2 P1
1 0 64
0 . . X X PA OFF
1 1 128
0 . . 0 0 –16.0dBm
0 . . 0 1 –16 + 0.45dBm
0 . . 1 0 –16 + 0.90dBm
. . . . . .
MC3 MC2 MC1 GFSK_MOD_CONTROL . . . . . .
1 1 . 1 1 13dBm
0 0 0 0
0 0 1 1
05669-045
. . . .
1 1 1 7
Figure 45.
Notes
1. GFSK_DEVIATION = (2GFSK_MOD_CONTROL × PFD)/212.
2. Data rate = PFD/(INDEX_COUNTER × DIVIDER_FACTOR).
3. PA bias default = 9 µA.
REGISTER 3—RECEIVER CLOCK REGISTER
CLOCK DIVIDE
CLOCK DIVIDE
BB OFFSET
DEMOD
ADDRESS
SEQUENCER CLOCK DIVIDE CDR CLOCK DIVIDE BITS
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C4(0)
C3(0)
C2(1)
C1(1)
OK2
OK1
BK2
BK1
SK8
SK7
SK6
SK5
SK4
SK3
SK2
SK1
FS8
FS7
FS6
FS5
FS4
FS3
FS2
FS1
SK8 SK7 ... SK3 SK2 SK1 SEQ_CLK_DIVIDE BK2 BK1 BBOS_CLK_DIVIDE
0 0 ... 0 0 1 1 0 0 4
0 0 ... 0 1 0 2 0 1 8
. . ... . . . . 1 x 16
1 1 ... 1 1 0 254
1 1 ... 1 1 1 255
OK2 OK1 DEMOD_CLK_DIVIDE
0 0 4
0 1 1
1 0 2
1 1 3
FS8 FS7 ... FS3 FS2 FS1 CDR_CLK_DIVIDE

0 0 ... 0 0 1 1
0 0 ... 0 1 0 2
. . ... . . . .
05669-046
1 1 ... 1 1 0 254
1 1 ... 1 1 1 255
Figure 46.
Notes
1. Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where
XTAL
BBOS _ CLK =
BBOS _ CLK _ DIVIDE .
2. The demodulator clock (DEMOD_CLK) must be <12 MHz for FSK and <6 MHz for ASK, where
XTAL
DEMOD _ CLK = .
DEMOD _ CLK _ DIVIDE
3. Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 × data rate), where
DEMOD _ CLK
CDR _ CLK = .
CDR _ CLK _ DIVIDE
Note that this might affect your choice of XTAL, depending on the desired data rate.
4. The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz for FSK and close to
40 kHz for ASK:
XTAL
SEQ _ CLK = .
SEQ _ CLK _ DIVIDE
REGISTER 4—DEMODULATOR SET-UP REGISTER
DB24 SYNC WORD MATCH

DEMOD LOCK/
SELECT
DEMOD
ADDRESS
DEMODULATOR LOCK SETTING POSTDEMODULATOR BW BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DW10 DB15
DW9 DB14
DW8 DB13
DW7 DB12
DW6 DB11
DW5 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C4(0)
C3(1)
C2(0)
C1(0)
DW4
DW3
DW2
DW1
LM2
LM1
DS2
DS1
DL8
DL7
DL6
DL5
DL4
DL3
DL2
DL1
DEMODULATOR
DS2 DS1 TYPE
0 0 LINEAR DEMODULATOR
0 1 CORRELATOR/DEMODULATOR
1 0 ASK/OOK
1 1 INVALID
DEMOD MODE LM2 LM1 DL8 DEMOD LOCK/SYNC WORD MATCH INT/LOCK PIN
0 0 0 0 SERIAL PORT CONTROL—FREE RUNNING –
1 0 0 1 SERIAL PORT CONTROL—LOCK THRESHOLD –
2 0 1 0 SYNC WORD DETECT—FREE RUNNING OUTPUT
3 0 1 1 SYNC WORD DETECT—LOCK THRESHOLD OUTPUT
4 1 0 X INTERRUPT/LOCK PIN LOCKS THRESHOLD INPUT
5 1 1 DL8 DEMOD LOCKED AFTER DL8–DL1 BITS –
MODE5 ONLY
DL8 DL7 ... DL3 DL2 DL1 LOCK_THRESHOLD_TIMEOUT

0 0 ... 0 0 0 0
0 0 ... 0 0 1 1
0 0 ... 0 1 0 2
. . ... . . . .
05669-047
1 1 ... 1 1 0 254
1 1 ... 1 1 1 255
Figure 47.
Notes
1. Demodulator Modes 1, 3, 4, and 5 are modes that can be activated to allow the ADF7020-1 to demodulate data-encoding schemes
that have run-length constraints greater than 7.
2. Post_Demod_BW = 211 π FCUTOFF/DEMOD_CLK, where the cutoff frequency (FCUTOFF) of the postdemodulator filter should typically
be 0.75 times the data rate.
3. For Mode 5, the timeout delay to lock threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK, where SEQ_CLK is defined in the
Register 3—Receiver Clock Register section.
REGISTER 5—SYNC BYTE REGISTER
TOLERANCE
SYNC BYTE
MATCHING
LENGTH
CONTROL
SYNC BYTE SEQUENCE BITS
DB11
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C4(0)
C3(1)
C2(0)
C1(1)
MT2
MT1
PL2
PL1
SYNC BYTE
PL2 PL1 LENGTH
0 0 12 BITS
0 1 16 BITS
1 0 20 BITS
1 1 24 BITS
MATCHING
MT2 MT1 TOLERANCE
0 0 0 ERRORS
0 1 1 ERROR
05669-048
1 0 2 ERRORS
1 1 3 ERRORS
Figure 48.
Notes
1. Sync byte detect is enabled by programming Bits R4_DB (25:23) to [010] or [011].
2. This register allows a 24-bit sync byte sequence to be stored internally. If the sync byte detect mode is selected, the INT/LOCK pin
goes high when the sync byte is detected in Rx mode. Once the sync word detect signal goes high, it goes low again after nine data bits.
3. The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte
detection hardware.
4. Choose a sync byte pattern that has good autocorrelation properties, for example, an unequal amount of digital 1s and 0s.
REGISTER 6—CORRELATOR/DEMODULATOR REGISTER
LNA MODE
LINEARITY
PRODUCT
CURRENT
IF FILTER
RxDATA
INVERT
MIXER
Rx ADDRESS
DOT
CAL
LNA
RESET IF FILTER DIVIDER DISCRIMINATOR BW BITS
DB11
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
TD10 DB13
DB12
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C4(0)
C3(1)
C2(1)
C1(0)
CA1
ML1
LG1
DP1
FC9
FC8
FC7
FC6
FC5
FC4
FC3
FC2
FC1
TD9
TD8
TD7
TD6
TD5
TD4
TD3
TD2
TD1
RI1
LI2
LI1
CA1 FILTER CAL DP1 DOT PRODUCT
DEMOD
0 NO CAL 0 CROSS PRODUCT
RESET
1 CALIBRATE 1 DOT PRODUCT
CDR
ML1 MIXER LINEARITY LG1 LNA MODE
RESET
0 DEFAULT 0 DEFAULT
RxDATA 1 HIGH 1 REDUCED GAIN
RI1 INVERT
0 RxDATA LI2 LI1 LNA BIAS
1 RxDATA 0 0 800µA (DEFAULT)
FILTER CLOCK
FC9 . FC6 FC5 FC4 FC3 FC2 FC1 DIVIDE RATIO
0 . 0 0 0 0 0 1 1
0 . 0 0 0 0 1 0 2
. . . . . . . . .
. . . . . . . . .
. . . . . . . . .
05669-049
. . . . . . . . .
1 . 1 1 1 1 1 1 511
Figure 49.
Notes
1. See the FSK Correlator/Demodulator section for an example of how to determine register settings.
2. Nonadherence to correlator programming guidelines results in poorer sensitivity.
3. The filter clock is used to calibrate the IF filter. The filter clock divide ratio should be adjusted so that the frequency is 50 kHz. The
formula is XTAL/FILTER_CLOCK_DIVIDE.
4. The filter should be calibrated only when the crystal oscillator is settled. The filter calibration is initiated every time Bit R6_DB19 is
set high.
5. Discriminator_BW = (DEMOD_CLK × K)/(800 × 103). See the FSK Correlator/Demodulator section.
Maximum value = 600.
6. When LNA Mode = 1 (reduced gain mode), this prevents the Rx from selecting the highest LNA gain setting. This might be used
when linearity is a concern. See Table 6 for details of the Rx modes.
REGISTER 7—READBACK SET-UP REGISTER
READBACK ADC CONTROL

SELECT MODE BITS
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RB3 RB2 RB1 AD2 AD1 C4(0) C3(1) C2(1) C1(1)
RB3 READBACK AD2 AD1 ADC MODE

0 DISABLED 0 0 MEASURE RSSI
1 ENABLED 0 1 BATTERY VOLTAGE
1 0 TEMP SENSOR
1 1 TO EXTERNAL PIN
RB2 RB1 READBACK MODE
0 0 AFC WORD
0 1 ADC OUTPUT
05669-050
1 0 FILTER CAL
1 1 SILICON REV
Figure 50.
Notes
1. Readback of the measured RSSI value is valid only in Rx mode. To enable readback of the battery voltage, the temperature sensor, or
the voltage at the external pin in Rx mode, users must disable the AGC function in Register 9. To read back these parameters in Tx
mode, users must first power up the ADC using Register 8, because it is off by default in Tx mode to save power. This is the
recommended method of using the battery readback function since most configurations typically require use of the AGC function.
2. Readback of the AFC word is valid in Rx mode only if either the linear demodulator or the correlator/demodulator is active.
3. See the Readback Format section for more information.
REGISTER 8—POWER-DOWN TEST REGISTER
SWITCH ENABLE
INTERNAL Tx/Rx
PA ENABLE
LNA/MIXER
Rx MODE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
DEMOD
FILTER
SYNTH
LOG AMP/ CONTROL
ADC
VCO
RSSI BITS
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PD7 SW1 LR2 LR1 PD6 PD5 PD4 PD3 PD2 PD1 C4(1) C3(0) C2(0) C1(0)
PD7 PA (Rx MODE) PLE1 LOOP

0 PA OFF (FROM REG 0) PD2 PD1 CONDITION
1 PA ON 0 0 0 VCO/PLL OFF
0 0 1 PLL ON
0 1 0 VCO ON
SW1 Tx/Rx SWITCH 0 1 1 PLL/VCO ON
0 DEFAULT (ON) 1 X X PLL/VCO ON
1 OFF
LR2 LR1 RSSI MODE PD3 LNA/MIXER ENABLE

X 0 RSSI OFF 0 LNA/MIXER OFF
X 1 RSSI ON 1 LNA/MIXER ON
PD6 DEMOD ENABLE PD4 FILTER ENABLE

0 DEMOD OFF 0 FILTER OFF
1 DEMOD ON 1 FILTER ON
PD5 ADC ENABLE
05669-051
0 ADC OFF
1 ADC ON
Figure 51.
Notes
1. For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition.
2. It is not necessary to write to this register under normal operating conditions.
REGISTER 9—AGC REGISTER
CONTROL
CURRENT
SEARCH
FILTER
DIGITAL FILTER LNA ADDRESS
GAIN
AGC
TEST IQ GAIN GAIN AGC HIGH THRESHOLD AGC LOW THRESHOLD BITS
DB11
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C4(1)
C3(0)
C2(0)
C1(1)
GC1
GH7
GH6
GH5
GH4
GH3
GH2
GH1
GS1
FG2
FG1
LG2
LG1
GL7
GL6
GL5
GL4
GL3
GL2
GL1
FI1
FI1 FILTER CURRENT GS1 AGC SEARCH AGC LOW
GL7 GL6 GL5 GL4 GL3 GL2 GL1 THRESHOLD
0 LOW 0 AUTO AGC
1 HIGH 1 HOLD SETTING 0 0 0 0 0 0 1 1
0 0 0 0 0 1 0 2
0 0 0 0 0 1 1 3
FG2 FG1 FILTER GAIN GC1 GAIN CONTROL 0 0 0 0 1 0 0 4
0 0 8 0 AUTO . . . . . . . .
0 1 24 1 USER . . . . . . . .
1 0 72 . . . . . . . .
1 1 INVALID 1 1 1 1 1 0 1 61
1 1 1 1 1 1 0 62
1 1 1 1 1 1 1 63
RSSI LEVEL
GH7 GH6 GH5 GH4 GH3 GH2 GH1 CODE
0 0 0 0 0 0 1 1
0 0 0 0 0 1 0 2
0 0 0 0 0 1 1 3
LG2 LG1 LNA GAIN 0 0 0 0 1 0 0 4
0 0 <1 . . . . . . . .
0 1 3 . . . . . . . .
1 0 10 . . . . . . . .
1 1 30 1 0 0 1 1 1 0 78
05669-052
1 0 0 1 1 1 1 79
1 0 1 0 0 0 0 80
Figure 52.
Notes
1. Default AGC_LOW_THRESHOLD = 30, default AGC_HIGH_THRESHOLD = 70. See the RSSI/AGC for details.
2. AGC high and low settings must be more than 30 settings apart to ensure correct operation.
3. LNA gain of 30 is available only if the LNA mode bit, R6_DB15, is set to 0.
REGISTER 10—AGC 2 REGISTER
RESERVED
UP/DOWN
SELECT
SELECT
I/Q I/Q PHASE ADDRESS
I/Q
ADJUST I/Q GAIN ADJUST AGC DELAY LEAK FACTOR PEAK RESPONSE BITS
DB11
DB31
DB30
DB29
SIQ2 DB28
DB27
DB26
DB25
DB24
DB23
SIQ1 DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB9
DB8
DB7
DB6
DB5
DB4
C4 (1) DB3
C3 (0) DB2
C2 (1) DB1
C1 (0) DB0
GC5
GC4
GC3
GC2
GC1
UD1
DH4
DH3
DH2
DH1
PH4
PH3
PH2
PH1
PR4
PR3
PR2
PR1
GL7
GL6
GL5
GL4
R1
SIQ2 SELECT IQ SIQ2 SELECT IQ DEFAULT = 0xA
05669-053
0 PHASE TO I CHANNEL 0 GAIN TO I CHANNEL
1 PHASE TO Q CHANNEL 1 GAIN TO Q CHANNEL DEFAULT = 0xA DEFAULT = 0x2
Figure 53.
Notes
1. This register is not used under normal operating conditions.
REGISTER 11—AFC REGISTER

DB20 AFC ENABLE
CONTROL
AFC SCALING COEFFICIENT BITS
DB11
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C4(0)
C3(0)
C2(1)
C1(0)
M11
AE1
M16
M15
M14
M13
M12
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
INTERNAL
AE1 AFC
05669-054
0 OFF
1 ON
Figure 54.
Notes
1. See the Internal AFC section to program AFC scaling coefficient bits.
2. The AFC scaling coefficient bits can be programmed using the following formula:
AFC_Scaling_Coefficient = Round((500 × 224)/XTAL).
REGISTER 12—TEST REGISTER
DB31 PRESCALER
OSC TEST
COUNTER
SOURCE
LD HIGH
RESET
FORCE
ANALOG TEST DIGITAL Σ-∆ ADDRESS
MUX IMAGE FILTER ADJUST TEST MODES TEST MODES PLL TEST MODES BITS
DB11
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C4(1)
C3(1)
C2(0)
C1(0)
PRE
QT1
CS1
SF6
SF5
SF4
SF3
SF2
SF1
T9
T8
T7
T6
T5
T4
T3
T2
T1
P PRESCALER DEFAULT = 32. INCREASE CR1 COUNTER RESET
NUMBER TO INCREASE BW
0 4/5 (DEFAULT) 0 DEFAULT
IF USER CAL ON
1 8/9 1 RESET
CS1 CAL SOURCE
05669-055
0 INTERNAL
1 SERIAL IF BW CAL
Figure 55.
Using the Test DAC on the ADF7020-1 to Implement Programming the test register, Register 12, enables the test
Analog FM Demodulation and Measuring of SNR DAC. In correlator mode, this can be done by writing Digital
The test DAC allows the output of the postdemodulator filter Test Mode 7 or 0x0001C00C.
for both the linear and correlator/demodulators (Figure 31 and To view the test DAC output when using the linear demodulator,
Figure 32) to be viewed externally. It takes the 16-bit filter the user must remove a fixed offset term from the signal using
output and converts it to a high frequency, single-bit output Register 13. This offset is nominally equal to the IF frequency.
using a second-order error feedback Σ-Δ converter. The output The user can determine the value to program by using the
can be viewed on the CLKOUT pin. This signal, when IF frequency error readback to determine the actual IF and then
filtered appropriately, can then be used to programming half this value into the offset removal field. It also
• Monitor the signals at the FSK/ASK postdemodulator filter has a signal gain term to allow the usage of the maximum dynamic
output. This allows the demodulator output SNR to be range of the DAC.
measured. Eye diagrams can also be constructed of the Setting Up the Test DAC
received bit stream to measure the received signal quality. • Digital test modes = 7: enables the test DAC, with no
• Provide analog FM demodulation. offset removal (0x0001 C00C).
While the correlators and filters are clocked by DEMOD_CLK, • Digital test modes = 10: enables the test DAC, with
CDR_CLK clocks the test DAC. Note that, although the test offset removal (needed for linear demod only, 0x02 800C).
DAC functions in a regular user mode, the best performance is The output of the active demodulator drives the DAC; that is, if
achieved when the CDR_CLK is increased up to or above the the FSK correlator/demodulator is selected, the correlator filter
frequency of DEMOD_CLK. The CDR block does not function output drives the DAC.
when this condition exists.
REGISTER 13—OFFSET REMOVAL AND SIGNAL GAIN REGISTER
PULSE CONTROL
TEST DAC GAIN TEST DAC OFFSET REMOVAL EXTENSION KI KP BITS
DB11
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C4(1)
C3(1)
C2(0)
C1(1)
PE4
PE3
PE2
PE1
PE4 PE3 PE2 PE1 PULSE EXTENSION
0 0 0 0 NORMAL PULSE WIDTH
0 0 0 1 2 × PULSE WIDTH
. . . . .
. . . . .
05669-056
. . . . .
Figure 56.
Notes
1. Because the linear demodulator’s output is proportional to frequency, it usually consists of an offset combined with a relatively low
signal. Up to a maximum of a 300 kHz offset can be removed and gained to use the full dynamic range of the DAC:
DAC_input = (2Test_DAC_Gain) × (Signal − Test_DAC_Offset_Removal/4096).
OUTLINE DIMENSIONS
7.00 0.30
BSC SQ 0.23
PIN 1 0.18 PIN 1
INDICATOR INDICATOR
37 48
36 1
0.50
BSC EXPOSED 4.25
PAD
4.10 SQ
3.95
25 12
24 13
0.45 0.20 MIN
TOP VIEW BOTTOM VIEW
0.40
0.35 FOR PROPER CONNECTION OF
0.80 THE EXPOSED PAD, REFER TO
0.75 THE PIN CONFIGURATION AND
0.05 MAX FUNCTION DESCRIPTIONS
0.70 SECTION OF THIS DATA SHEET.
0.02 NOM
COPLANARITY
0.08
SEATING 0.20 REF
08-16-2010-B
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.
Figure 57. 48-Lead Lead Frame Chip Scale Package [LFCSP]

7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
ADF7020-1BCPZ −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-5
ADF7020-1BCPZ-RL −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-5
ADF7020-1BCPZ-RL7 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-5
EVAL-ADF7020-1DBZ4 400 MHz to 435 MHz Daughter Board
1
Z = RoHS-Compliant Part.
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D05669–0–1/18(A)

High Performance FSK/ASK Transceiver IC: Data Sheet

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High Performance FSK/ASK Transceiver IC: Data Sheet

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High Performance

FUNCTIONAL BLOCK DIAGRAM

RLNA POLARIZATION LDO(1:4) TEMP TEST MUX

L1 L2 VCOIN CPOUT OSC1 OSC2 CLKOUT

Rev. A Document Feedback

Typical Performance Characteristics ........................................... 13 Register 2—Transmit Modulation Register (GFSK/GOOK

12/2005—Revision 0: Initial Version

Programmable Step Size

performance as seen at the PA output: –198 + 10 log(fPFD) + 20 log N.

DB1 DB0 (LSB)

Figure 2. Serial Interface Timing Diagram

SREAD X RV16 RV15 RV2 RV1

Figure 3. Readback Timing Diagram

Figure 5. TxData/TxCLK Timing Diagram

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 6. Pin Configuration

Table 4. Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS

–45 150kHz FILTER BW LgAv

–350 –250 –150 –50 50 150 250 350 450 550

1kHz FREQUENCY OFFSET 10MHz RF I/P LEVEL (dBm)

–95 CORRELATION LINEAR AFC ON

–120 –100 –80 –60 –40 –20 0 20

DIVIDER Figure 21. MUXOUT Circuit

Digital Lock Detect

Voltage Regulators N Counter

The combination of the integer-N (maximum = 255) and the

less than the LBW.

500 The occurrence of beat-note spurs is rare, because the integer

250 values in the fractional register. By having a channel 1 MHz

VCO Bias Current

Table 5. Recommended VCO Bias Currents

LOOP FILTER VCO ÷2 MUX TO PA

VCO SELECT BIT

Figure 25. Voltage Controlled Oscillator (VCO)

 FSK/GFSK: The output power is set using bits MODULATION SCHEMES

Figure 27. PA Configuration in ASK/OOK Mode

LNA/MIXER ENABLE Once initiated by setting Bit R6_DB19, the calibration is

Table 6. LNA/Mixer Modes

take an accurate RSSI measurement is typically 150 µs, although I IF Rx DATA

appropriate parameters. DB(8:15)

Table 12. Minimum Register Writes Required for Tx/Rx Setup

Figure 38. Rx Programming Sequence and Timing Diagram

Table 13. Power-Up Sequence Description

REG. WR0 WR1 WR2 TxDATA TIME

Figure 39. Tx Programming Sequence and Timing Diagram

READBACK MODE READBACK VALUE

Figure 40. Readback Value Table

IC2 IC1 MC3 MC2 MC1 0 OFF

PA2 PA1 PA BIAS S3 S2 S1 MODULATION SCHEME

IC2 IC1 MC3 MC2 MC1 0 OFF

POWER AMPLIFIER OUTPUT LEVEL

INDEX GFSK MOD MODULATION ADDRESS

PA2 PA1 PA BIAS GAUSSIAN – OOK S3 S2 S1 MODULATION SCHEME

IC2 IC1 INDEX_COUNTER

FS8 FS7 ... FS3 FS2 FS1 CDR_CLK_DIVIDE

DB24 SYNC WORD MATCH

DL8 DL7 ... DL3 DL2 DL1 LOCK_THRESHOLD_TIMEOUT