Codesign: Introduction

DAMERGI Emir
INSAT 2016/17
INTRODUCTION:

 Many terms related to embedded systems:

- GPP, DSP, ASIP, SPP, SOC, ASIC, FPGA, SISD, SIMD,
CISC, RISC, etc..

Many terms related to embedded systems:

- GPP, DSP, ASIP, ASIC, FPGA, SISD, SIMD, etc..

DAMERGI Emir – INSAT 2017/18 2

INTRODUCTION

Problem Solution:
- Algorithms
(Scientific or Industrial) - Mathematical computing

Processing

Software approach Dedicated Hardware

(standard Hardware: Processor)

Design of a tailord HW
Processor GPP SPP « Single
DSP Purpose Processor »
ASIP
DAMERGI Emir – INSAT 2017/18 3
Dedicated Hardware (SPP)

Finite State Machines

Algorithm
Truth/Transition Tables

SPP: DataPath + control Program

(VHDL, Verilog)

SPP: Single Purpose Processor

DAMERGI Emir – INSAT 2017/18

 Dedicated Hardware (SPP)

Memory
Data
Inputs Data
Outputs

Control DataPath
Predifiend
control Unit
sequence

DAMERGI Emir – INSAT 2017/18

Software approach

Target Platform (Processor) Algorithm

chosen according to the
application constraints:
(GPP, DSP, ASIP)

GPP: General Purpose Processor

Program (C, C++, ASM, …)
memory
Processing
Unit
(Control
+ Binary File
DataPath)

DAMERGI Emir – INSAT 2017/18

 Software approach: Processing Unit

Memory
Instructi Data
ons Inputs Data
Outputs

Control DataPath (ALU)

Control sequence
Unit
depends on
Instructions

Code and Data are placed generally in different memories:

• RAM: Data variables.
• Flash: Code and Data constants
DAMERGI Emir – INSAT 2017/18
Software approach: Processing Unit
• When Instructions and Data are fetched through the same Bus (Data Bus)
 Von Neuman Architecture

Memory
Control DataPath (ALU)
Unit Code
(Instructions)

Address Bus

Data
C D
O A
D T
E A
Data Bus (Data + Code)

DAMERGI Emir – INSAT 2017/18

Software approach: Processing Unit
• When Instructions and Data are fetched through 2 differents Buses:
 HARVARD Architecture

Memory Memory
Control DataPath (ALU)
Code Data
(Instructions) Unit

Address Address
Bus Bus

C D
O A
D T
E A
Code Data

DAMERGI Emir – INSAT 2017/18

Selection Criteria

Criteria 1: (FC = Final Cost per Product)

NRE NRE: Non Recurrent Engineering

FC   UC Cost
Q : Quantity
Q
UC: Unit Cost

Criteria 2 : Time To Market

On-Time Peak
Revenues (R)
Delayed Peak
R (P-D)/P

Product Release Temps

0 D P 2P
Delay
DAMERGI Emir – INSAT 2017/18
Selection Criteria

Criteria 3 : Performance

• Number of executed Instructions (resp Floating Operations) per

time unit for 1Mhz Clock Frequency : MIPS/MHz (resp.
MFLOPS/MHz)
• Clock Frequency
 Absolute Performance = Clock Frequency * MIPS/Mhz
• Memory Access Bandwidth (Octets/sec)

ARM Cortex-M0 0.9 MIPS/MHz

ARM Cortex-M3/M4 1.25 MIPS/MHz
ARM Cortex-A5 1.57 MIPS/MHz
ARM Cortex-A7 1.9 MIPS/MHz

DAMERGI Emir – INSAT 2017/18

Selection Criteria

Criteria 4 : Power (Energy Consumption)

• Power is expressed in Watt [W]

• Energy is expressed in Joule [J] = Power * Time

Consequences on:
• Battery Lifetime (Ah)  Autonomy
• Heat dissipation  System size and weight

Examples:
PCs: Tens of WATTs
SmartPhones: Watts
MCU: microWatts  MilliWatts

DAMERGI Emir – INSAT 2017/18

Selection Criteria

Criteria 5 : Flexibility

How hard it is to make the system evolve or to change

completely his behavior?

DAMERGI Emir – INSAT 2017/18

Example
The expression of the form

Is present in a large number of mathematical models

Convolution (Filter): y(k) =

Correlation: c(m)=

Matrix computation

DAMERGI Emir – INSAT 2017/18 14

Example : Execution on GPP
)+ )+ )+( Memory
Ri a0
Rj  x3
Control
Processing Rres= Rj* Ri
Unit
Unit Rk  Rres
Ri Rj Rk Ri a1
Rj  x2
UAL Rres = Rj* Ri
(+,*,-,/, ..) Ri  Rres

Acc Rres= Rj + Rk +
Rk  Rres
……
…….
……
…… + +

+ + +

DAMERGI Emir – INSAT 2017/18 15

 Example : Execution on GPP
instructions Memory
Ri  a 0
22 instructions:
Rj  x3
4
Rres = Rj* Ri
- 22 instr. fetching from Memory
Rk  Rres
Ri  a 1 - 8 Mem to reg transfers
Rj  x2
4
Rres = Rj* Ri - 7 Reg to Reg transfers
Ri  Rres
- 4 Multiplications
Rres = Rj + Rk +
2
Rk  Rres - 4 additions
……
4 …….
……
2 …… + +

4
2 + + +

DAMERGI Emir – INSAT 2017/18 16

Example : Execution on Dedicated Hardware
)+ )+ )+(

Memory (only data, No instruction) - 8 Mem to reg transfers

a0 , a1, a2, a3
(Parallel)
x0, x1, x2, x3
- 4 (2 Terms) Multiplication
Control
(executed in parallel)
Unit

- 1 (4 Terms) Addition

* * * *

DAMERGI Emir – INSAT 2017/18

Example: Performance

GPP Dedicated Hardware

- 22 Instr. Fetch Cycles - 0

- 8 Mem to reg transfer Cycles - 1 Mem to reg transfer Cycle

- 7 Reg to Reg transfer Cycles - 0

- 4 Multiplication Cycles - 1 Multiplication Cycle

- 4 addition Cycles - 1 addition Cycle

--- +++

DAMERGI Emir – INSAT 2017/18 18

Example: Energy

GPP Dedicated Hardware

- 22 Instr. Fetch - 0

- 8 Mem to reg transfers - 8 Mem to reg transfers

- 7 Reg to Reg Transfers - 0

- 4 Multiplications - 4 Multiplications

- 4 additions - 4 additions

--- +++
Furthermore, the GPP controller is more complex and consumes more energy

DAMERGI Emir – INSAT 2017/18 19

Example: Flexibility/Time To market

change the processing to:

GPP Dedicated Hardware

- Very easy: Rewrite the software - Impossible: A new HW design

and compile must be realized

+++ ---

DAMERGI Emir – INSAT 2017/18 20

Example: Criteria comparison
Best ( +++ ) Software Approach
Flexibility / Time To Market

GPP

Dedicated HW (SPP)

SPP

Performance / Power Best ( +++ )

DAMERGI Emir – INSAT 2017/18 21

Example: Tradeoff GPP/SPP

A Trade off between Flexibility and Performance ?

Instructions Specialized
(Processor) Hardware

A Processor with and Specialized Datapath (ALU)

DAMERGI Emir – INSAT 2017/18

Example: Trade off GPP/SPP

Memory
Instructi Data
ons Data
Inputs Outputs

A Instruction processor
Control Specialized DataPath (ALU)
Unit with support:
- Hardwired Application
Specific instructions
- Parallelization

DAMERGI Emir – INSAT 2017/18

Example : trade off GPP/SPP

Multiple ALUs
Processing Unit
Parallel procesing
Ri Rj Rk Rl
MAC : Multiply ACcumulate
Control Unit

ALU ALU
SIMD: Single Instruction Multiple Data

ADD
With 2 ALUs: and 1 MAC Unit
ACC
ACC  ACC + (Ri * Rj + Rk * Rl)

DAMERGI Emir – INSAT 2017/18

Example : trade off GPP/SPP
( ∗ )+( ∗ )+( ∗ )+( ∗ )
Memory
Ri  a 0
Processing Unit Rj  x3

Ri Rj Rk Rl Rk  a 1
Rl  x2
Control Unit

ACCACC+ a0 x3+ a1x2

ALU ALU Ri  a 2
Rj  x1
Rk  a 3
ADD
Rl  x0
ACCACC+ a0 x3+ a1x2
ACC ……
…….
……

25
DAMERGI Emir – INSAT 2017/18
Example : Trade off GPP/SPP
( ∗ )+( ∗ )+( ∗ )+( ∗ )

Memory
Ri a0 10 instructions:
Rj  x3
Rk a1
- 10 instr. fetching from Memory
Rl  x2
- 8 Mem to reg transfers
ACC a0 x3+ a1x2

Ri a2 - 2 MAC operation

Rj  x1 • 2*2 Multiplications
Rk a3
• 2*1 additions
Rl  x0
ACCACC+ a0 x3+ a1x2
……
…….
……

DAMERGI Emir – INSAT 2017/18

26
 Example : Trade off GPP/SPP

Processing Unit The number of ALUs can be

Registers (Data) higher (4, 8, 16 , …)

Control Unit

All ALUs are controlled by

ALU ALU …… ALU the same ctrl signal
 All ALUs execute the
same Instruction

SIMD Architecture: Single Instruction Multiple Data

SIMD Architecture + MAC are found in DSP (Digital Signal Processors)

DAMERGI Emir – INSAT 2017/18

Example: Criteria comparison
Best ( +++ ) Software Approach

GPP
Flexibility / Time To Market

DSP

Dedicated HW (SPP)

SPP

Performance / Power Best ( +++ )

DAMERGI Emir – INSAT 2017/18 28

Flynn Taxonomy:

SISD Architecture: Single SIMD Architecture: Single

Instruction Single Data Instruction Multiple Data
(Cortex-M3) (Cortex-M4)

PU: Processing Unit (ALU)

DAMERGI Emir – INSAT 2017/18

Flynn Taxonomy:

MISD Architecture: Single MIMD Architecture: Single

Instruction Single Data Instruction Multiple Data

PU: Processing Unit

DAMERGI Emir – INSAT 2017/18

What else

Memory • Deep Specialization of

Instruct Data
ions Inputs
Data the core (ALU)
Output
s
• Instruction set tailored
for a Specific Application
Control Application Specific
Unit DataPath (ALU)

ASIP
Application Specific
Instruction Processor

DAMERGI Emir – INSAT 2017/18

Example: Criteria comparison
Best ( +++ ) Software Approach

GPP
Flexibility / Time To Market

DSP

ASIP Dedicated HW (SPP)

SPP

Performance / Power Best ( +++ )

DAMERGI Emir – INSAT 2017/18 32

SPP: Implementation
SPP

on silicon: Transisitors on FPGA: Logic Blocks

Fixed Architecture (HW) Programmable Architecture (HW)

ASIC: Application Specific SPP on FPGA

Integrated Circuit

DAMERGI Emir – INSAT 2017/18 33

Example: Criteria comparison
Best ( +++ ) Software Approach

GPP
Flexibility / Time To Market

DSP
Dedicated HW (SPP)
ASIP
SPP
on
FPGA ASIC

Performance / Power Best ( +++ )

DAMERGI Emir – INSAT 2017/18 34

Choice dilemma
Smart Phone Satellite Receiver
• Flexibility: Update The
GUI, applications…

• Performance: Decryption,
Sound & image decoding,
3G/4G Communications...

GPP, DSP, ASIP, ASIC, FPGA ?

35
DAMERGI Emir – INSAT 2017/18
Choice dilemma : solution
Smart Phone Satellite Receiver
SPP
(HW )
GPP

SPP
(HW )

ASIP

FPGA

SOC: System On Chip

Choice of SOC components guided by the Application

 Single Purpose

36
DAMERGI Emir – INSAT 2017/18
SOCs: Set-top Box STi5518 OMEGA
ASIP, SPP, FPGA

Embedded processor (GPP)

37
DAMERGI Emir – INSAT 2017/18
SOCs: 4G SOC « Snapdragon »

ASIP

DSP

SPP
(ASIC, FPGA)

Embedded processor (GPP)

38
DAMERGI Emir – INSAT 2017/18
Example: Self Driving Car

• Video Stream
Decoding
• Image Processig
• Sensors Data
Processing
• Decision/Drive
• ….

HW / SW ?

39
DAMERGI Emir – INSAT 2017/18
HW/SW DESIGN: Classical Approach
Analysis of requirements and analysis
HW/SW Partitionnig (Manually)

HW Specs SW/HW Interface Specs SW Specs

HW Desc SW Desc (C,Java))

(VHDL)

SW Compilatiob
HW Synthesis

SW/HW Interfaces SW Modules

HW Components

Test/Verif Test/Verif Test/Verif

HW Tool Integration SW Tool

40
Test/Verif
DAMERGI Emir – INSAT 2017/18
HW/SW DESIGN: CODESIGN Approach
Analysis of Constraints
and Requirements

System Specs

System Desc (SystemC, C++ )

HW/SW
Partitioning

Hardware Descript. Software Descript. SW/HW

CoDesign
Software Gen.
HW Synth. Interface Synthesis
& Parameterization
Tool

Hardware HW/SW Software

Components Interfaces Modules

HW/SW Integration
and Cosimulation

Integrated
System 41
System Evaluation Design Verification
DAMERGI Emir – INSAT 2017/18