Stm8 Programming Manual

PM0044
Programming manual
STM8 CPU programming manual
Introduction
The STM8 family of HCMOS microcontrollers is designed and built around an enhanced
industry standard 8-bit core and a library of peripheral blocks, which include ROM, Flash,
RAM, EEPROM, I/O, Serial Interfaces (SPI, USART, I2C,...), 16-bit Timers, A/D converters,
comparators, power supervisors etc. These blocks may be assembled in various
combinations in order to provide cost-effective solutions for application-specific products.
The STM8 family forms a part of the STMicroelectronics 8-bit MCU product line, which finds
its place in a wide variety of applications such as automotive systems, remote controls,
video monitors, car radio and numerous other consumer, industrial, telecom, and multimedia
products.
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Contents PM0044
Contents
1 STM8 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 STM8 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 Enhanced STM8 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 STM8 core description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 STM8 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 Program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Memory interface architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 Pipelined execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 Description of pipelined execution stages . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.1 Fetch stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.2 Decoding and addressing stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.3 Execution stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 Data memory conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3 Pipelined execution examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4.1 Optimized pipeline example – execution from Flash Program memory . 24
5.4.2 Optimize pipeline example – execution from RAM . . . . . . . . . . . . . . . . 26
5.4.3 Pipeline with Call/Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4.4 Pipeline stalled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4.5 Pipeline with 1 wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6 STM8 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.1 Inherent addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2 Immediate addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3 Direct addressing mode (Short, Long, Extended) . . . . . . . . . . . . . . . . . . 34
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6.3.1 Short Direct addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.3.2 Long Direct addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3.3 Extended Direct addressing mode (only for CALLF and JPF) . . . . . . . . 38
6.4 Indexed addressing mode (No Offset, Short, SP, Long, Extended) . . . . . 39
6.4.1 No Offset Indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.4.2 Short Indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.4.3 SP Indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.4.4 Long Indexed addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.4.5 Extended Indexed (only LDF instruction) . . . . . . . . . . . . . . . . . . . . . . . . 44
6.5 Indirect (Short Pointer Long, Long Pointer Long) . . . . . . . . . . . . . . . . . . . 45
6.6 Short Pointer Indirect Long addressing mode . . . . . . . . . . . . . . . . . . . . . 46
6.7 Long Pointer Indirect Long addressing mode . . . . . . . . . . . . . . . . . . . . . . 47
6.8 Indirect Indexed (Short Pointer Long, Long Pointer Long,
Long Pointer Extended) addressing mode . . . . . . . . . . . . . . . . . . . . . . . . 48
6.9 Short Pointer Indirect Long Indexed addressing mode . . . . . . . . . . . . . . 49
6.10 Long Pointer Indirect Long Indexed addressing mode . . . . . . . . . . . . . . . 51
6.11 Long Pointer Indirect Extended Indexed addressing mode . . . . . . . . . . . 53
6.12 Relative Direct addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.13 Bit Direct (Long) addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.14 Bit Direct (Long) Relative addressing mode . . . . . . . . . . . . . . . . . . . . . . . 59
7 STM8 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.2.1 Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.2.2 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.2.3 Code condition bit value notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.2.4 Memory and addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.2.5 Operation code notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.3 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.4 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ADDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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BCCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
BCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
BCPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
BREAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
BRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
BSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
BTJF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
BTJT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
CALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
CALLF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
CALLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
CCF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
CLR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
CLRW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
CPW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
CPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
CPLW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
DEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
DECW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
DIVW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
EXG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
EXGW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
HALT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
INC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
INCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
INT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
IRET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
JP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
JPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
JRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
JRxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
LDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
LDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
MOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
MUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
NEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
NEGW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
POP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
POPW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
PUSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
PUSHW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
RCF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
RET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
RETF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
RIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
RLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
RLCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
RLWA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
RRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
RRCW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
RRWA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
RVF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SCF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
SLL/SLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SLLW/SLAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SRAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SRLW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
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SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SUBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SWAPW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
TNZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
TNZW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
TRAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
WFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
WFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
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List of tables
Table 1. Interruptability levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 2. Data/address decoding examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 3. Example with exact number of cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 4. Example with conventional number of cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5. Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 6. Optimized pipeline example - execution from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. Optimize pipeline example – execution from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 9. Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. Example of pipeline with Call/Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. Example of stalled pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 14. Pipeline with 1 wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15. Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 16. STM8 core addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 17. STM8 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 18. Inherent addressing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 19. Immediate addressing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 20. Overview of Direct addressing mode instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21. Available Long and Short Direct addressing mode instructions . . . . . . . . . . . . . . . . . . . . . 34
Table 22. Available Extended Direct addressing mode instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 23. Available Long Direct addressing mode instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 24. Overview Indexed addressing mode instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 25. No Offset, Long, Short and SP Indexed instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 26. No Offset, Long, Short Indexed Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 27. Extended Indexed Instructions only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 28. Overview of Indirect addressing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 29. Available Long Pointer Long and Short Pointer Long Indirect Instructions. . . . . . . . . . . . . 45
Table 30. Available Long Pointer Long Indirect Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 31. Overview of Indirect indexed instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 32. Available Long Pointer Long and Short Pointer Long Indirect
Indexed instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 33. Available Long Pointer Long Indirect Indexed instructions . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 34. Long Pointer Extended Indirect Indexed instructions instruction . . . . . . . . . . . . . . . . . . . . 48
Table 35. Overview of Relative Direct addressing mode instructions. . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 36. Available Relative Direct instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 37. Overview of Bit Direct addressing mode instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 38. Available Bit Direct instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 39. Overview of Bit Direct (Long) Relative addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 40. Available Bit Direct Relative instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 41. Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 42. Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 43. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Doc ID 13590 Rev 3 7/162

List of figures PM0044
List of figures
Figure 1. Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2. Context save/restore for interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. Address spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4. Memory Interface Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 5. Pipelined execution principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. Pipelined execution stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. Immediate addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 8. Short Direct addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 9. Long Direct addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 10. Far Direct addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 11. No Offset Indexed addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 12. Short Indexed - 8-bit offset - addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 13. SP Indexed - 8-bit offset - addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 14. Long Indexed - 16-bit offset - addressing mode example. . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 15. Far Indexed - 16-bit offset - addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16. Short Pointer Indirect Long addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 17. Long Pointer Indirect Long addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 18. Short Pointer Indirect Long Indexed addressing mode example . . . . . . . . . . . . . . . . . . . . 50
Figure 19. Long Pointer Indirect Long Indexed addressing mode example. . . . . . . . . . . . . . . . . . . . . 52
Figure 20. Long Pointer Indirect Extended Indexed addressing mode example . . . . . . . . . . . . . . . . . 54
Figure 21. Relative Direct addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 22. Bit Long Direct addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 23. Bit Long Direct Relative addressing mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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PM0044 STM8 architecture
1 STM8 architecture
The 8-bit STM8 Core is designed for high code efficiency. It contains 6 internal registers, 20
addressing modes and 80 instructions. The 6 internal registers include two 16-bit Index
registers, an 8-bit Accumulator, a 24-bit Program Counter, a 16-bit Stack Pointer and an 8-
bit Condition Code register. The two Index registers X and Y enable Indexed Addressing
modes with or without offset, along with read-modify-write type data manipulation. These
registers simplify branching routines and data/arrays modifications.
The 24-bit Program Counter is able to address up to 16-Mbyte of RAM, ROM or Flash
memory. The 16-bit Stack Pointer provides access to a 64K-level Stack. The Core also
includes a Condition Code register providing 7 Condition flags that indicate the result of the
last instruction executed.
The 20 Addressing modes, including Indirect Relative and Indexed addressing, allow
sophisticated branching routines or CASE-type functions. The Indexed Indirect Addressing
mode, for instance, permits look-up tables to be located anywhere in the address space,
thus enabling very flexible programming and compact C-based code. The stack pointer
relative addressing mode permits optimized C compiler stack model for local variables and
parameter passing.
The Instruction Set is 8-bit oriented with a 2-byte average instruction size. This Instruction
Set offers, in addition to standard data movement and logic/arithmetic functions, 8-bit by 8-
bit multiplication, 16-bit by 8-bit and 16-bit by 16-bit division, bit manipulation, data transfer
between Stack and Accumulator (Push / Pop) with direct stack access, as well as data
transfer using the X and Y registers or direct memory-to-memory transfers.
The number of Interrupt vectors can vary up to 32, and the interrupt priority level may be
managed by software providing hardware controlled nested capability. Some peripherals
include Direct Memory Access (DMA) between serial interfaces and memory. Support for
slow memories allows easy external code execution through serial or parallel interface
(ROMLESS products for instance).
The STM8 has a high energy-efficient architecture, based on a Harvard architecture and
pipelined execution. A 32-bit wide program memory bus allows most of the instructions to be
fetched in 1 CPU cycle. Moreover, as the average instruction length is 2 bytes, this allows for
a reduction in the power consumption by only accessing the program memory half of the
time, on average. The pipelined execution allowed the execution time to be minimized,
ensuring high system performance, when needed, together with the possibility to reduce the
overall energy consumption, by using different power saving operating modes. Power-saving
can be managed under program control by placing the device in SLOW, WAIT, SLOW-WAIT,
ACTIVE-HALT or HALT mode (see product datasheet for more details).
Doc ID 13590 Rev 3 9/162

STM8 architecture PM0044
Additional blocks
The additional blocks take the form of integrated hardware peripherals arranged around the
central processor core. The following (non-exhaustive) list details the features of some of the
currently available blocks:
Boot ROM Memory area containing the bootloader code

Flash Flash-based devices
RAM Sizes up to several Kbytes
Sizes up to several Kbytes. Erase/programming operations do not require
Data EEPROM
additional external power sources.
Different versions based on 8/16-bit free running or autoreload timer/counter are
available. They can be coupled with either input captures, output compares or
Timers PWM facilities. PWM functions can have software programmable duty cycle
between 0% to 100% in up to 256/65536 steps. The outputs can be filtered to
provide D/A conversion.
The Analog to Digital Converter uses a sample and hold technique. It has 12-bit
A/D converter
resolution.
Multi/master, single master, single slave modes, DMA or 1byte transfer, standard
I2C
and fast I2C modes, 7 and 10-bit addressing.
The Serial peripheral Interface is a fully synchronous 3/4 wire interface ideal for
SPI Master and Slave applications such as driving devices with input shift register
(LCD driver, external memory,...).
The USART is a fast synchronous/asynchronous interface which features both
USART duplex transmission, NRZ format, programmable baud rates and standard error
detection. The USART can also emulate RS232 protocol.
It has the ability to induce a full reset of the MCU if its counter counts down to
Watchdog zero prior to being reset by the software. This feature is especially useful in noisy
applications.
They are programmable by software to act in several input or output
I/O ports configurations on an individual line basis, including high current and interrupt
generation. The basic block has eight bit lines.
1.1 STM8 development support

The STM8 family of MCUs is supported by a comprehensive range of development tools.
This family presently comprises hardware tools (emulators, programmers), a software
package (assembler-linker, debugger, archiver) and a C-compiler development tool.
STM8 and ST7 CPUs are supported by a single toolchain allowing easy reuse and
portability of the applications between product lines.
10/162 Doc ID 13590 Rev 3

PM0044 STM8 architecture
1.2 Enhanced STM8 features

● 16-Mbyte linear program memory space with 3 FAR instructions (CALLF, RETF, JPF)
● 16-Mbyte linear data memory space with 1 FAR instruction (LDF)
● Up to 32 24-bit interrupt vectors with optimized context save management
● 16-bit Stack Pointer (SP=SH:S) with stack manipulation instructions and addressing
modes
● New register and memory access instructions (EXG, MOV)
● New arithmetic instructions: DIV 16/8 and DIVW 16/16
● New bit handling instructions (CCF, BCPL, BCCM)
● 2 x 16-bit index registers (X=XH:XL, Y=YH:YL). 8-bit data transfers address the low
byte. The high-byte is not affected, with a reset value of 0. This allows the use of X/Y as
8-bit values.
● Fast interrupt handling through alternate register files (up to 4 contexts) with standard
stack compatible mode (for real time OS kernels)
● 16-bit/8-bit stack operations (X, Y, A, CC stacking)
● 16-bit pointer direct update with 16-bit relative offset (ADDW/SUBW for X/Y/SP)
● 8-bit & 16-bit arithmetic and signed arithmetic support
Doc ID 13590 Rev 3 11/162

Glossary PM0044
2 Glossary
mnem mnemonic
src source
dst destination
cy duration of the instruction in CPU clock cycles (internal clock)
lgth length of the instruction in byte(s)
op-code instruction byte(s) implementation (1..4 bytes), operation code.
mem memory location
imm immediate value
off offset
ptr pointer
pos position
byte a byte
word 16-bit value
short represent a short 8-bit addressing mode
long represent a long 16-bit addressing mode
EA Effective Address: The final computed data byte address
Page Zero all data located at [00..FF] addressing space (single byte address)
(XX) content of a memory location XX
XX a byte value
ExtB Extended byte
MS Most Significant byte of a 16-bit value (MSB)
LS Least Significant byte of a 16-bit value (LSB)
A Accumulator register
X 16-bit X Index register
Y 16-bit Y Index register
reg A, XL or YL register (1-byte LS part of X/Y), XH or YH (1-byte MS part of X/Y)
ndx index register, either X or Y
PC 24-bit Program Counter register
SP 16-bit Stack Pointer
S Stack Pointer LSB
CC Condition Code register
12/162 Doc ID 13590 Rev 3

PM0044 STM8 core description
3 STM8 core description
3.1 Introduction
The CPU has a full 8-bit architecture, with 16-bit operations on index registers (for address
computation). Six internal registers allow efficient 8-bit data manipulation. The CPU is able
to execute 80 basic instructions. It features 20 addressing modes and can address 6 internal
registers and 16 Mbytes of memory/peripheral registers.
3.2 CPU registers

The 6 CPU registers are shown in the programming model in Figure 1. Following an
interrupt, the register context is saved. The context is saved by pushing registers onto the
stack in the order shown in Figure 2. They are popped from the stack in the reverse order.
Accumulator (A)
The accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations as well as data manipulations.
Index registers (X and Y)

These 16-bit registers are used to create effective addresses or as temporary storage area
for data manipulations. In most of the cases, the cross assembler generates a PRECODE
instruction (PRE) to indicate that the following instruction refers to the Y register. Both X and
Y are automatically saved on interrupt routine branch.
Program Counter (PC)

The program counter is a 24-bit register used to store the address of the next instruction to
be executed by the CPU. It is automatically refreshed after each processed instruction. As a
result, the STM8 core can access up to 16-Mbytes of memory.
Figure 1. Programming model

7 0
A ACCUMULATOR
15 8 7 0
XH XL X INDEX
15 8 7 0
YH YL Y INDEX
15 0
SP STACK POINTER
23 16 15 8 7 0
PCE PCH PCL PC PROGRAM COUNTER
7 0
V - I1 H I0 N Z C CC CODE CONDITION
Doc ID 13590 Rev 3 13/162

STM8 core description PM0044
Stack Pointer (SP)

The stack pointer is a 16-bit register. It contains the address of the next free location of the
stack. Depending on the product, the most significant bits can be forced to a preset value.
The stack is used to save the CPU context on subroutines calls or interrupts. The user can
also directly use it through the POP and PUSH instructions.
After an MCU reset the Stack Pointer is set to its upper limit value. It is then decremented
after data has been pushed onto the stack and incremented after data is popped from the
stack. When the lower limit is exceeded, the stack pointer wraps around to the stack upper
limit. The previously stored information is then overwritten, and therefore lost.
A subroutine call occupies two or three locations.
When an interrupt occurs, the CPU registers (CC, X, Y, A, PC) are pushed onto the stack.
This operation takes 9 CPU cycles and uses 9 bytes in RAM.
Note: The WFI/HALT instructions save the context in advance. If an interrupt occurs while the CPU
is in one of these modes, the latency is reduced.
Figure 2. Context save/restore for interrupts
).4%22504'%.%2!4)/.EXECUTEPIPELINE
#OMPLETEINSTRUCTIONINEXECUTESTAGE CYCLELATENCY
053(0#,
053(0#(
053(0#%
053(9
053(8
053(!
053(## #05#9#,%3
*5-04/).4%225042/54).%')6%."94(%).4%225046%#4/2
).4%225042/54).% 0#,
0#,
%8%#54)/.
).4%22504
0#(
0#, 34!#+
0#%
0#, 053(
2%452.
9,
0#,
9(
0#,
5.34!#+ 8,
0#,
0/0 8(
0#,
)2%4).3425#4)/.
!
0#,
##
0#,
0/0##
0/0!
0/08
0/09
0/00#%
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0/00#,
#05#9#,%3
*5-04/4(%!$$2%33')6%."902/'2!-#/5.4%22ELOAD0IPELINE
-36
14/162 Doc ID 13590 Rev 3

PM0044 STM8 core description
Global configuration register (CFG_GCR)

The global configuration register is a memory mapped register. It controls the configuration
of the processor. It contains the AL control bit:
AL: Activation level
If the AL bit is 0 (main), the IRET will cause the context to be retrieved from stack and the
main program will continue after the WFI instruction.
If the AL bit is 1 (interrupt only active), the IRET will cause the CPU to go back to WFI/HALT
mode without restoring the context.
This bit is used to control the low power modes of the MCU. In a very low power application,
the MCU spends most of the time in WFI/HALT mode and is woken up (through interrupts)
at specific moments in order to execute a specific task. Some of these recurring tasks are
short enough to be treated directly in an ISR, rather than going back to the main program. In
this case, by programming the AL bit to 1 before going to low power (by executing WFI/HALT
instruction), the run time/ISR execution is reduced due to the fact that the register context is
not saved/restored each time.
Condition Code register (CC)

The Condition Code register is a 8-bit register which indicates the result of the instruction
just executed as well as the state of the processor. These bits can be individually tested by a
program and specified action taken as a result of their state. The following paragraphs
describe each bit.
● V: Overflow
When set, V indicates that an overflow occurred during the last signed arithmetic
operation, on the MSB operation result bit. See INC, INCW, DEC, DECW, NEG, NEGW,
ADD, ADC, SUB, SUBW, SBC, CP, CPW instructions.
● I1: Interrupt mask level 1
The I1 flag works in conjunction with the I0 flag to define the current interruptability level
as shown in the following table. These flags can be set and cleared by software through
the RIM, SIM, HALT, WFI, IRET, TRAP and POP instructions and are automatically set
by hardware when entering an interrupt service routine.
Table 1. Interruptability levels

Interruptability Priority I1 I0
Interruptable Main 1 0
Interruptable Level 1 Lowest 0 1

↕
Interruptable Level 2 Highest 0 0
Non Interruptable 1 1
● H: Half carry bit

The H bit is set to 1 when a carry occurs between the bits 3 and 4 of the ALU during an
ADD or ADC instruction. The H bit is useful in BCD arithmetic subroutines.
For ADDW, SUBW it is set when a carry occurs from bit 7 to 8, allowing to implement
byte arithmetic on 16-bit index registers.
Doc ID 13590 Rev 3 15/162

STM8 core description PM0044
● I0: Interrupt mask level 0

See Flag I1
● N: Negative
When set to 1, this bit indicates that the result of the last arithmetic, logical or data
manipulation is negative (i.e. the most significant bit is a logic 1).
● Z: Zero
When set to 1, this bit indicates that the result of the last arithmetic, logical or data
manipulation is zero.
● C: Carry
When set, C indicates that a carry or borrow out of the ALU occurred during the last
arithmetic operation on the MSB operation result bit (bit 7 for 8-bit result/destination or
bit 15 for 16-bit result). This bit is also affected during bit test, branch, shift, rotate and
load instructions. See ADD, ADC, SUB, SBC instructions.
In bit test operations, C is the copy of the tested bit. See BTJF, BTJT instructions.
In shift and rotates operations, the carry is updated. See RRC, RLC, SRL, SLL, SRA
instructions.
This bit can be set, reset or complemented by software using SCF, RCF, CCF
instructions.
Example: Addition
$B5 + $94 = "C" + $49 = $149
C 7 0
0 1 0 1 1 0 1 0 1
C 7 0
+ 0 1 0 0 1 0 1 0 0
C 7 0
= 1 0 1 0 0 1 0 0 1
The results of each instruction on the Condition Code register are shown by tables in
Section 7: STM8 instruction set. The following table is an example:
V I1 H I0 N Z C
V 0 0 N Z 1
where
Nothing = Flag not affected

Flag name = Flag affected
0= Flag cleared
1= Flag set
16/162 Doc ID 13590 Rev 3

PM0044 STM8 memory interface
4 STM8 memory interface
4.1 Program space

The program space is 16-Mbyte and linear. To distinguish the 1, 2 and 3 byte wide
addressing modes, naming has been defined as shown in Figure 3:
● "Page" [0xXXXX00 to 0xXXXXFF]: 256-byte wide memory space with the same two
most significant address bytes (XXXX defines the page number).
● "Section" [0xXX0000 to 0xXXFFFF]: 64-Kbyte wide memory space with the same most
significant address byte (XX defines the section number).
The reset and interrupt vector table are placed at address 0x8000 for the STM8 family.
(Note: the base address may be different for later implementations.) The table has 32 4-byte
entries: RESET, Trap, NMI and up to 29 normal user interrupts. Each entry consists of the
reserved op-code 0x82, followed by a 24-bit value: PCE, PCH, PCL address of the
respective Interrupt Service Routine. The main program and ISRs can be mapped
anywhere in the 16 Mbyte memory space.
CALL/CALLR and RET must be used only in the same section. The effective address for the
CALL/RET is used as an offset to the current PCE register value. For the JP, the effective
address 16 or 17-bit (for indexed addressing) long, is added to the current PCE value. In
order to reach any address in the program space, the JPF jump and CALLF call instructions
are provided with a three byte extended addressing mode while the RETF pops also three
bytes from the stack.
As the memory space is linear, sections can be crossed by two CPU actions: next
instruction byte fetch (PC+1), relative jumps and, in some cases, by JP (for indexed
addressing mode).
Note: For safe memory usage, a function which crosses sections MUST:
- be called by a CALLF
- include only far instructions for code operation (CALLF & JPF)
All label pointers are located in section 0 (JP [ptr.w] example: ptr.w is located in section 0
and the jump address in current section)
Any illegal op-code read from the program space triggers a MCU reset.
4.2 Data space

The data space is 16-Mbyte and linear. As the stack must be located in section 0 and as
data access outside section 0/1 can be managed only with LDF instructions, frequently used
data should be located in section 0 to get the optimum code efficiency.
All data pointers are located in section 0 only.
Indexed addressing (with 16-bit index registers and long offset) allows data access over
section 0 and 1.
All the peripherals are memory mapped in the data space.
Doc ID 13590 Rev 3 17/162

STM8 memory interface PM0044
Figure 3. Address spaces
PROGRAM SPACE DATA SPACE

0xFFFFFF
SECTION 256
0x82 INT28E INT28H INT28L 0x00807C
0xFF0000 3-BYTE ADDRESSING MODE
ACCESSIBLE DATA
0x82 INT1E INT1H INT1L
0x82 INT0E INT0H INT0L
0x01FFFF
0x82 NMIE NMIH NMIL
SECTION 1
0x82 TRAPE TRAPH TRAPL
0x82 RESETE RESETH RESETL 0x008000 0x010000
0x00FFFF
2-BYTE ADDRESSING MODE
0x00807F BIT HANDLING CAPABILITY
SECTION 0
VECTORS POWERFUL DATA MANAGEMENT
0x008000 STACK AREA
POINTERS
0x0000FF
PAGE 0 1-BYTE ADDRESSING MODE
0x000000 BIT HANDLING CAPABILITY
FAST DATA ACCESS WITH
SHORT GENERATED CODE
18/162 Doc ID 13590 Rev 3

PM0044 STM8 memory interface
4.3 Memory interface architecture

The STM8 uses a Harvard architecture, with separate program and data memory buses.
However, the logical address space is unified, all memories sharing the same 16-Mbytes
space, non-overlapped. The memory interfaces are shown in Figure 4. It consists of two
buses: address, data, read/write control signal (R/W) and memory acknowledge signal
(STALL).
The STALL acknowledge signal makes the CPU compatible with slow serial or parallel
memory interfaces. When the memory interface is slow the CPU waits the memory
acknowledge before executing the instruction. So in such a case, the instruction CPU cycle
time is prolonged compare to the value given in this manual.
The program memory bus is 32-bit wide, allowing the fetch of most of the instructions in one
cycle.
As the address space is unified, the architecture allows data to be stored also in the Flash
memory and program to be fetched also from RAM (data bus). In this later case the
performance is impacted, besides the fact that data and fetch operation share the same bus,
the instructions will be fetched one byte at a time, thus taking longer (1 cycle /byte).
Figure 4. Memory Interface Architecture
Memory Interface (Flash)

DATABUS
(FETCH)
D31..0
STALL A23..0
@BUS
24
0x00 Data@E Data@E0:H:L
CPU
@DATABUS 24
N Y 17
"LDF" INSTRUCTION
PROGRAM COUNTER
7 PCE PCH PCL
24
@DATABUS 24
RAM FETCH INSTRUCTION N Y

@BUS
DATABUS
STALL A15..0 R/W

D7..0
Memory Interface (RAM)
Doc ID 13590 Rev 3 19/162

Pipelined execution PM0044
5 Pipelined execution
The STM8 family uses a 3-stage pipeline to increase the speed of the flow of instructions
sent to the processor. Pipelined execution allows several operations to be performed
simultaneously, rather than serially:
● Fetch
● Decode and address
● Execute
The Program Counter (PC) points always to the instruction in decode stage as shown in
Figure 5.
Figure 5. Pipelined execution principle
&%4#( )NSTRUCTIONSS FETCHEDFROMMEMORY

0#N
0# $%#/$% )NSTRUCTIONSDECODINGANDDATAREADFROMMEMORYIFNEEDED
2EGISTERS DATAREADFROMREGISTERBANK
0# N %8%#54% 3HIFTAND!,5OPERATION
7RITEBACKREGISTERS DATATO2EGISTERBANK
7RITEBACKDATATOMEMORY
-36
5.1 Description of pipelined execution stages

Figure 6 and Section 5.1.1, Section 5.1.2, and Section 5.1.3 provide a detailed description
of each stage of the pipeline execution.
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PM0044 Pipelined execution
Figure 6. Pipelined execution stages
0#
7"ADD
7RITE"ACK
!DDRESS
-%-/29 COMPUTATION
#/.42/,
!,5
-RD
&LASH
INSTRUCTION
BIT )4#
MEMORY
0REFETCHBUFFER
)MM
$ECODE
%XECUTION
!LIGN
0ERIPHERALS
2EGISTER
BIT
/P CODE
2!- BIT
&ETCH $ECODE-EM2EAD %XECUTE7RITEBACK

-36
5.1.1 Fetch stage

The first pipeline stage includes a 64-bit fetch buffer and a 32-bit prefetch buffer, totalling 3
words named F1, F2 and F3. This buffer structure allows any instruction code (up to 5 bytes)
to be available for decoding immediately after F1 (and F2 when needed) is/are loaded.
The instruction access from Flash Program memory is 32-bit wide and it is performed from
an aligned address i.e. 0xXXX0, 0xXXX4, 0xXXX8, or 0xXXXC.
Unlike the decode and execute stages that are performed at every cycle, the fetch stage
accesses the program memory only when needed, and stops memory access when the
buffer is full. This allows reducing the core power consumption,
Reading program from RAM is similar to reading program from ROM. However, since the
RAM data bus is 8-bit wide, 4 consecutive read operations have to be performed to load one
FX word, thus resulting in RAM execution being slower than Flash execution.
5.1.2 Decoding and addressing stage

The decoding stage includes an instruction alignment unit. The alignment unit uses the 64-
bit input from the fetch unit and feeds an instruction (from 1 to 5 bytes depending on the
instruction) to the decoding unit.
The instruction code consists of 2 parts (see examples in Table 2):
● The op-code itself (1 or 2 bytes)
● and a data/address part (0 to 3 bytes).
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The op-code is decoded in this stage. When present, the instruction address is used for
address computation, whilst the immediate operand is forwarded to the execution stage.
Table 2. Data/address decoding examples

Instruction Syntax Op-code Data/address
Register to register
LD A, XH 0x95 -
move
Register load LD A,($12,SP) 0x7B 0x12
Register store LD ($12,SP),A 0x6B 0x12
Data load / store with
LDF A,($123456,Y) 0x90 AF 0x12 34 56
extended address
Long/unaligned instructions
For long instructions (i.e. 5-bytes instructions), the fetch may need 2 program memory
accesses to be completed. In this case, the decoding stage (after decoding the op-code
part), is stalled waiting for the fetch stage to complete the 2nd fetch.
In case of shorter instructions, this may also happen when they cross a 32-bit boundary.
Indirect addressing
For indirect addressing, the CPU is stalled in this stage to read the pointer from the data
memory (i.e. RAM). The number of cycles during which the CPU is stalled depends on the
pointer size (short, long or extended addressing mode).
5.1.3 Execution stage

In the execution stage, the operation is executed and the result is stored in the accumulator,
index register or RAM.
5.2 Data memory conflicts

3 types of operations perform accesses to the data memory:
● Effective address computation in case of indirect addressing
● Data read: source operand
● Data write: destination for store or read-modify-write operations
In case of simultaneous accesses to the same memory area both in execution stage (write)
and decoding stage (read), the decode stage is stalled till the execution stage releases the
resource.
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5.3 Pipelined execution examples

A few pipelined execution examples are reported below. The numbers of cycles for the
decoding and execution stages correspond to the minimum number of cycles needed by the
instruction itself. In some cases, depending on the instruction sequence, the cycle taken
could be more than that number.
5.4 Conventions
Although the decode and/or execute stage of some instructions may take a different number
of cycles, a simplified convention providing a good match with reality, has been used in this
section:
● The decode stage of each instruction takes one cycle only
● The execution stage takes a number of cycles equal to
C y = DecCy + ExeCy – 1
Where
Cy is the number of execution cycles. In case of decode and execute cycles, It
corresponds to the minimum number of cycles needed by the instruction itself, and
does not take into account the impact of the instruction sequence.
DecCy is the exact number of decode cycles.
ExeCy is the exact number of execute cycles.
The decode stage of the next instruction starts during the last execution cycle. In
instructions performing pipeline flush, the convention is that, in case the branch is taken, the
next fetch are performed during the last instruction execution cycle.
The exact number of cycles (see Table 3) and the number of cycles obtained using this
convention (see Table 4) are identical.
Table 3. Example with exact number of cycles

Time (cycle)
Decode Execute
Address Instruction lgth
cycles cycles
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0xC000 LDW X, [$50.w] 4 1 3 D D D D E

F1
0xC003 ADDW X, #20 2 2 3 D D D D D E E
F2
0xC006 LD A, [$30].w 3 1 3 D D D D D D E
F3
0xC009 ….
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Table 4. Example with conventional number of cycles

Time (cycle)
Decode Execute
cycles cycles
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0xC000 LDW X, [$50.w] 4 3 3 D E E E E

F1
0xC003 ADDW X, #20 3 3 3 D D D D E E E
F2
0xC006 LD A, [$30].w 3 3 3 D D D D E E E
F3
0xC009 ….
Table 5. Legend
Symbol/Color Definition
F Fetch
D Decode stalled
D Decode
E Execute
5.4.1 Optimized pipeline example – execution from Flash Program memory

In the example shown in Table 6, the code is stored in the Flash Program memory (32-bit
bus). As a result, 3 cycles are needed to fill the 96-bit prefetch buffer. At each cycle, one
word is loaded and stored in F1, F2 and F3. The next fetch operation can start only when all
the instructions contained in one of the Fx word are decoded. In fact, at cycle 9, the last
instruction contained in F3 (SWAP A) is decoded, and a fetch operation can start to fill F3
word.
24/162 Doc ID 13590 Rev 3

Table 6. Optimized pipeline example - execution from Flash

Cycle
Decod. Exec.
Add. Instruction lgth
cycles cycles
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0xC000 NEG A 1 1 1 D E
0xC001 XOR A, $10 1 1 2 F1 D E
0xC003 LD A, #20 1 1 2 D E
F2
0xC005 SUB A,$1000 1 1 3 D E
0xC008 INC A 1 1 1 D E
0xC009 LD XL, A 1 1 1 D E
F3
0xC00A SRL A 1 1 1 D E
0xC00B SWAP A 1 1 1 D E
0xC00C SLA $15 1 1 2 D E
F1
0xC00E CP A,#$FE 1 1 2 D E
0xC010 MOV $100, #11 1 1 4 F2 D E
0xC014 MOV $101, #22 1 1 4 F3 D E
Table 7. Legend
F Fetch
D Decode
E Execute
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5.4.2 Optimize pipeline example – execution from RAM

In the example shown in Table 8, the RAM is accessed through an 8-bit bus. As a result, 12
cycles are required to fill the 96-bit pre-fetch buffer. Every 4 cycles, one word is loaded and
stored in Fx. The decoding of the first word instruction can start only when the Fx word is
filled. This occurs for example till the 4th cycle, and the first instruction (NEG A) can be
decoded only at the 5th cycle.
In case of read/write access to the RAM, the fetch is stalled. This occurs during the 6th cycle
since RAM address 10 is read during the decode stage of XOR A, $10.
Table 8. Optimize pipeline example – execution from RAM

Execute cycles
Decode cycles
Cycle
Instruction
lgth
Add.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
F1_1
0xC000 NEG A 1 1 1 D D D D E
XOR A,
F1_2
F1_3
0xC001 1 1 2 D E
$10
F1_4
F2_1
0xC003 LD A, #20 1 1 2 D D D D E
SUB
F2_2
F2_3
F2_4
0xC005 1 1 3 FS D E
A,$1000
F3_1
0xC008 INC A 1 1 1 D D D D E
F3_2
0xC009 LD XL, A 1 1 1 FS D E
F3_3
0xC00A SRL A 1 1 1 D E
F3_4
0xC00B SWAP A 1 1 1 D E
F1_1
F1_2
0xC00C SLA $15 1 1 2 D E
CP
F1_3
F1_4
0xC00E 1 1 2 D E
A,#$FE
Table 9. Legend
F Fetch
FS Fetch stalled
D Decode
D Decode stalled
E Execute
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5.4.3 Pipeline with Call/Jump

In the example shown in Table 10, a branch is taken after the JP/CALL instruction, and the
fetched instruction(s) are lost (flush). New instructions must be fetched. 3 fetch sequences
are required to refill the pre-fetch buffer. The fetch start depends on the instruction being
executed.
For a JP instruction, the fetch can start during the first cycle of the "dummy" execution.
For the CALL instruction, it starts after the last cycle of the CALL execution.
Table 10. Example of pipeline with Call/Jump

Cycle
Decode Execute
Add. Instruction lgth
cycles cycles
1 2 3 4 5 6 7 8 9 10 11
0xC000 INC A 1 1 1 D E
F1
0xC001 JP label 1 1 3 D E
Flush
0xC004 LDW X,[$5432.w] X X 4 F2
0xD010 label: NEG A 1 1 1 D E

F1
0xD011 CALL label2 1 2 3 D E E
0xD014 LDW X,[$5432.w] X X 4 F2
Flush
0xD018 LDW X,[$7895.w] X X 4 F3 FS
0xE030 label2: INCW X 1 1 1 F1 D E
Table 11. Legend

F Fetch
FS Fetch stalled
D Decode
E Execute
5.4.4 Pipeline stalled

The decode stage can be stalled when the execution lasts more than one cycle.
The flush is due to the branch. Fetching the branch address is performed during the second
execution cycle of the BTJF instruction.
The Decode operation can also be stalled when the memory target is modified during the
previous instruction. In the example given in Table 12, the INCW Y instruction writes the X
Doc ID 13590 Rev 3 27/162

register during the first execution cycle. As a result, in this cycle, the next instruction
(LD A,(X)) cannot be decoded since it reads the X register.
Table 12. Example of stalled pipeline

Time (cycles)
Decode Execute
cycles cycles
1 2 3 4 7 8 9 10 11 12 13 14
0xC000 SUB SP, #20 1 1 2 D E

F1
0xC002 LD A, #20 1 1 2 D E
0xC004 BTJT 0x10, #5, to 1 2 5 F2 D E E
0xC009 INC A 1 1 1 F3 D D E
0xC00A BTJF 0x20, #3, to 1 2 5 D E E
F1
0xC00F NOP X X 1
Flush
0xC010 LDW X,[$5432.w] X X 4 F2
0xC014 LDW X,[$1234.w] X X 4 F3
0xD020 to: INCW Y 1 1 2 D E
F1
0xD023 LD A,(X) 1 1 2 D D E
Table 13. Legend

F Fetch
D Decode stalled
D Decode
E Execute
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5.4.5 Pipeline with 1 wait state

In the example given in Table 14, performing the fetch takes 2 cycles, and there is no
overlap between the 2 fetch cycles.
If the instruction is decoded/executed during the last 2 fetch cycles, then the wait state is
transparent compared to the no-wait state execution.
Table 14. Pipeline with 1 wait state

Time (cycle)
Decode Execute
cycles cycles
1 2 3 4 5 6 7 8 9 10
0xC000 NEG A 1 1 1 MS D E
F1
0xC001 DEC ($10, X) 1 1 3 D E
0xC004 LDW X, #20 1 1 3 MS D E E
F2
0xC007 LD (X), A 1 1 1 D D E
0xC008 INC A 1 1 1 MS D E
F3
0xC009 NEG ($5A, Y) 1 1 1 D E
Table 15. Legend

F Fetch
D Decode stalled
D Decode
MS Memory stalled
E Execute
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STM8 addressing modes PM0044
6 STM8 addressing modes
The STM8 core features 18 different addressing modes which can be classified in 8 main
groups:
Table 16. STM8 core addressing modes

Addressing mode groups Example
Inherent NOP
Immediate LD A,#$55
Direct LD A,$55
Indexed LD A,($55,X)
SP Indexed LD A,($55,SP)
Indirect LD A,([$55],X)
Relative JRNE loop
Bit operation BSET byte,#5
The STM8 Instruction set is designed to minimize the number of required bytes per
instruction. To do so, most of the addressing modes can be split in three sub-modes called
extended, long and short:
● The extended addressing mode ("e") can reach any byte in the 16-Mbyte addressing
space, but the instruction size is bigger than the short and long addressing mode.
Moreover, the number of instructions with this addressing mode (far) is limited (CALLF,
RETF, JPF and LDF)
● The long addressing mode ("w") is the most powerful for program management, when
the program is executed in the same section (same PCE value). The long addressing
mode is optimized for data management in the first 64-Kbyte addressing space (from
0x000000 to 0x00FFFF) with a complete set of instructions, but the instruction size is
bigger than the short addressing mode.
● The short addressing mode ("b") is less powerful because it can only access the page
zero (from 0x000000 to 0x0000FF), but the instruction size is more compact.
Table 17. STM8 addressing mode overview

Pointer
Destination Pointer
size
Mode Syntax
address address
Inherent NOP
Immediate LD A,#$55
Short Direct LD A,$10 000000..0000FF
Long Direct LD A,$1000 000000..00FFFF
Extended Direct LDF A,$100000 000000..FFFFFF
No Offset Direct Indexed LD A,(X) 000000..00FFFF
Short Direct Indexed LD A,($10,X) 000000..0100FE
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PM0044 STM8 addressing modes
Table 17. STM8 addressing mode overview (continued)
Pointer
Destination Pointer
size
Mode Syntax
address address
SP
Short Direct LD A,($10,SP) 00..(FF+Stacktop)
Indexed
Long Direct Indexed LD A,($1000,X) 000000..01FFFE
Extended Direct Indexed LDF A,($100000,X) 000000..FFFFFF
Short
Indirect LD A,[$10.w] 000000..00FFFF 000000..0000FF 2
Pointer Long
Long Pointer
indirect LD A,[$1000.w] 000000..00FFFF 000000..00FFFF 2
Long
Long Pointer
indirect LDF A,[$1000.e] 000000..FFFFFF 000000..00FFFF 3
Extended
Short
Indirect Indexed LD A,([$10.w],X) 000000..01FFFE 000000..0000FF 2
Pointer Long
Long Pointer Indexed

Indirect LD A,([$1000.w],X) 000000..01FFFE 000000..00FFFF 2
Long (X only)
Long Pointer
Indirect Indexed LDF A,([$1000.e],X) 000000..FFFFFF 000000..00FFFF 3
Extended
Relative Direct JRNE loop PC+127/-128
Long
Bit BSET $1000,#7 000000..00FFFF
Direct
Long
Bit Relative BTJT $1000,#7,skip 000000..00FFFF PC+127/-128
Direct
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6.1 Inherent addressing mode

All related instructions are 1 or 2 byte. The op-code fully specifies all required information for
the CPU to process the operation.
Table 18. Inherent addressing instructions

Instructions Functions
NOP No operation
TRAP S/W Interrupt
WFI, WFE Wait For Interrupt / Event (Low Power Mode)
HALT Halt Oscillator (Lowest Power Mode)
RET Sub-routine Return
RETF Far Sub-routine Return
IRET Interrupt Sub-routine Return
SIM Set Interrupt Mask
RIM Reset Interrupt Mask
SCF Set Carry Flag
RCF Reset Carry Flag
RVF Reset Overflow Flag
CCF Complement Carry Flag
LD, LDW Load
CLR, CLRW Clear
PUSH, POP, PUSHW, POPW Push/Pop to/from the stack
INC, DEC, INCW, DECW Increment/Decrement
TNZ, TNZW Test Negative or Zero
CPL, NEG, CPLW, NEGW 1’s or 2’s Complement
MUL Byte Multiplication
DIV, DIVW Division
EXG, EXGW Exchange
SLA, SLL, SRL, SRA, RLC,
RRC, SLAW, SLLW, SRLW, Shift and Rotate Operations
SRAW, RLCW, RRCW
SWAP, SWAPW Swap Nibbles/Bytes
Example:
1000 98 RCF ; Reset carry flag
1001 9D NOP ; No operation
1002 9F LD A,X; Transfer X register content into accumulator
1004 88 PUSH A; Push accumulator content onto the stack
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6.2 Immediate addressing mode

The data byte required for the operation, follows the op-code.
Table 19. Immediate addressing instructions

LD, MOV, LDW Load and move operation

CP, CPW Compare
BCP Bit Compare
AND, OR, XOR Logical Operations
ADC, ADD, SUB, SBC, ADDW, SUBW Arithmetic Operations
PUSH Stack Operations
These are two byte instructions, one for the op-code and the other one for the immediate
data byte.
Example:
05BA AEFF LD X,#$FF
05BC A355 CP X,#$55
05BE A6F8 LD A,#$F8
Action:
Load X = $FF
Compare (X, $55)
A = $F8
Doc ID 13590 Rev 3 33/162

Figure 7. Immediate addressing mode example

Before Completion
A
Steps to Determine
Previous Value Effective Address
PC
LD A, #0F8h A6 05BE PC = 05BE
05BE
F8 05BF PC = PC + 1 = 05BF
EA = PC = 05BF
05C0
New PC = PC + 1
= 05C0
After Completion
Instruction Complete
A
F8 A = (EA) = F8
A6 05BE New PC = 05C0
F8 05BF New PC
05C0 05C0
VR02059A
6.3 Direct addressing mode (Short, Long, Extended)

Table 20. Overview of Direct addressing mode instructions
Addressing mode Syntax EA formula Ptr Adr Ptr Size Dest adr
Short Direct shortmem (shortmem) op + 1 Byte 00..FF

Long Direct longmem (longmem) op + 1..2 Word 0000..FFFF
Extended Direct extmem (extmem) op + 1..3 Ext word 000000..FFFFFF
The data byte required for the operation is found by its memory address, which follows the
op-code.
Direct addressing mode is made of three sub-modes:
Table 21. Available Long and Short Direct addressing mode instructions
LD, LDW Load

CP Compare
ADC, ADD, SUB, SBC, ADDW, SUBW Arithmetic Addition/Subtraction operations
BCP Bit Compare
34/162 Doc ID 13590 Rev 3

Table 21. Available Long and Short Direct addressing mode instructions
MOV Move
CLR Clear
INC, DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1’s or 2’s Complement
SLA, SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations
SWAP Swap Nibbles
CALL, JP Call or Jump subroutine
Table 22. Available Extended Direct addressing mode instructions

Instructions Function
CALLF, JPF Call or Jump FAR subroutine

LDF Far load
Table 23. Available Long Direct addressing mode instructions

Instructions Function
EXG Exchange
PUSH, POP Stack operation
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6.3.1 Short Direct addressing mode

The address is a byte, thus require only one byte after the op-code, but only allow 00..FF
addressing space.
Example:
004B 20 coeff dc.b $20
052D B64B LD A,coeff
Action:
A = (coeff) = ($4B) = $20
Figure 8. Short Direct addressing mode example

Before Completion
Steps to Determine
A Effective Address
Coeff .byte 20h 20 004B Previous Value

PC = 052D
PC
PC = PC + 1 = 052E
B6 052D 052D
EA = (PC)
LD A,Coeff 4B 052E = (4B + 0000)
052F = 004B
EA 004B
After Completion
A
Coeff .byte 20h 20 004B 20 Instruction Complete
B6 052D A = (EA) = 20
LD A,Coeff 4B 052E New PC New PC = PC + 1 = 052F
052F 052F
VR02059L
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6.3.2 Long Direct addressing mode

The address is a word, thus allowing 0000 to FFFF addressing space, but requires 2 bytes
after the op-code.
Example:
0409 C606E5 LD A,coeff
06E5 40 coeff dc.b $ 40
Action:
A = (coeff) = ($06E5) = $40
Figure 9. Long Direct addressing mode example

Before Completion
Previous Value Steps to Determine

Effective Address
PC
LD A,Coeff C6 0409 0409 PC = 0409

06 040A 06E5 PC = PC + 1 = 040A
E5 040B EA = (PC) : (PC+1) = 06E5
040C
Coeff .byte 040h 40 06E5 EA 06E5
After Completion
LD A,Coeff C6 0409
06 A = (EA) = 40
040A
New PC = PC + 2 = 040C
E5 040B New PC
040C 040C
A
Coeff .byte 040h 40 06E5 40
VR02059B
Doc ID 13590 Rev 3 37/162

6.3.3 Extended Direct addressing mode (only for CALLF and JPF)
The address is an extended word, thus allowing 000000 to FFFFFF addressing space, but
requires 3 bytes after the op-code.
Example:
000409 8D0106E5 CALLF sw_routine
0106E5 4C sw_routine INC A
Action:
PC = $0106E5
Figure 10. Far Direct addressing mode example

Before Completion
Previous Value Steps to Determine

Effective Address
PC
CALLF 0409
sw_routine 8D 0409 PC = 0409
01 040A PC=PC+1
0106E5 EA=(PC):(PC+1):(PC+2)
06 040B =0106E5
New PC = EA
E5 040C
EA 0106E5
INC A 4C 0106E5
After Completion
CALLF 0409
8D
sw_routine
New PC = 0106E5
01 040A
06 040B
E5
040C
New PC
INC A 4C 0106E5 0106E5
VR02059U
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6.4 Indexed addressing mode (No Offset, Short, SP, Long,

Extended)
Table 24. Overview Indexed addressing mode instructions
No offset Direct Indexed (ndx) (ndx) --- --- 00..FFFF

Short Direct Indexed (shortoff,ndx) (ptr + ndx) op + 1 Byte 00..100FE
Stack
Direct Indexed (shortoff,SP) (ptr + SP) op + 1 Byte 00..(FF+stacktop)
Pointer
Long Direct Indexed (longoff,ndx) (ptr.w + ndx) op + 1..2 Word 000000..01FFFE
Extended Direct Indexed (extoff,ndx) (ptr.e + ndx) op + 1..3 Ext Word 000000..FFFFFF
The data byte required for operation is found by its memory address, which is defined by the
unsigned addition of an index register (X or Y or SP) with an offset which follows the op-
code.
The indexed addressing mode is made of five sub-modes:
Table 25. No Offset, Long, Short and SP Indexed instructions

LD, LDW Load

CLR Clear
CP Compare
ADC, ADD, SUB, SBC, ADDW, SUBW Arithmetic Addition/Subtraction operations
SWAP Swap Nibbles
Table 26. No Offset, Long, Short Indexed Instructions

Table 27. Extended Indexed Instructions only

LDF Far Load
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6.4.1 No Offset Indexed addressing mode

There is no offset, (no extra byte after the op-code), but only allows 00..FF addressing
space.
Example:
00B8 11223344 table dc.w $1122, $3344
05F2 AEB8 LD X,#table
05F4 F6 LD A,(X)
Action:
X = table
A = (X) = (table) = ($B8) = $11
Figure 11. No Offset Indexed addressing mode example

Before completion
A
Steps to determine
Effective Address
Previous Value
Table .word 1122 11 00B8
X
00B9 PC = 05F4
22
B8 EA = X + 0000 = 00B8
33 00BA
44 00BB
PC
LD A,(X) F6 05F4 05F4
EA
00B8
After completion
A Instruction Complete
Table .word 1122 11 00B8 11
22 A = (EA) = 11
X
New PC = PC +1 = 05F5
33 B8
44
LD A,(X) F6 05F4 New PC
05F5 05F5
VR02059C
40/162 Doc ID 13590 Rev 3

6.4.2 Short Indexed addressing mode

The offset is a byte, thus requires only one byte after the op-code, but only allows 00..1FE
addressing space.
Example:
0089 11223344 table dc.l $11223344
0759 AE03 LD X,#3
075B E689 LD A,(table,X)
Action:
X = 3
A = (table, X) = ($89, X) = ($89, 3) = ($8C) = $44
Figure 12. Short Indexed - 8-bit offset - addressing mode example

Before completion
A Steps to determine
Effective Address
Table .long 11223344 11 0089 Previous Value
22 008A X
PC = 075B
33 008B 03 PC = PC + 1 = 075C
44 008C EA = (PC) + X = 89 + 03 = 008C
PC
LD A, (table,X) E6 075B 075B
89 075C
075D 89 03
Adder
EA 008C
After Completion
Table .long 11223344 Instruction Complete

11 0089
22 008A A
A = (EA) = 44
33 008B 44
New PC = PC + 1 = 075D
44 008C X
03
LD A, (table,X) E6 075B
89 075C New PC
075D 075D
VR02059D
Doc ID 13590 Rev 3 41/162

6.4.3 SP Indexed addressing mode

The offset is a byte, thus require only one byte after the op-code, but only allow 00..(FF +
stack top) addressing space.
Example:
0086 4B11 PUSH #$11
0087 4B22 PUSH #$22
0088 4B33 PUSH #$33
0089 7B03 LD A,($03,SP)
Action:
A = ($03, SP) = ($03, $1FFC) = ($1FFF) = $11
Figure 13. SP Indexed - 8-bit offset - addressing mode example

Before completion
PC
Steps to determine
LD A, ($03,SP) 7B 0089 0089
effective address
03 008A
A
008B PC = 0089
Previous Value
PC = PC + 1 = 008A
SP EA = (PC) + SP=03+1FFC= 1FFF

1FFC 1FFC
33 1FFD
22 1FFE
11 1FFF 1FFC 03
Adder
EA 1FFF
After completion
LD A, ($03,SP) 7B 0089
03 008A New PC
008B 008B A = (EA) = 11
New PC = PC+1 = 008B
SP
1FFC 1FFC
33 1FFD
22 1FFE A
11 1FFF 11
VR02059D
42/162 Doc ID 13590 Rev 3

6.4.4 Long Indexed addressing mode

The offset is a word, thus allowing up to 128 KB addressing space, but requires 2 bytes after
the op-code.
Example:
0690 AE02 LD X,#2
0692 D6077E LD A,(table,X)
077E BF table dc.b $BF
86 dc.b $86
DBCF dc.w $DBCF
Action:
X = 2
A = (table, X) = ($077E, X) = ($077E, 2) = ($0780) = $DB
Figure 14. Long Indexed - 16-bit offset - addressing mode example

Before completion
PC Steps to Determine
LD A, (table, X) D6 0692 Effective Address

0692
07 0693
PC = 0692
7E 0694 X
PC = PC + 1 = 0693
02 EA = (PC):(PC+1) + X
table . byte BF BF 077E A = 077E + 02 = 0780
86 077F Previous Value
DB 0780
CF 0781 077E 02
Adder
EA 0780
After Completion
X Instruction Complete
LD A, (table, X) D6 0692 02
A = (EA) = DB
07 0693
New PC = PC + 2 = 0695
7E 0694 New PC
0695 0695
table . byte BF BF 077E
86 077F A
DB 0780 DB
CF 0781 VR02059E
Doc ID 13590 Rev 3 43/162

6.4.5 Extended Indexed (only LDF instruction)

The offset is an extended word, thus allowing 16Mbyte addressing space (from 000000 to
FFFFFF), but requires 3 bytes after the op-code.
Example:
0690 AE02 LD X,#2
0692 AF010780 LDF A,(table,X)
010780 BF table dc.b $BF
86 dc.b $86
DDFE dc.w $DDFE
Action:
X = 2, A = (table, X) = ($010780,X) = ($010780+2)) = ($010782) = $DD
Figure 15. Far Indexed - 16-bit offset - addressing mode example

Before Completion
PC Steps to determine
LDF A, (table, X) AF 0692 0692 Effective Address
01 0693
PC = 0692
07 0694 X PC = PC + 1 = 0693
80 0695 02 EA= (PC):(PC+1):(PC+2)+X
A = 010780+02 = 010782
Previous Value
table . byte BF BF 010780
86 010781 010780 02
DD 010782 Adder
FE 010783
EA 010782
After Completion
X Instruction Complete
LD A, (table, X) AF 0692
02
01 0693 A = (EA) = DD
07 0694 New PC = PC+3 = 0696
80 0695 New PC
0696 0696
table . byte BF
BF 010780
86 010781 A
DD 010782 DD
FE
010783
VR02059R
44/162 Doc ID 13590 Rev 3

6.5 Indirect (Short Pointer Long, Long Pointer Long)

Table 28. Overview of Indirect addressing instructions
Ptr
Addressing mode Syntax EA formula Ptr Adr Dest adr
Size
Short Pointer Long Indirect ((shortptr.w)) ((shortptr.w)) 00..FF Word 0000..FFFF

Long Pointer Long Indirect ((longptr.w)) ((longptr.w)) 0000..FFFF Word 0000..FFFF
The data byte required for the operation is found by its memory address, located in memory
(pointer).
The pointer address follows the op-code. The indirect addressing mode is made of three
sub-modes:
Table 29. Available Long Pointer Long and Short Pointer Long Indirect Instructions
LD, LDW Load

CP Compare
ADC, ADD, SUB, SBC Arithmetic Addition/Subtraction operations
BCP Bit Compare
Table 30. Available Long Pointer Long Indirect Instructions

CLR Clear
SWAP Swap Nibbles
Doc ID 13590 Rev 3 45/162

6.6 Short Pointer Indirect Long addressing mode

The pointer address is a byte, the pointer size is a word, thus allowing up to 128 KB
addressing space, and requires 1 byte after the op-code.
Example:
0040 42E5 ptr dc.w var
0409 92C640 LD A,[shortptr.w]
42E5 11 var dc.b $11
Action:
A = [shortptr.w] = ((shortptr.w)) = (($40.w)) = ($42E5) =
$11
Figure 16. Short Pointer Indirect Long addressing mode example

Before Completion
Steps to determine
Effective Address
ptr .word var 42 0040 A

PC = 0409
E5 0041 Previous Value
PC = PC + 2 = 40B
PC
EA = ((PC)) :((PC)+1)
LD A, [shortptr.w] 92 0409 0409 = 42E5
C6 040A
40 040B
040C
var.byte 0x011 11 42E5 EA 42E5
After Completion
ptr .word var 42 0040
0041 A = (EA) = 0x11

E5
New PC = PC +1 = 040C
LD A, [shortptr.w] 92 0409
C6 040A
40 040B New PC
040C 040C
var .byte 0x011 11 42E5 0x11
46/162 Doc ID 13590 Rev 3

6.7 Long Pointer Indirect Long addressing mode

The pointer address is a word, the pointer size is a word, thus allowing 64 KB addressing
space, and requires 2 bytes after the op-code.
Example:
1040 42E5 ptr dc.w var
1409 72C61040 LD A,[longptr.w]
42E5 11 var dc.b $11
Action:
A = [longptr.w] = ((longptr.w)) = (($1040.w)) = ($42E5) = $11
Figure 17. Long Pointer Indirect Long addressing mode example

Before Completion
Steps to determine
Effective Address
ptr .word var 42 1040 A

PC = 1409
E5 1041 Previous Value
PC = PC + 2 = 140B
PC
EA =((PC):(PC+1)):
LD A, [longptr.w] 72 1409 1409 ((PC):(PC+1)+1)
= 42E5
C6 140A
10 140B
40 140C
140D
EA 42E5
var.byte 0x011 11 42E5
After Completion
Instruction complete
ptr .word var 42 1040
1041 A = (EA) = 0x11

E5
New PC = PC + 2 = 140D
LD A, [longptr.w] 72 1409
C6 140A
10 140B
40 140C New PC
140D 040D
var .byte 0x11 11 42E5 0x11 VR02059G
Doc ID 13590 Rev 3 47/162

6.8 Indirect Indexed (Short Pointer Long, Long Pointer Long,

Long Pointer Extended) addressing mode
Table 31. Overview of Indirect indexed instructions
Short Pointer
Indirect Indexed ([shortptr.w],ndx) ((shortptr.w) + ndx) 00..FF Word 000000.01FFFE
Long
Long Pointer
Indirect Indexed ([longptr.w],ndx) ([longptr.w] +ndx) 00..FFFF Word 000000.01FFFE
Long
Long Pointer
Indirect Indexed ([longptr.e],ndx) ([longptr.e] +ndx) 00..FFFF Extword 000000.FFFFFE
Extended
This is a combination of indirect and indexed addressing mode. The data byte required for
the operation is found by its memory address, which is defined by the unsigned addition of
an index register value (X or Y) with a pointer value located in memory. The pointer address
follows the op-code.
The indirect indexed addressing mode is made of four sub-modes:
Table 32. Available Long Pointer Long and Short Pointer Long Indirect
Indexed instructions
LD, LDW Load

CP Compare
ADC, ADD, SUB, SBC Arithmetic Addition/Subtraction operations
BCP Bit Compare
Table 33. Available Long Pointer Long Indirect Indexed instructions

CLR Clear
SLA,SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations
SWAP Swap Nibbles
Table 34. Long Pointer Extended Indirect Indexed instructions instruction

LDF Far load
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6.9 Short Pointer Indirect Long Indexed addressing mode

The pointer address is a byte, the pointer size is a word, thus allowing up to 128 KB
addressing space, and requires 1 byte after the op-code.
Example:
0089 0800 ptr dc.w table
0800 10203040 table dc.b $10,$20,$30,$40
0690 AE03 LD X,#3

0692 92D689 LD A,([shortptr.w],X)
X = 3
A = ([shortptr.w],X) = ((shortptr.w), X)
= (($89.w), 3)
= ($0800,3) = ($0803) = $40
Doc ID 13590 Rev 3 49/162

Figure 18. Short Pointer Indirect Long Indexed addressing mode example
Before completion
ptr .word table 08 0089

00 008A Steps to determine
PC Effective Address
LD A,([shortptr.w],X) 92 0692 0692

PC = 0692
D6 0693 PC = PC + 2 = 0694
89 0694 X EA = ((PC)) : ((PC)+1) + X
03 EA = 0803
table .byte 0x10,0x20,0x30, 10 800 A

0x40
20 801 Previous value
30 802
40 803 800 03
Adder
EA 0803
After completion
ptr .word table 08 0089 Instruction Complete

00 008A
X A = (EA) = 40
New PC = PC + 1 = 0695
LD A,([shortptr.w],X) 92 0692 03
D6 0693
89 0694 New PC
0695 0695
table .byte 0x10,0x20,0x30 10 0800

0x40
20 0801
30 0802 A
40 0803 40
50/162 Doc ID 13590 Rev 3

6.10 Long Pointer Indirect Long Indexed addressing mode

The pointer address is a word, the pointer size is a word, thus allowing up to 128 KB
addressing space, and requires 2 bytes after the op-code.
Example:
1089 1800 ptr dc.w table
1800 10203040 table dc.b $10,$20,$30,$40
1690 AE03 LD X,#3

1692 72D61089 LD A,([longptr.w],X)
X = 3
A = ([longptr.w],X) = ((longptr.w), X) =
(($1089.w), 3)
= ($1800,3) = ($1803) = $40
Doc ID 13590 Rev 3 51/162

Figure 19. Long Pointer Indirect Long Indexed addressing mode example
Before completion
ptr .word table 18 1089

00 108A Steps to determine
Effective Address
PC
LD A,([longptr.w],X) 72 1692 1692 PC = 1692
D6 1693 PC = PC + 2 = 1694
10 X
1694 EA = (((PC) : (PC+1)) :
89 1695 03 ((PC) : (PC+1) +1)) + X
A
EA = 1803
table .byte 0x10,0x20,0x30, 10 1800 Previous value
0x40
20 1801
30 1802 1800 03
Adder
40 1803
EA 1803
After completion
ptr .word table 18 1089 Instruction Complete
00 108A
X A = (EA) = 40
New PC = PC + 2 = 1696
LD A,([longptr.w],X) 92 1692 03
D6 1693
10 1694
89 1695 New PC
1696 1696
table .byte 0x10,0x20,0x30, 10 1800

0x40
20 1801
30 1802 A
40 1803 40
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6.11 Long Pointer Indirect Extended Indexed addressing mode

The pointer address is a word, the pointer size is an extended word, thus allowing 16-Mbyte
addressing space, and requires 2 bytes after the op-code.
Example:
1089 180000 ptr dc.b page(table), high(table), low(table)
180000 10203040 table dc.b $10,$20,$30,$40
1690 AE03 LD X,#3

1692 72A71089 LDF A,([longptr.e],X)
X = 3
A = ([longptr.e],X) = ((longptr.e), X) =
(($1089.e), 3)
= ($180000,3) = ($180003) = $40
Doc ID 13590 Rev 3 53/162

Figure 20. Long Pointer Indirect Extended Indexed addressing mode example
Before completion
18 1089
ptr .word table 00 108A

00 108B Steps to Determine
Effective Address
PC
LDF A,([longptr.w],X) 72 1692 1692 PC = 1692
A7 1693 PC = PC + 2 = 1694
10 X
1694 EA = (((PC) : (PC+1)) :
89 1695 03 ((PC) : (PC+1) +1) :
((PC) : (PC+1) +2)) + X
A
EA = 180003
table .byte 0x10,0x20,0x30, 10 180000 Previous value
0x40
20 180001
30 180002 180000 03
Adder
40 180003
EA 180003
After completion
18 1089
ptr .word table 00 108A Instruction Complete

00 108B
X A = (EA) = 40
New PC = PC + 2 = 1696
LDF A,([longptr.w],X) 72 1692 03
A7 1693
10 1694
89 1695 New PC
1696 1696
table .byte 0x10,0x20,0x30, 10 180000

0x40
20 180001
30 180002 A
VR02059I
40 180003 40
54/162 Doc ID 13590 Rev 3

6.12 Relative Direct addressing mode

Table 35. Overview of Relative Direct addressing mode instructions
Direct Relative off PC = PC + off op + 1 --- PC +127/-128
This addressing mode is used to modify the PC register value, by adding an 8-bit signed
offset to it. The offset added to the PC register value is relative to the start of the next
instruction.
Table 36. Available Relative Direct instructions

JRxx Conditional Jump

JRA Jump Relative Always
CALLR Call Relative
The offset follows the op-code.

Example:
04A7 2717 jreq skip
04A9 9D nop
04AA 9D nop
04C0 20FE skip jra* ; Infinite loop
Action:
if (Z == 1)then PC = PC + $17 = $04A9 + $17 = $04C0
elsePC = PC= $04A9
Doc ID 13590 Rev 3 55/162

Figure 21. Relative Direct addressing mode example
Before completion
CC
Z Steps to Determine
JREQ SKIP 27 04A7 Effective Address
PC
17 04A8 04A7
PC = 04A7
04A9 02
PC = PC + 1 = 04A8
TEMP = (PC) = 17
04A7
Adder PC = PC +1 = 04A9
Stop here if there
is no Branch; i.e., Z = 0
04A9 EA = PC + TEMP
= 04A9 + 17
EA
= 04C0
New PC = EA if Branch is taken
After completion
(Branch taken)
CC
Z=1
PC
JREQ SKIP 27 04A7 New PC = EA = 04C0
04A9
17 04A8
04A9
17 04A9
Adder
SKIP : 04C0 04C0
New PC
04C0 EA
After completion
(No branch taken)
CC
Z=0 Instruction Complete
JREQ SKIP New PC = EA = 04A9

27 04A7
17 New PC
04A8
04A9 04A9
56/162 Doc ID 13590 Rev 3

6.13 Bit Direct (Long) addressing mode

Table 37. Overview of Bit Direct addressing mode instruction
Bit Long Direct longmem, #pos (longmem) op + 1..2 Word 0000..FFFF
op-code. The bit used for the operation is selected by the bit selector which is encoded in
the instruction op-code.
Table 38. Available Bit Direct instructions

BRES Bit Reset

BSET Bit Set
BCPL Bit Complement
BCCM Copy Carry Bit to Memory
The address is a word, thus allowing 0000 to FFFF addressing space, but requires 2 bytes
after the op-code. The bit selector #n (n=0 to 7) selects the nth bit from the byte pointed to by
the address.
Example:
0408 721006E5 BCPL coeff, #0
06E5 40 coeff dc.b $ 40
Action:
(coeff) = ($06E5) XOR 2**0 = $40 XOR $01 = $41
Doc ID 13590 Rev 3 57/162

Figure 22. Bit Long Direct addressing mode example

Before c ompletion
Steps to d etermine
PC
e ffective a ddress
BCPL Coeff,#0 90 0408 0408
10 0409 PC = 0408
06 040A 06E5 PC = PC + 2 = 040A
E5 040B EA = (PC ) :(PC+1) = 06E5
040C
Coeff .byte 040h 40 06E5 EA 06E5

EA = (PC ): (PC+1) = 06E5
After c ompletion
BCPL Coeff,#0 90 0408 Instruction c omplete

10 0409
06 (EA) = (EA) | 2**0 = 40 | 01 = 41
040A
New PC = PC + 2 = 040C
E5 040B New PC
040C 040C
Coeff .byte 040h 41 06E5 40 XOR 01
58/162 Doc ID 13590 Rev 3

6.14 Bit Direct (Long) Relative addressing mode

Table 39. Overview of Bit Direct (Long) Relative addressing mode
(longmem) op + 1..2 Word 0000..FFFF

Long
Bit Relative longmem, #pos, off PC +127/-
Direct PC = PC + off op + 3 Byte
128
This addressing mode is a combination between the Bit Direct addressing mode (for data
addressing) and Relative Direct mode (for PC computation).
op-code. The bit used for the test operation is selected by the bit selector which is encoded
in the instruction op-code. Following the logical test operation, the PC register value can be
modified, by adding an 8-bit signed offset to it.
Table 40. Available Bit Direct Relative instructions

BTJT, BTJF Bit Test and Jump
The data address is a word, thus allowing 0000 to FFFF addressing space (requires 2 bytes
after the op-code). The bit selector #n (n=0 to 7) selects the nth bit from the byte pointed to
by the address. The offset follows the op-code and data address.
Example:
104B 00 DRA dc.b $00 ; Port A data
register (input
value)
bit0 equ $0 ; data bit 0
04A7 7201104BFB wait_1 BTJF DRA, bit0, wait_1

04AC .... cont_0
Action:
Test = select_bit(0, ($4B)) = select_bit(0, DRA)
if (Test /= 1) then PC = PC + $FB = $0004AC - $05 =
$0004A7
else PC = PC = $0004AC
Doc ID 13590 Rev 3 59/162

Figure 23. Bit Long Direct Relative addressing mode example
DRA.b0 =? 0 Steps to Determine

DRA .byte DRA b0 104B Effective Address
PC
104C
04A7
PC = 04A7
05
PC = PC + 2 = 04A9
EA = (PC):(PC+1) = 104B
04A7
Test = (EA).b0
wait_1 Adder
BTJF DRA, #0, wait_1 72 04A7 PC = PC + 2 = 04AB
01 TEMP = (PC) = FC
04A8
10 PC = PC +1 = 04AC
04A9 04AC
Stop here if there
4B 04AA EA is no Branch; i.e., Test = TRUE (1)
FB
04AB EA = PC + TEMP
= 04AA + FD
After completion = 04A7
(Branch taken)
New PC = EA if Branch is taken
(EA)
b0 = 0
wait_1
BTJF DRA, #0, wait_1 72 04A7 PC
04A7
New PC = EA = 04A7
01 04A8 New PC 04AC
10 04A9
4B 04AA
FB 04AB FB 04AC
Adder
04A7 EA
After completion
(No branch taken)
(EA)
b0 = 1 Instruction Complete
72 04A7
wait_1 New PC = EA = 04AC
BTJF DRA, #0, wait_1 01 04A8
10 04A9
4B 04AA
FB New PC
04AB
04AC 04AC
60/162 Doc ID 13590 Rev 3

PM0044 STM8 instruction set
7 STM8 instruction set
7.1 Introduction
This chapter describes all the STM8 instructions. There are 96 and they are described in
alphabetical order. However, they can be classified in 13 main groups as follows:
Table 41. Instruction groups

Load and
LD LDF CLR MOV EXG LDW CLRW EXGW
Transfer
Stack PUSH
PUSH POP POPW
operation W
Increment/
INC DEC INCW DECW
Decrement
Compare and
CP TNZ BCP CPW TNZW
Tests
Logical
AND OR XOR CPL CPLW
operations
Bit Operation BSET BRES BCPL BCCM
Conditional Bit
Test and BTJT BTJF
Branch
Arithmetic
NEG ADC ADD SUB SBC MUL DIV DIVW NEGW ADDW SUBW
operations
Shift and SLL SRL SRA RLC RRC SWAP SLLW SRLW SRAW RLCW RRCW
Rotates SWAP RLWA RRWA
Unconditional
JRA JRT JRF JP JPF CALL CALLR CALLF RET RETF NOP
Jump or Call
Conditional
Branch/ JRxx WFE
Execution
Interrupt
TRAP WFI HALT IRET
management
Condition
Code Flag SIM RIM SCF RCF CCF RVF
modification
Breakpoint/
BREAK
software break
The instructions are described with one to five bytes.

PC-1 End of previous instruction
PC Op-code
PC+1..4 Additional word (0 to 4) according to the number of bytes required to compute the
effective address(es)
Doc ID 13590 Rev 3 61/162

STM8 instruction set PM0044
Using a pre-code (two-byte op-codes)

In order to extend the number of available op-codes for an 8-bit CPU (256 op-codes), four
different pre-code bytes are defined. These pre-codes modify the meaning of the instruction
they precede.
The whole instruction becomes:
PC-1 End of previous instruction

PC Pre-code
PC+1 Op-code
PC+2 Additional word (0 to 3) according to the number of bytes required to compute the
effective address
These pre-bytes are:
0x90 = PDY Replaces an X based instruction using immediate, direct, indexed or
inherent addressing mode by a Y one.
It also provides read/modify/write instructions using Y indexed
addressing mode with long offset and two bit handling instructions
(BCPL and BCCM)
0x92 = PIX Replaces an instruction using direct, direct bit, or direct relative
addressing mode to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed addressing mode to
an instruction using indirect X indexed addressing mode.
0x91 = PIY Replace an instruction using indirect X indexed addressing mode by
a Y one.
0x72 = PWSP Provide long addressing mode for bit handling and read/modify/write
instructions.
It also provides indirect addressing mode with two byte pointer for
read/modify/write and register/memory instructions.
Finally it provides stack pointer indexed addressing mode on
register/memory instructions.
62/162 Doc ID 13590 Rev 3

7.2 Nomenclature
7.2.1 Operators
← is loaded with ...
↔ has its value exchanged with ...
7.2.2 CPU registers

A accumulator
X X index register (2 bytes)
XL least significant byte of the X index register (1 byte)
XH most significant byte of the X index register (1 byte)
Y Y index register (2 bytes)
YL least significant byte of the Y index register (1 byte)
YH most significant byte of the Y index register (1 byte)
PC program counter register (3 bytes)
PCL low significant byte of the program counter register (1 byte)
PCH high significant byte of the program counter register (1 byte)
PCE extended significant byte of the program counter register (1 byte)
SP stack pointer register (2 bytes)
CC Condition code register (1 byte)
CC.V overflow flag of the code condition register (1 bit)
CC.I0 interrupt mask bit 0 of the code condition register (1 bit)
CC.H half carry flag of the code condition register (1 bit)
CC.I1 interrupt mask bit 1 of the code condition register (1 bit)
CC.N negative flag of the code condition register (1 bit)
CC.Z zero flag of the code condition register (1 bit)
CC.C carry flag of the code condition register (1 bit)
7.2.3 Code condition bit value notation

- bit not affected by the instruction
1 bit forced to 1 by the instruction
0 bit forced to 0 by the instruction
X bit modified by the instruction
7.2.4 Memory and addressing

M(...) content of a memory location
R 8-bit operation result value
R(...) 8-bit operation result value stored into the register or memory shown inside parentheses
Rn bit n of the operation result value (0≤n≤7)
XX.B bit B of the XX register or memory location
imm.b byte immediate value
imm.w 16-bit immediate value
shortmem memory location with short addressing mode (1 byte)
longmem memory location with long addressing mode (2 bytes)
extmem memory location with extended addressing mode (3 bytes)
shortoff short offset (1 byte)
longoff long offset (2 bytes)
extoff extended offset (3 bytes)
[shortptr.w] short pointer (1 byte) on long memory location (2 bytes). Assembler notation = [$12.w].
[longptr.w] long pointer (2 bytes) on long memory location (2 bytes). Assembler notation = [$1234.w]
[longptr.e] long pointer (2 bytes) on extended memory location (3 bytes). Assembler notation = [$1234.e]
Doc ID 13590 Rev 3 63/162

7.2.5 Operation code notation

ee extended order byte of 24-bit extended address
ww high order byte of 16-bit long address or middle order byte of 24-bit extended address
bb short address or low order byte of 16-bit long address or 24-bit extended address
ii immediate data byte or low order byte of 16-bit immediate data
iw high order byte of 16-bit immediate data
rr relative offset byte in a range of [-128..+127]
7.3 Instruction set summary

Table 42. Instruction set summary
Cycles(1)
Effect on CC register Example
Mnemo
Pipe
Description Syntax example Operation op-
V I1 H I0 N Z C code(s)
Set if there is a carry from bit 3 to 4 Set if there is a carry from bit 3 to 4
Set if there is a carry from R7

different from the carry bit C
Set if the carry from R6 is
cleared otherwise
cleared otherwise
cleared otherwise
cleared otherwise
Set if R7 is set
Set if R=$00
A ← A + M(SP+shortoff) +
ADC Add with carry - - ADC A,($12,SP) 19 bb 1
CC.C
cleared otherwise
cleared otherwise
cleared otherwise
cleared otherwise
Set if R7 is set
Set if R=$00
Add without - - ADD A,($12,SP) A ← A + M(SP+shortoff) 1B bb 1

ADD
carry
- - - - - - - ADD SP,#$12 SP ← SP + imm.b 5B ii 2

Set if there is a carry from bit 7 to 8

cleared otherwise
cleared otherwise
cleared otherwise
cleared otherwise
Set if R15 is set
Set if R=$0000
Add word
ADDW - - ADDW X,($12,SP) X ←-X + M(SP+shortoff) 72 FB bb 2
without carry
cleared otherwise
cleared otherwise
Set if R7 is set
Set if R=$00
A ← A AND
AND Logical AND - - - - AND A,($12,SP) 14 bb 1
-
M(SP+shortoff)
64/162 Doc ID 13590 Rev 3

Table 42. Instruction set summary (continued)
Cycles(1)
Mnemo
Pipe
Copy carry 90 1n ww bb
BCCM - - - - - - - BCCM $1234,#1 M(longmem).bit ← CC.C 1
in memory bit n= 2*bit
cleared otherwise
cleared otherwise
Set if R7 is set
Set if R=$00
test {A AND
Logical bit M(SP+shortoff) }
BCP - - - - BCP A,($12,SP) 15 bb 1
compare N and Z are updated
accordingly
Complement bit M(longmem).bit ← 90 1n ww bb

BCPL - - - - - - - BCPL $1234,#1 1
in memory M(longmem).bit n= 2*bit
Software
BREAK - - - - - - - SW-BREAK 8B 1 Flush
breakpoint
72 1n ww bb
BRES Bit reset - - - - - - - BRES $1234,#1 M(longmem).bit ← 0 1
n= 1 + 2*bit
72 1n ww bb
BSET Bit set - - - - - - - BSET $1234,#1 M(longmem).bit ← 1 1
n= 2*bit
Bit test and
relative if M(longmem).bit=0
tested
72 0n ww bb Flush
BTJF jump if - - - - - - BTJF $1234,#1,label then PC ← PC + 4 + rr 2/3
bit
n= 1 + 2*bit (2)
condition is else PC ← PC + 4
false
Bit test and
if M(longmem).bit=1
tested
relative 72 0n ww bb Flush
BTJT - - - - - - BTJT $1234,#1,label then PC ← PC + 4 + rr 2/3
bit
jump if n= 2*bit (2)

else PC ← PC + 4
condition is true
PC ← PC + 4
Call to M(SP--) ← PCL
Subroutine with
CALL - - - - - - - CALL [$1234.w] M(SP--) ← PCH 72 CD ww bb 6 Flush
address in
same section PCH ← M(longmem)
PCL← M(longmem + 1)
PC ← PC+4
Call to
M(SP--) ← PCL
subroutine
CALLF - - - - - - - CALLF $123456 M(SP--) ← PCH 8D ee ww bb 5 Flush
with extended
M(SP--) ← PCE
address
PC ← extmem
PC ← PC + 4
Call Subroutine M(SP--) ← PCL
CALLR - - - - - - - CALLR label AD bb 4 Flush
relative M(SP--) ← PCH
PC ← PC + rr
Complement
CCF - - - - - - C CCF CC.C ← CC.C 8C 1
carry flag
Clears the M( M(longmem).w + X ) ←
CLR - - - - 0 1 - CLR ([$1234.w],X) 72 6F ww bb 4
destination byte 0x00
Clears the
CLRW destination - - - - 0 1 - CLRW X X ← 0x0000 5F 1
index register
Set if A<mem (unsigned values)
Set if A-mem (signed values)
overflows, cleared otherwise
cleared otherwise
cleared otherwise
cleared otherwise
Set if R7 is set
Set if R=$00
CP Compare - - - CP A,($12,SP) test { A - M(SP+shortoff) } 11 bb 1
Doc ID 13590 Rev 3 65/162

Cycles(1)
Mnemo
Pipe
Set if X<mem (unsigned values)

Set if Xmmem (signed values)
overflows, cleared otherwise
cleared otherwise
cleared otherwise
cleared otherwise
Set if R15 is set
Set if R=$0000
CPW Compare word - - - CPW X,($12,SP) test { X - M(SP+shortoff) } 13 bb 2
cleared otherwise cleared otherwise

M(M(longmem).w +X) ←
Set if R7 is set
Set if R=$00
FF - M(M(longmem).w+X)
Logical 1’s
CPL - - 1 CPL ([$1234.w],X) or 72 63 ww bb 4
complement
M(M(longmem).w+X)
XOR FF
Set if R15 is set
Set if R=$0000
X ← FFFF - X
Logical 1’s
CPLW - - 1 CPLW X or 53 2
complement
X XOR FFFF
Set if sign overflow Set if sign overflow
cleared otherwise
cleared otherwise
Set if R7 is set
Set if R=$00
Decrement byte M(M(longmem).w + X) ←

DEC - - - - DEC ([$1234.w],X) 72 6A ww bb 4
by one M(M(longmem).w + X) - 1
cleared otherwise
cleared otherwise
Set if R15 is set
Set if R=$0000
Decrement
DECW - - - - DECW X X← X - 1 5A 1
word by one
X ← X/A (Quotient)

Set if divide by 0 Set if divide by 0
DIV X,A 62 16
Set if Q=$0000
A ← X%A (Remainder)
16 by 8
DIV Unsigned 0 - 0 - 0
division Y ← Y/A (Quotient)
DIV Y,A 90 62 16
A ← Y%A (Remainder)
Set if Q=$0000
16 by 16
X ← X/Y (Quotient)
DIVW Unsigned 0 - 0 - 0 DIVW X,Y 65 16
Y ← X%Y (Remainder)
division
EXG A,$1234 A ↔ M(longmem) 31 ww bb 3

Data byte
EXG - - - - - - - EXG A,XL A ↔ XL 41 1
exchange
EXG A,YL A ↔ YL 61 1
Data word
EXGW - - - - - - - EXGW X,Y X↔Y 51 1
exchange
Halt oscillator CC.I0 ← 0 , CC.I1 ← 1
HALT (CPU + - 1 - 0 - - - HALT Oscillator stopped till an 8E 10
Peripherals) interrupt occurs
66/162 Doc ID 13590 Rev 3

Cycles(1)
Mnemo
Pipe
Set if sign overflow Set if sign overflow

cleared otherwise
cleared otherwise
Set if R7 is set
Set if R=$00
Increment byte M(M(longmem).w + X) ←
INC - - - - INC ([$1234.w],X) 72 6C ww bb 4
by one M(M(longmem).w + X) + 1
cleared otherwise
cleared otherwise
Set if R15 is set
Set if R=$0000
Increment word
INCW - - - - INCW X X←X+1 5C 2
by one
INT Interrupt - - - - - - - INT $123456 PC ← extmem 82 ee ww bb 2

(++SP)
CC ← M(++SP)
Updated according to the value pop A ← M(++SP)
from the stack into CC register X ← M(++SP); SP++
IRET Interrupt return IRET 80 11 Flush
Y ← M(++SP); SP++
PCE ← M(++SP)
PCH ← M(++SP)
PCL ← M(++SP)
Jump to an
JP address in - - - - - - - JP ([$1234.w],X) PC ← M(longmem).w + X 72 DC ww bb 5 Flush
section 0
Jump to
JPF an extended - - - - - - - JPF $123456 PC ← extmem AC ee ww bb 2 Flush
address
Unconditional
JRA - - - - - - - JRA Label PC ← PC + 2+ rr 20 bb 2 Flush
relative jump
if CC.C =1
Flush
JRC Jump if C = 1 - - - - - - - JRC Label then PC ← PC + 2+ rr 25 bb 1/2 (2)
else PC ← PC + 2
if CC.Z = 1
Jump if Z = Flush
JREQ - - - - - - - JREQ Label then PC ← PC + 2+ rr 27 bb 1/2 (2)
1(equal)
else PC ← PC + 2
JRF Never Jump - - - - - - - JRF Label ---------------- 21 bb 1
if CC.H = 1
Flush
JRH Jump if H = 1 - - - - - - - JRH Label then PC ← PC + 2+ rr 90 29 bb 1/2 (2)
else PC ← PC + 2
if Port INT pin =1
Jump if Port INT Flush
JRIH - - - - - - - JRIH Label then PC ← PC + 2+ rr 90 2F bb 1/2 (2)
pin = 1
else PC ← PC + 2
if Port INT pin = 0
Jump if Port INT Flush
JRIL - - - - - - - JRIL Label then PC ← PC + 2+ rr 90 2E bb 1/2 (2)
pin = 0
else PC ← PC + 2
Jump if if I0 AND I1 = 1
Flush
JRM Interrupts are - - - - - - - JRM Label then PC ← PC + 2 + rr 90 2D bb 1/2 (2)
masked else PC ← PC + 2
if CC.N = 1
Jump if N = Flush
JRMI - - - - - - - JRMI Label then PC ← PC + 2+ rr 2B bb 1/2 (2)
1(minus)
else PC ← PC + 2
if CC.C =0
Flush
JRNC jump if C = 0 - - - - - - - JRNC Label then PC ← PC + 2+ rr 24 bb 1/2 (2)
else PC ← PC + 2
Doc ID 13590 Rev 3 67/162

Cycles(1)
Mnemo
Pipe
if CC.Z = 0
Jump if Z =0 Flush
JRNE - - - - - - - JRNE Label then PC ← PC + 2+ rr 26 bb 1/2 (2)
(not equal)
else PC ← PC + 2
if CC.H = 0
Flush
JRNH Jump if H = 0 - - - - - - - JRNH Label then PC ← PC + 2+ rr 90 28 bb 1/2 (2)
else PC ← PC + 2
Jump if if I0 AND I1= 0
Flush
JRNM Interrupts are - - - - - - - JRNM Label then PC ← PC + 2 + rr 90 2C bb 1/2 (2)
not masked else PC ← PC + 2
if CC.C =0
Flush
JRNV jump if V = 0 - - - - - - - JRNV Label then PC ← PC + 2+ rr 28 bb 1/2 (2)
else PC ← PC + 2
if CC.N = 0
Jump if Flush
JRPL - - - - - - - JRPL Label then PC ← PC + 2+ rr 2A bb 1/2 (2)
N = 0 (plus)
else PC ← PC + 2
if (CC.N xor CC.V) = 0
Jump if Flush
JRSGE - - - - - - - JRSGE Label then PC ← PC + 2+ rr 2E bb 1/2 (2)
(N xor V) = 0
else PC ← PC + 2
if (CC.Z or (CC.N xor
Jump if
CC.V)) = 0 Flush
JRSGT (Z or (N xor V)) - - - - - - - JRSGT Label 2C bb 1/2 (2)
then PC ← PC + 2+ rr
=0
else PC ← PC + 2
if (CC.Z or (CC.N xor
Jump if
CC.V)) = 1 Flush
JRSLE (Z or (N xor V)) - - - - - - - JRSLE Label 2D bb 1/2 (2)
then PC ← PC + 2+ rr
=1
else PC ← PC + 2
if (CC.N xor CC.V) = 1
Jump if Flush
JRSLT - - - - - - - JRSLT Label then PC ← PC + 2+ rr 2F bb 1/2 (2)
(N xor V) = 1
else PC ← PC + 21
JRT Jump relative - - - - - - - JRT Label PC ← PC + 2+ rr 20 bb 2 Flush
if CC.C = 0
Flush
JRUGE Jump if C = 0 - - - - - - - JRUGE Label then PC ← PC + 2+ rr 24 bb 1/2 (2)
else PC ← PC + 2
if (CC.C = 0 and CC.Z = 0)
Jump if
JRUGT - - - - - - - JRUGT Label then PC ← PC + 2+ rr 22 bb 1/2 Flush
(C+Z = 0)
else PC ← PC + 2
if (CC.C = 1 and CC.Z = 1)
Jump if
JRULE - - - - - - - JRULE Label then PC ← PC + 2+ rr 23 bb 1/2 Flush
(C+Z =1)
else PC ← PC + 2
if CC.C = 1
Flush
JRULT Jump if C = 1 - - - - - - - JRULT Label then PC ← PC + 2+ rr 25 bb 1/2 (2)
else PC ← PC + 21
if CC.V =1
JRV Jump if V = 1 - - - - - - - JRV Label then PC ← PC + 2+ rr 29 bb 1/2 Flush
else PC ← PC + 2
A register load LD A,($12,SP) A ← M(SP+shortoff) 7B bb 1
cleared otherwise
cleared otherwise
Set if R7 is set
Set if R=$00
A register store LD ($12,SP),A M(SP+shortoff) ← A 6B bb 1

LD - - - - -
Register to
- - LD A, XH A ← XH 95 1
register move
68/162 Doc ID 13590 Rev 3

Cycles(1)
Mnemo
Pipe
AF ee ww
LDF A,($123456,X) A ← M(X+extoff) 1
bb
90 AF ee ww
A ← M(Y+extoff)
cleared otherwise
cleared otherwise
LDF A,($123456,Y) 1
bb
Set if R7 is set
Set if R=$00
Data load /
store LDF A,([$1234.e],X) A ← M(X+[longptr.e]) 92 AF ww bb 5
LDF - - - - -
with extended A7 ee ww
address LDF ($123456,X),A M(X+extoff) ← A 1
bb
90 A7 ee ww
LDF ($123456,Y),A M(Y+extoff) ← A 1
bb
LDF ([1234.e],X),A M(X+[longptr.e]) ← A 92 A7 ww bb 5
X register load LDW X,($12,SP) X ← M(SP+shortoff) 1E bb 2
cleared otherwise
cleared otherwise
Set if R15 is set
Set if R=$0000
X register store LDW ($12,SP),X M(SP+shortoff) ← X 1F bb 2

Y register load LDW Y,($12,SP) Y ← M(SP+shortoff) 16 bb 2
Y register store LDW ($12,SP),Y M(SP+shortoff) ← Y 17 bb 2

LDW - - - - -
SP register load LDW SP,X SP ← X 94 1

/ store LDW X,SP X ← SP 96 1
- -
Index register
LDW X, Y X←Y 93 1
move
MOV $1234,#$12 M(longmem) ← imm.b 35 ii ww bb 1
MOV $12,$34 M(mem1.b) ←
44 b2 b1 1
MOV Data byte move - - - - - - - MOV mem1,mem2 M(mem2.b)
MOV $1234,$5678 M(mem1.w) ← 45 w2 b2 w1
1
MOV mem1,mem2 M(mem2.w) b1
8 by 8 MUL X,A X ← X*A 42 4
MUL multiplication - - 0 - - - 0
(unsigned) MUL Y,A Y ← Y*A 90 42 4
cleared otherwise

Cleared if R=$0000 Cleared if R=$00
Set if R7 is set
set otherwise
Set if M=$80
Set if R=$00
Logical 2’s M(M(longmem) + X) ←

NEG - - - NEG ([$1234.w],X) 72 60 ww bb 4
complement 00 - M(M(longmem) + X)
cleared otherwise
Set if R15 is set
Set if R=$0000
Set if X=$8000
set otherwise
Logical 2’s
NEGW - - - NEGW X X ← 0000 - X 50 2
complement
NOP No operation - - - - - - - NOP --------- 9D 1

cleared otherwise
cleared otherwise
Set if R7 is set
Set if R=$00
OR Logical OR - - - - - OR A,($12,SP) A ← A OR M(SP+shortoff) 1A bb 1
Pop data byte

- - - - - - - POP $1234 M(longmem) ← M(++SP) 32 ww bb 1
from stack
POP Pop
code condition POP CC CC ← M(++SP) 86 1
register
Doc ID 13590 Rev 3 69/162

Cycles(1)
Mnemo
Pipe
Pop index
XH ← M(++SP)
POPW register from - - - - - - - POPW X 85 2
XL ← M(++SP)
stack
Push PUSH $1234 M(SP--) ← M(longmem) 3B ww bb 1
PUSH data byte onto - - - - - - -
stack PUSH #$12 M(SP--) ← imm.b 4B bb 1
Push index
M(SP--) ← XL
PUSHW register onto - - - - - - - PUSHW X 89 2
M(SP--) ← XH
stack
RCF Reset carry flag - - - - - - 0 RCF CC.C ← 0 98 1
Subroutine
PCH ← M(++SP)
RET return - - - - - - - RET 81 4 Flush
PCL ← M(++SP)
from section 0
Subroutine
PCE ← M(++SP)
return
RETF - - - - - - - RETF PCH ← M(++SP) 87 5 Flush
from extended
PCL ← M(++SP)
address
Reset interrupt
RIM mask/ - 1 - 0 - - - RIM CC.I1 ← 1 9A 1
Interrupt enable
Bit 7 of the byte before rotation Bit 7 of the byte before rotation
R0 ← CC.C
R1 ← bit 0
cleared otherwise
cleared otherwise
R2 ← bit 1
Set if R7 is set
Set if R=$00
Rotate left R3 ← bit 2

RLC logical through - - - - RLC ([$1234.w],X) R4 ← bit 3 72 69 ww bb 4
carry R5 ← bit 4
R6 ← bit 5
R7 ← bit 6
CC.C ← bit 7
R0 ← CC.C
R1 ← bit 0
cleared otherwise
cleared otherwise
Set if R15 is set
Set if R=$0000
R2 ← bit 1
Rotate word left
...
RLCW logical through - - - - RLCW X 59 2
R13 ← bit 12
carry
R14 ← bit 13
R15 ← bit 14
CC.C ← bit 15
cleared otherwise
cleared otherwise
Set if R15 is set
Set if R=$0000
Rotate word left A ← XH

RLWA through - - - - - RLWA X XH ← XL 02 1
Accumulator XL ← A
Bit 0 of the byte before rotation
R7 ← CC.C
R6 ← bit 7
cleared otherwise
cleared otherwise
R5 ← bit 6
Set if R7 is set
Set if R=$00
Rotate right R4 ← bit 5

RRC logical through - - - - RRC ([$1234.w],X) R3 ← bit 4 72 66 ww bb 4
carry R2 ← bit 3
R1 ← bit 2
R0 ← bit 1
CC.C ← bit 0
70/162 Doc ID 13590 Rev 3

Cycles(1)
Mnemo
Pipe
Bit 0 of the byte before rotation

R15 ← CC.C
R14 ← bit 15
cleared otherwise
cleared otherwise
Set if R7 is set
Set if R=$00
R13 ← bit 14
Rotate word
...
RRCW right logical - - - - RRCW X 56 2
R2 ← bit 3
through carry
R1 ← bit 2
R0 ← bit 1
CC.C ← bit 0
cleared otherwise
cleared otherwise
Set if R15 is set
Set if R=$0000
Rotate word A ← XL
RRWA right through - - - - - RRWA X XL ← XH 01 1
Accumulator XH ← A
Reset overflow
RVF 0 - - - - - - RVF CC.V ← 0 9C 1
flag
Set if the signed subtraction generates
an overflow, cleared otherwise

cleared otherwise
cleared otherwise
cleared otherwise
Set if R7 is set
Set if R=$00
Subtract with A ← A -M(SP+shortoff) -

SBC - - - SBC A,($12,SP) 12 bb 1
carry CC.C
SCF Set Carry Flag - - - - - - 1 SCF CC.C ← 1 99 1

Set interrupt
mask/ CC.I0 ← 1
SIM - 1 - 1 - - - SIM 9B 1
Disable CC.I1 ← 1
interrupts
Bit 7 of the byte before shifting
R0 ← 0
R1 ← bit 0
cleared otherwise
cleared otherwise
R2 ← bit 1
Set if R7 is set
Set if R=$00
R3 ← bit 2
Shift left
SLA - - - - SLA ([$1234.w],X) R4 ← bit 3 72 68 ww bb 4
arithmetic
R5 ← bit 4
R6 ← bit 5
R7 ← bit 6
CC.C ← bit 7
Doc ID 13590 Rev 3 71/162

Cycles(1)
Mnemo
Pipe

R0 ← 0
R1 ← bit 0
cleared otherwise
cleared otherwise
Set if R15 is set
Set if R=$0000
R2 ← bit 1
Shift word left R3 ← bit 2
SLAW - - - - SLAW X 58 2
arithmetic .....
R14 ← bit 13
R15 ← bit 14
CC.C ← bit 15
Bit 7 of the byte before shifting R0 ← 0

R1 ← bit 0
cleared otherwise
cleared otherwise
R2 ← bit 1
Set if R7 is set
Set if R=$00
R3 ← bit 2
SLL Shift left logical - - - - SLL ([$1234.w],X) R4 ← bit 3 72 68 ww bb 4
R5 ← bit 4
R6 ← bit 5
R7 ← bit 6
CC.C ← bit 7
R0 ← 0
R1 ← bit 0
cleared otherwise
cleared otherwise
Set if R15 is set
Set if R=$0000
R2 ← bit 1
Shift word left R3 ← bit 2
SLLW - - - - SLLW X 58 2
logical .....
R14 ← bit 13
R15 ← bit 14
CC.C ← bit 15
CC.C ← bit 0
R0 ← bit 1
cleared otherwise
cleared otherwise
R1 ← bit 2
Set if R7 is set
Set if R=$00
R2 ← bit 3
Shift right
SRA - - - - SRA ([$1234.w],X) R3 ← bit 4 72 67 ww bb 4
arithmetic
R4 ← bit 5
R5 ← bit 6
R6 ← bit 7
R7 ← bit 7 (unchanged)
CC.C ← bit 0
R0 ← bit 1
cleared otherwise
cleared otherwise
cleared otherwise
Set if R15 is set
R1 ← bit 2
Set if R=$0000
Set if R7 set
R2 ← bit 3
Shift word right
SRAW - - - SRAW X .... 57 2
arithmetic
R12 ← bit 13
R13 ← bit 14
R14 ← bit 15
R15 ← bit 15 (unchanged)
72/162 Doc ID 13590 Rev 3

Cycles(1)
Mnemo
Pipe

CC.C ← bit 0
R0 ← bit 1
cleared otherwise
cleared otherwise
R1 ← bit 2
Set if R=$00
Set if R7 set
R2 ← bit 3
Shift right
SRL - - - - SRL ([$1234.w],X) R3 ← bit 4 72 64 ww bb 4
logical
R4 ← bit 5
R5 ← bit 6
R6 ← bit 7
R7 ← 0

CC.C ← bit 0
R0 ← bit 1
cleared otherwise
cleared otherwise
R1 ← bit 2
Set if R=$0000
Set if R15 set
R2 ← bit 3
Shift word right
SRLW - - - - SRLW X .... 54 2
arithmetic
R12 ← bit 13
R13 ← bit 14
R14 ← bit 15
R15 ← 0
Set if the signed operation generates
an overflow, cleared otherwise

cleared otherwise
cleared otherwise
cleared otherwise
Set if R7 is set
Set if R=$00
- - - SUB A,($12,SP) A ← A -M(SP+shortoff) 10 bb 1

Subtract without
SUB
carry
- - - - - - - SUB SP,#$12 SP ← SP + imm.b 52 ii 2

(unsigned values) cleared otherwise
Set if dst < mem (unsigned values)

Set if X< mem (unsigned 16-bit
values), cleared otherwise
Set if dst(7:0)< mem(7:0)
cleared otherwise
cleared otherwise
cleared otherwise
Set if R15 is set
Set if R=$0000
Subtract word
SUBW - - SUBW X,($12,SP) X ← X -M(SP+shortoff) 72 F0 bb 2
without carry
cleared otherwise
cleared otherwise
Set if R7 is set
Set if R=$00
R0 ↔ R4
R1 ↔ R5
SWAP Swap nibbles - - - - - SWAP ([$1234.w],X) 72 6E ww bb 4
R2 ↔ R6
R3 ↔ R7
Doc ID 13590 Rev 3 73/162

Cycles(1)
Mnemo
Pipe
R0 ↔ R8
R1 ↔ R9
cleared otherwise
cleared otherwise
Set if R15 is set
Set if R=$0000
R2 ↔ R10
R3 ↔ R11
SWAPW Swap bytes - - - - - SWAPW X 5E 1
R4 ↔ R12
R5 ↔ R13
R6 ↔ R14
R7 ↔ R15

Set if R7 is set
Test for Set if R=$00 CC.N ← R7

TNZ - - - - - TNZ ([$1234.w],X) CC.Z ← 1 if R=$00 72 6D ww bb 4
negative or zero
← 0 otherwise
Set if R15 is set
Set if R=$0000
CC.N ← R15
Test word for
TNZW - - - - - TNZW X CC.Z ← 1 if R=$0000 5D 2
negative or zero
← 0 otherwise
PC ← PC+1
M(SP--) ← PCL
M(SP--) ← PCH
M(SP--) ← PCE
M(SP--) ← YL
Software M(SP--) ← YH
TRAP - 1 - 1 - - - TRAP 83 9 Flush
interrupt M(SP--) ← XL
M(SP--) ← XH
M(SP--) ← A
M(SP--) ← CC
PC ← TRAP vector
address
Wait for event CPU clock stopped till the
(CPU stopped, event input is activated.
WFE - - - - - - - WFE 72 8F 1
Low power Internal peripherals are
mode) still running
Wait for CC.I0 ← 0, CC.I1 ← 1
interrupt CPU clock stopped till an
WFI (CPU stopped, - 1 - 0 - - - WFI interrupt occurs. Internal 8F 10
Low power peripherals are still
mode) running
cleared otherwise
cleared otherwise
Set if R7 is set
Set if R=$00
Logical A ← A XOR
XOR - - - - - XOR A,($12,SP) 18 bb 1
exclusive OR M(SP+shortoff)
1. Number of cycles corresponding to the example op-code.

2. If branch taken.
7.4 Instruction set

The following pages give a detailed description of each STM8 instruction.
74/162 Doc ID 13590 Rev 3

ADC Addition with Carry ADC

Syntax ADC A, src e.g. ADC A,#$15
Operation A <= A+ src + C
Description The source byte, along with the carry flag, is added to the contents of the
accumulator and the result is stored in the accumulator. This instruction is
useful for addition of operands that are larger than eight.
The source is
a memory or data byte.
Instruction overview:
Affected condition flags

mnem dst src
V I1 H I0 N Z C
ADC A Mem V - H - N Z C
V⇒ (A7.M7 + M7.R7 + R7.A7) ⊕ (A6.M6 + M6.R6 + R6.A6)

Set if the signed operation generates an overflow, cleared otherwise.
H⇒ A3.M3 + M3.R3 + R3.A3
Set if a carry occurred from bit 3 of the result, cleared otherwise.
N⇒ R7
Set if bit 7 of the result is set (negative value), cleared otherwise.
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0
Set if the result is zero (0x00), cleared otherwise.
C⇒ A7.M7 + M7.R7 + R7.A7
Doc ID 13590 Rev 3 75/162

Detailed description:
dst src Asm cy lgth Op-code(s) ST7

A #byte ADC A,#$55 1 2 A9 XX ✗
A shortmem ADC A,$10 1 2 B9 XX ✗
A longmem ADC A,$1000 1 3 C9 MS LS ✗
A (X) ADC A,(X) 1 1 F9 ✗
A (shortoff,X) ADC A,($10,X) 1 2 E9 XX ✗
A (longoff,X) ADC A,($1000,X) 1 3 D9 MS LS ✗
A (Y) ADC A,(Y) 1 2 90 F9 ✗
A (shortoff,Y) ADC A,($10,Y) 1 3 90 E9 XX ✗
A (longoff,Y) ADC A,($1000,Y) 1 4 90 D9 MS LS ✗
A (shortoff,SP) ADC A,($10,SP) 1 2 19 XX
A [shortptr.w] ADC A,[$10.w] 4 3 92 C9 XX ✗
A [longptr.w] ADC A,[$1000.w] 4 4 72 C9 MS LS
A ([shortptr.w],X) ADC A,([$10.w],X) 4 3 92 D9 XX ✗
A ([longptr.w],X) ADC A,([$1000.w],X) 4 4 72 D9 MS LS
A ([shortptr.w],Y) ADC A,([$10.w],Y) 4 3 91 D9 XX ✗
See also: ADD, SUB, SBC, MUL, DIV
76/162 Doc ID 13590 Rev 3

ADD Addition ADD

Syntax ADD A,src e.g. ADD A,#%11001010
Operation A <= A+ src
Description The source byte is added to the contents of the accumulator and the result
is stored in the accumulator. The source is a memory or data byte.
Instruction overview

mnem dst src
V I1 H I0 N Z C
ADD A Mem V - H - N Z C
V⇒ (A7.M7 + M7.R7 + R7.A7) ⊕ (A6.M6 + M6.R6 + R6.A6)

H⇒ A3.M3 + M3.R3 + R3.A3
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0
C⇒ A7.M7 + M7.R7 + R7.A7
Detailed description

A #byte ADD A,#$55 1 2 AB XX ✗
A shortmem ADD A,$10 1 2 BB XX ✗
A longmem ADD A,$1000 1 3 CB MS LS ✗
A (X) ADD A,(X) 1 1 FB ✗
A (shortoff,X) ADD A,($10,X) 1 2 EB XX ✗
A (longoff,X) ADD A,($1000,X) 1 3 DB MS LS ✗
A (Y) ADD A,(Y) 1 2 90 FB ✗
A (shortoff,Y) ADD A,($10,Y) 1 3 90 EB XX ✗
A (longoff,Y) ADD A,($1000,Y) 1 4 90 DB MS LS ✗
A (shortoff,SP) ADD A,($10,SP) 1 2 1B XX
A [shortptr.w] ADD A,[$10.w] 4 3 92 CB XX ✗
A [longptr.w] ADD A,[$1000.w] 4 4 72 CB MS LS
A ([shortptr.w],X) ADD A,([$10.w],X) 4 3 92 DB XX ✗
A ([longptr.w],X) ADD A,([$1000.w],X) 4 4 72 DB MS LS
A ([shortptr.w],Y) ADD A,([$10.w],Y) 4 3 91 DB XX ✗
See also: ADDW, ADC, SUB, SBC, MUL, DIV
Doc ID 13590 Rev 3 77/162

ADDW Word Addition with index registers ADDW

Syntax ADDW dst,src e.g. ADDW X,#$1000
Operation dst <= dst + src
Description The source (16-bit) is added to the contents of the destination, which is an
index register (X/Y) and the result is stored in the same index register. The
source is a 16-bit memory or data word. The ADDW instruction can also be
used to add an immediate value to the stack pointer (SP).

mnem dst src
V I1 H I0 N Z C
ADDW X Mem V - H - N Z C
ADDW Y Mem V - H - N Z C
ADDW SP Imm - - - - - - -
V⇒ (A15.M15 + M15.R15 + R15.A15) ⊕ (A14.M14 + M14.R14 + R14.A14)

H⇒ X7.M7 + M7.R7 + R7.X7
N⇒ R15
Z⇒ R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
C⇒ X15.M15 + M15.R15 + R15.X15

X #word ADDW X,#$1000 2 3 1C MS LS
X longmem ADDW X,$1000 2 4 72 BB MS LS
X (shortoff,SP) ADDW X,($10,SP) 2 3 72 FB XX
Y #word ADDW Y,#$1000 2 4 72 A9 MS LS
Y longmem ADDW Y,$1000 2 4 72 B9 MS LS
Y (shortoff,SP) ADDW Y,($10,SP) 2 3 72 F9 XX
SP #byte ADDW SP,#$9 2 2 5B XX
See also: ADD, ADC, SUB, SBC, MUL, DIV
78/162 Doc ID 13590 Rev 3

AND Logical AND AND

Syntax AND A,src e.g. AND A,#%00110101
Operation A <= A AND src
Description The source byte, is ANDed with the contents of the accumulator and the
result is stored in the accumulator. The source is a memory or data byte.
Truth table:
AND 0 1
0 0 0
1 0 1

mnem dst src
V I1 H I0 N Z C
AND A Mem - - - - N Z -
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0

A #byte AND A,#$55 1 2 A4 XX ✗
A shortmem AND A,$10 1 2 B4 XX ✗
A longmem AND A,$1000 1 3 C4 MS LS ✗
A (X) AND A,(X) 1 1 F4 ✗
A (shortoff,X) AND A,($10,X) 1 2 E4 XX ✗
A (longoff,X) AND A,($1000,X) 1 3 D4 MS LS ✗
A (Y) AND A,(Y) 1 2 90 F4 ✗
A (shortoff,Y) AND A,($10,Y) 1 3 90 E4 XX ✗
A (longoff,Y) AND A,($1000,Y) 1 4 90 D4 MS LS ✗
A (shortoff,SP) AND A,($10,SP) 1 2 14 XX
A [shortptr.w] AND A,[$10.w] 4 3 92 C4 XX ✗
A [longptr.w] AND A,[$1000.w] 4 4 72 C4 MS LS
A ([shortptr.w],X) AND A,([$10.w],X) 4 3 92 D4 XX ✗
AND
A ([longptr.w],X) 4 4 72 D4 MS LS
A,([$1000.w],X)
A ([shortptr.w],Y) AND A,([$1000],Y) 4 3 91 D4 XX ✗
See also: OR, XOR, CPL, NEG
Doc ID 13590 Rev 3 79/162

BCCM Copy Carry Bit to Memory BCCM

Syntax BCCM dst, #pos (pos=0..7) e.g. BCCM $1234,#1
Operation dst(pos) <= CC.C
Description Copies the Carry flag of the Condition Code (CC) register in the bit
position of the memory location given by the destination address.
M(longmem).bit <- CC.C

mnem dst bit position
V I1 H I0 N Z C
BCCM Mem #pos - - - - - - -
dst pos = 0..7 Asm cy lgth Op-code(s) ST7

longmem n =1+2*pos BCCM $1000,#2 1 4 90 1n MS LS
See also: LD, RCF, SCF
80/162 Doc ID 13590 Rev 3

BCP Logical Bit Compare BCP
Syntax BCP A,src

Operation {N, Z} <= A AND src
Description The source byte, is ANDed to the contents of the accumulator. The result is
lost but condition flags N and Z are updated accordingly. The source is a
memory or data byte. This instruction can be used to perform bit tests on
A.

mnem dst src
V I1 H I0 N Z C
BCP A Mem - - - - N Z -
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0

A #byte BCP A,#$55 1 2 A5 XX ✗
A shortmem BCP A,$10 1 2 B5 XX ✗
A longmem BCP A,$1000 1 3 C5 MS LS ✗
A (X) BCP A,(X) 1 1 F5 ✗
A (shortoff,X) BCP A,($10,X) 1 2 E5 XX ✗
A (longoff,X) BCP A,($1000,X) 1 3 D5 MS LS ✗
A (Y) BCP A,(Y) 1 2 90 F5 ✗
A (shortoff,Y) BCP A,($10,Y) 1 3 90 E5 XX ✗
A (longoff,Y) BCP A,($1000,Y) 1 4 90 D5 MS LS ✗
A (shortoff,SP) BCP A,($10,SP) 1 2 15 XX
A [shortptr.w] BCP A,[$10.w] 4 3 92 C5 XX ✗
A [longptr.w] BCP A,[$1000.w] 4 4 72 C5 MS LS
A ([shortptr.w],X) BCP A,([$10.w],X) 4 3 92 D5 XX ✗
A ([longptr.w],X) BCP A,([$1000.w],X) 4 4 72 D5 MS LS
A ([shortptr.w],Y) BCP A,([$10.w],Y) 4 3 91 D5 XX ✗
See also: CP, TNZ
Doc ID 13590 Rev 3 81/162

BCPL Bit Complement BCPL
Syntax BCPL dst, #pos (pos=0..7) e.g. BCPL PADR,#4

Operation dst(pos) <= 1 - dst(pos)
Description Complements the bit position in destination location. Leaves all other bits
unchanged.
M(longmem).bit <- -M(longmem).bit

mnem dst
V I1 H I0 N Z C
BCPL Mem - - - - - - -

longmem n = 2*pos BCPL $1000,#2 1 4 90 1n MS LS
See also: CPL, BRES, BSET
82/162 Doc ID 13590 Rev 3

BREAK Software break BREAK

Syntax
Operation
Description In debug mode, the CPU is stalled and can be restarted by the debugger.
This instruction equals a NOP when the debugger is not connected.

mnem
V I1 H I0 N Z C
SIM - 1 - 1 - - -
Addressing
Asm cy lgth Op-code(s) ST7
mode
Inherent BREAK 1 1 8B ✗
Doc ID 13590 Rev 3 83/162

BRES Bit Reset BRES

Syntax BRES dst,#pos pos = [0..7] e.g. BRES PADR,#6
Operation dst <= dst AND COMPLEMENT (2**pos)
Description Read the destination byte, reset the corresponding bit (bit position), and
write the result in destination byte. The destination is a memory byte. The
bit position is a constant. This instruction is fast, compact, and does not
affect any register. Very useful for boolean variable manipulation.

V I1 H I0 N Z C
BRES Mem #pos - - - - - - -

longmem n=1+2*pos BRES $1000,#7 1 4 72 1n MS LS
See also: BSET
84/162 Doc ID 13590 Rev 3

BSET Bit Set BSET

Syntax BSET dst,#pos pos = [0..7] e.g. BSET PADR,#7
Operation dst <= dst OR (2**pos)
Description Read the destination byte, set the corresponding bit (bit position), and write
the result in destination byte. The destination is a memory byte. The bit
position is a constant. This instruction is fast, compact, and does not affect
any register. Very useful for boolean variable manipulation.

V I1 H I0 N Z C
BSET Mem #pos - - - - - - -

longmem n=2*pos BSET $1000,#1 1 4 72 1n MS LS
See also: BRES
Doc ID 13590 Rev 3 85/162

BTJF Bit Test and Jump if False BTJF
Syntax BTJF dst,#pos,rel pos = [0..7], rel is relative jump label

e.g.: BTJFPADR,#3,skip
Operation PC = PC+lgth
PC = PC + rel IF (dst AND (2**pos)) = 0
Description Read the destination byte, test the corresponding bit (bit position), and
jump to 'rel' label if the bit is false (0), else continue the program to the next
instruction. The tested bit is saved in the C flag. The destination is a
memory byte. The bit position is a constant. The jump label represents a
signed offset to be added to the current PC/instruction address (relative
jump). This instruction is used for boolean variable manipulation, hardware
register flag tests, or I/O polling. This instruction is fast, compact, and does
not affect any registers. Very useful for boolean variable manipulation.

mnem dst bit position jump label
V I1 H I0 N Z C
BTJF Mem #pos rel - - - - - - C
C ⇒Tested bit is saved in the C flag.


BTJF
longmem n = 1+2*pos 2/3 5 72 0n MS LS XX
$1000,#1,loop
See also: BTJT
86/162 Doc ID 13590 Rev 3

BTJT Bit Test and Jump if True BTJT
Syntax BTJT dst,#pos,rel pos = [0..7], rel is relative jump label

e.g.: BTJT PADR,#7,skip
PC = PC + rel IF (dst AND (2**pos)) <> 0
Description Read the destination byte, test the corresponding bit (bit position), and
jump to 'rel' label if the bit is true (1), else continue the program to the next
instruction. The tested bit is saved in the C flag. The destination is a
memory byte. The bit position is a constant. The jump label represents a
signed offset to be added to the current PC/instruction address (relative
jump). This instruction is used for boolean variable manipulation, hardware
register flag tests, or I/O polling.

mnem dst bit position jump label
V I1 H I0 N Z C
BTJT Mem #pos rel - - - - - - C
C⇒ Tested bit is saved in the C flag.


BTJT
longmem n= 2*pos 2/3 5 72 0n MS LS XX
$1000,#1,loop
See also: BTJF
Doc ID 13590 Rev 3 87/162

CALL CALL Subroutine CALL

(Absolute)
(SP--) = PCL
(SP--) = PCH
PC = dst
Description The current PC register value is pushed onto the stack, then PC is loaded
with the destination address in same section of memory. The CALL
destination and the instruction following the CALL should be in the same
section as PCE is not stacked. The corresponding RET instruction should
be executed in the same section. This instruction should be used versus
CALLR when developing a program.

mnem dst
V I1 H I0 N Z C
CALL Mem - - - - - - -
dst Asm cy lgth Op-code(s) ST7

longmem CALL $1000 4 3 CD MS LS ✗
(X) CALL(X) 4 1 FD ✗
(shortoff,X) CALL($10,X) 4 2 ED XX ✗
(longoff,X) CALL($1000,X) 4 3 DD MS LS ✗
(Y) CALL(Y) 4 2 90 FD ✗
(shortoff,Y) CALL($10,Y) 4 3 90 ED XX ✗
(longoff,Y) CALL($1000,Y) 4 4 90 DD MS LS ✗
[shortptr.w] CALL[$10.w] 6 3 92 CD XX ✗
[longptr.w] CALL[$1000.w] 6 4 72 CD MS LS
([shortptr.w],X) CALL([$10.w],X) 6 3 92 DD XX ✗
([longptr.w],X) CALL([$1000.w],X) 6 4 72 DD MS LS
([shortptr.w],Y) CALL([$10.w],Y) 6 3 91 DD XX ✗
See also:RET, CALLR, CALLF
88/162 Doc ID 13590 Rev 3

CALLF CALL Far Subroutine CALLF

Syntax CALLF dst e.g. CALLF label
(SP--) = PCL
(SP--) = PCH
(SP--) = PCE
PC = dst
with the destination address.This instruction is used with extended memory
addresses. For safe memory usage, a function which crosses sections
must be called by CALLF.

mnem dst
V I1 H I0 N Z C
CALLF Mem - - - - - - -

extmem CALLF $35AA00 5 4 8D ExtB MS LS
[longptr.e] CALLF [$2FFC.e] 8 4 92 8D MS LS
See also: RETF, CALL, JPF
Doc ID 13590 Rev 3 89/162

CALLR CALL Subroutine Relative CALLR
Syntax CALLR dst e.g. CALLR chk_pol

(SP--) = PCL
(SP--) = PCH
PC = PC + dst
with the relative destination address. This instruction is used, once a
program is debugged, to shrink the overall program size. The CALLR
destination and the corresponding RET instruction address must be in the
same section, as PCE is not stacked.

mnem dst
V I1 H I0 N Z C
CALLR Mem - - - - - - -

shortmem CALLR $10 4 2 AD XX ✗
See also: CALL, RET
90/162 Doc ID 13590 Rev 3

CCF Complement Carry Flag CCF

Syntax CCF
Operation CC.C <- CC.C
Description Complements the Carry flag of the Condition Code (CC) register.

mnem
V I1 H I0 N Z C
CCF - - - - - - C
C =C ,
Complements the carry flag of the CC register.
Addressing
mode
Inherent CCF 1 1 8C
See also: RCF, SCF
Doc ID 13590 Rev 3 91/162

CLR Clear CLR

Syntax CLR dst e.g. CLR A
Operation dst <= 00
Description The destination byte is forced to 00 value. The destination is either a
memory byte location or the accumulator. This instruction is compact, and
does not affect any register when used with RAM variables.

mnem dst
V I1 H I0 N Z C
CLR Mem - - - - 0 1 -
CLR A 0 1
N: 0
Cleared
Z: 1
Set

A CLR A 1 1 4F ✗
shortmem CLR $10 1 2 3F XX ✗
longmem CLR $1000 1 4 72 5F MS LS
(X) CLR (X) 1 1 7F ✗
(shortoff.X) CLR ($10,X) 1 2 6F XX ✗
(longoff,X) CLR ($1000,X) 1 4 72 4F MS LS
(Y) CLR (Y) 1 2 90 7F ✗
(shortoff,Y) CLR ($10,Y) 1 3 90 6F XX ✗
(longoff,Y) CLR ($1000,Y) 1 4 90 4F MS LS
(shortoff,SP) CLR ($10,SP) 1 2 0F XX
[shortptr.w] CLR [$10] 4 3 92 3F XX ✗
[longptr.w] CLR [$1000].w 4 4 72 3F MS LS
([shortptr.w],X) CLR ([$10],X) 4 3 92 6F XX ✗
CLR
([longptr.w].X] 4 4 72 6F MS LS
([$1000.w],X)
([shortptr.w],Y) CLR ([$10],Y) 4 3 91 6F XX ✗
See also: LD
92/162 Doc ID 13590 Rev 3

CLRW Clear word CLRW

Syntax CLRW dst e.g. CLRW X
Operation dst <= 00
Description The destination is forced to 0000 value. The destination is an index
register.

mnem dst
V I1 H I0 N Z C
CLRW X - - - - 0 1 -
CLRW Y - - - - 0 1 -
N: 0
Cleared
Z: 1
Set

X CLRW X 1 1 5F
Y CLRW Y 1 2 90 5F
See also: LD
Doc ID 13590 Rev 3 93/162

CP Compare CP
Syntax CP dst,src e.g. CP A,(tbl,X)
Operation {N, Z, C} = Test (dst - src)
Description The source byte is subtracted from the destination byte and the result
is lost. However, N, Z, C flags of Condition Code (CC) register are updated
according to the result.The destination is a register, and the source is a
memory or data byte. This instruction generally is used just before a
conditional jump instruction.

mnem dst src
V I1 H I0 N Z C
CP Reg Mem V - - - N Z C
V⇒ (A7.M7 + A7.R7 + A7.M7.R7) ⊕ (A6.M6 + A6.R6 + A6.M6.R6)

Set if the signed subtraction of the destination (dst) value from the
source (src) value generates a signed overflow (signed result cannot be
represented on 8 bits).
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0
C⇒ (A7.M7 + A7.R7 + A7.M7.R7)
Set if the unsigned value of the contents of source (src) is larger than the
unsigned value of the destination (dst), cleared otherwise.

A #byte CP A,#$10 1 2 A1 XX ✗
A shortmem CP A,$10 1 2 B1 XX ✗
A longmem CP A,$1000 1 3 C1 MS LS ✗
A (X) CP A,(X) 1 1 F1 ✗
A (shortoff,X) CP A,($10,X) 1 2 E1 XX ✗
A (longoff,X) CP A,($1000,X) 1 3 D1 MS LS ✗
A (Y) CP A,(Y) 1 2 90 F1 ✗
A (shortoff,Y) CP A,($10,Y) 1 3 90 E1 XX ✗
A (longoff,Y) CP A,($1000,Y) 1 4 90 D1 MS LS ✗
A (shortoff,SP) CP A,($10,SP) 1 2 11 XX
A [shortptr.w] CP A,[$10.w] 4 3 92 C1 XX ✗
A [longptr.w] CP A,[$1000.w] 4 4 72 C1 MS LS
A ([shortptr.w],X) CP A,([$10.w],X) 4 3 92 D1 XX ✗
A ([longptr.w],X) CP A,([$1000.w],X) 4 4 72 D1 MS LS
A ([shortptr.w],Y) CP A,([$10.w],Y) 4 3 91 D1 XX ✗
See also: CPW, TNZ, BCP
94/162 Doc ID 13590 Rev 3

CPW Compare word CPW

Syntax CPW dst,src e.g. CPW Y,(tbl,X)
Operation {N, Z, C} = Test (dst - src)
Description The source byte is subtracted from the destination byte and the result is
lost. However, N, Z, C flags of Condition Code (CC) register are updated
according to the result. The destination is an index register, and the source
is a memory or data word. This instruction generally is used just before a
conditional jump instruction.

mnem dst src
V I1 H I0 N Z C
CPW Reg Mem V - - - N Z C
V⇒ (X15.M15 + X15.R15 + X15.M15.R15) ⊕ (X14.M14 + X14.R14 + X14.M14.R14)

Set if the signed subtraction of the destination (dst) value from the source (src)
value generates a signed overflow (signed result cannot be represented on 16
bits).
N⇒ R15
C⇒ (X15.M15 + X15.R15 + X15.M15.R15)
Set if the unsigned value of the contents of source (src) is larger than the
unsigned value of the destination (dst), cleared otherwise.

X #word CPW X,#$10 2 3 A3 MS LS ✗
X shortmem CPW X,$10 2 2 B3 XX ✗
X longmem CPW X,$1000 2 3 C3 MS LS ✗
X (Y) CPW X,(Y) 2 2 90 F3 ✗
X (shortoff,Y) CPW X,($10,Y) 2 3 90 E3 XX ✗
X (longoff,Y) CPW X,($1000,Y) 2 4 90 D3 MS LS ✗
X (shortoff,SP) CPW X,($10,SP) 2 2 13 XX
X [shortptr.w] CPW X,[$10.w] 5 3 92 C3 XX ✗
X [longptr.w] CPW X,[$1000.w] 5 4 72 C3 MS LS
X ([shortptr.w],Y) CPW X,([$10.w],Y) 5 3 91 D3 XX ✗
Doc ID 13590 Rev 3 95/162

CPW detailed description (Continued)

Y #word CPW Y,#$10 2 4 90 A3 MS LS ✗
Y shortmem CPW Y,$10 2 3 90 B3 XX ✗
Y longmem CPW Y,$1000 2 4 90 C3 MS LS ✗
Y (X) CPW Y,(X) 2 1 F3 ✗
Y (shortoff,X) CPW Y,($10,X) 2 2 E3 XX ✗
Y (longoff,X) CPW Y,($1000,X) 2 3 D3 MS LS ✗
Y [shortptr.w] CPW Y,[$10.w] 5 3 91 C3 XX ✗
Y ([shortptr.w],X) CPW Y,([$10.w],X) 5 3 92 D3 XX ✗
Y ([longptr.w],X) CPW Y,([$1000.w],X) 5 4 72 D3 MS LS
Note: CPW Y, (shortoff, SP) is not implemented, but can be emulated through a macro using
EXGW X,Y & CPW X, (shortoff, SP)
See also: CP, TNZW, BCP
96/162 Doc ID 13590 Rev 3

CPL Logical 1’s Complement CPL

Syntax CPL dst e.g. CPL (X)
Operation dst <= dst XOR FF, or FF - dst
Description The destination byte is read, then each bit is toggled (inverted) and the
result is written to the destination byte. The destination is either a memory
byte or a register. This instruction is compact, and does not affect any
registers when used with RAM variables.

mnem dst
V I1 H I0 N Z C
CPL Mem - - - - N Z 1
CPL Reg - - - - N Z 1
N⇒ R7
Z ⇒R7.R6.R5.R4.R3.R2.R1.R0
C⇒ 1
Set.

A CPL A 1 1 43 ✗
shortmem CPL$10 1 2 33 XX ✗
longmem CPL$1000 1 4 72 53 MS LS
(X) CPL(X) 1 1 73 ✗
(shortoff.X) CPL($10,X) 1 2 63 XX ✗
(longoff,X) CPL($1000,X) 1 4 72 43 MS LS
(Y) CPL(Y) 1 2 90 73 ✗
(shortoff,Y) CPL($10,Y) 1 3 90 63 XX ✗
(longoff,Y) CPL($1000,Y) 1 4 90 43 MS LS
(shortoff,SP) CPL($10,SP) 1 2 03 XX ✗
[shortptr.w] CPL[$10] 4 3 92 33 XX ✗
[longptr.w] CPL[$1000].w 4 4 72 33 MS LS
([shortptr.w],X) CPL([$10],X) 4 3 92 63 XX ✗
([longptr.w].X] CPL([$1000.w],X) 4 4 72 63 MS LS
([shortptr.w],Y) CPL([$10],Y) 4 3 91 63 XX ✗
See also: NEG, XOR, AND, OR
Doc ID 13590 Rev 3 97/162

CPLW Logical 1’s Complement Word CPLW

Syntax CPLW dst e.g. CPLW X
Operation dst <= dst XOR FFFF, or FFFF - dst
Description The destination index register is read, then each bit is toggled (inverted)
and the result is written back to the destination index register.

mnem dst
V I1 H I0 N Z C
CPLW Reg - - - - N Z 1
N⇒ R15
C⇒ 1
Set

X CPLW X 2 1 53 ✗
Y CPWL Y 2 2 90 53 ✗
See also: CPL, NEGW, XOR, AND, OR
98/162 Doc ID 13590 Rev 3

DEC Decrement DEC

Syntax DEC dst
Operation dst <= dst - 1
Description The destination byte is read, then decremented by one, and the result is
written to the destination byte. The destination is either a memory byte or a
register. This instruction is compact, and does not affect any registers when
used with RAM variables.

mnem dst
V I1 H I0 N Z C
DEC Mem V - - - N Z -
DEC Reg V - - - N Z -
V⇒ (A7.M7 + M7.R7 + R7.A7) ⊕ (A6.M6 + M6.R6 + R6.A6)

N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0

A DEC A 1 1 4A ✗
shortmem DEC $10 1 2 3A XX ✗
longmem DEC $1000 1 4 72 5A MS LS
(X) DEC(X) 1 1 7A ✗
(shortoff.X) DEC($10,X) 1 2 6A XX ✗
(longoff,X) DEC($1000,X) 1 4 72 4A MS LS
(Y) DEC(Y) 1 2 90 7A ✗
(shortoff,Y) DEC($10,Y) 1 3 90 6A XX ✗
(longoff,Y) DEC($1000,Y) 1 4 90 4A MS LS
(shortoff,SP) DEC($10,SP) 1 2 0A XX
[shortptr.w] DEC[$10] 4 3 92 3A XX ✗
[longptr.w] DEC[$1000].w 4 4 72 3A MS LS
([shortptr.w],X) DEC([$10],X) 4 3 92 6A XX ✗
([longptr.w].X] DEC([$1000.w],X) 4 4 72 6A MS LS
([shortptr.w],Y) DEC([$10],Y) 4 3 91 6A XX ✗
See also: DECW, INC
Doc ID 13590 Rev 3 99/162

DECW Decrement word DECW

Syntax DECW dst
Operation dst <= dst - 1
Description The value of the destination index register is decremented by one.

mnem dst
V I1 H I0 N Z C
DECW Reg V - - - N Z -
V⇒ (A15.M15 + M15.R15 + R15.A15) ⊕ (A14.M14 + M14.R14 + R14.A14)

N⇒ R15

X DECW X 1 1 5A
Y DECW Y 1 2 90 5A
See also: INCW, DEC
100/162 Doc ID 13590 Rev 3

DIV Divide (unsigned) DIV

Syntax DIV dst,A e.g. DIV X,A
Operation dst <= dst / A (Quotient) A <= dst%A (Remainder)
Description Divides a 16-bit unsigned value, dividend, contained in an index register (X
or Y) by an 8-bit value, divisor, contained in A. The quotient is placed in the
same index register and the remainder is placed in A.
The register values are unchanged in the case of a division by zero.
Note: Note: This instruction is interruptible, generating a latency of 1 cycle only.

mnem dst src
V I1 H I0 N Z C
DIV X A 0 - 0 - 0 Z C
DIV Y A 0 - 0 - 0 Z C
V⇒ 0
Reset.
H⇒ 0
Reset.
N⇒ 0
Reset.
Z⇒ Q15.Q14.Q13.Q12.Q11.Q10.Q9.Q8.Q7.Q6.Q5.Q4.Q3.Q2.Q1.Q0
Set if the quotient is zero (0x0000), cleared otherwise.
C⇒ A7.A6.A5.A4.A3.A2.A1.A0
Set if division by 0, cleared otherwise.

X A DIV X,A 2 to 17 1 62
Y A DIV Y,A 2 to 17 2 90 62
See also: DIVW, ADD, ADC, SUB, SBC, MUL
Doc ID 13590 Rev 3 101/162

DIVW Divide word (unsigned) DIVW

Operation X <= X / Y (Quotient) Y <= X%Y (Remainder)
Description Divides a 16-bit unsigned value, dividend, contained in X register by a
16-bit value, divisor, contained in Y. The quotient is placed in the X register
and the remainder is placed in Y register.
The quotient and remainder values are indeterminate in the case of a
division by zero.
Note: This instruction is interruptible, generating a latency of 1 cycle only.

mnem dst src
V I1 H I0 N Z C
DIV X Y 0 - 0 - 0 Z C
V⇒ 0
Reset
H⇒ 0
Reset
N⇒ 0
Reset
Z⇒ Q15.Q14.Q13.Q12.Q11.Q10.Q9.Q8.Q7.Q6.Q5.Q4.Q3.Q2.Q1.Q0
Set if the quotient is zero (0x0000), cleared otherwise.
C⇒ Y15.Y14.Y13.Y12.Y11.Y10.Y9.Y8.Y7.Y6.Y5.Y4.Y3.Y2.Y1.Y0
Set if division by 0, cleared otherwise.

X Y DIV X,Y 2 to 17 1 65
See also: ADD, ADC, SUB, SBC, MUL, DIV
102/162 Doc ID 13590 Rev 3

EXG Exchange register EXG

contents
Syntax EXG dst, src e.g. EXG A, XL
Operation dst <=> src
src <= dst
dst<= src
Description Exchanges the contents of registers specified in the instruction as shown
below.

mnem dst src
V I1 H I0 N Z C
EXG A XL - - - - - - -
EXG A YL - - - - - - -
EXG A Mem - - - - - - -

A XL EXG A,XL 1 1 41
A YL EXG A,YL 1 1 61
A longmem EXG A,$1000 3 3 31 MS LS
See also: EXGW, LD
Doc ID 13590 Rev 3 103/162

EXGW Exchange Index register EXGW

contents
Syntax EXG dst, src e.g. EXGW X, Y
Operation dst <=> src
src <= dst
dst<= src
Description Exchanges the contents of registers specified in the instruction as shown
below.

mnem dst src
V I1 H I0 N Z C
EXGW X Y - - - - - - -

X Y EXGW X,Y 1 1 51
See also: EXG, LDW
104/162 Doc ID 13590 Rev 3

HALT HALT Oscillator HALT

(CPU + Peripherals)
Syntax HALT
Operation I1 = 1, I0 = 0, The oscillator is stopped till an interrupt occurs.
Description The interrupt mask is reset, allowing interrupts to be fetched. Then the
oscillator is stopped thus stopping the CPU and all internal peripherals,
reducing the microcontroller to its lowest possible power consumption. The
microcontroller resumes program execution after an external interrupt or
reset, by restarting the oscillator, and then, fetching the corresponding
external interrupt, which is an I/O interrupt, a specific peripheral interrupt,
or the reset vector.

mnem
V I1 H I0 N Z C
HALT - 1 - 0 - - -
I1: 1
Set.
I0: 0
Cleared.
Addressing
mode
Inherent HALT 10 1 8E ✗
See also: WFI
Doc ID 13590 Rev 3 105/162

INC Increment INC

Syntax INC dst e.g. INC counter
Operation dst <= dst + 1
Description The destination byte is read, then incremented by one, and the result is
written to the destination byte. The destination is either a memory byte or a
register. This instruction is compact, and does not affect any registers when

mnem dst
V I1 H I0 N Z C
INC Mem V - - - N Z -
INC A V - - - N Z -
V⇒ (A7.M7 + M7.R7 + R7.A7) ⊕ (A6.M6 + M6.R6 + R6.A6)

N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0

A INC A 1 1 4C ✗
shortmem INC $10 1 2 3C XX ✗
longmem INC $1000 1 4 72 5C MS LS
(X) INC (X) 1 1 7C ✗
(shortoff.X) INC ($10,X) 1 2 6C XX ✗
(longoff,X) INC ($1000,X) 1 4 72 4C MS LS
(Y) INC (Y) 1 2 90 7C ✗
(shortoff,Y) INC ($10,Y) 1 3 90 6C XX ✗
(longoff,Y) INC ($1000,Y) 1 4 90 4C MS LS
(shortoff,SP) INC ($10,SP) 1 2 0C XX
[shortptr.w] INC [$10] 4 3 92 3C XX ✗
[longptr.w] INC [$1000].w 4 4 72 3C MS LS
([shortptr.w],X) INC ([$10],X) 4 3 92 6C XX ✗
([longptr.w].X] INC ([$1000.w],X) 4 4 72 6C MS LS
([shortptr.w],Y) INC ([$10],Y) 4 3 91 6C XX ✗
See also: INCW, DEC
106/162 Doc ID 13590 Rev 3

INCW Increment word INCW

Syntax INCW dst e.g. INCW X
Operation dst <= dst + 1
Description The destination index register value is incremented by one.

mnem dst
V I1 H I0 N Z C
INCW Reg V - - - N Z -
V⇒ (A15.M15 + M15.R15 + R15.A15) ⊕ (A14.M14 + M14.R14 + R14.A14)

N⇒ R15

X INCW X 1 1 5C
Y INCW Y 1 2 90 5C
See also: INC, DECW
Doc ID 13590 Rev 3 107/162

INT Interrupt INT

Syntax INT dst
Operation PC <= dst
Description This instruction is used only in the interrupt vector table.

mnem dst
V I1 H I0 N Z C
INT Mem - - - - - - -

extmem INT $2FFFFC 2 4 82 ExtB MS LS
See also: JP, JPF, CALLF
108/162 Doc ID 13590 Rev 3

IRET Interrupt Return IRET

Syntax IRET
Operation CC = (++SP)
A = (++SP)
XH = (++SP)
XL = (++SP)
YH = (++SP)
YL = (++SP)
PCE = (++SP)
PCH = (++SP)
PCL = (++SP)
Description Placed at the end of an interrupt routine, returns to the original program
context before the interrupt occurred. All registers, which have been
saved/pushed onto the stack are restored/popped. The I bit will be reset if
the corresponding bit stored on the stack is zero.

mnem
V I1 H I0 N Z C
IRET V I1 H I0 N Z C
Condition flags set or reset according to the first byte pulled from the stack.
Addressing
mode
Inherent IRET 11 1 80 ✗
See also: Interrupts, TRAP
Doc ID 13590 Rev 3 109/162

JP Jump (absolute) JP
Syntax JP dst e.g. JP test
Operation PC <= dst
Description The unconditional jump, simply replaces the content of PC by destination
address in same section of memory. Control then passes to the statement
addressed by the program counter. This instruction should be used instead
of JRA during S/W development.

mnem dst
V I1 H I0 N Z C
JP Mem - - - - - - -

longmem JP $1000 1 3 CC MS LS ✗
(X) JP(X) 1 1 FC ✗
(shortoff,X) JP($10,X) 1 2 EC XX ✗
(longoff,X) JP($1000,X) 1 3 DC MS LS ✗
(Y) JP(Y) 1 2 90 FC ✗
(shortoff,Y) JP($10,Y) 2 3 90 EC XX ✗
(longoff,Y) JP($1000,Y) 2 4 90 DC MS LS ✗
[shortptr.w] JP[$10.w] 5 3 92 CC XX ✗
[longptr.w] JP[$1000.w] 5 4 72 CC MS LS
([shortptr.w],X) JP([$10.w],X) 5 3 92 DC XX ✗
([longptr.w],X) JP([$1000.w],X) 5 4 72 DC MS LS
([shortptr.w],Y) JP([$10.w],Y) 5 3 91 DC XX ✗
See also: JRT
110/162 Doc ID 13590 Rev 3

JPF Jump far JPF

Syntax JPF dst e.g.:JPF test
Operation PC <= dst
Description The unconditional jump simply replaces the content of the PC by a
destination with an extended address. Control then passes to the
statement addressed by the program counter. For safe memory usage, this
instruction must be used, when the operation crosses a memory section.

mnem dst
V I1 H I0 N Z C
JPF Mem - - - - - - -

extmem JPF $2FFFFC 2 4 AC ExtB MS LS
[longptr.e] JPF [$2FFC.e] 6 4 92 AC MS LS
See also: JP, CALLF
Doc ID 13590 Rev 3 111/162

JRA Jump Relative Always JRA

Syntax JRA dst e.g. JRA loop
PC <= PC + dst, if Condition is True
Description Unconditional relative jump. PC is updated by the signed addition of PC
and dst. Control then passes to the statement addressed by the program
counter. Else, the program continues normally.

mnem dst
V I1 H I0 N Z C
JRA Mem - - - - - - -

shortoff JRA $2B 2 2 20 XX ✗
See also: JP
112/162 Doc ID 13590 Rev 3

JRxx Conditional Jump JRxx

Relative Instruction
Syntax JRxx dst e.g. JRxx loop
PC <= PC + dst, if Condition is True
Description Conditional relative jump. PC is updated by the signed addition of PC and
dst, if the condition is true. Control, then passes to the statement
addressed by the program counter. Else, the program continues normally.

mnem dst
V I1 H I0 N Z C
JRxx Mem - - - - - - -
Instruction List
mnem meaning sym Condition Op-code (OC)

JRC Carry C=1 25
JREQ Equal = Z=1 27
JRF False False 21
JRH Half-Carry H=1 90 29
JRIH Interrupt Line is High 90 2F
JRIL Interrupt Line is Low 90 2E
JRM Interrupt Mask I=1 90 2D
JRMI Minus <0 N=1 2B
JRNC Not Carry C=0 24
JRNE Not Equal <> 0 Z=0 26
JRNH Not Half-Carry H=0 90 28
JRNM Not Interrupt Mask I=0 90 2C
JRNV Not Overflow V=0 28
JRPL Plus >= 0 N=0 2A
JRSGE Signed Greater or Equal >= (N XOR V) = 0 2E
JRSGT Signed Greater Than > (Z OR (N XOR V)) = 0 2C
JRSLE Signed Lower or Equal <= (Z OR (N XOR V)) = 1 2D
JRSLT Signed Lower Than < (N XOR V) = 1 2F
JRT True True 20
JRUGE Unsigned Greater or Equal C=0 24
JRUGT Unsigned Greater Than > C = 0 and Z = 0 22
JRULE Unsigned Lower or Equal <= C = 1 or Z = 1 23
JRC Carry C=1 25
JRULT Unsigned Lower Than C=1 25
JRV Overflow V=1 29

shortoff JRxx $15 1/2 2 Op-code XX ✗
shortoff JRxx $15 1/2 3 90 Op-code XX ✗
Doc ID 13590 Rev 3 113/162

LD Load LD
Syntax LD dst,src e.g. LD A,#$15
Operation dst <= src
Description Load the destination byte with the source byte. The dst and src can be a
register, a byte (low/high) of an index register or a memory/data byte. When
half of an index register is loaded, the other half remains unchanged.

mnem dst src
V I1 H I0 N Z C
LD Reg Mem - - - - N Z -
LD Mem Reg - - - - N Z -
LD Reg Reg - - - - - - -
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0

A #byte LD A,#$55 1 2 A6 XX ✗
A shortmem LD A,$50 1 2 B6 XX ✗
A longmem LD A,$5000 1 3 C6 MS LS ✗
A (X) LD A,(X) 1 1 F6 ✗
A (shortoff,X) LD A,($50,X) 1 2 E6 XX ✗
A (longoff,X) LD A,($5000,X) 1 3 D6 MS LS ✗
A (Y) LD A,(Y) 1 2 90 F6 ✗
A (shortoff,Y) LD A,($50,Y) 1 3 90 E6 XX ✗
A (longoff,Y) LD A,($5000,Y) 1 4 90 D6 MS LS ✗
A (shortoff,SP) LD A,($50,SP) 1 2 7B XX
A [shortptr.w] LD A,[$50.w] 4 3 92 C6 XX ✗
A [longptr.w] LD A,[$5000.w] 4 4 72 C6 MS LS
A ([shortptr.w],X) LD A,([$50.w],X) 4 3 92 D6 XX ✗
A ([longptr.w],X) LD A,([$5000.w],X) 4 4 72 D6 MS LS
A ([shortptr.w],Y) LD A,([$50.w],Y) 4 3 91 D6 XX ✗
114/162 Doc ID 13590 Rev 3

LD detailed description (Continued)

shortmem A LD $50,A 1 2 B7 XX ✗
longmem A LD $5000,A 1 3 C7 MS LS ✗
(X) A LD (X),A 1 1 F7 ✗
(shortoff,X) A LD ($50,X),A 1 2 E7 XX ✗
(longoff,X) A LD ($5000,X),A 1 3 D7 MS LS ✗
(Y) A LD (Y),A 1 2 90 F7 ✗
(shortoff,Y) A LD ($50,Y),A 1 3 90 E7 XX ✗
(longoff,Y) A LD ($5000,Y),A 1 4 90 D7 MS LS ✗
(shortoff,SP) A LD ($50,SP),A 1 2 6B XX
[shortptr.w] A LD [$50.w],A 4 3 92 C7 XX ✗
[longptr.w] A LD [$5000.w],A 4 4 72 C7 MS LS
([shortptr.w],
A LD ([$50.w],X),A 4 3 92 D7 XX ✗
X)
LD
([longptr.w],X) A 4 4 72 D7 MS LS
([$5000.w],X),A
([shortptr.w],
A LD ([$50.w],Y),A 4 3 91 D7 XX ✗
Y)

XL A LD XL,A 1 1 97 ✗
A XL LD A,XL 1 1 9F ✗
YL A LD YL,A 1 2 90 97 ✗
A YL LD A,YL 1 2 90 9F ✗
XH A LD XH,A 1 1 95
A XH LD A,XH 1 1 9E
YH A LD YH,A 1 2 90 95
A YH LD A,YH 1 2 90 9E
See also: LDW, LDF, CLR
Doc ID 13590 Rev 3 115/162

LDF Load Far LDF

Syntax LDF dst,src e.g. LDF A,($555555,X)
Description Load the destination byte with the source byte. The dst and src can be a
memory location or accumulator register.

mnem dst src
V I1 H I0 N Z C
LDF A Mem - - - - N Z -
LDF Mem A - - - - N Z -
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0

A extmem LDF A, $500000 1 4 BC ExtB MS LS
A (extoff,X) LDF A,($500000,X) 1 4 AF ExtB MS LS
A (extoff,Y) LDF A,($500000,Y) 1 5 90 AF ExtB MS LS
A ([longptr.e],X) LDF A,([$5000.e],X) 5 4 92 AF MS LS
A ([longptr.e],Y) LDF A,([$5000.e],Y) 5 4 91 AF MS LS
A [longptr.e] LDF A,[$5000.e] 5 4 92 BC MS LS

extmem A LDF $500000,A 1 4 BD ExtB MS LS
(extoff,X) A LDF ($500000,X),A 1 4 A7 ExtB MS LS
(extoff,Y) A LDF ($500000,Y),A 1 5 90 A7 ExtB MS LS
([longptr.e],X) A LDF ([$5000.e],X),A 4 4 92 A7 MS LS
([longptr.e],Y) A LDF ([$5000.e],Y),A 4 4 91 A7 MS LS
[longptr.e] A LDF [$5000.e],A 4 4 92 BD MS LS
See also: LD, CALLF
116/162 Doc ID 13590 Rev 3

LDW Load word LDW

Syntax LDW dst,src e.g. LDW X,#$1500
Description Load the destination word (16-bit value) with the source word. The dst and
src can be a 16-bit register (X, Y or SP) or a memory/data 16-bit value.

mnem dst src
V I1 H I0 N Z C
LD Reg Mem - - - - N Z -
LD Mem Reg - - - - N Z -
LD Reg Reg - - - - - - -
LD SP Reg - - - - - - -
LD Reg SP - - - - - - -
N⇒ R15

X #word LDW X,#$55AA 2 3 AE MS LS ✗
X shortmem LDW X,$50 2 2 BE XX ✗
X longmem LDW X,$5000 2 3 CE MS LS ✗
X (X) LDW X,(X) 2 1 FE ✗
X (shortoff,X) LDW X,($50,X) 2 2 EE XX ✗
X (longoff,X) LDW X,($5000,X) 2 3 DE MS LS ✗
X (shortoff,SP) LDW X,($50,SP) 2 2 1E XX
X [shortptr.w] LDW X,[$50.w] 5 3 92 CE XX ✗
X [longptr.w] LDW X,[$5000.w] 5 4 72 CE MS LS
X ([shortptr.w],X) LDW X,([$50.w],X) 5 3 92 DE XX ✗
LDW
X ([longptr.w],X) 5 4 72 DE MS LS
X,([$5000.w],X)

shortmem X LDW $50,X 2 2 BF XX ✗
longmem X LDW $5000,X 2 3 CF MS LS ✗
(X) Y LDW (X),Y 2 1 FF
(shortoff,X) Y LDW ($50,X),Y 2 2 EF XX
(longoff,X) Y LDW ($5000,X),Y 2 3 DF MS LS
Doc ID 13590 Rev 3 117/162

LDW detailed description (Continued)

(shortoff,SP) X LDW ($50,SP),X 2 2 1F
[shortptr.w] X LDW [$50.w],X 5 3 92 CF XX ✗
[longptr.w] X LDW [$5000.w],X 5 4 72 CF MS LS
([shortptr.w],X) Y LDW ([$50.w],X),Y 5 3 92 DF XX ✗
([longptr.w],X) Y LDW ([$5000.w],X),Y 5 4 72 DF MS LS

Y #word LDW Y,#$55AA 2 4 90 AE MS LS ✗
Y shortmem LDW Y,$50 2 3 90 BE XX ✗
Y longmem LDW Y,$5000 2 4 90 CE MS LS ✗
Y (Y) LDW Y,(Y) 2 2 90 FE ✗
Y (shortoff,Y) LDW Y,($50,Y) 2 3 90 EE XX ✗
Y (longoff,Y) LDW Y,($5000,Y) 2 4 90 DE MS LS ✗
Y (shortoff,SP) LDW Y,($50,SP) 2 2 16 XX
Y [shortptr.w] LDW Y,[$50.w] 5 3 91 CE XX ✗
Y ([shortptr.w],Y) LDW Y,([$50.w],Y) 5 3 91 DE XX ✗

shortmem Y LDW $50,Y 2 3 90 BF XX ✗
longmem Y LDW $5000,Y 2 4 90 CF MS LS ✗
(Y) X LDW (Y),X 2 2 90 FF ✗
(shortoff,Y) X LDW ($50,Y),X 2 3 90 EF XX ✗
(longoff,Y) X LDW ($5000,Y),X 2 4 90 DF MS LS ✗
(shortoff,SP) Y LDW ($50,SP),Y 2 2 17 XX
[shortptr.w] Y LDW [$50.w],Y 5 3 91 CF XX ✗
([shortptr.w],Y) X LDW ([$50.w],Y),X 5 3 91 DF XX ✗
dst src cy lgth Op-code(s) ST7

Y X LDW Y,X 1 2 90 93 ✗
X Y LDW X,Y 1 1 93 ✗
X SP LDW X,SP 1 1 96 ✗
SP X LDW SP,X 1 1 94 ✗
Y SP LDW Y,SP 1 2 90 96 ✗
SP Y LDW SP,Y 1 2 90 94 ✗
Note: LDW Y,[longptr.w] and LDW [longptr.w],Y are not implemented. They can be emulated using
EXGW X,Y.
See also: LD, CLRW
118/162 Doc ID 13590 Rev 3

MOV Move MOV

Syntax MOV dst,src e.g. MOV $80,#$AA
Operation dst<= src
Description Moves a byte of data from a source address to a destination address. Data
is examined as it is moved. The accumulator is not affected.
There are 3 addressing modes for the MOV instruction:
● An immediate byte to a direct memory location
● A direct memory location to another direct memory location (from $00
to $FF)
● A direct memory location to another direct memory location (from
$0000 to $FFFF)

mnem dst src
V I1 H I0 N Z C
MOV Mem Imm - - - - - - -
MOV Mem Mem - - - - - - -

longmem #byte MOV $8000, #$AA 1 4 35 XX MS LS
shortmem shortmem MOV $80,$10 1 3 45 XX2 XX1
MOV
longmem longmem 1 5 55 MS2 LS2 MS1 LS1
$8000,$1000
See also: LD, EXG
Doc ID 13590 Rev 3 119/162

MUL Multiply (unsigned) MUL

Syntax MUL dst,src e.g. MUL X,A
Operation dst:src <= dst x src
Description Multiplies the 8-bit value in index register, low byte, (XL or YL) by the 8-bit
value in the accumulator to obtain a 16-bit unsigned result in the index
register. After the operation, index register contains the 16-bit result. The
accumulator remains unchanged. The initial value of the high byte of the
index register (XH or YH) is ignored.

mnem dst src
V I1 H I0 N Z C
MUL X XL,A - - 0 - - - 0
MUL Y YL,A - - 0 - - - 0
C: 0
Cleared.

X A MUL X,A 4 1 42
Y A MUL Y,A 4 2 90 42
See also: ADD, ADC, SUB, SBC
120/162 Doc ID 13590 Rev 3

NEG Negate (Logical 2’s complement) NEG

Syntax NEG dst e.g. NEG (X)
Operation dst <= (dst XOR FF) + 1, or 00 - dst
Description The destination byte is read, then each bit is toggled (inverted), and the
result is incremented before it is written at the destination byte. The
destination is either a memory byte or a register. The Carry is cleared if the
result is zero. This instruction is used to negate signed values. This
instruction is compact, and does not affect any register when used with
RAM variables.

mnem dst
V I1 H I0 N Z C
NEG Mem V - - - N Z C
NEG A V - - - N Z C
V⇒ R7.R6.R5.R4.R3.R2.R1.R0
Set if there is an arithmetic overflow on the 8-bit representation of the
result. The V bit will set when the content of "dst" was $80 (-128) prior to
the NEG operation, cleared otherwise.
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0
C⇒ R7+R6+R5+R4+R3+R2+R1+R0
Set if a borrow in the implied subtraction from zero, cleared otherwise. The
C bit will be set in all cases except when the contents of "dst" was $00 prior
to the NEG operation.
A NEG A 1 1 40 ✗
shortmem NEG $F5 1 2 30 XX ✗
longmem NEG $F5C2 1 4 72 50 MS LS
(X) NEG(X) 1 1 70 ✗
(shortoff,X) NEG($F5,X) 1 2 60 XX ✗
(longoff,X) NEG($F5C2,X) 1 4 72 40 MS LS
(Y) NEG(Y) 1 2 90 70 ✗
(shortoff,Y) NEG($F5,Y) 1 3 90 60 XX ✗
(longoff,Y) NEG($F5C2,Y) 1 4 90 40 MS LS
(shortoff,SP) NEG($F5,SP) 1 2 00 XX
[shortptr.w] NEG($F5) 4 3 92 30 XX ✗
Doc ID 13590 Rev 3 121/162

NEG detailed description (continued)

[longptr.w] NEG($F5C2.w) 4 4 72 30 MS LS
([shortptr.w],X) NEG([$F5],X) 4 3 92 60 XX ✗
([longptr.w],X) NEG([$F5C2.w],X) 4 4 72 60 MS LS
([shortptr.w],Y) NEG([$F5],Y) 4 3 91 60 XX ✗
See also: NEGW, CPL, AND, OR, XOR
122/162 Doc ID 13590 Rev 3

NEGW Negate word (Logical 2’s Complement) NEGW

Syntax NEGW dst e.g. NEGW X
Operation dst <= (dst XOR FFFF) + 1, or 0000 - dst
Description The destination word is read, then each bit is toggled (inverted), and the
result is incremented before it is written at the destination word. The
destination is an index register.
Instruction overview.

mnem dst
V I1 H I0 N Z C
NEGW X V - - - N Z C
NEGW Y V - - - N Z C
V⇒ R15.R14.R13.R12.R11.R10.R9.R8.R7.R6.R5.R4.R3.R2.R1.R0
Set if there is an arithmetic overflow on the 16-bit representation. The V bit
will set when the content of "dst" was $8000 prior to the NEGW operation,
cleared otherwise.
N⇒ R15
C⇒ R15+R14+R13+R12+R11+R10+R9+R8+R7+R6+R5+R4+R3+R2+R1+R0
Set if a borrow in the implied subtraction from zero, cleared otherwise. The
C bit will be set in all cases except when the contents of "dst" was $0000
prior to the NEGW operation.

X NEGW X 2 1 50
Y NEGW Y 2 2 90 50
See also: NEG, CPLW, AND, OR, XOR
Doc ID 13590 Rev 3 123/162

NOP No operation NOP

Syntax NOP
Operation
Description This is a single byte instruction that does nothing. This instruction can be
used either to disable an instruction, or to build a waiting delay.No register
or memory contents are affected by this instruction

mnem
V I1 H I0 N Z C
NOP - - - - - - -
Addressing
mode
Inherent NOP 1 1 9D ✗
See also: JRF
124/162 Doc ID 13590 Rev 3

OR Logical OR OR
Syntax OR A,src e.g. OR A,#%00110101
Operation A <= A OR src
Description The source byte, is logically ORed with the contents of the accumulator
and the result is stored in the accumulator. The source is a memory or data
byte.
Truth table
OR 0 1
0 0 1
1 1 1

mnem dst src
V I1 H I0 N Z C
OR A Mem - - - - N Z -
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0

A #byte OR A,#$55 1 2 AA XX ✗
A shortmem OR A,$10 1 2 BA XX ✗
A longmem OR A,$1000 1 3 CA MS LS ✗
A (X) OR A,(X) 1 1 FA ✗
A (shortoff,X) OR A,($10,X) 1 2 EA XX ✗
A (longoff,X) OR A,($1000,X) 1 3 DA MS LS ✗
A (Y) OR A,(Y) 1 2 90 FA ✗
A (shortoff,Y) OR A,($10,Y) 1 3 90 EA XX ✗
A (longoff,Y) OR A,($1000,Y) 1 4 90 DA MS LS ✗
A (shortoff,SP) OR A,($10,SP) 1 2 1A XX
A [shortptr.w] OR A,[$10.w] 4 3 92 CA XX ✗
A [longptr.w] OR A,[$1000.w] 4 4 72 CA MS LS
A ([shortptr.w],X) OR A,([$10.w],X) 4 3 92 DA XX ✗
A ([longptr.w],X) OR A,([$1000.w],X) 4 4 72 DA MS LS
A ([shortptr.w],Y) OR A,([$1000],Y) 4 3 91 DA XX ✗
See also: AND, XOR, CPL, NEG
Doc ID 13590 Rev 3 125/162

POP Pop from stack POP

Syntax POP dst e.g. POP CC
Operation dst <= (++SP)
Description Restore from the stack a data byte which will be placed in dst location. The
stack pointer is incremented by one. This instruction is used to restore a
register/memory value.

mnem dst
V I1 H I0 N Z C
POP A - - - - - - -
POP CC V I1 H I0 N Z C
POP Mem - - - - - - -

A POP A 1 1 84 ✗
CC POP CC 1 1 86 ✗
longmem POP $1000 1 3 32 MS LS
See also: PUSH, POPW
126/162 Doc ID 13590 Rev 3

POPW Pop word from stack POPW

Syntax POPW dst e.g. POPW X
Operation dstH <= (++SP)
dstL <= (++SP)
Description Restore from the stack a data value which will be placed in dst location
(index register). The stack pointer is incremented by two. This instruction is
used to restore an index register value.

mnem dst
V I1 H I0 N Z C
POPW X - - - - - - -
POPW Y - - - - - - -

X POPW X 2 1 85 ✗
Y POPW Y 2 2 90 85 ✗
See also: PUSHW, POP
Doc ID 13590 Rev 3 127/162

PUSH Push into the Stack PUSH

Syntax PUSH src e.g.:PUSH A
Operation (SP--) <= dst
Description Save into the stack the dst byte location. The stack pointer is decremented
by one. Used to save a register value and a memory byte on to the stack.

mnem dst
V I1 H I0 N Z C
PUSH A - - - - - - -
PUSH CC - - - - - - -
PUSH Imm - - - - - - -
PUSH Mem - - - - - - -

A PUSH A 1 1 88 ✗
CC PUSH CC 1 1 8A ✗
#byte PUSH #$10 1 2 4B XX
longmem PUSH $1000 1 3 3B MS LS
See also: POP, PUSHW
128/162 Doc ID 13590 Rev 3

PUSHW Push word onto the Stack PUSHW

Syntax PUSHW src e.g. PUSHW X
Operation (SP--) <= dstL
(SP--) <= dstH
Description Save the dst index register onto the stack. The stack pointer is
decremented by two. Used to save an index register value onto the stack.

mnem dst
V I1 H I0 N Z C
PUSHW X - - - - - - -
PUSHW Y - - - - - - -

X PUSHW X 2 1 89 ✗
Y PUSHW Y 2 2 90 89 ✗
See also: POPW, PUSH
Doc ID 13590 Rev 3 129/162

RCF Reset Carry Flag RCF

Syntax RCF
Operation C=0
Description Clear the carry flag of the Condition Code (CC) register. May be used as a
boolean user controlled flags.

mnem
V I1 H I0 N Z C
RCF - - - - - - 0
C: 0
Cleared.
Addressing
mode
Inherent RCF 1 1 98 ✗
See also: SCF, RVF
130/162 Doc ID 13590 Rev 3

RET Return from subroutine RET

Syntax RET
Operation MSB (PC) = (++SP)
LSB (PC) = (++SP)
Description Restore the PC from the stack. The stack pointer is incremented twice. This
instruction, is the last instruction of a subroutine in same section.

mnem
V I1 H I0 N Z C
RET - - - - - - -
Addressing
mode
Inherent RET 4 1 81 ✗
See also: CALL, CALLR

Note: Please note that the RET should be in the same section as the corresponding CALL.
Doc ID 13590 Rev 3 131/162

RETF Far Return from RETF

subroutine
Syntax RETF
Operation PCE = (++SP)
PCH = (++SP)
PCL = (++SP)
Description Restore the PC from the stack then restore the Condition Code (CC)
register. The stack pointer is incremented three times. This instruction is
the last one of a subroutine in extended memory.

mnem
V I1 H I0 N Z C
RETF - - - - - - -
Addressing
mode
Inherent RETF 5 1 87
See also: CALLF
132/162 Doc ID 13590 Rev 3

RIM Reset Interrupt RIM

Mask/Enable Interrupt
Syntax RIM
Operation I1 = 1, I0 = 0
Description Clear the Interrupt mask of the Condition Code (CC) register, which enable
interrupts. This instruction is generally put in the main program, after the
reset routine, once all desired interrupts have been properly configured.
This instruction is not needed before WFI and HALT instructions.

mnem
V I1 H I0 N Z C
RIM - 1 - 0 - - -
I1: 1
Set.
I0: 0
Cleared.
Addressing
mode
Inherent RIM 1 1 9A ✗
See also: SIM
Doc ID 13590 Rev 3 133/162

RLC Rotate Left Logical RLC

through Carry
Syntax RLC dst e.g. RLC (X)
Operation
Description The destination is either a memory byte or a register. This instruction is
compact, and does not affect any register when used with RAM
variables.This instruction shifts all bits of the register or memory, one place
to the left, through the Carry bit. Bit 0 of the result is a copy of the CC.C
value before the operation.

mnem dst
V I1 H I0 N Z C
RLC Reg - - - - N Z bit7

RLC Mem - - - - N Z bit7
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0
C⇒ b7
Set if, before the shift, the MSB of register or memory was set, cleared
otherwise.
C b7 b0
A RLC A 1 1 49 ✗
shortmem RLC $10 1 2 39 XX ✗
longmem RLC $1000 1 4 72 59 MS LS
(X) RLC (X) 1 1 79 ✗
(shortoff,X) RLC ($10,X) 1 2 69 XX ✗
(longoff,X) RLC ($1000,X) 1 4 72 49 MS LS
(Y) RLC (Y) 1 2 90 79 ✗
(shortoff,Y) RLC ($10,Y) 1 3 90 69 XX ✗
(longoff,Y) RLC ($1000,Y) 1 4 90 49 MS LS
(shortoff,SP) RLC ($10,SP) 1 2 09 XX ✗
[shortptr.w] RLC [$10] 4 3 92 39 XX ✗
[longptr.w] RLC [$1000].w 4 4 72 39 MS LS
([shortptr.w],X) RLC ([$10],X) 4 3 92 69 XX ✗
([longptr.w],X) RLC ([$1000.w],X) 4 4 72 69 MS LS
([shortptr.w],Y) RLC ([$10],Y) 4 3 91 69 XX ✗
See also: RLCW, RRC, SLL, SRL, SRA, ADC, SWAP, SLA
134/162 Doc ID 13590 Rev 3

RLCW Rotate Word Left Logical RLCW

through Carry
Syntax RLCW dst e.g. RLCW X
Operation
Description The destination is an index register. This instruction shifts all bits of the
register one place to the left through Carry bit. Bit 0 of the result is a copy
of CC.C value before the operation.

mnem dst
V I1 H I0 N Z C
RLCW Reg - - - - N Z bit15
N⇒ R15
C⇒ b15
otherwise.
C b15 b0

X RLCW X 2 1 59 ✗
Y RLCW Y 2 2 90 59 ✗
See also: RLC, RRCW, SLLW, SRLW, SRAW, SWAPW, SLAW
Doc ID 13590 Rev 3 135/162

RLWA Rotate Word Left through A RLWA

Syntax RLWA dst e.g. RLWA Y,A
Operation A <= dstH <= dstL <= A
Description The destination index register and Accumulator are rotated left by 1-byte.

mnem dst src
V I1 H I0 N Z C
RLWA X A - - - - N Z -
RLWA Y A - - - - N Z -
N⇒ R15

X A RLWA X 1 1 02
Y A RLWA Y 1 2 90 02
See also: RRWA, SWAPW
136/162 Doc ID 13590 Rev 3

RRC Rotate Right Logical through Carry RRC

Syntax RRC dst e.g. RRC (X)
Operation
Description The destination is either a memory byte location or a register. This
instruction is compact, and does not affect any register when used with
RAM variables.This instruction shifts all bits of the register or memory, one
place to the right. Bit 7 of the result is a copy of the CC.C bit value before
the operation.

mnem dst
V I1 H I0 N Z C
RRC Reg - - - - N Z bit0
RRC Mem - - - - N Z bit0
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0
C⇒ b0
Set if, before the shift, the LSB of register or memory was set, cleared
otherwise.
C b7 b0
A RRC A 1 1 46 ✗
shortmem RRC $10 1 2 36 XX ✗
longmem RRC $1000 1 4 72 56 MS LS
(X) RRC (X) 1 1 76 ✗
(shortoff,X) RRC ($10,X) 1 2 66 XX ✗
(longoff,X) RRC ($1000,X) 1 4 72 46 MS LS
(Y) RRC (Y) 1 2 90 76 ✗
(shortoff,Y) RRC ($10,Y) 1 3 90 66 XX ✗
(longoff,Y) RRC ($1000,Y) 1 4 90 46 MS LS
(shortoff,SP) RRC ($10,SP) 1 2 06 XX ✗
[shortptr.w] RRC [$10] 4 3 92 36 XX ✗
[longptr.w] RRC [$1000].w 4 4 72 36 MS LS
([shortptr.w],X) RRC ([$10],X) 4 3 92 66 XX ✗
([longptr.w],X) RRC ([$1000.w],X) 4 4 72 66 MS LS
([shortptr.w],Y) RRC ([$10],Y) 4 3 91 66 XX ✗
See also: RLC, SRL, SLL, SRA, SWAP, ADC, SLA
Doc ID 13590 Rev 3 137/162

RRCW Rotate Word Right Logical through Carry RRCW

Syntax RRCW dst e.g. RRCWX
Operation
Description The destination is an index register. This instruction shifts all bits of the
register or memory, one place to the right, through the Carry bit. Bit 15 of
the result is a copy of the CC.C bit value before the operation.

mnem dst
V I1 H I0 N Z C
RRCW Reg - - - - N Z bit0
N⇒ R15
C⇒ b0
otherwise.
C b15 b0

X RRCW X 2 1 56 ✗
Y RRCW Y 2 2 90 56 ✗
See also: RRC, RLCW, SRLW, SLLW, SRAW, SWAPW, SLAW
138/162 Doc ID 13590 Rev 3

RRWA Rotate Right Word through A RRWA

Syntax RRWA dst e.g. RRWA Y,A
Operation A => dstH => dstL => A
Description The destination index register and Accumulator are rotated right by 1-byte.

mnem dst src
V I1 H I0 N Z C
RLWA X A - - - - N Z -
RLWA Y A - - - - N Z -
N⇒ R15

X A RRWA X 1 1 01
Y A RRWA Y 1 2 90 01
See also: RLWA, SWAPW
Doc ID 13590 Rev 3 139/162

RVF Reset overflow flag RVF

Syntax RVF
Operation V=0
Description Clear the overflow flag of the Condition Code (CC) register. May be used
as a boolean user controlled flags.

mnem
V I1 H I0 N Z C
RCF 0 - - - - - -
V: 0
Cleared.
Addressing
mode
Inherent RVF 1 1 9C ✗
See also: RCF, SCF
140/162 Doc ID 13590 Rev 3

SBC Subtraction with SBC

Carry/Borrow
Syntax SBC A,src e.g. SBC A,#$15
Operation A <= A- src - C
Description The source byte, along with the carry flag, is subtracted from the contents
of the accumulator and the result is stored in the accumulator. The source
is a memory or data byte.

mnem dst src
V I1 H I0 N Z C
SBC A Mem V - - - N Z C

Set if the signed subtraction generates an overflow, cleared otherwise.
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0
C⇒ A7.M7 + A7.R7 + A7.M7.R7
Set if a borrow request occurred from bit 7 of the result, cleared otherwise.

A #byte SBC A,#$55 1 2 A2 XX ✗
A shortmem SBC A,$10 1 2 B2 XX ✗
A longmem SBC A,$1000 1 3 C2 MS LS ✗
A (X) SBC A,(X) 1 1 F2 ✗
A (shortoff,X) SBC A,($10,X) 1 2 E2 XX ✗
A (longoff,X) SBC A,($1000,X) 1 3 D2 MS LS ✗
A (Y) SBC A,(Y) 1 2 90 F2 ✗
A (shortoff,Y) SBC A,($10,Y) 1 3 90 E2 XX ✗
A (longoff,Y) SBC A,($1000,Y) 1 4 90 D2 MS LS ✗
A (shortoff,SP) SBC A,($10,SP) 1 2 12 XX
A [shortptr.w] SBC A,[$10.w] 4 3 92 C2 XX ✗
A [longptr.w] SBC A,[$1000.w] 4 4 72 C2 MS LS
SBC
A ([shortptr.w],X) 4 3 92 D2 XX ✗
A,([$10.w],X)
SBC
A,([$1000.w],X)
SBC
A ([shortptr.w],Y) 4 3 91 D2 XX ✗
A,([$10.w],Y)
See also: ADD,ADC,SUB, MUL
Doc ID 13590 Rev 3 141/162

SCF Set Carry Flag SCF

Syntax SCF
Operation C=1
Description Set the carry flag of the Condition Code (CC) register. It may be used as
user controlled flag.
mnem
SCF

mnem
V I1 H I0 N Z C
SCF - - - - - - 1
C: 1
Set.
Addressing
mode
Inherent SCF 1 1 99 ✗
See also: RCF, RVF
142/162 Doc ID 13590 Rev 3

SIM Set Interrupt SIM

Mask/Disable Interrupt
Syntax sim
Operation I1 = 1, I0 = 1
Description Set the Interrupt mask of the Condition Code (CC) register, which disables
interrupts. This instruction is useless at the beginning of reset routine. It
need not be used at the beginning of interrupt routines as the interrupt level
is set automatically in CC.I[1:0].

mnem
V I1 H I0 N Z C
SIM - 1 - 1 - - -
I1 and I0: 1
Set.
Addressing
mode
Inherent SIM 1 1 9B ✗
See also: RIM
Doc ID 13590 Rev 3 143/162

SLL/SLA Shift Left Logical/Shift SLL/SLA

Left Arithmetic
Syntax SLL dst e.g. SLL (X)
SLA dst e.g. SLA (X)
Operation
Description The destination is either a memory byte or a register.It double the affected
value. This instruction is compact, and does not affect any register when

mnem dst
V I1 H I0 N Z C
SLL/SLA Mem - - - - N Z bit7
SLL/SLA Reg - - - - N Z bit7
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0
C⇒ b7
Set if, before the shift, bit 7 of register or memory was set, cleared
otherwise.
C b7 b0 0
dst Asm(1) cy lgth Op-code(s) ST7

A SLL A 1 1 48 ✗
shortmem SLL $15 1 2 38 XX ✗
longmem SLL $1505 1 4 72 58 MS LS
(X) SLL (X) 1 1 78 ✗
(shortoff,X) SLL ($15,X) 1 2 68 XX ✗
(longoff,X) SLL ($1505,X) 1 4 72 48 MS LS
(Y) SLL (Y) 1 2 90 78 ✗
(shortoff,Y) SLL ($15,Y) 1 3 90 68 XX ✗
(longoff,Y) SLL ($1505,Y) 1 4 90 48 MS LS
(shortoff,SP) SLL ($15,SP) 1 2 08 XX ✗
[shortptr.w] SLL [$15] 4 3 92 38 XX ✗
[longptr.w] SLL [$1505].w 4 4 72 38 MS LS
([shortptr.w],X) SLL ([$15],X) 4 3 92 68 XX ✗
144/162 Doc ID 13590 Rev 3

([longptr.w],X) SLL ([$1505.w],X) 4 4 72 68 MS LS

([shortptr.w],Y) SLL ([$15],Y) 4 3 91 68 XX ✗
1. For the shift left arithmetic instruction, replace SLL by SLA.
See also: SLA, SRA, SRL, RRC, RLC, SWAP
Doc ID 13590 Rev 3 145/162

SLLW/SLAW Shift Left Logical SLLW/SLAW

Word/Shift Left Arithmetic
Word
Syntax SLLW dst e.g. SLLW X
SLAW dst e.g. SLAW X
Operation
Description The destination is an index register.It double the affected value.

mnem dst
V I1 H I0 N Z C
SLLW/SLAW Reg - - - - N Z bit15
N⇒ R15
Set if bit 15of the result is set (negative value), cleared otherwise.
C⇒ b15
Set if, before the shift, bit 15 of register or memory was set, cleared
otherwise.
C b15 b0 0
dst Asm(1) cy lgth Op-code(s) ST7

X SLLW X 2 1 58
Y SLLW Y 2 2 90 58
1. For the shift left arithmetic word instruction, replace SLLW by SLAW.
See also: SLL, SRAW, SRLW, RRCW, RLCW, SWAPW, SLAW
146/162 Doc ID 13590 Rev 3

SRA Shift Right Arithmetic SRA

Syntax SRA dst e.g. SRA (X)
Operation
Description The destination is either a memory byte or a register. It performs an signed
division by 2: The sign bit 7 is not modified.This instruction is compact, and

mnem dst
V I1 H I0 N Z C
SRA Reg - - - - N Z bit0
SRA Mem - - - - N Z bit0
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0
C⇒ b0
otherwise.
b7 b7 b0 C

A SRA A 1 1 47 ✗
shortmem SRA $15 1 2 37 XX ✗
longmem SRA $1505 1 4 72 57 MS LS
(X) SRA (X) 1 1 77 ✗
(shortoff,X) SRA ($15,X) 1 2 67 XX ✗
(longoff,X) SRA ($1505,X) 1 4 72 47 MS LS
(Y) SRA (Y) 1 2 90 77 ✗
(shortoff,Y) SRA ($15,Y) 1 3 90 67 XX ✗
(longoff,Y) SRA ($1505,Y) 1 4 90 47 MS LS
(shortoff,SP) SRA ($15,SP) 1 2 07 XX ✗
[shortptr.w] SRA [$15] 4 3 92 37 XX ✗
[longptr.w] SRA [$1505].w 4 4 72 37 MS LS
([shortptr.w],X) SRA ([$15],X) 4 3 92 67 XX ✗
([longptr.w],X) SRA ([$1505.w],X) 4 4 72 67 MS LS
([shortptr.w],Y) SRA ([$15],Y) 4 3 91 67 XX ✗
See also: SRAW, SRL, SLL, RRC, RLC, SWAP
Doc ID 13590 Rev 3 147/162

SRAW Shift Right Arithmetic SRAW

Word
Syntax SRAW dst e.g. SRAW X
Operation
Description The destination is an index register. It performs a signed division by 2. The
sign bit (15) is not modified.

mnem dst
V I1 H I0 N Z C
SRAW Reg - - - - N Z bit0
N⇒ R15
C⇒ b0
otherwise.
b15 b15 b0 C

X SRAW X 2 1 57
Y SRAW Y 2 2 90 57
See also: SRA, SRLW, SLLW, RRCW, RLCW, SWAPW
148/162 Doc ID 13590 Rev 3

SRL Shift Right Logical SRL

Syntax SRL dst e.g. SRL (X)
Operation
Description The destination is either a memory byte or a register.It perform an
unsigned division by 2.This instruction is compact, and does not affect any
register when used with RAM variables.

mnem dst
V I1 H I0 N Z C
SRL Reg - - - - N Z bit0
SRL Mem - - - - N Z bit0
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0
C⇒ b0
otherwise.
0 b7 b0 C

A SRL A 1 1 44 ✗
shortmem SRL $15 1 2 34 XX ✗
longmem SRL $1505 1 4 72 54 MS LS
(X) SRL (X) 1 1 74 ✗
(shortoff,X) SRLL ($15,X) 1 2 64 XX ✗
(longoff,X) SRL ($1505,X) 1 4 72 44 MS LS
(Y) SRL (Y) 1 2 90 74 ✗
(shortoff,Y) SRL ($15,Y) 1 3 90 64 XX ✗
(longoff,Y) SRL ($1505,Y) 1 4 90 44 MS LS
(shortoff,SP) SRL ($15,SP) 1 2 04 XX ✗
[shortptr.w] SRL [$15] 4 3 92 34 XX ✗
[longptr.w] SRL [$1505].w 4 4 72 34 MS LS
([shortptr.w],X) SRL ([$15],X) 4 3 92 64 XX ✗
([longptr.w],X) SRL ([$1505.w],X) 4 4 72 64 MS LS
([shortptr.w],Y) SRL ([$15],Y) 4 3 91 64 XX ✗
See also: RLC, RRC, SRA, SWAP, SLL, SRLW
Doc ID 13590 Rev 3 149/162

SRLW Shift Right Logical Word SRLW

Syntax SRLW dst e.g. SRLW X
Operation
Description The destination is an index register. It performs an unsigned division by 2.

mnem dst
V I1 H I0 N Z C
SRLW Reg - - - - N Z bit0
N⇒ R15
C⇒ b0
Set if, before the shift, the LSB of the register was set, cleared
otherwise.
0 b15 b0 C

X SRLW X 2 1 54
Y SRLW Y 2 2 90 54
See also: SRL, RLCW, RRCW, SRLW, SRAW, SWAPW, SLLW
150/162 Doc ID 13590 Rev 3

SUB Subtraction SUB

Syntax SUB A,src e.g. SUB A,#%11001010
Operation A <= A- src
Description The source byte is subtracted from the contents of the accumulator/SP and
the result is stored in the accumulator/SP. The source is a memory or data
byte.

mnem dst src
V I1 H I0 N Z C
SUB A Mem V - - - N Z C
SUB SP Imm - - - - - - -

N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0
C⇒ A7.M7 + A7.R7 + A7.M7.R7
Set if a borrow request occurred from bit 7, cleared otherwise.

A #byte SUB A,#$55 1 2 A0 XX ✗
A shortmem SUB A,$10 1 2 B0 XX ✗
A longmem SUB A,$1000 1 3 C0 MS LS ✗
A (X) SUB A,(X) 1 1 F0 ✗
A (shortoff,X) SUB A,($10,X) 1 2 E0 XX ✗
A (longoff,X) SUB A,($1000,X) 1 3 D0 MS LS ✗
A (Y) SUB A,(Y) 1 2 90 F0 ✗
A (shortoff,Y) SUB A,($10,Y) 1 3 90 E0 XX ✗
A (longoff,Y) SUB A,($1000,Y) 1 4 90 D0 MS LS ✗
A (shortoff,SP) SUB A,($10,SP) 1 2 10 XX
A [shortptr.w] SUB A,[$10.w] 4 3 92 C0 XX ✗
A [longptr.w] SUB A,[$1000.w] 4 4 72 C0 MS LS
A ([shortptr.w],X) SUB A,([$10.w],X) 4 3 92 D0 XX ✗
SUB
A,([$1000.w],X)
A ([shortptr.w],Y) SUB A,([$10.w],Y) 4 3 91 D0 XX ✗
SP #byte SUB SP,#$9 1 2 52 XX
See also: SUBW, ADD, ADC, SBC, MUL
Doc ID 13590 Rev 3 151/162

SUBW Word Subtraction SUBW

Syntax SUBW dst,src e.g. SUBW X, #$5500
Operation dst <= dst - src
Description The source 16-bit word is subtracted from the contents of the destination
index register and the result is stored in the same index register. The
source is a memory or 16-bit data.

mnem dst src
V I1 H I0 N Z C
SUBW X Mem V - H - N Z C
SUBW Y Mem V - H - N Z C
V⇒ (X15.M15 + X15.R15 + X15.M15.R15) ⊕ (X14.M14 + X14.R14 +

X14.M14.R14)
H⇒ X7.M7 + X7.R7 + X7.M7.R7
Set if a carry occurred from bit 7, cleared otherwise.
N⇒ R15
C⇒ X15.M15 + X15.R15 + X15.M15.R15
Set if a borrow request occurred from bit 15, cleared otherwise.

X #word SUBW X,#$5500 2 3 1D MS LS
X longmem SUBW X,$1000 2 4 72 B0 MS LS
X (shortoff, SP) SUBW X,($10,SP) 2 3 72 F0 XX
Y #word SUBW Y,#$5500 2 4 72 A2 MS LS
Y longmem SUBW Y,$1000 2 4 72 B2 MS LS
Y (shortoff, SP) SUBW Y,($10,SP) 2 3 72 F2 XX
See also: SUB, ADDW, ADC, SBC, MUL
152/162 Doc ID 13590 Rev 3

SWAP Swap nibbles SWAP

Syntax SWAP dst e.g. SWAP counter
Operation
Description The destination byte upper and low nibbles are swapped over. The
destination is either a memory byte or a register. This instruction is
compact, and does not affect any register when used with RAM variables.

mnem dst
V I1 H I0 N Z C
SWAP Reg - - - - N Z -
SWAP Mem - - - - N Z -
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0

A SWAP A 1 1 4E ✗
shortmem SWAP $15 1 2 3E XX ✗
longmem SWAP $1505 1 4 72 5E MS LS
(X) SWAP (X) 1 1 7E ✗
(shortoff,X) SWAPL ($15,X) 1 2 6E XX ✗
(longoff,X) SWAP ($1505,X) 1 4 72 4E MS LS
(Y) SWAP (Y) 1 2 90 7E ✗
(shortoff,Y) SWAP ($15,Y) 1 3 90 6E XX ✗
(longoff,Y) SWAP ($1505,Y) 1 4 90 4E MS LS
(shortoff,SP) SWAP ($15,SP) 1 2 0E XX ✗
[shortptr.w] SWAP [$15] 4 3 92 3E XX ✗
[longptr.w] SWAP [$1505].w 4 4 72 3E MS LS
([shortptr.w],X) SWAP ([$15],X) 4 3 92 6E XX ✗
([longptr.w],X) SWAP ([$1505.w],X) 4 4 72 6E MS LS
([shortptr.w],Y) SWAP ([$15],Y) 4 3 91 6E XX ✗
See also: SWAPW, RRC, RLC, SLL, SRL, SRA
Doc ID 13590 Rev 3 153/162

SWAPW Swap bytes SWAPW

Syntax SWAPW dst e.g. SWAPW Y
Operation
Description The destination index register upper and low bytes are swapped over.

mnem dst
V I1 H I0 N Z C
SWAP Reg - - - - N Z -
N⇒ R15

X SWAPW X 1 1 5E ✗
Y SWAPW Y 1 2 90 5E ✗
See also: SWAP, RRC, RLC, SLL, SRL, SRA
154/162 Doc ID 13590 Rev 3

TNZ Test for Negative or Zero TNZ

Syntax TNZ dst e.g. TNZ A
Operation {N, Z} = Test(dst)
Description The destination byte is tested and both N and Z flags of the Condition Code
(CC) register are updated accordingly. This instruction is compact, and

mnem dst
V I1 H I0 N Z C
TNZ Reg - - - - N Z -
TNZ Mem - - - - N Z -
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0

A TNZ A 1 1 4D ✗
shortmem TNZ $15 1 2 3D XX ✗
longmem TNZ $1505 1 4 72 5D MS LS
(X) TNZ (X) 1 1 7D ✗
(shortoff,X) TNZL ($15,X) 1 2 6D XX ✗
(longoff,X) TNZ ($1505,X) 1 4 72 4D MS LS
(Y) TNZ (Y) 1 2 90 7D ✗
(shortoff,Y) TNZ ($15,Y) 1 3 90 6D XX ✗
(longoff,Y) TNZ ($1505,Y) 1 4 90 4D MS LS
(shortoff,SP) TNZ ($15,SP) 1 2 0D XX ✗
[shortptr.w] TNZ [$15] 4 3 92 3D XX ✗
[longptr.w] TNZ [$1505].w 4 4 72 3D MS LS
([shortptr.w],X) TNZ ([$15],X) 4 3 92 6D XX ✗
([longptr.w],X) TNZ ([$1505.w],X) 4 4 72 6D MS LS
([shortptr.w],Y) TNZ ([$15],Y) 4 3 91 6D XX ✗
See also: TNZW, CP, BCP
Doc ID 13590 Rev 3 155/162

TNZW Word Test for Negative or TNZW

Zero
Syntax TNZW dst e.g. TNZW X
Operation {N, Z} = Test(dst)
Description The destination 16-bit word, index register, is tested and both N and Z flags
of the Condition Code (CC) register are updated accordingly.

mnem dst
V I1 H I0 N Z C
TNZW Reg - - - - N Z -
N⇒ R15

X TNZW X 2 1 5D
Y TNZW Y 2 2 90 5D
See also: TNZ, CPW
156/162 Doc ID 13590 Rev 3

TRAP Software interrupt TRAP

Syntax TRAP
Operation PC = PC + 1
(SP--) = LSB (PC)
(SP--) = MSB (PC)
(SP--) = Ext(PC)
(SP--) = YL
(SP--) = YH
(SP--) = XL
(SP--) = XH
(SP--) = A
(SP--) = CC
PC = TRAP Interrupt Vector Contents
Description When processed, this instruction forces the trap interrupt to occur and to be
processed. It cannot be masked by the I0 or I1 flags.

mnem
V I1 H I0 N Z C
TRAP - 1 - 1 - - -
I1 and I0: 1
Set.
Addressing
mode
Inherent TRAP 9 1 83 ✗
See also: IRET
Doc ID 13590 Rev 3 157/162

WFE Wait for Event WFE

(CPU stopped,
low power mode)
Syntax WFE
Operation The CPU Clock is stopped till an external event occurs. Internal peripherals
are still running. It is used for synchronization with other computing
resources (e.g coprocessor).
Description The state of the CPU is frozen, waiting for synchronization with an external
event. The CPU clock also is stopped, reducing the power consumption of
the microcontroller. Interrupt requests during this period are served
normally, depending on the CC.I[1:0] value.

mnem
V I1 H I0 N Z C
WFE - - - - - - -
Addressing
mode
Inherent WFE 1 2 72 8F
See also: HALT
158/162 Doc ID 13590 Rev 3

WFI Wait for Interrupt WFI

(CPU stopped,
low power mode)
Syntax WFI
Operation CC.I1= 1, CC.I0 = 0. The CPU Clock is stopped till an interrupt occurs.
Internal peripherals are still running.
Description The interrupt flag is cleared, allowing interrupts to be fetched. Then the
CPU clock is stopped, reducing the power consumption of
the microcontroller. The micro will continue the program upon an internal or
external interrupt.

mnem
V I1 H I0 N Z C
WFI - 1 - 0 - - -
I1: 1
Set.
I0: 0
Cleared.
Addressing
mode
Inherent WFI 10 1 8F ✗
See also: HALT
Doc ID 13590 Rev 3 159/162

XOR Logical Exclusive OR XOR

Syntax XOR A,src e.g. XOR A,#%00110101
Operation A <= A XOR src
Description The source byte, is logically XORed with the contents of the accumulator
and the result is stored in the accumulator. The source is a memory or data
byte.
Truth table
XOR 0 1
0 0 1
1 1 0

mnem dst src
V I1 H I0 N Z C
XOR A Mem - - - - N Z -
N⇒ R7
Z⇒ R7.R6.R5.R4.R3.R2.R1.R0

A #byte XOR A,#$55 1 2 A8 XX ✗
A shortmem XOR A,$10 1 2 B8 XX ✗
A longmem XOR A,$1000 1 3 C8 MS LS ✗
A (X) XOR A,(X) 1 1 F8 ✗
A (shortoff,X) XOR A,($10,X) 1 2 E8 XX ✗
A (longoff,X) XOR A,($1000,X) 1 3 D8 MS LS ✗
A (Y) XOR A,(Y) 1 2 90 F8 ✗
A (shortoff,Y) XOR A,($10,Y) 1 3 90 E8 XX ✗
A (longoff,Y) XOR A,($1000,Y) 1 4 90 D8 MS LS ✗
A (shortoff,SP) XOR A,($10,SP) 1 2 18 XX
A [shortptr.w] XOR A,[$10.w] 4 3 92 C8 XX ✗
A [longptr.w] XOR A,[$1000.w] 4 4 72 C8 MS LS
XOR
A ([shortptr.w],X) 4 3 92 D8 XX ✗
A,([$10.w],X)
XOR
A,([$1000.w],X)
XOR
A ([shortptr.w],Y) 4 3 91 D8 XX ✗
A,([$1000],Y)
See also: AND, OR, CPL, NEG
160/162 Doc ID 13590 Rev 3

PM0044 Revision history
8 Revision history
Table 43. Document revision history

Date Revision Changes
14-Jan-2008 1 Initial release.

05-Jun-2008 2 Modified Figure 2: Context save/restore for interrupts on page 14
Changed notation for hexadecimal numbers from XXh to 0xXX.
Removed CPU register context saving from Section 3.2: CPU
registers.
Added LDF in Table 22: Available Extended Direct addressing mode
instructions.
Updated Figure 2: Context save/restore for interrupts.
Added BREAK instruction in Table 41: Instruction groups.
Added Section 5: Pipelined execution.
Table 42: Instruction set summary: updated ADDW, BCCM, BRES,
20-Sep-2011 3
BSET, BTJF, BTJT, CALLR, DEC, DECW, DIV, EXGW, JRA, JRC,
JREQ, JRH, JRIH, JRIL, JRM, JRMI, JRNC, JRNE, JRNH, JRNM,
JRNV, JRPL, JRSGE, JRSGT, JRSLE, JRSLT, JRUGE, JRULT, LDF,
LDW, MOV, NEG, PUSH, RRCW, SBC, SLA, SLAW, SLL, SLLW,
SRA, SRAW, SRL, SRLW, SUB. Added BREAK and INT instructions.
Section 7: STM8 instruction set: updated ADD, ADDW, BCCM, BCP,
BCPL, BRES, BSET, BTJF, BTJT, CLR, CP, CPW, DEC, DECW,
HALT, INCW, INT, JP, JRxx, MOV, RLWA, RRCW, RRWA, SBC,
SRLW, SUB, and SWAPW. Added BREAK instruction. Merged JRA
with JRL instructions, SLA with SLL, and SLAW with SLLW.
Doc ID 13590 Rev 3 161/162

PM0044
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PM0044

STM8 CPU programming manual

September 2011 Doc ID 13590 Rev 3 1/162

3 STM8 core description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 STM8 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 STM8 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/162 Doc ID 13590 Rev 3

6.3.1 Short Direct addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7 STM8 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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4/162 Doc ID 13590 Rev 3

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8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

6/162 Doc ID 13590 Rev 3

Table 1. Interruptability levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Doc ID 13590 Rev 3 7/162

Figure 1. Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

8/162 Doc ID 13590 Rev 3

Doc ID 13590 Rev 3 9/162

Boot ROM Memory area containing the bootloader code

1.1 STM8 development support

10/162 Doc ID 13590 Rev 3

1.2 Enhanced STM8 features

Doc ID 13590 Rev 3 11/162

12/162 Doc ID 13590 Rev 3

3 STM8 core description

3.2 CPU registers

Index registers (X and Y)

Program Counter (PC)

Figure 1. Programming model

Doc ID 13590 Rev 3 13/162

Stack Pointer (SP)

Figure 2. Context save/restore for interrupts

14/162 Doc ID 13590 Rev 3

Global configuration register (CFG_GCR)

Condition Code register (CC)

Table 1. Interruptability levels

Interruptable Level 1 Lowest 0 1

● H: Half carry bit

Doc ID 13590 Rev 3 15/162

● I0: Interrupt mask level 0

Nothing = Flag not affected

16/162 Doc ID 13590 Rev 3

4 STM8 memory interface

4.1 Program space

4.2 Data space

Doc ID 13590 Rev 3 17/162

Figure 3. Address spaces

PROGRAM SPACE DATA SPACE

18/162 Doc ID 13590 Rev 3

4.3 Memory interface architecture

Figure 4. Memory Interface Architecture

Memory Interface (Flash)

RAM FETCH INSTRUCTION N Y

STALL A15..0 R/W

Memory Interface (RAM)

Doc ID 13590 Rev 3 19/162

Figure 5. Pipelined execution principle

&%4#( )NSTRUCTIONSS FETCHEDFROMMEMORY

5.1 Description of pipelined execution stages

&%4#( )NSTRUCTIONSS FETCHEDFROMMEMORY

&ETCH $ECODE-EM2EAD %XECUTE7RITEBACK