Regulation – 2018 Basic Electronics-18ELN14

Module 2

FET and SCR

Introduction, JFET: Construction and operation, JFET Drain Characteristics and parameters, JFET
Transfer chacteristics, Square law expression for I D, Input resistance, MOSFET: Depletion and
Enhancement type MOSFET-Construction, Operation, Characteristics and Symbols, CMOS
Silicon Controlled Rectifier(SCR)-Two Transistor model, Switching action, Characteristics, Phase
Control application

Introduction
A field effect transistor (FET)is a voltage operated device that can be used in amplifiers and
switching circuits. There are two major categories of FET’s Junction FET(JFET) and Metal oxide
semiconductor FET(MOSFET). These are further subdivided into p-channel and n-channel devices.

JFET: Construction
A JFET is a type of FET that operates with a reverse biased pn junction to control current in a
channel. Depending on their structures, JFETs fall into either of two categories, n channel or p channel.

Fig(a) shows basic structure of an n-channel JFET. Wire leads are connected to each end of the n-
channel; drain is at the upper end and the source is at the lower end. Two p-type regions are diffused in
the n-type material to form a channel, both p-type regions are connected to the gate lead. A p-channel
JFET is shown in fig(b).

Operation

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 To illustrate the operation of a JFET, fig shows dc bias voltages applied to an n-channel
device.VDD provides a drain to source voltage and supplies current from drain to source.V GG sets the
reverse bias voltage between the gate and the source as shown. JFET is always operated with gate source
pn junction reverse biased. Reverse biasing of the gate source junction with a negative gate voltage
produces a depletion region along the pn junction, which extends into the n channel and thus increases its
resistance by restricting the channel width. The channel width and channel resistance can be controlled by
varying the gate voltage, thereby controlling the amount of drain current ID.

JFET Symbols

JFET Drain Characteristics and Parameters

Drain Characteristics curve

Consider the case when the gate-to-source voltage is zero(V GS=0V)This is produce by shorting the
gate to source, as in fig(a) where both are grounded. As V DD is increased from 0V,ID will increase
proportionally as shown in the graph of fig(b) between points A and B. In this area, the channel resistance
is essentially constant because the depletion region is not large enough to have significant effect. This is
called ohmic region because VDS and ID are related by ohm’s law.
At point B in fig(b),the curve levels off and enters the active region where I D becomes essentially
constant. As VDS increases from point B to Point C, the reverse bias voltage from gate to drain (V GD)
produces a depletion region large enough to offset the increase in VDS. Thus keeping ID relatively
constant.
Pinch-off-voltage
For VGS =0 V, the value of VDS at which ID becomes essentially constant (point B on the curve in
Figure (b)) is the pinch-off voltage, VP. For a given JFET, VP has a fixed value. As you can see, a
continued increase in VDS above the pinch off voltage produces an almost constant drain current. This
value of drain current is IDSS (Drain to Source current with gate Shorted) and is always specified on JFET
datasheets. IDSS is the maximum drain current that a specific JFET can produce regardless of the external
circuit, and it is always specified for the condition, VGS= 0 V.

Breakdown
As shown in the graph in Figure (b), breakdown occurs at point C when ID begins to increase very
rapidly with any further increase in VDS. Breakdown can result in irreversible damage to the device, so
JFETs are always operated below breakdown and within the active region (constant current) (between
points B and C on the graph).

VGS Controls ID

Let’s connect a bias voltage, VGG, from gate to source as shown in Figure(a). As VG is set to
increasingly more negative values by adjusting VGG, a family of drain characteristic curves is produced, as
shown in Figure (b). Notice that ID decreases as the magnitude of VGS is increased to larger negative
values because of the narrowing of the channel. Also notice that, for each increase in VGS, the JFET
reaches pinch-off (where constant current begins) at values of VDS less than VP. The term pinch-off is not
the same as pinchoff voltage, Vp. Therefore, the amount of drain current is controlled by VGS

Cut off Voltage

The value of VGS that makes ID approximately zero is the cut off voltage, VGS(off),.The JFET
must be operated between VGS= 0 V and VGS(off). For this range of gate-to-source voltages, ID will vary
from a maximum of IDSS to a minimum of almost zero.

Comparison of Pinch-Off Voltage and Cut off Voltage

As we seen, there is a difference between pinch-off and cut off voltages. There is also a
connection. The pinch-off voltage VP is the value of VDS at which the drain current becomes constant and
equal to IDSS and is always measured at VGS = 0 V. However, pinch-off occurs for VDS values less than VP
when VGS is nonzero. So, although VP is a constant, the minimum value of VDS at which ID becomes
constant varies with VGS. VGS(off) and VP are always equal in magnitude but opposite in sign. A datasheet
usually will give either VGS(off) or VP, but not both. However, when you know one, you have the other.
For example, if VGS(off) = -5 V, then VP = +5 V, as shown in Figure (b).

JFET Transfer Characteristic

A range of VGS values from zero to VGS(off) controls the amount of drain current. For an n-
channel JFET, VGS(off) is negative, and for a p-channel JFET, VGS(off) is positive. Because VGS does
control ID, the relationship between these two quantities is very important. Figure is a general transfer
characteristic curve that illustrates graphically the relationship between VGS and ID. This curve is also
known as a transconductance curve.

Notice that the bottom end of the curve is at a point on the VGS axis equal to VGS(off ),and the top end of
the curve is at a point on the ID axis equal to IDSS. This curve shows that

The transfer characteristic curve can also be developed from the drain characteristic curves by plotting
values of ID for the values of VGS taken from the family of drain curves at pinch-off, as illustrated in
Figure for a specific set of curves. Each point on the transfer characteristic curve corresponds to specific
values of VGS and ID on the drain curves.
For example, when VGS = -2V, ID = 4.32 mA. Also, for this specific JFET, VGS(off) = -5 V and IDSS = 12
mA.
Square Law Expression for ID

A JFET transfer characteristic curve is expressed approximately as

----------- (1)

With Equation (1), ID can be determined for any VGS if VGS(off) and IDSS are known. These quantities are
usually available from the datasheet for a given JFET. Notice the squared term in the equation. Because
of its form, a parabolic relationship is known as a square law, and therefore, JFETs and MOSFETs are
often referred to as square-law devices.

Input Resistance
A JFET operates with its gate-source junction reverse-biased, which makes the input resistance at
the gate very high. This high input resistance is one advantage of the JFET over the BJT. (Recall that a
bipolar junction transistor operates with a forward-biased base-emitter junction.) JFET datasheets often
specify the input resistance by giving a value for the gate reverse current, IGSS, at a certain gate-to-source
voltage. The input resistance can then be determined using the following equation, where the vertical lines
indicate an absolute value (no sign):

For example, the 2N5457 datasheet, maximum IGSS of -1.0nA for VGS=-15V at 25oC, at IGSS increases
with temperature, so the input resistance decreases.

MOSFET
The MOSFET (metal oxide semiconductor field-effect transistor) is another category of field-
effect transistor. The MOSFET, different from the JFET, has no pn junction structure; instead, the gate of
the MOSFET is insulated from the channel by a silicon dioxide (SiO 2) layer. The two basic types of
MOSFETs are enhancement (E) and depletion (D). Of the two types, the enhancement MOSFET is more
widely used. Because polycrystalline silicon is now used for the gate material instead of metal, these
devices are sometimes called IGFETs (insulated-gate FETs).

Enhancement MOSFET (E-MOSFET): Construction and Operation

The E-MOSFET operates only in the enhancement mode and has no depletion mode. It differs in
construction from the D-MOSFET, in that it has no structural channel. Notice in Figure (a) that the
substrate extends completely to the SiO 2 layer. For an n-channel device, a positive gate voltage above a
threshold value induces a channel by creating a thin layer of negative charges in the substrate region
adjacent to the SiO2 layer, as shown in Figure (b). The conductivity of the channel is enhanced by
increasing the gate-to-source voltage and thus pulling more electrons into the channel area. For any gate
voltage below the threshold value, there is no channel.
E-MOSFET Symbols
The schematic symbols for the n-channel and p-channel E-MOSFETs are shown in figure . The
broken lines symbolize the absence of a physical channel. An inward pointing substrate arrow is for n
channel, and an outward-pointing arrow is for p channel.Some E-MOSFET devices have a separate
substrate connection.

Depletion MOSFET (D-MOSFET): Construction and operation

Another type of MOSFET is the depletion MOSFET (D-MOSFET), and figure illustrates its basic
structure. The drain and source are diffused into the substrate material and then connected by a narrow
channel adjacent to the insulated gate. Both n-channel and p-channel devices are shown in the figure.We
will use the n-channel device to describe the basic operation. The p-channel operation is the same, except
the voltage polarities are opposite those of the n-channel.

The D-MOSFET can be operated in either of two modes—the depletion mode or the enhancement
mode—and is sometimes called a depletion/enhancement MOSFET. Since the gate is insulated from the
channel, either a positive or a negative gate voltage can be applied. The n-channel MOSFET operates in
the depletion mode when a negative gate-to-source voltage is applied and in the enhancement mode
when a positive gate-to-source voltage is applied. These devices are generally operated in the depletion
mode.
D-MOSFET Symbols
The schematic symbols for both the n-channel and the p-channel depletion MOSFETs are shown
in figure. The substrate, indicated by the arrow, is normally (but not always) connected internally to the
source. Sometimes, there is a separate substrate pin.

E-MOSFET Transfer Characteristic

The E-MOSFET uses only channel enhancement. Therefore, an n-channel device requires a
positive gate-to-source voltage, and a p-channel device requires a negative gate-to-source voltage. Figure
shows the general transfer characteristic curves for both types of E-MOSFETs. As we see, there is no
drain current when VGS= 0. Therefore, the E-MOSFET does not have a significant I DSS parameter, as do
the JFET and the D-MOSFET. Notice also that there is ideally no drain current until V GS reaches a certain
nonzero value called the threshold voltage, VGS(th).

The equation for the parabolic transfer characteristic curve of the E-MOSFET differs from that of
the JFET and the D-MOSFET because the curve starts at V GS(th) rather than VGS(off ) on the horizontal axis
and never intersects the vertical axis. The equation for the E-MOSFET transfer characteristic curve is

The constant K depends on the particular MOSFET and can be determined from the datasheet by taking
the specified value of ID, called ID(on), at the given value of VGS

D-MOSFET Transfer Characteristic

The D-MOSFET can operate with either positive or negative gate voltages. This is indicated on
the general transfer characteristic curves in Figure 8–45 for both n-channel and p-channel MOSFETs. The
point on the curves where VGS =0 corresponds to IDSS. The point where ID= 0 corresponds to VGS(off) = -VP.
As with the JFET, The square-law expression in Equation (1) for the JFET curve also applies to
the D-MOSFET curve,
CMOS
CMOS is the complementary metal oxide semiconductor, where in two enhancement MOSFET’s,
one N-type(NMOS) and other P-type(PMOS),are connected as a complementary pair. The two gates are
connected to form the input terminal and the two drains are connected to form the output terminals as
shown in fig(a).

The CMOS circuit offers two advantages:

1. The drain current is very low and flows mainly during transition from one state to the other (ON/OFF).
2. The power drawn in steady state is extremely small.

Digital Circuit Applications

The circuit for a CMOS digital inverter is as in fig(a).The source terminal of PMOS (T2) is
connected to Vss=5V,while the source terminal of NMOS(T1)is grounded.
Operation
1. Input
Vi=5V 1-state
VGS=5-5=0V
T2 is nonconducting, OFF (its VT is negative),draws only leakage current, offers high resistance (R2)
VGS1=5V>VT
T1 is conducting, ON offers very low resistance(R1).The circuit equivalent in this state is drawn in fig(b)
Output V0=0 0-state
It can be seen from the circuits of fig(b) that
VO=(R1/R1+R2)VSS =0V

2.Input
Vi=0V 0-state
VGS2= -5V , T2 is conducting(low resistance)
VGS1= -5V , T1 is non conducting(high resistance)
Output
V0=5V 1-state
Thus we can see that the circuit acts as an inverter;1-state input produces 0-state output and 0-state input
produces 1-state output.

Silicon Controlled Oscillator(SCR)

It is a four layer device which along with its associated circuitry has a very wide range of
applications-Rectifiers, Regulated power supplies,DC to AC conversion, Relay Control,Time Delay
circuits and many more.

Basic Operations and Symbols

The material used for SCR is silicon because of high temperature requirement of handling large
current and power. Its four layers are arranged as pnpn shown in fig. The outer layers are connected to
terminals to form Anode (positive terminal) and Cathode (negative terminal).The P-layer closer to the
cathode is connected to the gate terminal. The SCR symbol is drawn in fig.It is similar to that of diode,
the difference being the indication of the gate terminal.

As a forward voltage is applied across the anode(+) and cathode(-),no conduction takes place as
the middle np junction is reverse biased. If a positive pulse is applied at the gate, such that a current of
magnitude equal to more than IG, (turn-on)flows into the gate, the processes in the device cause it to go
into conduction. The forward current (anode to cathode) is offered a resistance as 0.01 to 0.1Ω.However,
because of regenerative action, removing the gate current does not cause the device to turn off. The
dynamic reverse resistance of an SCR is as high as 100KΩ or more.

Two Transistor Model

The cross sectional view of an SCR with its four layers is drawn in fig. The device comprises one
PNP and one NPN transistor. The base of PNP is connected to the collector of NPN, and the collector of
PNP is connected to the base of NPN, while gate is connected to the base of NPN.
The corresponding two transistor model equivalent circuit is drawn in fig.
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Fig: Two transistor model

Switching Action
Let a positive V is applied to the anode (E 1),and the cathode (E2) and gate(G) be both grounded as
shown in fig(a). As VG=VBE2=0, the transistor T2 is in ‘off’ state. It means that CB junction of T2, through
EB-junction of T1 is reverse biased. Therefore, IB1=ICO(minority carrier current)is too small to ‘turn –
on’T1.Thus T1 and T2 are ‘off’ and so anode current.
IA= IB1=ICO
is off negligible order. It means that SCR is in ‘turn-off’ state, that is the switch between anode (E 1) and
cathode (E2) is open.

Now ,let a voltage +VG be applied at the gate as shown in fig(b). As VBE2=VG, on making VG
sufficiently large ,IB2 will cause T2 to turn on and the collector and the collector IC2 becomes large. As

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IB1=IC2,T2 turns on causing a large collector current IC1(IA=IC1) to flow. This in turn, increases IB2 causing a
regenerative action to set in. The result is that the SCR is turned on, that is switch between anode(E1) and
cathode(E2) is closed (turn-on).The current IA must be limited by the external circuit,say a series
resistance between the source and E1.
The turn-on time of an SCR is typically 0.1 to 1µs.However,for high power devices in the range of
100-400A,turn-on time may be 10-25µs.

TURN -OFF
When the SCR is in conduction mode, the gate is ineffective in turning it off. The turn off
mechanism is called commutation and it can be achieved in two ways
Natural commutation: When the source that feeds the current to anode of SCR is such that naturally
passes through zero, the SCR turns off at the current zero. This is the case when the SCR is fed from the
ac source. In this situation, the commutation is also known as line commutation.
Forced commutation: In this method of commutation, the current through the SCR is forced to become
zero by passing a current through it in opposite direction from an independent circuit.

Turn-off Circuit
Basic Turn-off circuit is shown in fig. A transistor and a dc battery source in series are connected
to the SCR. When the SCR is in conduction mode(on),I B=0 and when the transistor is off, it is almost an
open circuit. To turn off the SCR, a positive IB pulse of magnitude large enough to drive the transistor
into saturation is applied at the transistor base. The transistor acts almost like a short circuit. This causes
flow of very large Ioff through the SCR in the opposite direction to its conduction current. The total SCR
current reduces to zero in a very short time causing it to turn off.The transistor has to withstand a large
current but for a very short time.Turn-off time of an SCR is typically 5-30µ s.

SCR Characteristics
The symbol and I-V characteristics of an SCR are given in fig. Various voltages and currents
which provide important information for SCR application.

1. Forward breakover voltage VF (BR) is the voltage at which for a given IG,the SCR enters into
conduction mode. As in fig, that this voltage reduces as IG ,increases. VF (BR) has dependence on
the circuit connection between G and K terminals.
2. Holding current IH is the value of the current below which SCR switches from conduction state
to forward blocking regions of specified conditions.

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3. Forward and reverse blocking regions are those regions in which the SCR is open circuited and
no current flows from anode to cathode.
4. Reverse breakdown voltage corresponds to zener or avalanche region of a diode.

Applications of SCR
Variable Resistance Phase Control
A variable phase control circuit is as in fig. The SCR gate current is controlled through R and the
variable R1.Let RG be adjusted to high value so that even at the peak value v i(positive),IG<IG(turn-on) and no
conduction takes place. As R1 is reduced, IG rises to turn on the value at a particular angle(time)of vi. The
conduction then begins and continues till vi reaches zero (1800).Varying R1 allows the adjust of SCR
firing angle from 00 to 900 as shown in fig.

At R1,corresponding to the firing angle of 900, vi= vi(max) .If R1 is adjusted for firing angle at α,the
firing will takes place at angle α<900 but not at angle β=(1800-α)>900 as the angle α is reached in time on
the vi wave. So the operation of this circuit is known as half-wave, variable –resistance phase control.
Thus, iL(dc) can be adjusted to the maximum value at 00 to the minimum value of 900.It may be
noted that a diode is provided in the firing circuit to prevent the flow of reverse gate current.

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