At76c712 jt064

Features
• Advanced RISC Architecture, 130 Powerful Instructions, most Single Clock Cycle
Execution
• JTAG (IEEE std. 1149.1 compliant) Interface
• Boundary-Scan Capabilities According to the JTAG Standard
• Extensive On-Chip Debug Support
• Clock Generator Provides CPU Rates Up to 48MHz
• Only One External Clock Crystal of 12MHz can generate all the required System
Clocks:
• Internal Clock for Standard UART Rates High Speed
(48MHz) AVR®
• A 48MHz and 96MHz clock for USB Data Recovery
• AVR Processor and System Clock.
• On Chip Bootstrap ROM Provides a Variety of Firmware Upgrade Modes
• Device Firmware Upgrade through USB for the internal Program SRAM (No
based Bridging
External Non-Volatile SPI Memory Required)
• Device Firmware Upgrade through USB for both the internal Program SRAM
Device
and the External SPI DataFlash® or EEPROM or Serial Flash.
• SPI Program Mode from the External DataFlash or EEPROM or Serial Flash.
• Two On Chip 16550 UARTs Supporting Baud Rates Up to 921Kbaud. AT76C712
• Both UARTs incorporate individual Transmit and Receive FIFOs of 16 Bytes
• UART0 Supports Modem Control Signals
• Programmable SPI interface
• Full-Speed USB Interface (12Mbit/s) 2.0 Compliant
• DMA Channels allow fast data transfers between Endpoint Buffers and internal SRAM.
The DMA transfer rate is 12MHz for all channels.
• 8K x 16bits (Up to 11K x 16bits), in-system SRAM for Program Code (Program Memory)
• On Chip 8KBytes SRAM. Default use of this memory is for Data and Variables. You can
configure 2, 4 or 6Kbyte to be remapped for program storage in the Address Area
above the Program Memory. Thus, reallocating 6KBytes, the Program Space becomes
11K x 16bits and the Data Space 2KBytes.
• Two 8-bit Timer/Counters
• One 16-bit Timer/Counter
• Two External interrupts Through GPIOs
• Programmable Watchdog Timer
• Low voltage operation:
• 1.8V for the Core,
• 1.8V or 3.3V for the periphery
• 3.3V for the USB.
• Low cost 64-pin leadfree TQFP Package, suitable for USB-to-UART Bridge Applications
5635AX–USB–10/06
1. Overview
The Atmel AT76C712 is a low-power USB peripheral, which can connect various types of
devices to a common USB port.
It is based on the AVR enhanced RISC architecture core which combines a rich instruction set
with 32 general purpose working registers. By executing powerful instructions in a single clock
cycle, the AT76C712 achieves throughputs approaching 1MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
The clock generation circuit requires a clock input of 12MHz and provides standard clock rates
for the USB module and the on chip UARTs as well as several AVR CPU rates varying from
16MHz up to 48MHz.
Internal DMA channels allow fast data transfers between the USB buffers and the on-chip mem-
ory without processor interruption. USB DMA transfers use devoted data paths with
12Mbytes/sec transfer rate.
25 multipurpose I/O pins, provide the signals for the external interfaces. The AT76C712 offers in
addition two external interrupts, programmable Watchdog Timer, flexible timer/counters with
compare modes and supports various power down modes.
On power up, the bootstrap code is executed from the Boot ROM. The purpose of the bootstrap
code is to load the application code into the Program Memory. The application code is executed
from the on-chip SRAM Program Memory contributing to the low power consumption. Different
programming modes are supported depending on the application (the mode is selected exter-
nally by the PMODE0 and PMODE1 pins).
In a slave programming mode, an external system (the host), operating as SPI master, can
transfer in a raw format the program image into the program memory of the device. In this case,
the AT76C712 operates as SPI slave and starts running from the internal boot ROM code which
switches to the start of program memory, when it detects the end of a valid program transfer
from the host to the AT76C712 (see the “Slave Programmming Mode” on page 9).
In a Master Programming Mode, the AT76C712 reads the whole program image from an exter-
nal SPI EEPROM or DataFlash® or Serial Flash and switches to the start of Program Memory
when it completes the reading (see the “Master Programming Modes” on page 10). Alternatively,
the AT76C712 reads only configuration parameters from a small serial non-volatile memory
(Serial EEPROM or DataFlash® or Serial Flash), enables the USB Controller and executes the
USB Device Firmware Upgrade (DFU) code which is stored in the boot ROM.
The USB Controller consists of a Serial Interface Engine (SIE), a Function Interface Unit (FIU)
and a System Interface (SI). The SIE performs bit processing, line coding, packet generation
and packet type recognition, serial-parallel data conversion and packet delineation. The Func-
tion Interface Unit consists of a protocol engine and a USB device with one Control Endpoint
(EP0) and four programmable Endpoints with up to 512bytes maximum total size. All Endpoints
support double buffering in order to provide the maximum performance specified for the USB.
The AT76C712 supports two 16550 UART modules with 16-bytes FIFOs in each direction.
UART0 serial interface provides full modem control functionality with the RTS/CTS, DTR/DSR,
RI and CD signals. These signals are provided by the general purpose I/O pins of PORTD.
The AT76C712 AVR is supported with a full suite of program and system development tools
including: C compiler, macro assemblers, program debugger/simulators, in-circuit emulators,
evaluation kits, etc.
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2. AT76C712 Functional Diagram
LFT XIN XOUT PM0 PM1 nRST
Program Memory SUSP

Clock USB_ATTACH
Controller
TESTEN Generator
TEST_CK Boot 8Kx16bits
POR_VSEL ROM SRAM
I/O Mapped modules PA[0:1]
VEXT
WD Timer PB0/T0
PB1/T1
Timers PB2/T2
TMS PB3/ICP
JTAG TAP
TCK PB4/nSS
OCD
AVR core Register SPI
Boundary Scan Chain (JTAG)

TDI File Controller PB5/MOSI
TDO PB6/MISO
PB7/SCK
PC[0:2]
Port Interface
PD0/SIN0
PD1/SOUT0
PD2/ RTS
PD3/CTS
PD4/DSR
Memory PD5/ DTR
UART0 PD6/CD
Controller PD7/RI
FIFOs
IrDA 1.0
DMA
USB Controller SRAM PE0 /SIN1
DP, DM UART1 PE1/SOUT1
Controller 8Kbytes
PE2/INT0
PE3/INT1
FIFOs
Memory Mapped modules
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3. Pin Diagram
3.1 64–pin TQFP Package
USB_ATTACH
TEST_CLK
TEST_EN
PB0/T0
PB1/T1
CGND
PGND
CVDD
PVDD
PVDD
TDO
TMS
TCK
PA0
PA1
TDI
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48 PVDD_USB
PGND 1
47 DM
nRST 2
46 DP
CVDD 3
45 SUSP
PE3/INT1 4
44 CGND
PE2/INT0 5
43 PGND
PE1/SOUT 6
42 CVDD
PE0/SIN1 7
41 PD0/SIN0
PVDD 8
40 PD1/SOUT0
PMODE0 9
39 PD2/RTS
PMODE1 10
38 PD3/CTS
CGND 11
37 PD4/DSR
LFT 12
36 PD5/DTR
PAGND 13
35 PD6/CD
XIN 14
34 PD7/RI
XOUT 15
33 PVDD_PORT D
PAVDD 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PGND
VEXT
CVDD
PC2
PC1
PC0
PB2/T2
POR_VSEL
PVDD
PB6/MISO
PB5/MOSI
PVDD
PB3/ICP
PB4/nSS
CGND
PB7/SCK
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4. Pin Summary – Pin Assignment of the 64–pin Package
Table 4-1. Pin Summary – Pin Assignment of the 64–pin Package

Pin # Pin Name Pin # Pin Name Pin # Pin Name
1 PGND 23 PC0 45 SUSP
2 nRST 24 CVDD 46 DP
3 CVDD 25 PB7/SCK 47 DM
4 PE3/INT1 26 PB6/MISO 48 PVDD_USB
5 PE2/INT0 27 PB5/MOSI 49 PGND
6 PE1/SOUT1 28 PB4/nSS 50 PVDD
7 PE0/SIN1 29 PB3/ICP 51 USB_ATTACH
8 PVDD 30 PB2/T2 52 TCK
9 PMODE0 31 PVDD 53 TMS
10 PMODE1 32 PGND 54 TDI
11 CGND 33 PVDD_PORTD 55 TDO
12 LFT 34 PD7/RI 56 CGND
13 PAGND 35 PD6/CD 57 CVDD
14 XIN 36 PD5/DTR 58 PA1
15 XOUT 37 PD4/DSR 59 PA0
16 PAVDD 38 PD3/CTS 60 PB1/T1
17 VEXT 39 PD2/RTS 61 PB0/T0
18 POR_VSEL 40 PD1/SOUT0 62 TEST_EN
19 PVDD 41 PD0/SIN0 63 TEST_CLK
20 CGND 42 CVDD 64 PVDD
21 PC2 43 PGND
22 PC1 44 CGND
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5. Signal Description
Table 5-1. Signal Description

Type: I = Input, O = Output, I/O = Bi-directional, A = Analog Signal
Name Type Description
JTAG Signals
TCK I JTAG clock input
TDI I Scan chain bitstream input
TDO O Scan chain bitstream output
TMS I JTAG mode select input
Port Signals
Port A serves as an 2-bit bi-directional I/O port with internal pull-up resistors. Port A output buffers can sink
PA[0:1] B 20 mA and can drive LED displays directly. As inputs, Port A pins that are externally pulled low will source
current. The Port A pins are inputs when a reset condition becomes active, even if the clock is not running.
The high nibble of port B (PB[7–4]) offers the signals for the SPI interface. The low-nibble (PB[3-0]) is used
from the three internal timers as trigger and capture inputs. These functions can operate regardless the
direction of the PB[3-0] pins.
Port B serves also as an 8-bit bi-directional I/O port with internal pull-up resistors, if the alternative
functions of the port are not used. The Port B output buffers can sink 20 mA and can drive LED displays
directly. As inputs, Port B pins that are externally pulled low will source current. The Port B pins are inputs
when a reset condition becomes active, even if the clock is not running.
The alternative functions of Port B are explained in more details at the following table and at the proper
sections.
Alternative Functions Of Port B

Port Alternate Function
PB[0:7] B
PB0 T0: Timer/Counter 0 clock input
PB3 ICP1: Input Capture Pin for Timer/Counter1
PB4 nSS: SPI slave port select input
PB5 MOSI: SPI slave port select input
PB6 MISO: SPI master data in, slave data out.
PB7 SCK: SPI master clock out, slave clock in.
Port C serves as an 3-bit bi-directional I/O port with internal pull-up resistors. The Port C output buffers
can sink 20 mA and can drive LED displays directly. As inputs, Port C pins that are externally pulled low
PC[0:2] B
will source current. The Port C pins are inputs when a reset condition becomes active, even if the clock is
not running.
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Table 5-1. Signal Description (Continued)
Port D offers the data and handshaking signals for UART0 interface, as listed bellow. These functions are
explained in more detail on UART section.
Port D, when the UART0 is not used, is also an 8-bit bi-directional I/O port with internal pull-up resistors.
The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source
current. The Port D pins are inputs when a reset condition becomes active, even if the clock is not running.
Alternative Functions of Port D

SIN0, Serial In UART0 (I): This pin provides the serial receive data
PD0
input to UART0.
PD[0:7] B
SOUT0, Serial Out UART0 (O): This pin provides the serial
PD1
transmit data from the UART0.
PD2 nRTS, Ready To Send (B): RTS UART0 handshaking signal.
PD3 nCTS, Clear To Send (B): CTS UART0 handshaking signal.
PD4 nDSR, Data Set Ready (B): DSR UART0 handshaking signal.
PD5 nDTR, Data Terminal Ready (B): DTR UART0 handshaking signal.
PD6 nCD, Carrier Detect (B): CD UART0 handshaking signal.
PD7 nRI, Ring Indicator (B): RI UART0 handshaking signal.
Port E offers the data signals for UART1 interface and offers 2 external interrupt lines (edge triggered or
level sensitive external interrupt). These functions are explained in more detail on the following sections.
Port E, when the alternative functions are not used, is also an 8-bit bi-directional I/O port with internal pull-
up/down resistors. Pins PE2 and PE3 have pull-down resistors while the rest pins have pull-up resistors.
The output buffers of Port E pads can sink 20 mA. As inputs, Port E pins that are externally pulled low (or
high for PE2 and PE3) will source current. The Port E pins are inputs when a reset condition becomes
active, even if the clock is not running.
Alternative Functions of Port E

PE[0:3] B
SIN1, Serial In UART1 (I): This pin provides the serial receive
PE0
data input to UART1.
SOUT1, Serial Out UART1 (O): This pin provides the serial
PE1
transmit data from the UART1.
PE2 INT0, edge triggered or level sensitive interrupt with pull-down
PE3 INT1, edge triggered or level sensitive interrupt with pull-down
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Table 5-1. Signal Description (Continued)
USB Serial Interface
USB data I/O (positive differential line). DP and DM form the differential signal pin pair connected to the
DP I/O Host Controller or an upstream Hub.The DP/DM lines require the addition of external series
resistors of 27Ω
DM I/O USB data I/O (negative differential line)
This output controls the pullup resistor of the DP signal. When low, it enforces the host to re-enumerate the
USB_ATTACH O
device.
Programming Mode Control Signals
PMODE0 PMODE0 and PMODE1 pins are used from the on-chip bootstrap code and define the programming
I
PMODE1 mode. For more details refer to the Program Modes section.
Test Signals
TEST_EN I General-purpose signal for test. Tied to VSS in normal conditions.
TEST_CLK I Used only for production setting. Tied to VSS in normal conditions.
POR_VSEL I Used in production phase only. Tied to VSS in normal conditions.
VEXT I Used in production phase only. Tied to 1.8V in normal conditions.
Other Signals
Reset input. A low on this pin for two clock cycles while the oscillator is running resets the device. Note that
nRST I
there is no internal pull-up resistor on this pin.
SUSP O Indicates if the IC is in power down mode
System clock oscillator pad, input to the inverting oscillator amplifier and input to the internal system clock
XIN I
operating circuit.
XOUT O System clock oscillator pad, output from the inverting oscillator amplifier.
An external RC filter should be connected to this pin to stabilize the lock-in time of the internal PLL for the
LFT A
master clock input XIN.Main PLL LFT input
Power Supply pins
CGND Power 0 Volts supply to the core
CVDD Power 1.8 Volts supply to the core
PGND Power 0 Volts supply to the external section of the I/O circuitry
PVDD Power 1.8V or 3.3 Volts supply to the external section of the I/O circuitry
PVDD_PortD Power 1.8V or 3.3 Volts supply to the external section of the Port D I/O circuitry
PVDD_USB Power 3.3 Volts supply for the USB and SUSPEND pins
PAGND Power 0 Volts Analog supply to the core, AC and DC sections of the I/O circuitry
PAVDD Power 1.8 Volts Analog supply to the core, AC and DC sections of the I/O circuitry
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6. Functional Description
6.1 Bootstrap ROM and Programming Modes

The bootstrap code in boot-ROM of AT76C712 is always activated on power up or after a sys-
tem reset. The functionality of the bootstrap code is configured by pins PMODE0 and PMODE1
according to Table 6-1. In SPI master programming modes, AT76C712 is master over the SPI
interface and can support an external Serial EEPROM or DataFlash or Serial Flash. SPI slave
programming mode is useful in a system where an external host is present and keeps the image
code for the AT76C712 in its own memory.
Table 6-1. Programming Modes

PMODE0 PMODE1 Programming Mode
0 0 USB DFU only (SPI disabled)
0 1 SPI Slave: SPI master host must be present
1 0 SPI Master: SPI Serial EEPROM or Serial Flash is assumed
1 1 SPI Master: SPI DataFlash is assumed
6.1.1 USB DFU-only Mode

When both PMODE0 and PMODE1 are tied to low, the bootstrap code will not enable the SPI
Controller but only the USB Controller. The system will wait for a USB DFU sequence using the
default USB descriptors (stored in boot ROM).
6.1.2 Slave Programmming Mode

When PMODE0 is tied low and PMODE1 high, the bootstrap ROM configures the SPI as slave
and waits for a specific sequence of data through SPI. The squence is:
1. nSS pin is enabled
2. 256 bytes of Configuration Header
3. Image of the code to be stored in Program memory starting from address 0. (The code
size is determined in the Configuration Header.)
4. nSS pin is disabled and re-enabled
5. Confirmation byte 1
6. Confirmation byte 2
7. nSS pin is disabled
Figure 6-1. Slave Programming Mode Sequence
Configuration Data transfer Confirmation
MISO Config. Header Image Code Data C1 C2
MOSI (8-bit Received Data Counter) C1 C2
nSS
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During the transmission of the configuration data and code Image, AT76C712 returns an 8-bit
counter value, which counts the received bytes. Thus, the host can verify whereas AT76C712
received the correct amount of data.
During the first confirmation cycle, the SPI master sends $CA to command “Continue Analyzing”
or $AB to command “Abort”. SPI Slave will return if the transmission of “Data was OK” by send-
ing $D0 or “Error” by sending $EE.
During the second confirmation cycle, the SPI master data are ignored and the SPI slave sends
the positive acknowledge $AD “Analyzing Data”, or one of the error messages: $DD “Discarding
data”, $DE “Discarding due to transmission error” or $EE “Error in confirmation command”.
Table 6-2 presents all possible cases.
Table 6-2. Possible Cases of Programming during Slave Program Mode

Case 1 2 3 4
Master $CA $AB xx invalid
Cycle 1
Slave $D0 $D0 $EE xx
Master xx xx xx xx
Cycle 2
Slave $AD $DD $DE $EE
Programming OK Fail Fail Fail
If the slave programming sequence fail, then the AT76C712 will enable the USB controller wait-
ing for DFU sequence, using the default USB descriptors.
6.1.3 Master Programming Modes

When PMODE0 is high, the bootstrap ROM configures the SPI as master and is prepared to
communicate either with a Serial EEPROM or Serial Flash, if PMODE1 is tied low, or with a
DataFlash, if PMODE1 is high. The AT76C713 supports any Atmel EEPROM of the AT25xxx
type (for example, AT25128AN) and DataFlash ® of the AT45xxx type (for example,
AT45DB011B) and Serial Flash of the AT25Fxxx type (for example, AT25F512AN).
The first 256 bytes that are read by the EEPROM or DataFlash or Serial Flash is the Configura-
tion Header containing useful information for the rest of the downloading procedure.
The bytes fetched from the external serial memory may be image code or just configuration
parameters. If it is image code, when data fetching has finished, the program running in the
boot-ROM resets the AVR program counter and switches to the SRAM Program memory by set-
ting the “Remap” bit in the Memory Access Interface.
If the data fetched from the external serial memory are configuration parameters only, the boot-
strap code of boot-ROM will not switch to the Program memory at the end of data fetching, and it
will enable the USB Controller. The USB will enumerate using the descriptors loaded from the
SPI memory. Upon the enumeration completion, if a DFU application is enabled in the host, the
bootstrap ROM will support program storing in the Program memory through USB. When pro-
gram storing is completed, the device will switch to the Program memory as described above.
6.1.4 Configuration Header

The Configuration Header is at least 256 bytes length and consumes the first page of the SPI
memory. For systems that use SPI-Slave programming or SPI EEPROM memory (e.g.
AT25128A) or Serial Flash, the Configuration Header length is fixed to 256 bytes. For systems
that use SPI DataFlash, the page size is equal to the page size of the used DataFlash. For
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example, using the AT45DB011B, the page size is 264 bytes and thus, the Configuration
Header will consume 264 bytes.
The meaning of each byte is described in Table 6-3.
Table 6-3. Configuration Header

Byte Description
0 $55
1 $AA
2 Size[7:0]
3 Size[15:8]
4 Control Byte
5 MEMMAP
Device Descriptor
Configuration Descriptor
6 CIS[ ]
Serial Descriptor
Product Descriptor
The first 2 bytes must be $55 and $AA in order to detect as valid the rest information. If those
bytes are invalid, then the bootstrap code rejects the operation immediately and starts the USB
DFU procedures.
Size[15:0] is the length of the Image code counted in pages. During the Slave Programming
mode and SPI EEPROM Master Programming mode, each page is 256 bytes length.
Control Bitmap (or Control Byte) is described in Table 6-4.
Table 6-4. Control Bitmap

Control Byte
Bit Field Description
7 WSOF Wait USB SOF.
6 — Reserved to zero (‘0’).
If set, then don’t use the PLL Lock signal (see also the PLCK bit of “Clock
5 PLCK
Control Register - CLK_CNTR” on page 46).
If set, then remap right after the downloading of the image code is
4 REMAP
successful.
If set, use for sleep state in suspend mode the stand-by mode instead of
3 STDBY
power-down mode.
2 INTPROT Interrupt Protect.
1 DTCH Detach Enable: If set, detach before remap.
0 SUSP If set the Suspend Circuit is on.
Note: Bits 7, 3, 2, 1 and 0 affect only the bootstrap USB DFU process
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MEMMAP byte will be assigned immediately to the MEMMAP register (see MEMMAP descrip-
tion in the “Memory Access Interface” on page 15). This register configures the size of the
Program Memory and Data Memory.
CIS[ ] is a table that carries the USB descriptors. Each descriptor starts right after the end of the
previous one. The order is shown in Table 6-3. The remaining bytes from the end of the CIS[ ]
table up to the end of the page have no meaning.
Note: Note that if the REMAP bit of the Control Byte is cleared, then the Image code will be loaded into
AT76C712 Program Memory (see Size[15:0]), the system will not remap, and the bootstrap code
will enable the USB core and enumerate using the new USB Descriptors (CIS[ ]) instead of the
default USB Descriptors.
6.2 The AVR core

The AT76C712 chip is based on the AVR core architecture. All peripherals, apart from SPI, IrDA
and timers, are memory mapped to the data address space.
6.2.1 Interrupt Handling

The interrupt vector table of the AT76C712 is shown in Table 6-5.
Table 6-5. Interrupt Vector table of the AT76C712

Vector Program
Number Address Source Interrupt Definition
1 $0000 RESET H/W Pin and Watchdog Reset
2 $0002 SUSP_RESM USB Suspend and Resume
3 $0004 USB USB H/W & USB DMA Interrupt
4 $0006 INT0 External Interrupt Request 0
5 $0008 INT1 External Interrupt Request 1
6 $000A INT2 External Interrupt Request 2
7 $000C INT3 External Interrupt Request 3
8 $000E TIMER2_OVF Timer/Counter2 Overflow
9 $0010 TIMER1_CAPT Timer/Counter1 Capture Event
10 $0012 TIMER1_COMPA Timer/Counter1 Compare Match A
11 $0014 TIMER1_COMPB Timer/Counter1 Compare Match B
12 $0016 TIMER1_OVF Timer/Counter1 Overflow
13 $0018 TIMER0_OVF Timer/Counter0 Overflow
14 $001A SPI_STC SPI Serial Transfer Complete
15 $001C UART0_IRQ UART0 Interrupt Request
16 $001E UART1_IRQ UART1 Interrupt Request
Note: The Program Memory word length is 16-bits wide.
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AT76C712
6.3 Oscillator and Clock Generator
The AT76C712 clock generation circuit is based on a single clock input from an external 12MHz
crystal through the oscillator pad. All internal clocks are generated by multiplying this clock input
incorporating an on-chip PLL. The output of the PLL can be configured in 96MHz (default) or
192MHz. In order to produce the desired clocks the clock generator circuit divides the PLL out-
put. By generating a high frequency PLL output and then dividing that, reduces the impact of the
jitter imported by the PLL.
An elaborate gobbling circuit produces a 14.769MHz clock from the PLL output which can sup-
port all standard baud rates with an acceptable frequency error.
Figure 6-2. AT76C712 Clock Generation Tree

CLK_CNTR.PLCK
PLL Lock
M
O P U PLL Stable
XTAL S L Delay X
12MHz C L
96or 192MHz
/2
M 96MHz /32 3MHz WDT
CLK_CNTR.OSC_NSLP U
X
/2 48MHz
CLK_CNTR.MUL16 96MHz USB
CLK_CNTR.NPCIP
CLK_CNTR.PIVOC1 14.769MHz
2/13 UARTs
CLK_CNTR.MUL16 /4
M
/5 U System
X
/6 (AVR,etc)
CLK_CNTR.MCSP1.0
6.3.1 PLL LFT Pin

Figure 6-3 shows the circuit that must be attached to LFT pin. The circuit consists of R1=330
Ohm, C1 = 33nF and C2=3.3nF.
Figure 6-3. LFT pin circuit

LFT
R1
330 Ohm
C2
3.3nF
C1
33nF
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6.4 Memory Map
Base Address Module Description

Program Memory Controller
$FF00
Memory Access Interface
$F800 Memory Mapped Peripherals
UART1
$F300
UART0
$F200
USB
$F000
$2000
Internal SRAM Bank 6,7
$1800
Max. Internal
$1000
Data Memory
$0800
Internal SRAM Bank 0,1 Min. Internal
Data Memory
$0060
I/O Registers
$0020 Registers
AVR Core Registers
$0000
Table 6-6. Memory Map

Address Space Size (bytes) Module
$FF00-$FF04 5 Program Memory Controller (PMC)
$F800-$F802 3 Memory Access Interface
$F300-$F30C 13 UART1
$F200-$F20C 13 UART0
$F000-$F0FD 254 USB
$1800-$1FFF 2048 Internal SRAM bank 3
$1000-$17FF 2048 Internal SRAM bank 2
$0800-$0FFF 2048 Internal SRAM bank 1
$0060-$07FF 2048 Internal SRAM bank 0
$0020-$005F 64 I/O Registers
$0000-$001F 32 AVR Registers
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AT76C712
6.5 Memory Access Interface
The Memory Access Interface consists of the Memory Remapping Interface.
6.5.1 Memory Remapping Interface

On power-up, the device has 11K words (22Kx8) of Program SRAM and 2K Bytes of Data
SRAM.
Utilizing the MEMMAP register (allocated in $F800 Data Memory address) it is possible to resize
the two memory spaces. The last three 2KByte banks of Program Memory can be reallocated
and used as Data Memory and vise versa. According to Table 6-7, there are three cases:
1. to remap the last 2K Bytes only (Data Banks 6 and 7);
2. to remap the last 4K Bytes (Data Banks 4 to 7); and
3. to remap the last 6K Bytes (Data Banks 2 to 7).
Figure 6-4 and Table 6-7 illustrate the remapping:
Figure 6-4. Memory remapping
Data Memory Program Memory
16
8 8
8K Program Memory 0 8K Program Memory 1 Program SRAM Bank 0,1

(dedicated)
8 8 Program SRAM Bank 2, 3

1K Data Memory 7 1K Data Memory 6 (Data SRAM Bank 7, 6)
8 8 8
1K Data Memory 0 Program SRAM Bank 4, 5
1K Data Memory 5 1K Data Memory 4
Data SRAM bank 0,1 (Data SRAM Bank 5, 4)
(dedicated) 8 8 8
1K Data Memory 1 1K Data Memory 3 1K Data Memory 2 Program SRAM Bank 6, 7
(Data SRAM Bank 3, 2)
8
1K Data Memory 2
Data SRAM bank 2,3 8
1K Data Memory 3
8
1K Data Memory 4
Data SRAM bank 4,5
8
1K Data Memory 5
8
1K Data Memory 6
Data SRAM bank 6,7 8
1K Data Memory 7
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Table 6-7. Memory Map Allocation Cases
Data banks
MEMMAP
allocated to Data Data Address Space Program Address Space
Register value
Memory space
0 1 $0000-$07FF (2KBytes) $8000-$D7FF (22Kbytes)
2 3 $0000-$0FFF (4Kbytes) $8000-$CFFF (20Kbytes)
4 5 $0000-$17FF (6Kbytes) $8000-$C7FF (18Kbytes)
6 7 $0000-$1FFF (8Kbytes) $8000-$BFFF (16Kbytes)
6.6 USB DMA Controller

The AT76C712 offers a flexible DMA mechanism for fast data transfers between the Endpoint
buffers and the memory. Using DMA, the AVR program is not occupied with data transfers and
this results in saving processing time. The DMA controller is capable of moving data as fast as
12Mbytes/s.
The USB DMA Controller has direct access to internal data memory. When the USB starts a
DMA transfer to or from the data memory, then the DMA Controller prevents the AVR to access
the data memory area. During a DMA transfer the AVR can access any of the general purpose
registers. Once the AVR performs an access to the data memory area where a DMA transfer is
occupied, the DMA Controller imposes wait cycles to AVR until the DMA transfer is completed.
Thus, no extra care is required from the firmware to prevent internal memory access during DMA
transfers.
To enable a DMA transfer, the following steps should be performed:
1. Program the offset address of the FIFO Data Register of the associated endpoint (this
is the address of the FDRx register, i.e. $F0CE for FDR1)
2. Program the number of the bytes to be moved to/from the FIFO Data Register
3. Enable write or read DMA cycle.
The AVR must poll the USB in order to detect the DMA completion.
6.7 USB Controller

The USB controller contains its own internal register file which is memory mapped onto the AVR
data bus. The USB Block implements the low level processing functions of the USB protocol
stack described in Universal Serial Bus Specification, Version 1.1 and handles the data transfers
between the Endpoint (EP) FIFOs and the system memory. The DP/DM lines require the addi-
tion of external series resistors of 27Ω.
The USB Controller consists of a Serial Interface Engine (SIE), a Function Interface Unit (FIU)
and the System Interface (SI).
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Figure 6-5. USB Controller
USB Controller
AVR Memory Bus

FI U
DP
SI SIE
DM
FIFOs
The USB controller supports one control EP and seven programmable Endpoints in terms of the
type (BULK, INT or ISO) and the direction (IN, OUT). The Function Interface Unit (FIU) includes
the endpoint buffers and the controllers of endpoints shown in Table 6-8.
Table 6-8. USB Function Interface Unit Structure

Endpoint Type Number of Bytes Buffer Type
Endpoint 0 Control 16 Single
Endpoint 1..3 Any 128 (2 x 64) Double
Endpoint 4 Any 64 Single
Endpoints 5..7 0
A Pair Endpoint address scheme is also supported. According to this sceme, two Endpoints may
have the same address provided one of them has been configured as IN and other as OUT.
6.7.1 USB System Interface (SI)

The USB System Interface is necessary to bridge the AVR data bus with the USB Controller,
since the system clock and the USB Controller clock are asynchronous.
When the AVR accesses the USB registers, the USB System Interface inserts wait cycles to
AVR core in order to synchronize the data memory bus with the USB local bus.
6.7.2 USB Interrupt Handling

All interrupt signals from the USB functions (Protocol Handler) are consolidated into the “USB
Interrupt” line. The Interrupt line from the USB Protocol handler is then multiplexed with the indi-
vidual interrupt signals generated internally and a single interrupt output is provided to the
system interrupt controller.
All interrupts are masked through the interrupt enable registers that exist in the USB controller.
The External Resume and Received Resume interrupts are cleared when the firmware clears
the interrupt bit, (the Suspend interrupt is automatically cleared when activity is detected). All
other interrupts are cleared when the processor sets a corresponding bit in an interrupt acknowl-
edge register in the USB macro cell. There is only one bit for each interrupt source.
Table 6-9 describes all the interrupt sources of the USB Protocol Handler (see also the UISR
Register).
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Table 6-9. USB Interrupt Sources
Interrupt Description
Function EP0 Interrupt See control transfers at function EP0 for details
For an OUT Endpoint it indicates that Function Endpoint1 has received a
valid OUT packet and that the data is in the FIFO. For an IN Endpoint it
Function EP1 Interrupt means that the Endpoint has received an IN token, sent out the data stored
in the FIFO and received an ACK from the Host. The FIFO is now ready to be
written by new data from the processor.
Function EP2 Interrupt see Function EP1 Interrupt
Function EP3 Interrupt See Function EP1 Interrupt
SOF Received Whenever USB H/W decodes a valid Start of Frame.
EXT RSM The H/W has received a remote wake-up request
The H/W has received resume signaling. The processor's firmware should
RCVD RSM
take the function out of the suspended state.
The H/W has detected a suspend condition and is preparing to enter the
SUSP suspend mode. The processor's firmware should place the embedded
function in the suspend mode.
6.7.3 Interrupt Priority

The USB macro interrupt priority is defined in Table 6-10.
Table 6-10. USB Macro interrupt Priority

Priority Level Interrupt Name
2 :High level SOF Received
1:Same Level (Low level) Function EP0 to EP6
6.7.4 Endpoint Interrupt

Endpoint interrupts are triggered by setting or clearing one or more bits in the Control and Status
Register of an Endpoint. These interrupts are caused by events during packet transactions and
are different for Control and non-Control Endpoints. The interrupts are described below, with
respect to the Control and Status Register bit definitions. Please refer to the Endpoint Control
and Status Register definition.
6.7.5 Interrupt for Non-Control Endpoints

1. RX OUT Packet set (0 -> 1).
2. TX Packet Ready clear (1 -> 0).
6.7.6 Interrupt for Control Endpoints

1. RX OUT Packet set (0 -> 1).
2. RX SETUP set (0 -> 1).
3. TX Packet Ready clear (1 -> 0).
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4. TX Complete set (0 -> 1).
6.7.7 USB Function Interface (FIU)

The Function Interface Unit (FIU) provides the interface between the processor (via SI) and the
SIE. It manages transactions at the packet level with minimal intervention from the processor,
handles the Endpoints’ FIFOs, monitors the status of the transactions and communicates with
the AVR through a set of status and control registers.
The FIU is designed to operate in single-packet mode and to manage the USB packet protocol
layer. To operate the FIU, the firmware must first enable the Endpoints of the FIU, and select
direction and Ping-Pong capability. After being enabled, the Endpoints are in receive mode by
default. The FIU notifies the processor when a valid token has been received. The data con-
tained in the data packet will be supplied in the FIFO.
The processor transfers the data to and from the Host by interacting with each Endpoint's FIFO
and Control and Status Registers.
For example, when transmitting an IN packet, the FIU assembles the data of the Endpoint's
FIFO in a USB packet, transmits the packet and will signal the processor after the Host receives
and acknowledges the packet. The FIU performs automatic data packet retransmission and
DATA0/DATA1 PID toggling.
For SETUP tokens, the processor must parse the Device Request and then respond appropri-
ately. After a SETUP token there may be zero (0) or more DATA IN or DATA OUT packets for
which the processor must either supply or receive the data.
6.7.8 USB Serial Interface Engine (SIE)

The SIE performs the following functions:
• NRZI data encoding and decoding.
• Bit stuffing and un-stuffing.
• CRC generation and checking.
• ACKs and NACKs.
• Identifying the type of a token.
• Address checking.
• Clock generation (via DPLL).
6.7.9 Control Transfers at Function EP0

Legend: DATA1/DATA0 = Data packet with DATA1 or DATA0 PID
DATA 1 (0) = Zero length DATA1 packet
Host USB macro Micro Controller

SETUP Stage
1. [SYNC]-[SETUP]
2. [SYNC]-[DATA0]
3. Data are put in FIFO
4. If CRC OK, send:[SYNC]-[ACK]
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5. if CRC OK, set RX_SETUP bit
6. INTERRUPT
7. Read UISR (bit 0 is set)
8. Read FCSR0 (RX_SETUP bit)
9. Read FBYTE_CNT0
10. Read FIFO 0
11. Parse Data
If Control Read Phase:
Set Control Direction.
Clear RX_SETUP bit.
Fill FIFO with data.
Set TX_Packet_Ready
If Control Write Phase:
Clear Control Direction.
Clear RX_SETUP bit.
If No data Stage Phase:
Clear Control Direction.
Set Data_End bit.
Set FORCE_STALL bit.
If Unsupported Command:
Set FORCE_STALL bit
12. SET UIAR (EP0 INTA)
Status Stage, No DATA Stage
1. [SYNC]-[IN]
2. Send DATA1(0)
3. If CRC Ok,
send [SYNC]-[ACK]
4. Set TX_Complete bit
5. INTERRUPT
6. Read UISR
7. Read CSR
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AT76C712
8.
If SET_ADDRESS,
write Device Address to
FADDR.
Set FADD Enable bit of Glo-
bal State Register
If SET_CONFIGURATION with a 1:
Set CONFIG bit of Global
State Register.
9. Clear Tx_Complete bit
10. Clear Data_End bit
11. Set FORCE_STALL bit
DATA Stage, Control READ
1. [SYNC]-[IN]
2. If TX_Packet_Ready = 1
send DATA0 / DATA1
else, send STALL
3. If CRC OK,
send [SYNC]-[ACK]
4. Clear TX_Packet_Ready
6. INTERRUPT
7. Read UISR
8. Read CSR
10.
If more data
fill FIFO with data and set
TX_Packet_Ready
else
if a NULL packet should be sent,
set DATA_END and set
TX_Packet_Ready
else
if all bytes sent and need to send a
NULL packet,
set DATA_END and set
SET_FORCE_STALL.
STATUS/Early STATUS Stage with READ DATA Stage
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1. [SYNC]-[OUT]
2. [SYNC]-[DATA1(0)]
3. If TX_Complete = 0 then send
[SYNC]-[ACK] and set RX_OUT
else
send [SYNC]-[NACK]
4. INTERRUPT
5. Read UISR
6. Read CSR
7. Clear RX-OUT
8. Set Data_end
9. Set Force_Stall
Comment: A SETUP token will clear
Data_End. Not cleared by firmware in
case Host retries 1 through 3.
10. 11. SET UIAR (EP0 INTA)
DATA Stage, Control WRITE
1. [SYNC]-[OUT]
2. [SYNC]-
[DATA1/DATA0]
3. Data are put in FIFO
4. If CRC ok send [SYNC]- [ACK]
5. if CRC ok, set RX_OUT
6. INTERRUPT
7. Read UISR
8. Read CSR
9. Read FIFO
10. Clear RX_OUT
If last packet,
Set Data_End
Set Force_Stall
STATUS Stage with WRITE DATA Stage
1. [SYNC]-[IN]
2. Send DATA1(0)
3. If CRC Ok,
send [SYNC]-[ACK]
5. INTERRUPT
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AT76C712
6. Read UISR
7. Read CSR
9. Clear Data_End bit
10. Set FORCE_STALL bit
6.7.10 Interrupt and Bulk In Transfers

The USB hardware automatically starts the Endpoint in receive mode and NAKs all IN tokens as
long as the CSR[TX Packet Ready] is cleared. The processor checks this bit and if it is 0, writes
the data into the FIFO, then sets CSR[TX Packet Ready]. At the next IN token, the USB hard-
ware sends the packet out and waits for an ACK. Until an ACK is received, the USB hardware
will retransmit the packet. After receiving an ACK, the USB hardware clears the CSR[TX Packet
Ready], signaling a successful completion to the processor.
Figure 6-6. Bulk IN Transfers
IN Token without Ping-pong

HOST reads USB fifo UC fills USB fifo HOST reads USB fifo
TX_pkt_rdy = 0 TX_pkt_rdy = 0
TX_Complete =0
IN token TX_Complete= 1 Tx_pkt_rdy = 1 IN token TX_Complete= 1
ACK ACK
IN Token with Ping-pong

Uc polling Tx_pkt_rdy = 1 Uc polling Tx_pkt_rdy = 1
UC fills data Tx_Complete UC fills data Tx_Complete
HOST reads last data HOST reads last data

TX_Complete = 0 TX_Complete = 1 TX_Complete = 0 TX_Complete =1
IN token ACK IN token ACK
6.7.11 Interrupt and Bulk OUT Transfers

The USB hardware automatically starts the Endpoint in receive mode. When an OUT token is
received and if CSR[RX OUT Packet] is cleared, it stores the data in the FIFO. It ACKs the Host
if the data received are not corrupted and then interrupts the processor. If CSR[RX OUT Packet]
is set, the USB hardware responds with a NAK to the incoming OUT token. The processor
checks CSR[RX OUT Packet] and if it is 1, it reads the data from the FIFO and clears CSR[RX
OUT Packet Ready].
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Figure 6-7. Bulk OUT Transfers
OUT Token without Ping-pong
HOST fills USB fifo UC reads fifo HOST fills USB fifo UC reads fifo
OUT Token
OUT token Rx_OUT =1 ACK OUT token Rx_OUT =1
Rx_OUT = 0
OUT Token with Ping-pong

Uc pooling Rx_OUT =0 Uc pooling Rx_OUT =0
UC Reads last data Rx_out UC Reads last data Rx_out
HOST fills USB fifo HOST fills USB fifo

ACK ACK
OUT token Rx_OUT =1 OUT token Rx_OUT =1
6.7.12 Interrupt and Isochronous Transfers

Isochronous transfers use the same protocol with bulk transfers except that error correction and
data packet retransmission is not supported:
• No ACK token
• No NAK token
• Data PID is always zero.
6.7.13 Interrupt and Interrupt IN Transfers

Interrupt transfers use the same protocol with bulk in transfers (Interrupt OUT is not supported in
USB Spec 1.0)
6.7.14 Suspend
A USB device enters the suspend mode only when requested by the USB Host through bus
inactivity for at least 3ms. The USB H/W detects this request, sets the SUSP bit of the Sus-
pend/Resume Register (SPRSR), and interrupts the processor if the interrupt is enabled. The
processor should shut down any peripheral activity, enter Power Down mode and signal the
USB H/W that it can now enter the suspend mode by writing 1 to the “sleep mode” USB_Macro
input pin. At this moment, the firmware must execute the SLEEP instruction and set the system
to power-down state. The Oscillator, PLL, AVR and all peripherals will stop and the SUSP pin
will be set to high. The USB suspend interrupt hits twice; one time in the beginning of the sus-
pend and one time at the end of the suspend.
6.7.15 Resume
Resume is signaled by a J to K state transition at the USB port. The USB H/W enables the oscil-
lator/PLL and sets the RSM bit of the SPRSR, which generates an interrupt. The processor
starts executing where it left off and services the interrupt. Then, the firmware clears the RCVD
RSM bit.
6.7.16 Remote Wake Up

During "Remote Wake Up" a resume is signaled by the firmware by setting the RSM bit of the
SPRSR register.The firmware must wait for some time (8ms) before clearing the the RSM bit in
order to give time to the Host to detect the resume signal on the bus.
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6.8 UART0, UART1
UART0 and UART1 are 16550 compatible UARTs with some extra features.
The main features of the UARTs are:
• Capable of running 16550 software.
• After reset all registers are in 16550 compatible mode.
• Programmable Baud Rate Generator
• Maximum data rate 921.6Kbaud
• Exception handling using either prioritized interrupts or polled modes
• Parity, Framing and Overrun Error Detection
• Two Dedicated Controller channels
• 16-Byte transmit FIFO.
• 16-Byte plus 3 error bits receive FIFO.
• 5-, 6-, 7- and 8-bit word length.
• Bidirectional Handshaking Modem Control signals (available only for UART0).
• Line break generation and detection.
• Multi-drop mode: Address detection and generation.
• Diagnostic Loop-back mode (with or without echo)
6.8.1 Baud rate generator

The input to the baud rate generator is 14.769 MHz, derived from the internal clock generator.
6.8.2 Receiver
The UART detects the start of a received word by sampling the SIN signal until it detects a valid
start bit. A low level (space) on SIN is interpreted as a valid start bit if it is detected for more than
7 cycles of the sampling clock, which is 16 times the baud rate. Hence a space which is longer
than 7/16 of the bit period is detected as a valid start bit. A space, which is 7/16 of a bit period or
shorter, is ignored and the receiver continues to wait for a valid start bit. When a valid start bit
has been detected, the receiver samples the SIN at the theoretical midpoint of each bit. It is
assumed that each bit lasts 16 cycles of the sampling clock (one bit period) so the sampling
point is 8 cycles (0.5 bit periods) after the beginning of the bit. Therefore, the first sampling point,
is sampled 24 cycles (1.5 bit periods) after the falling edge of the start bit was detected. Each
subsequent bit is sampled 16 cycles (1 bit period) after the previous one.
6.8.3 Receive FIFO Operation

The 16-Byte plus 3 error bits receive data FIFO is enabled by the FCR bit 0. The user can set
the receiver trigger level.
6.8.4 Time-out
The receiver section includes a time-out mechanism in order to trace the time interval between
the received words.
The RTO register contains the maximum bit periods, for which the UART will wait the next word
to arrive. Whenever the time-out counter expires (reaches $00), then a Time-out Indication Inter-
rupt will be issued.
The XR1[5] Start Time-out Control bit selects the Start Time-out and RTO load mechanism. If
the XR1[5] bit is reset to ‘0’ (16550 compatible mode), then the RTO loads the value 4 times the
word length + 12 on each LCR write operation. After reset, the word length is 5 bits and the RTO
is $20. The time-out counter will then start counting down only in FIFO mode (FCR[0] is set) and
if the Rx FIFO holds at least 1 word. If XR1[5] is set to ‘1’, then the time-out function is available
and in FIFO disabled mode. The RTO value doesn’t change with LCR write operations. The
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time-out counter will start counting down whenever the RTO is not $00. In all cases, the core has
immediate access to the contents of the RTO.
The Time-out counter resets on a RHR read access from core or when a new word is completely
received and transferred at the Receive Holding Register or when the XR1[4] bit is forced to
logic ‘1’.
6.8.5 Receive Break

The break condition is detected by the receiver when the SIN line is held in the spacing state
(logic ‘0’) for longer than a full word transmission time (that is, the total time of all data, parity and
stop bits). At the moment of the low stop bit detection, the receiver asserts receive break indica-
tion (LSR[4]). The end of receive break is detected by a high level for at least 2/16 of the bit
period.
6.8.6 Transmitter
The start bit, data bits, parity bit and stop bits are serially shifted, with the lowest significant bit
first, on the falling edge of the UART clock. The LCR controls the number of data bits, the parity
bit and the number of stop bits. When a word is written to THR (Transmit Holding Register), it is
transferred to the Shift Register as soon as it is empty. When the transfer occurs, the THR ready
(bit-5) in LSR is set until a new word is written to THR. If the Transmit Shift Register and THR
are both empty, the transmitter empty (bit-6) in LSR is set.
6.8.7 Transmit FIFO Operation

When the FCR[0] is set to logic ‘1’ and XR2[7] is reset to ‘0’, then the 16-byte transmit FIFO is
enabled. The LCR[5] (and the XR2[5]) THR Empty bit indicates whether the Tx FIFO is empty or
full. When XR2[4] is in logic ‘0’ (16550 compatible mode), then THR Empty bit indicates that Tx
FIFO is empty. Setting XR2[4] to logic ‘1’, then THR Empty bit indicates Tx FIFO is not full.
Whenever THR Empty bit is active (high) a THR Empty interrupt will be issued.
The firmware has two choices. i) Reset XR2[4] bit to logic ‘0’ and enable THR Empty Interrupt.
Then, on each THR Empty interrupt, the software will transfer up to 16 words to the THR (no
check for FIFO full). ii) Set XR2[4] bit to logic ‘1’ and enable THR Empty Interrupt. Then, on each
THR Empty interrupt, the software will know that it is possible to transfer more words to THR
(until THR Empty bit is ‘0’).
6.8.8 Time-Guard
The Time-Guard function allows the transmitter to insert an idle state on the SOUT line between
two words. The duration of the idle state is programmed in U _TTG (Transmitter Time-Guard).
When this register is set to ‘0’, no time-guard is generated.
6.8.9 Transmit Break

The transmitter can generate a break condition on the SOUT line when the Start Break com-
mand is issued by setting LCR[6] to logic ‘1’. During the break condition SOUT line is held to
space state (logic ‘0’). The Start Break command will take effect right after the complete trans-
mission of all words in Transmit Shift Register and THR (or Tx FIFO, if enabled). That means
that no software synchronization is needed. To remove the break condition on the SOUT line,
we must issue a Stop Break command by resetting US_LCR[6] to logic ‘0’. The UART generates
minimum break duration of one word length. After the Stop Break command the SOUT line
returns to high level (idle state) for at least 12 bit periods to ensure that the end of break is cor-
rectly detected. Then the transmitter resumes normal operation.
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6.8.10 Interrupt Generation
The UART prioritizes interrupts into five levels and records these in the Interrupt Identification
Register (IIR). The five levels of interrupt conditions in order of priority are: Receiver Line Status,
RHR Ready, Time-out, THR Ready and Modem Status. When the CPU accesses the IIR, the
UART freezes the contents of IIR and indicates the highest priority pending interrupt to the CPU.
During this CPU access, the UART records new interrupts, but does not change its current indi-
cation until the access is complete.
The Interrupt Enable Register (IER) controls which interrupt condition will issue an interrupt to
the core. Disabling all interrupts, UART works in polled mode.
6.8.11 Handshaking Signals

Both UARTs implement all the Modem Control handshaking signals, but none of those signals
are mapped to any I/O port for UART1 and for UART0 the nOUT1 and nOUT2 signals are not
mapped at any I/O ports too. The only available handshaking signals are the nRTS, nCTS,
nDSR, nDTR, nCD and nRI of UART0 (see Port D).
All modem control signals are bi-directional and the firmware has the full control of their status.
6.8.12 Loop-back mode

In diagnostic Loop-back mode UART deactivate the output signals (stack at logic ‘1’) and loop-
back their status to the proper input signals. The UART offers and the option not to stack at logic
‘1’ the UART output pins, but to echo their status at the external UART interface.
Loop-back mode cannot be asserted if the direction of the Modem Control signals (MDR) are not
in the default state.
6.9 IrDA 1.0 codec

The IrDA 1.0 codec can be attached either on UART0 or on UART1. The operation of IrDA
codec is controlled by the IRDACR (page 48) Register.
It can effect on UARTs SIN and SOUT signals applying the 3/16 or 4/16 modulation of the
Return-to-Zero encoding scheme that UART produces.
According to the IrDA standard, for data rates up to and including 1.152 Mbit/s, RZI modulation
scheme is used and a ‘0’ is represented by a light pulse. For rates up to and including 115.2
kbit/s, the optical pulse duration is nominally 3/16 of a bit duration (or 3/16 of a 115.2 kbit/s bit
duration). For 0.576 Mbit/s and 1.152 Mbit/s, the optical pulse duration is nominally 4/16 of a bit
duration.
Figure 6-8. Pulse Duration
NRZ
1.6 µsec
<115.2Kbps
¼ bit
0.576 and
1.152 Mbps
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6.10 Watchdog Timer
The main features of the Watchdog timer are:
• 3MHz clock
• 22-bit up-counter
• Programmable prescaler
• Write access protection on timer disable
The Watchdog Timer (WDT) is used to prevent system lock-up if the software becomes trapped
in a deadlock.
The WDT is clocked with a 3MHz clock from the Clock Generator. In normal operation the user
resets the watchdog timer at regular intervals, using the WDR instruction. By controlling the
WDT prescaler, the Watchdog reset interval can be adjusted (see WDTCR register, WDP2..0
bits). Eight different clock cycle periods can be selected to determine the reset period. If the
reset period expires without another Watchdog Reset, the system resets and executes from the
reset vector.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be fol-
lowed when the Watchdog is disabled. Refer to the description of the WDTCR register for
details.
6.11 Serial Peripheral Interface - SPI

The AT76C712 SPI features are:
• Full-dublex 3-wire synchronous data transfers
• Master or Slave operation
• LSB first or MSB first data transfer
• Four programmable bit rates
• End-of-Transmission Interrupt Request
• Write Collision Flag protection
• Wake-up from Idle or Power-Down mode (Slave Mode Only)
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfers between the
AT76C712 and peripheral devices (memories, controllers, etc.). The interconnection between
master and slave SPI controllers is shown in Figure 6-9.
The two shift registers of the Master and the Slave SPI controllers, can be considerred as one
distributed 16-bit circular shift register. As Figure 6-9 shows, when data is shifted from the Mas-
ter to the Slave, data is also shifted in the opposite direction, simultaneously. This means that
during one shift cycle, data in the Master and the Slave are interchanged.
28 AT76C712
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Figure 6-9. Interconnection between master and slave SPI controllers
SPI Master SPI Slave
MOSI MOSI
8-bit Shift Register 8-bit Shift Register
MISO MISO
SPI SCK SCK

Clock Generator
nSS nSS
The PB4(SCK) pin is the clock output in the Master mode and the clock input in the Slave mode.
Writting to the SPI Data Register of the SPI Master starts the SPI clock generator and the data
written shifts out of the Master MOSI pin and into the Slave MOSI pin. After shifting one byte, the
SPI clock generator stops setting the End-of-Transmission flag (SPIF). If the SPI interrupt
enable bit (SPIE) in the SPCR register is set, an interrupt is issued. The Slave Select input (nSS)
is set low to select an individual slave SPI device.
The system is single-buffered in both transmit and receive direction. This means that bytes to be
transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed.
When receiving data, we must read the received byte before the next reception is started. other-
wise the first byte is lost.
When the SPI is enabled (PERIPHEN Register, SPI bit), the data direction of the MOSI, MISO,
SCK and nSS pins is overriden according to Table 6-11.
Table 6-11. Data Direction of SPI pins

Pin SPI Master SPI Slave Description
PB4 User defined Input nSS (SPI Slave Select Input)
PB5 Output Input MOSI (SPI Bus Master Output/Slave Input)
PB6 Input Output/Hi-Z MISO (SPI Bus Master Input/Slave Output)
PB7 Output Input SCK (SPI Bus Serial Clock)
6.11.1 nSS(PB4) Pin Functionality

When the SPI is configured as a master (MSTR in SPCR register), the user can determine the
direction of the nSS (PB4) pin. If nSS is configured as an output the pin is a general output pin,
which does not affect the SPI system. If nSS is configured as an input, it must be held high to
ensure master SPI operation. If the nSS pin is driven low by peripheral circuitry when the SPI is
configured as master with the nSS pin defined as an input, the SPI system interprets this as
another master selecting the SPI as a slave and starts to send data to it. To avoid bus conten-
tion, the SPI system takes the following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes slave. As a result of the
SPI becoming slave, the MOSI and SCK pins become inputs.
2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled and the I-bit in SREG is
set, the interrupt routine will be executed.
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Thus, when interrupt-driven SPI transmittal is used in Master Mode and there exists a possibility
that nSS is driven low, the interrupt should always check that the MSTR bit is still set. Once the
MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master
Mode.
When the SPI is configured as a slave, the nSS pin is always input. When nSS is held low, the
SPI is activated and MISO becomes an output. All other pins (MOSI and SCK) are inputs. When
nSS is driven high, all pins are inputs and the SPI is passive, which means that it will not receive
incoming data. Note that the SPI logic will be reset once the nSS pin is brought high. If the nSS
pin is brought high during a transmission, the SPI will stop sending and receiving immediately
and both data received and data send must be considered lost.
6.11.2 SPI Modes

The SPI bus protocol includes 4 modes. These modes determine the relationship between the
serial clock and the data bits. The SPI mode is fully programmable using the SPI Control Regis-
ter (SPICR). The four modes are determined with the CPOL and CPHA bits and illustrated in the
following four figures.
Note that in all modes, the data pins MOSI and MISO are driven in the opposite SCLK edge. For
example, if data input is latched on the rising edge, data output is driven on the falling edge.
Figure 6-10. SPI Mode 0
Mode 0: CPOL= 0,CPHA = 0
nSS
SCK
MOSI/MISO D7 D6 D5 D4 D3 D2 D1 D0
Mode 1: CPOL= 0,CPHA =1
nSS
SCK
Mode 2: CPOL=1, CPHA= 0
nSS
SCK
30 AT76C712
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AT76C712
Mode 3: CPOL=1, CPHA=1
nSS
SCK
6.12 JTAG Interface and On-Chip Debug System

The main Features of JTAG and On-Chip-Debug (OCD) System are:
• JTAG (IEEE std. 1149.1 Compliant) Interface
• Boundary Scan Capabilities according to the IEEE std. 1149.1 (JTAG)
• Debugger Access to:
– All Internal Peripheral Units
– Internal Data RAM
– Program Memory
– Internal Register File
– Program Counter
• Extensive On-Chip Debug Support for Break Conditions, including:
– AVR Break Instruction
– Break on Change of Program Memory Flow
– Single Step Break
– Program Memory Break Points on Single Address or Address Range
– Data Memory Break Points on Single Address or Address Range
The AVR IEEE Std. 1149.1 compliant JTAG interface can be used for
• Testing PCBs by using the JTAG Boundary-Scan capability
• On-Chip Debugging
A brief description is given in the following sections. Detailed descriptions for the Boundary-scan
Chain can be found in the section “IEEE 1149.1 (JTAG) Boundary-Scan” of the IEEE 1149.1
Standard. The On-Chip Debug support is considered being private JTAG instructions, and dis-
tributed within ATMEL and to selected third party vendors only.
Figure 6-14 shows a block diagram of the JTAG Interface and the On-Chip Debug system. The
TAP controller selects either the JTAG Instruction Register or one of several Data Registers as
the scan chain (Shift Register) between the TDI input and TDO output. The Instruction Register
holds JTAG instructions controlling the behavior of a Data Register.
The ID-Register, Bypass Register and the Boundary-scan Chain are the Data Registers used for
board-level testing. The Internal Scan-Chain and Break point Scan Chain are used for On-Chip
debugging only.
31
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Figure 6-14. JTAG Interface and On-Chip Debug System Block Diagram
TDI
TDO
TAP
TMS Controller
TCK
Internal Scan Chain

Instruction Register
Boundary Scan Chain

Program PC
ID Register Memory
Controller Instruction
M BYPASS Register I/O Pins

AVR CPU
U
X Break Point
Scan Chain Break Point Unit
Flow
Control
Unit JTAG/AVR core
Address
OCD Status Communication
Decoder
and Control Interface
Peripheral Units
6.12.1 Test Access Port - TAP

The JTAG Interface is accessed through four pins. In JTAG terminology, these pins constitute
the Test Access Port - TAP. These pins are:
• TMS: Test mode Select: This pin is used for navigating through the TAP-controller state
machine.
• TCK: Test Clock: JTAG Operation is synchronous to TCK.
• TDI: Test Data In: Serial input data to be shifted in to the Instruction Register or Data Register
(Scan Chains).
• TDO: Test Data Out: Serial output data from Instruction Register or Data Register.
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST -Test ReSeT- which is not
provided.
For the On-Chip Debug system, in addition to the JTAG interface pins, the nRST pin is moni-
tored by the debugger to be able to detect external reset sources. The debugger can also pull
the nRST pin low (using the AVR_RESET command) to reset the whole system.
6.12.2 TAP Controller

The TAP Controller is a 16-state finite-state machine that controls the operation of the Boundary
Scan circuitry, or On-Chip Debug system. The state transitions depicted in Figure 6-15 depend
on the signal present on TMS (shown adjacent to each state transition) at the time of rising edge
at TCK. The initial state after a Power-on-Reset is Test-Logic-Reset.
As a definition in this document, the LSB is shifted in and out first for all Shift Registers.
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:
• The TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift
Instruction Register - Shift-IR state. While in this state, shift the four bits of the JTAG
32 AT76C712
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AT76C712
instructions into the JTAG Instruction Register from the TDI input at the rising edge of TCK.
The TMS input must be held low during input of the 3 LSBs in order to remain in the Shift-IR
state. The MSB of the instruction is shifted in when this state is left by setting TMS high.
While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out
on the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI
and TDO and controls the circuitry surrounding the selected Data Register.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched
onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR,
Pause-IR, and Exit2-IR states are only used for navigating the state machine.
• At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift
Data Register – Shift-DR state. While in this state, upload the selected Data Register
(selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input
at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be
held low during input of all bits except the MSB. The MSB of the data is shifted in when this
state is left by setting TMS high. While the Data Register is shifted in from the TDI pin, the
parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the
TDO pin.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data
Register has a latched parallel-output, the latching takes place in the Update-DR state. The
Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine.
As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting
JTAG instruction and using Data Registers, and some JTAG instructions may select certain
functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state.
Note: Independent (unindependently) of the initial state of the TAP Controller, the Test-Logic-Reset state
can always be entered by holding TMS high for five TCK clock periods.
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Figure 6-15. JTAG TAP State Diagram
TMS = 1 Test-Logic-Reset
TMS =0 TMS =1
TMS=1
TMS = 0 Run-Test/Idle Select-DR-Scan TMS =1 Select-IR-Scan
TMS = 0 TMS = 0
Capture-DR Capture-IR
TMS =1 TMS = 0 TMS =1 TMS = 0
Shift-DR TMS = 0 Shift-IR TMS = 0
TMS =1 TMS =1
Exit1-DR Exit1-IR
TMS =1 TMS =1
TMS = 0 TMS = 0
Pause-DR TMS = 0 Pause-IR TMS = 0
TMS =1 TMS =1
TMS = 0 TMS = 0
Exit2-DR Exit2-IR
TMS =1 TMS =1
Update-DR Update-IR
TMS =1 TMS = 0 TMS =1 TMS = 0
6.12.3 Using the On-chip Debug system

As shown in Figure 6-14, the hardware support for On-chip Debugging consists mainly of
• A scan chain on the interface between the internal AVR CPU and the internal peripheral
units.
• Break Point unit.
• Communication interface between the CPU and JTAG system.
All read or modify/write operations needed for implementing the Debugger are done by applying
AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O
memory mapped location which is part of the communication interface between the CPU and the
JTAG system.
The Break Point Unit implements Break on Change of Program Flow, Single Step Break, two
Program Memory Break Points, and two combined Break Points. Together, the four Break
Points can be configured as either:
• 4 single Program Memory Break Points.
• 3 Single Program Memory Break Point + 1 single Data Memory Break Point.
• 2 single Program Memory Break Points + 2 single Data Memory Break Points.
• 2 single Program Memory Break Points + 1 Program Memory Break Point with mask (“range
Break Point”).
• 2 single Program Memory Break Points + 1 Data Memory Break Point with mask (“range
Break Point”).
34 AT76C712
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AT76C712
A debugger may however use one or more of these resources for its internal purpose, leaving
less flexibility to the end-user.
6.12.4 On-chip Debug Specific JTAG Instructions

The On-chip debug support is considered being private JTAG instructions, and distributed within
ATMEL and to selected third party vendors only. Instruction opcodes are listed for reference in
Table 6-12.
Table 6-12. OCD Specific JTAG Instructions

Opcode Description
PRIVATE 0; $8 Private JTAG instruction for accessing On-chip debug system.
PRIVATE 1; $9 Private JTAG instruction for accessing On-chip debug system.
PRIVATE 2; $A Private JTAG instruction for accessing On-chip debug system.
PRIVATE 3; $B Private JTAG instruction for accessing On-chip debug system.
6.13 IEEE 1149.1 (JTAG) Boundary-Scan

Features:
• JTAG (IEEE std. 1149.1 compliant) Interface
• Boundary-scan Capabilities According to the JTAG Standard
• Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections
• Supports the Optional IDCODE Instruction
• Additional Public AVR_RESET Instruction to Reset the AVR
The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins. At system level, all ICs having JTAG capabilities are connected serially by the
TDI/TDO signals to form a long Shift Register. An external controller sets up the devices to drive
values at their output pins, and observe the input values received from other devices. The con-
troller compares the received data with the expected result. In this way, Boundary-scan provides
a mechanism for testing interconnections and integrity of components on Printed Circuits Boards
by using the four TAP signals only.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAM-
PLE/PRELOAD, and EXTEST, as well as the AVR specific public JTAG instruction
AVR_RESET can be used for testing the Printed Circuit Board. Initial scanning of the Data Reg-
ister path will show the ID-Code of the device, since IDCODE is the default JTAG instruction. It
may be desirable to have the AVR device in reset during test mode. If not reset, inputs to the
device may be determined by the scan operations, and the internal software may be in an unde-
termined state when exiting the test mode. Entering reset, the outputs of any port pin will
instantly enter the high impedance state, making the HIGHZ instruction redundant. If needed,
the BYPASS instruction can be issued to make the shortest possible scan chain through the
device. The device can be set in the reset state either by pulling the external nRST pin low, or
issuing the AVR_RESET instruction with appropriate setting of the Reset Data Register.
The EXTEST instruction is used for sampling external pins and loading output pins with data.
The data from the output latch will be driven out on the pins as soon as the EXTEST instruction
is loaded into the JTAG IR-Register. Therefore, the SAMPLE/PRELOAD should also be used for
setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST
instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the
external pins during normal operation of the part.
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When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher
than the internal chip frequency is possible. The chip clock is not required to run.
6.13.1 Data Registers

The Data Registers relevant to Boundary-scan operations are:
• Bypass Register
• Device Identification Register
• Reset Register
• Boundary-scan Chain
6.13.1.1 Bypass Register

The Bypass Register consists of a single Shift Register stage. When the Bypass Register is
selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR
controller state. The Bypass Register can be used to shorten the scan chain on a system when
the other devices are to be tested.
6.13.1.2 Device Identification Register
Bit Field Value Description

Version is a 4-bit number identifying the revision of the
31:28 Version $1
component.
The part number is a 16-bit code identifying the component. The
27:12 Part Number $C712 unique JTAG Part Number for AT76C712 and AT76C713 is
$C712.
The Manufacturer ID is a 11-bit code identifying the
11:1 Manufacturer ID $01F
manufacturer. The JTAG manufacturer ID for ATMEL is $01F
0 1 $1
6.13.1.3 Reset Register

The Reset Register is a test Data Register used to reset the part. Since the AVR tri-states Port
Pins when reset, the Reset Register can also replace the function of the not implemented
optional JTAG instruction HIGHZ.
A high value in the Reset Register corresponds to pulling the external Reset low. The part is
reset as long as there is a high value present in the Reset Register. The output from this Data
Register is not latched, so the reset will take place immediately.
6.13.1.4 Boundary-Scan Chain Register

The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins. See the “Boundary-Scan Chain” on page 38 for a complete description.
6.13.2 Boundary-Scan Specific JTAG Instructions

The Instruction Register is 4-bit wide, supporting up to 16 instructions. Listed below are the
JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction
is not implemented, but all outputs with tri-state capability can be set in high-impedance state by
using the AVR_RESET instruction, since the initial state for all port pins is tri-state.
As a definition in this data sheet, the LSB is shifted in and out first for all Shift Registers.
36 AT76C712
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AT76C712
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which Data Register is selected as path between TDI and TDO for each instruction.
6.13.2.1 EXTEST; $0
Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing
circuitry external to the AVR package. The contents of the latched outputs of the Boundary-scan
chain is driven out as soon as the JTAG IR-Register is loaded with the EXTEST instruction. The
active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Internal Scan Chain is shifted by the TCK input.
• Update-DR: Data from the scan chain is applied to output pins.
6.13.2.2 IDCODE; $1
Optional JTAG instruction selecting the 32 bit ID-Register as Data Register. The ID-Register
consists of a version number, a device number and the manufacturer code chosen by JEDEC.
This is the default instruction after power-up. The active states are:
• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain.
• Shift-DR: The IDCODE scan chain is shifted by the TCK input.
6.13.2.3 SAMPLE_PRELOAD; $2
Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the
input/output pins without affecting the system operation. However, the output latches are not
connected to the pins. The Boundary-scan Chain is selected as Data Register. The active states
are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
• Update-DR: Data from the Boundary-scan chain is applied to the output latches. However,
the output latches are not connected to the pins.
6.13.2.4 AVR_RESET; $C
The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or
releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one bit
Reset Register is selected as Data Register. Note that the reset will be active as long as there is
a logic “one” in the Reset Chain. The output from this chain is
not latched. The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input.
6.13.2.5 BYPASS; $F
Mandatory JTAG instruction selecting the Bypass Register for Data Register. The active states
are:
• Capture-DR: Loads a logic “0” into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
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6.13.3 Boundary-Scan Chain
The Boundary scan chain consists of two kind of cells. The first one is a standard scan cell with
observe and drive capabilities, while the second one is an observe only cell.
6.13.3.1 AT76C712 Boundary-Scan Order

Table 6-13 shows the Scan order between TDI and TDO when the Boundary-scan chain is
selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The
scan order follows the pin-out order as far as possible. Therefore, the bits of Port A for example
are scanned not in order.
In Figure 6-16 we can see an I/O pin with scan logic.
Figure 6-16. I/O pin with scan logic
xINn
PINxn Scan Cel
xOUTn
PORTxn Scan Cell ENB
PA D
OExn
DDRDxn Scan Cell
I/O Registers Boundary Note:

Scan x=A,B,C,D,E
Signals n=0..7
Table 6-13. The AT76C712 Boundary-Scan Order

Bit Number Signal Name Description
(LSB) 0 TEST_EN (observe only)
1 TEST_CK (observe only)
2 nRST (observe only)
3 EOUT7
4 EIN7 PE7
5 EOE7
6 EOUT6
7 EIN6 PE6
8 EOE6
9 EOUT5
10 EIN5 PE5
11 EOE5
12 EOUT4
13 EIN4 PE4
14 EOE4
15 EOUT3
16 EIN3 PE3
17 EOE3
38 AT76C712
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AT76C712
Table 6-13. The AT76C712 Boundary-Scan Order (Continued)
18 EOUT2
19 EIN2 PE2
20 EOE2
21 EOUT1
22 EIN1 PE1
23 EOE1
24 EOUT0
25 EIN0 PE0
26 EOE0
27 PMODE0
28 PMODE1
29 COUT7
30 CIN7 PC7
31 COE7
32 COUT6
33 CIN6 PC6
34 COE6
35 COUT5
36 CIN5 PC5
37 COE5
38 COUT4
39 CIN4 PC4
40 COE4
41 COUT3
42 CIN3 PC3
43 COE3
44 COUT2
45 CIN2 PC2
46 COE2
47 COUT1
48 CIN1 PC1
49 COE1
50 COUT0
51 CIN0 PC0
52 COE0
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5635AX–USB–10/06
53 BOUT7
54 BIN7 PB7
55 BOE7
56 BOUT6
57 BIN6 PB6
58 BOE6
59 BOUT5
60 BIN5 PB5
61 BOE5
62 BOUT4
63 BIN4 PB4
64 BOE4
65 BOUT3
66 BIN3 PB3
67 BOE3
68 BOUT2
69 BIN2 PB2
70 BOE2
71 DOUT7
72 DIN7 PD7
73 DOE7
74 DOUT6
75 DIN6 PD6
76 DOE6
77 DOUT5
78 DIN5 PD5
79 DOE5
80 DOUT4
81 DIN4 PD4
82 DOE4
83 DOUT3
84 DIN3 PD3
85 DOE3
86 DOUT2
87 DIN2 PD2
88 DOE2
40 AT76C712
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AT76C712
89 DOUT1
90 DIN1 PD1
91 DOE1
92 DOUT0
93 DIN0 PD0
94 DOE0
95 SUSPEND
96 AOUT7
97 AIN7 PA7
98 AOE7
99 AOUT6
100 AIN6 PA6
101 AOE6
102 AOUT5
103 AIN5 PA5
104 AOE5
105 AOUT4
106 AIN4 PA4
107 AOE4
108 AOUT3
109 AIN3 PA3
110 AOE3
111 USB_ATTACH
112 nCS1
113 nCS0
114 nFWR
115 nFRD
116 AOUT2
117 AIN2 PA2
118 AOE2
119 AOUT1
120 AIN1 PA1
121 AOE1
122 AOUT0
123 AIN0 PA0
124 AOE0
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5635AX–USB–10/06
125 BOUT1
126 BIN1 PB1
127 BOE1
128 BOUT0
129 BIN0 PB0
130 BOE0
131 Idle-mode (sleep state) (observe only)
132 Power-down (sleep state) (observe only)
133 AVR clock stopped (observe only)
134 PLL Stable Indication (observe only)
(MSB) 135 PLL Lock signal (observe only)
7. I/O Space - Register Description

The I/O space definition of AT76C712 is shown in Table 7-1. This space is defined in the area
$00 - $3F and can be directly accessed by IN and OUT instructions or by ordinary SRAM
accesses in the area $20-$5F. The notation used (with the SRAM address in parentheses), will
be followed in the rest of this document.
Table 7-1. The AT76C712 I/O Space

I/O Address (SRAM Address) Name Function
$3F($5F) SREG Status Register
$3E($5E) SPH Stack Pointer High
$3D($5D) SPL Stack Pointer Low
$3C($5C) IDR OCD Debug Register
$39($59) TIMSK Timer Interrupt Mask Register
$38($58) TIFR Timer Interrupt Flag Register
$37($57) EIMSK External Interrupt Mask Register
$35($55) MCUCR MCU General Control Register
$34($54) MCUSR MCU Status Register
$33($53) TCCR0 Timer0 Control Register
$32($52) TCNT0 Timer0 (8-bit)
$31($51) PRELD0 Pre-load Register 0
$2E($4E) TCCR1B Timer1 Control Register B
$2D($4D) TCNT1H Timer1 High Byte
$2C($4C) TCNT1L Timer1 Low Byte
42 AT76C712
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AT76C712
Table 7-1. The AT76C712 I/O Space (Continued)
I/O Address (SRAM Address) Name Function
$2B($4B) OCR1AH Timer1 Output Compare Register A High Byte
$2A($4A) OCR1AL Timer1 Output Compare Register A Low Byte
$29($49) OCR1BH Timer1 Output Compare Register B High Byte
$28($48) OCR1BL Timer1 Output Compare Register B Low Byte
$27($47) ICR1H Timer1 Input Capture Register High Byte
$26($46) ICR1L Timer1 Input Capture Register Low Byte
$25($45) TCCR2 Timer2 Control Register
$24($44) TCNT2 Timer2 (8-bit)
$23($43) PRELD2 Pre-load Register 2
$22($42) IRDACR IrDA Control Register
$21($41) WDTCR Watchdog Timer Control Register
Program Mode (PMODE0, PMODE1 pins
$1F($3F) PMOD
value)
$1B($3B) PORTA Data Register, Port A
$1A($3A) DDRA Data Direction Register, Port A
$19($39) PINA Input Pins, Port A
$18($38) PORTB Data Register, Port B
$17($37) DDRB Data Direction Register, Port B
$16($36) PINB Input Pins, Port B
$15($35) PORTC Data Register, Port C
$14($34) DDRC Data Direction Register, Port C
$13($33) PINC Input Pins, Port C
$12($32) PORTD Data Register, Port D
$11($31) DDRD Data Direction Register, Port D
$10($30) PIND Input Pins, Port D
$0F($2F) SPDR SPI I/O Data Register
$0E($2E) SPSR SPI Status Register
$0D($2F) SPCR SPI Control Register
$0C($2C) CLK_CNTR Clock Control Register
$0B($2B) PERIPHEN Peripheral Enable Register
$0A($2A) PORTE Data Register, Port E
$09($29) DDRE Data Direction Register, Port E
$08($28) PINE Input Pins, Port E
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5635AX–USB–10/06
AVR Status Register - SREG
addr $3F($5F) 8 bits
Bit Field AVR Description
When set the interrupts are enabled. The individual interrupt
I:Global interrupt enable control is performed in the individual mask registers. This
7 R/W
enable bit is cleared by H/W after an interrupt has occurred and is set by
the RETI instruction to enable subsequent interrupts.
T: Bit Copy Bit load (BLD) and bit store (BST) instructions use the T bit as
6 R/W
Storage source and destination for the operated bit.
H: Half Carry
5 R/W Indicates a half carry in some arithmetic operations
Flag
Is an eXclusive OR between the negative flag N and the two’s
4 S: Sign Bit R/W
complement overflow flag V.
V: Two’s
3 complement R/W Supports two’s complement arithmetic.
overflow flag
When set indicates a negative result in arithmetic and logic
2 N: Negative Flag R/W
operations.
When set indicates a zero result after the different arithmetic and
1 Z: Zero Flag R/W
logic operations
0 C: Carry Flag. R/W When set indicates a carry in the arithmetic or logic operations.
Stack Pointer - SP
addr $3E($5E), $3D($5D) 11 bits
15:11 - R/W
10 SP10 R/W
SPH
9 SP9 R/W
8 SP8 R/W
7 SP7 R/W
6 SP6 R/W
5 SP5 R/W
4 SP4 R/W
SPL
3 SP3 R/W
2 SP2 R/W
1 SP1 R/W
0 SP0 R/W
44 AT76C712
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AT76C712
MCU Control Register - MCUCR
The MCU Control Register controls the effect of the SLEEP instruction (see AVR Instruction
Set). Note that when the AVR is in sleep mode (stand-by or power-down), it will wake-up on any
enabled interrupt or on any USB activity (if USB core is activated). Also, on any JTAG activity, if
the system is in power-down mode, it switches into stand-by mode.
addr $35 ($55)8 bits
Bit Field Default AVR Description

7 — 0 — Reserved
SE:Sleep When set permits the MCU to enter in sleep mode when the
6 0 R/W
Enable SLEEP instruction is executed.
This bit selects between the two available sleep modes.
When the MCU enters into the sleep state and the SM bit is
SM:Sleep
cleared, then it enters into Idle Mode and only the AVR clock
5 Mode 0 R/W
is stopped. Otherwise, if SM bit is set, then the MCU enters
Select Bit
into the Power Down Mode and the MCU disables the
oscillator stopping all clocks and any activity.
4:0 — 0 — Reserved
MCU Status Register - MCUSR

The MCUSR register provides information on which reset source caused an MCU reset.
addr $34 ($54) 8 bits
7:2 — — — —
EXTRF:
External Reset Flag. This Flag indicates that an external
1 External See R/W
reset has occurred.
Reset Flag Table 7-
PORF: Power 2
0 R/W This Flag indicates that a power on reset has occurred.
on Reset Flag
Table 7-2. PORF and EXTRF Values After Reset

Reset Source PORF EXTRF
Power on Reset 1 Undefined
External Reset Unchanged 1
Watchdog Reset Unchanged Unchanged
The user program must clear these bits as early as possible. If these bits are cleared before a
reset condition occurs, the source of resource can be found by using the truth table shown in
Table 7-3
45
5635AX–USB–10/06
Table 7-3. Reset Source Identification
PORF EXTRF Reset Source
0 0 Watchdog Reset
0 1 External Reset
1 x Power on Reset
External Interrupt Mask Register - EIMSK

This register is used for masking the external interrupts. External Interrupts should be acknowl-
edged using general purpose output pins.
addr $37 ($57) 8 bits
POL3: Polarity of
7 0 R/W INT3 is active high when this bit is low.
external interrupt 1
POL2: Polarity of
POL1: Polarity of
POL0: Polarity of
If it is set and the I-bit in the Status Register is
3 INT3 0 R/W
set, the external pin interrupt 3 is enabled
2 INT2 0 R/W
set, the external pin interrupt 2 is enabled.
1 INT1 0 R/W
set, the external pin interrupt 1 is enabled
0 INT0 0 R/W
set, the external pin interrupt 0 is enabled.
Note: The External Interrupts are assigned to I/O pins PE2 - PE5. Since PE4-PE5 pins are not available,
INT2 and INT3 can be used as software only interrupts.
Clock Control Register - CLK_CNTR

This register is used to control the clock generation circuit. For example, the PLL output clock
rate can be switched from 96MHz to 192MHz by setting the CLK_CNTR register to $4C.
addr $0C ($2C) 8 bits
Is equal to the reversed PLL ICP bit. Controls the PLL
7 NPICP 0 R/W
Charge-Pump current.
If set, the PLL Lock signal is used for ‘PLL Stable’ indication.
6 PLCK 0 R/W If cleared, the ‘PLL Stable’ indication is equal to the ‘PLL
Enable’ signal delayed by a significant factor.
5 UDPLL 0 R/W Select DPLL96 instead of DPLL48 for USB clock recovery.
46 AT76C712
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If set, then don't close the Oscillator during the power-down
4 OSC_NSLP 0 R/W
sleep mode.
PLL IVCO[1]. Selects the PLL frequency range. Normally,
3 PIVCO1 0 R/W
this bit must be equal to the MUL16 bit
Selects the multiplier of the PLL. When set the external
12MHz crystal frequency is multiplied by 16 to generate an
2 MUL16 0 R/W internal fast clock of 192MHz. When cleared, the external
12MHz crystal frequency is multiplied by 8 generating an
internal fast clock of 96MHz
1 MCSP1 0 R/W AVR core speed select bits. These bits control the AVR clock
0 MCSP0 0 R/W divisor according to Table 7-4
Table 7-4. Microcontroller Speed Select Bits

MUL16 MCSP1 MCSP0 AVR clock rate Notes
0 0 0 24 MHz 96 div 4
0 0 1 19, 2 MHz 96 div 5
0 1 0 16 MHz 96 div 6
0 1 1 Reserved
1 0 0 48 MHz 192 div 4
1 0 1 38,4 MHz 192 div 5
1 1 0 32 MHz 192 div 6
1 1 1 Reserved
Peripheral Enable Control Register - PERIPHEN

This register enables the peripheral components of the system. It controls the SPI, UARTs and
USB.
addr $0B ($2B) 8 bits
7:6 — 0 R Always read as zero.
5 SPI: SPI Enable 0 R/W If set enables the SPI controller
4 UART1 Enable 0 R/W When set enables the function of UART1
3 UART0 Enable 0 R/W When set enables the function of UART0
2 UATTACH 0 R/W When set activates (logic ‘1’) the USB_ATTACH pin.
1 USB Enable 0 R/W When set enables the function of USB (clock enable).
0 Reserved 0 R/W Always read as zero.
47
5635AX–USB–10/06
Program Mode Register – PMOD
This register returns the value of the PMODE0 and PMODE1 input pins.
addr $1F ($3F) 8 bits
7:2 — 0 R Always read as zero.
1 PMODE1 N/A R The value of the PMODE1 input pin.
0 PMODE0 N/A R The value of the PMODE0 input pin
I/O Debug Register - IDR

This register is used for the communication between the On-Chip Debug system (through JTAG)
and AVR CPU. It provides a communication channel from the running program in the microcon-
troller to the debugger. The CPU can transfer a byte to the debugger by writing to this location.
addr $3C ($5C) 8 bits
IDRD:I/O Debug This bit is set to indicate to the debugger that the
7 0 R/W
Register Dirty register has been written.
6 0 R/W
5 0 R/W
4 0 R/W When the CPU reads the IDR Register the 7 LSB will be
from the IDR Register, while the MSB is the IDRD bit.
3 0 R/W
The debugger clears the IDRD bit when it has read the
2 0 R/W information.
1 0 R/W
0 LSB 0 R/W
IrDA Control Register - IRDACR

This register controls the IrDA 1.0 codec. The IrDA codec is connected between the UART0 and
UART1 SIN and SOUT signals and the corresponding pins.
addr $22 ($42) 8 bits
7:5 — 0 R
TXPOL: Transmit
4 0 R/W If set the SOUT signal is inverted.
Polarity
RXPOL: Receive When set, the SIN signal is inverted before entering
3 0 R/W
Polarity the IrDA codec
48 AT76C712
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When cleared enables the 3/16 Return-to-Zero
2 MODE 0 R/W encoding scheme. When set enables the 4/16
Return-to-Zero encoding scheme
When cleared the codec uses UART0. When set
1 USEL: UART Select 0 R/W
the codec uses UART1.
When set enables the IrDA codec. When cleared
0 IRDAEN 0 R/W the codec is transparent to UART0/1 SIN/SOUT
pins.
7.1 Timers/Counters
Timer/Counter Interrupt Mask Register - TIMSK

This register is used for masking the internal timer interrupts.
addr $39 ($59) 8 bits
When this bit is set and the I-bit in the Status Register is
TOIE1: 1, the Timer/Counter1 Overflow interrupt is enabled. The
Timer/Counter1 corresponding interrupt (at vector $001C) is executed if
7 0 R/W
Overflow an overflow in Timer/Counter1 occurs. The
Interrupt Enable Timer/Counter1 Overflow Flag is set in the
Timer/Counter1 Interrupt Flag Register – TIFR.
OCIE1A:
1, the Timer/Counter1 Compare A Match interrupt is
Timer/Counter1
enabled. The corresponding interrupt (at vector $0018)
6 Output Compare 0 R/W
is executed if a Compare A match in Timer/Counter1
A Match Interrupt
occurs. The Compare A flag in Timer/Counter one is set,
Enable
in the Timer/Counter Interrupt flag register - TIFR.
OCIE1B:
one, the Timer/Counter1 Compare B Match interrupt is
Timer/Counter1
enabled. The corresponding interrupt (at vector $001A)
5 Output Compare 0 R/W
is executed if a Compare B match in Timer/Counter1
B Match Interrupt
occurs.The Compare B flag in Timer/Counter one is set,
Enable.
in the Timer/Counter Interrupt flag register - TIFR.
4 — 0 R
TICIE1: one, the Input Capture Event interrupt is enabled. The
Timer/Counter1 corresponding interrupt (at vector $0016) is executed if a
3 0 R/W
Input Capture capture event occurs on pin PB3. The Input Capture
Interrupt Enable Flag in Timer/Counter1 is set in the Timer/Counter
Interrupt Flag Register – TIFR.
49
5635AX–USB–10/06
TOIE2: one, the Timer/Counter2 Overflow interrupt is enabled.
Timer/Counter2 The corresponding interrupt (at vector $0020) is
2 0 R/W
Overflow executed if an overflow in Timer/Counter2 occurs. The
Interrupt Enable. Timer/Counter2 Overflow Flag is set in the
TOIE0: one, the Timer/Counter0 Overflow interrupt is enabled.
Timer/Counter0 The corresponding interrupt (at vector $0020) is
1 0 R/W
Overflow executed if an overflow in Timer/Counter0 occurs. The
Interrupt Enable Timer/Counter0 Overflow Flag is set in the
0 — 0 R
Timer/Counter Interrupt Flag Register - TIFR

addr $38 ($58) 8 bits
7 0 R/W
The OCFA is set when a compare match between
OCFA: Output
6 0 R/W Timer/Counter1 and the OCR1A register occurs. This
Compare Flag A
flag is cleared when written with a logic one.
OCFB: Output The OCF1B is set when a compare match between
5 Compare Flag 0 R/W Timer/Counter1 and the OCR1B register occurs. This
1B flag is cleared when written with a logic one.
4 — 0 R
This flag when set indicates an input capture event,
ICF1: Input where the contents of the Timer/Counter1 are
3 0 R/W
Capture Flag transferred to the ICR1 register. This flag is cleared
when written with a logic one.
TOV2: Timer/Counter2 Overflow Flag. The TOV2 is set when
2 Timer/Counter2 0 R/W an overflow occurs in Timer/Counter2. This flag is
Overflow Flag cleared when written with a logic one.
TOV0: Timer/Counter0 Overflow Flag. The TOV0 is set when
1 Timer/Counter1 0 R/W an overflow occurs in Timer/Counter0. This flag is
Overflow Flag. cleared when written with a logic one.
0 — 0 R
50 AT76C712
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7.2 Timer/Counter 0 and Timer/Counter 2
Timer/Counter 0 Control Register - TCCR0
addr $33 ($53) 8 bits
7:3 — 0 R
2 CS02 0 R/W
1 CS01 0 R/W
CS02 CS01 CS00 Description
Stop, Timer/Counter0
0 0 0
is stopped
0 0 1 CK
0 1 0 CK/8
0 1 1 CK/64
0 CS00 0 R/W 1 0 0 CK/256
1 0 1 CK/1024
External Pin T0 (orT2),
1 1 0
Falling Edge
External Pin T0 (or T2),
1 1 1
Rising Edge
The Timer/Counter2 Control Register - TCCR2

addr $25 ($45) 8 bits
7:3 Reserved 0 R —
CS02:Clock The Clock Select0 bits 2,1, and 0 define the pre-scaling
2 0 R/W
Select 0 bit 2 source of Timer0.
CS01:Clock
1 0 R/W
Select 0 bit 1
Stop, Timer/Counter0 is
0 0 0
stopped
0 0 1 CK
0 1 0 CK/8
0 1 1 CK/64
CS00:Clock
0 0 R/W 1 0 0 CK/256
Select 0 bit 0
1 0 1 CK/1024
1 1 0
Falling Edge
1 1 1
Rising Edge
51
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Timer/Counter0 Register - TCNT0
addr $32 ($52) 8 bits
7 MSB 0 R/W
6 0 R/W
5 0 R/W Both Timer/Counter0 and Timer/Counter2 are realized
as an up-counter with read and write access. If the
4 0 R/W TCNT0 (or TCNT2 respectively) is written and a clock
3 0 R/W source is present, the Timer/Counter0 (or
Timer/Counter2) continues counting in the clock cycle
2 0 R/W following the write operation.
1 0 R/W
0 LSB 0 R/W
Timer/Counter2 Register - TCNT2

Both Timer/Counter0 and Timer/Counter2 are realized as an up-counter with read and write
access. If the TCNT0 (or TCNT2 respectively) is written and a clock source is present, the
Timer/Counter0 (or Timer/Counter2) continues counting in the clock cycle following the write
operation.
addr $24 ($44) 8 bits
7 MSB 0 R/W
6: 0 R/W
5 0 R/W Both Timer/Counter0 and Timer/Counter2 are realized
as an up-counter with read and write access. If the
4 0 R/W TCNT0 (or TCNT2 respectively) is written and a clock
3 0 R/W source is present, the Timer/Counter0 (or
Timer/Counter2) continues counting in the clock cycle
2 0 R/W following the write operation.
1 0 R/W
0 LSB 0 R/W
52 AT76C712
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Pre-load Register 0 - PRELD0
addr $31 ($51) 8 bits
7 MSB 0 R/W
6 0 R/W
5 0 R/W
4 0 R/W An 8-bit R/W register with zero initial value. The contents
of this register are loaded to Timer/Counter0 TCNT0 (or
3 0 R/W Timer/Counter2 TCNT2 respectively) after an overflow.
2 0 R/W
1 0 R/W
0 LSB 0 R/W
Pre-load Register 2- PRELD2

addr $23 ($43) 8 bits
7 MSB 0 R/W
6 0 R/W
5 0 R/W
An 8-bit R/W register with zero initial value. The
4 0 R/W contents of this register are loaded to
3 0 R/W Timer/Counter0 TCNT0 (or Timer/Counter2 TCNT2
respectively) after an overflow.
2 0 R/W
1 0 R/W
0 LSB 0 R/W
53
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7.3 Timer/Counter 1
Timer/Counter1 Register - TCCR1B

addr $2E ($4E) 8 bits
When this bit is zero the input canceler function is
disabled. The input capture is triggered at the first
rising/falling edge sampled on the input capture pin
ICNC1: Input
(ICP), as specified by the ICES1 bit. When this bit is set
7 Capture 1 Noise 0 R/W
four successive samples are measures and all samples
Canceler (4 CKs
must be high/low according to the input capture trigger
specification in the ICES1 bit. The actual sampling
frequency is the CPU clock frequency.
When this bit is cleared the Timer/Counter1 contents are
ICES1: Input transferred to the Input Capture Register - ICR1 on the
6 Capture1 Edge 0 R/W falling edge of the input capture pin (ICP). When it is one
Select the contents are transferred on the rising edge.
5 — 0 R
4 — 0 R
CTCA1: Clear When it is one the Timer/Counter1 is reset to $0000
Timer/Counter1 after compare A match. If it is cleared the
3 0 R/W
on Compare A Timer/Counter1 continues counting after a compare A
match match.
CS12: Clock These bits select prescaling source for the
2 0 R/W
Select 1,bit 2 Timer/Counter1 according to the following table:
CS11:Clock
1 0 R/W
Select 1, bit 1
Stop, Timer/Counter0
0 0 0
is stopped
0 0 1 CK
0 1 0 CK/8
0 1 1 CK/64
CS11:Clock
0 0 R/W 1 0 0 CK/256
Select 0, bit 0
1 0 1 CK/1024
1 1 0
Falling Edge
1 1 1
Rising Edge
54 AT76C712
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Timer/Counter1 - TCNT1H and TCNT1L
The Timer/Counter1 is realized as an 16-bit up counter consisted of two 8-bit registers TCNT1H
and TCNT1L. These registers have read and write access with initial value of $00. If
Timer/Counter1 (TCNT1H and TCNT1L) register is written to and a clock source is selected, the
T/C1 continues counting in the timer clock cycle after it is preset with the written value.
To ensure that both the high and low bytes are read and written simultaneously when the CPU
access these registers, the access is performed using an 8-bit temporary register (TEMP). This
temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program
and also interrupt routines perform access to registers using TEMP, interrupts must be disabled
during access from the main program.
addr $2D ($4D), $2c ($4C) 16 bits
15 MSB 0 R/W
14 0 R/W
13 0 R/W
TCNT1 Timer/Counter1 Write:
12 0 R/W When the CPU writes to the high byte TCNT1H, the written data
11 0 R/W are placed in the TEMP register. Next, when the CPU writes the
low byte TCNT1L, this byte of data is combined with the TEMP
10 0 R/W register and all 16-bits are written simultaneously to
9 0 R/W Timer/Counter1 TCNT1 register. Consequently, the high byte
must be accessed first for a full 16-bit write operation. When
8 0 R/W using Timer/Counter1 as an 8-bit counter, it is sufficient to write
7 0 R/W the low byte only.
TCNT1 Timer/Counter1 Read:
6 0 R/W
When the CPU reads the low byte TCNT1L, the data are placed
5 0 R/W in the TEMP register. Next, when the CPU reads the high byte
TCNT1H, the CPU receives the data in the TEMP register.
4 0 R/W Consequently, the low byte must be accessed first for a full 16-bit
3 0 R/W read operation. When using Timer/Counter1 as an 8-bit counter,
it is sufficient to read the low byte only.
2 0 R/W
1 0 R/W
0 LSB 0 R/W
Timer/Counter1 Output Compare Register A - OCR1AH and OCR1AL

Timer/Counter Output Compare register A consists of 16-bits and is made by two 8-bit R/W reg-
isters, with initial value of zero, namely the OCR1AH and OCR1AL.
Full 16-bit write and read operations are made according to the way specified for the
Timer/Counter1 TCNT1.
addr $2B ($4B), $2A ($4A) 16 bits
15 MSB 0 R/W
OCR1AH
14:8 0 R/W
7:1 0 R/W
OCR1AL
0 LSB 0 R/W
55
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Timer/Counter1 Output Compare Register B - OCR1BH and OCR1BL
Timer/Counter Output Compare register B consists of 16-bits and is made by two 8-bit R/W reg-
isters, with initial value of zero, namely the OCR1BH and OCR1BL.
Full 16-bit write and read operations are made according to the way specified for the
Timer/Counter1 TCNT1.
addr $29 ($49), $28 ($48) 16 bits
15 MSB 0 R/W
OCR1BH
14:8 0 R/W
7:1 0 R/W
OCR1BL
0 LSB 0 R/W
The Timer/Counter1 Input Capture Register - ICR1H and ICR1L

The Timer/Counter Input Compare register consists of 16-bits and is made by two 8-bit read only
registers, with initial value of zero, namely the ICR1H and ICR1L.
When the rising or falling edge (according to the input capture edge setting (ICES1) of the signal
at the input capture pin (ICP) is detected, the current value of the Timer/Counter1 is transferred
to the Input Capture Register (ICR1). At the same time, the input capture flag (ICF1) is set to
one.
Full 16-bit read operations are made according to the way specified for the Timer/Counter1
TCNT1 above.
addr $27 ($47), $26 ($46) 16 bits
15 MSB 0 R
OCR1H
14:8 0 R
7:1 0 R
OCR1L
0 LSB 0 R
56 AT76C712
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7.4 Watchdog Timer
Watchdog Timer Control Register - WDTCR

addr $21 ($41) 8 bits
7:5 — 0 R
WDTOE: Watch This bit must be set when the WDE bit is cleared.
4 Dog Turn Off 0 R/W Otherwise, the watchdog will not be disabled. Once set,
Enable H/W will clear this bit to zero after four clock cycles.
When this bit is set the watchdog timer is enabled while
when it is zero the watchdog timer is disabled. WDE can
only be cleared when if the WDTOE is set. To disable an
enabled watchdog timer, the following procedure must
be followed:
WDE: Watchdog
3 0 R/W In the same operation, write a logical one to WDTOE
Enable
and WDE. A logical one must be written to WDE even
though it is set to one before the disable operation
starts.
Within the next four clock cycles, write a logical 0 to
WDE. This disables the watchdog.
WDP2: Watch
2 Dog Timer 0 R/W
Prescaler 2
WDP1:Watch These bits determine the Watchdog Timer prescaling
1 Dog Timer 0 R/W when the Watchdog Timer is enabled, according to
Prescaler 1 Table 7-5
WDP0:Watch
0 Dog Timer 0 0 R/W
Prescaler 0
Table 7-5. Watch Dog Timer Prescale Register Select

WDP2 WDP1 WDP0 Time-out Period
0 0 0 5.5ms 16K cycles
0 0 1 11ms 32K cycles
1 0 1 175ms 512K cycles
1 1 0 350ms 1024K cycles
1 1 1 700ms 2084K cycles
57
5635AX–USB–10/06
7.5 SPI Interface
SPI Control Register - SPCR

addr $0D ($2F) 8 bits
SPIE: SPI This bit causes setting of the SPIF bit in the SPSR register to
7 Interrupt 0 R/W execute the SPI interrupt provided that global interrupt are
Enable enabled.
SPE: SPI When it is set, the SPI is enabled and SS, MOSI, MISO and
6 0 R/W
Enable SCK are connected to pins PB4, PB5, PB6 and PB7.
When it is one, the LSB of the data word is transmitted first.
DORD: Data
5 0 R/W When it is cleared the MSB of the data word is transmitted
Order
first.
This bit selects Master SPI when set, and Slave SPI mode
MSTR: when cleared. If SS is configured as input and is driven low
4 Master/Slav 0 R/W while MSTR is set, MSTR will be cleared, and SPIF in SPSR
e Select will become set. The user will then have to set MSTR to re-
enable SPI master mode.
CPOL:
When this bit is set, SCK is high when idle. When CPOL is
3 Clock 0 R/W
cleared, SCK is low when idle.
Polarity
When set the data are valid in the falling edge of SCK if
CPHA: CPOL=0, or in the rising edge of SCK when CPOL=1. When
2 0 R/W
Clock Phase cleared data are valid in the rising edge of SCK if CPOL=0
and in the falling edge of SCK if CPOL=1.
SPR1: SPI These two bits control the SCK rate of the device configured
1 Clock Rate 0 R/W as a master. SPR1 and SPR0 have no effect during the slave
Select 1 mode. The relationship between the slave and the AVR Clock
Frequency is shown in the following table:
SPR1 SPR0 SCG Frequency

SPR0: SPI 0 0 {AVR clock rate} div 4
0 Clock Rate 0 R/W
0 1 {AVR clock rate} div 16
Select 0
58 AT76C712
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SPI Status Register - SPSR
addr $0E ($2E) 8 bits
When a serial transfer is complete, the SPIF bit is set and an
SPIF: SPI interrupt is generated if SPIE in SPCR is set and global
7 Interrupt 0 R/W interrupts are enabled. Alternatively, the SPIF bit is cleared
Flag by first reading the SPI status register with SPIF set, then
accessing the SPI Data Register.
WCOL: The WCOL bit is set if the SPI data register (SPDR) is written
Write during a data transfer. The WCOL bit (and the SPIF bit) are
6 0 R/W
Collision cleared by first reading the SPI Status Register with WCOL
Flag set, and then by accessing the SPI Data Register.
5:0 — 0 R Always read as zero
SPI Data Register — SPDR

addr $0F ($2F) 8 bits
7 MSB 0 R/W
6 0 R/W
5 0 R/W
It is used for data transfer between the register file and the
4 0 R/W SPI Shift register. Writing to the register initiates data
3 0 R/W transmission. Reading the register causes the Shift Register
Receive buffer to be read.
2 0 R/W
1 0 R/W
0 LSB 0 R/W
7.6 I/O PORTs
7.6.1 PORT A
Port A is an 2-bit bi-directional I/O Port with internal pull-up resistors.
Only PA0 - PA1 pins of Port A are available as external pins.
7.6.1.1 PORT A I/O Registers
PORT A Data Register - PORTA

addr $1B ($3B) 8 bits
7 MSB 0 R/W It is an 8-bit R/W register with zero initial value 0xff. The bits
in the Data Direction Register control the direction of the
6:1 0 R/W
corresponding pin in the PORT A.
When bit DDRBx is set, then PBx pin is input, while when
0 LSB 0 R/W
DDRBx is cleared PBx is output, x=0…7
59
5635AX–USB–10/06
PORT A Data Direction Register - DDRA
addr $1A($3A) 8 bits
7 MSB 0 R/W The bits in the Data Direction Register control the direction of
the corresponding pin in the PORT A.
6:1 0 R/W
When bit DDRAx is set then PAx pin is output, while when
0 LSB 0 R/W DDRAx is cleared PAx pin is input (x=0..7).
PORT A Input Pins Address - PINA

addr $19($39) 8 bits
7 MSB N/A R The Port A Input Pins address – PINA, is not a physical
register and this address enables access to the physical
6:1 N/A R
voltage value on each port pin. It is a read only address. The
initial value of PINA depends from status of each PORT A
0 LSB N/A R
pin.
7.6.2 PORT B
PORT B is an 8-bit bi-directional I/O port with internal pull-up resistors.
7.6.2.1 PORT B Alternative Functionality

Port B, besides its use as a general-purpose I/O port, is used to support alternate functions.
Specifically the SPI interface, the input capture pin for Timer/Counter1 and the external clocks
for the Timers/Counters are implemented through the B Port. When the SPI is enabled, the data
direction of port B pins 4..7 is overridden, according to Table 7-6.
Table 7-6. Port B Pins Alternate Functions

Port Pin Direction Alternate Function
PB0 (DDRB) External clock pin for Timer/Counter0
PB1 (DDRB) External clock pin for Timer/Counter1
PB2 (DDRB) Input Capture pin for Timer/Counter1
PB3 (DDRB) ICP: Capture for Timer/Counter 1
SPI Master SPI Slave
PB4 (DDRB) Input nSS (SPI Slave Select Input)
PB5 Output Input MOSI (SPI Bus Master Output/Slave Input)
PB6 Input Output/Hi-Z MISO (SPI Bus Master Input/Slave Output)
PB7 Output Input SCK (SPI Bus Serial Clock)
60 AT76C712
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7.6.2.2 PORT B I/O Registers
PORT B Data Register - PORTB

addr $18 ($38) 8 bits
6:1 0 R/W
corresponding pin in the PORT B.
When bit DDRBx is set then PBx pin is input, while when
0 LSB 0 R/W
DDRBx is cleared PBx is output, x=0…7
PORT B Data Direction Register - DDRB

addr $17 ($37) 8 bits
7 MSB 0 R/W The bits in the Data Direction Register control the direction of
the corresponding pin in the PORT B.
6:1 0 R/W
When bit DDRBx is set then PBx pin is output, while when
0 LSB 0 R/W DDRBx is cleared PBx pin is input (x=0..7).
PORT B Input Pins Address - PINB

addr $16 ($36) 8 bits
7 MSB N/A R The Port B Input Pins address – PINB, is not a physical
6:1 N/A R
initial value of PINB depends from status of each PORT B
0 LSB N/A R
pin.
7.6.3 PORT C
PORT C is a 3-bit Output Port with internal pull-up resistors.
Only PC0 - PC3 pins of Port C are available as external pins.
7.6.3.1 PORT C I/O Regsiters
PORT C Data Register - PORTC

addr $15 ($35) 8 bits
6:1 0 R/W
corresponding pin in the PORT C.
When bit DDRCx is set then PCx pin is input, while when
0 LSB 0 R/W
DDRCx is cleared PCx is output, x=0…7
61
5635AX–USB–10/06
PORT C Data Direction Register
addr $14 ($34) 8 bits
7 MSB 0 R/W The bits in the Data Direction Register controls the direction
of the corresponding pin in the PORT C.
6:1 0 R/W
When bit DDRCx is set then PCx pin is output, while when
0 LSB 0 R/W DDRCx is cleared PCx pin is input (x=0..7).
PORT C Input Pins Address - PINC

addr $13 ($33) 8 bits
7 MSB N/A R The Port C Input Pins address – PINC, is not a physical
6:1 N/A R
0 LSB N/A R initial value of PINC depends from status of each PORT C pin.
7.6.4 PORT D
PORT D is an 8-bit bi-directional I/O port with internal pull-up resistors.
7.6.4.1 PORT D Alternative Functionality

Port D, besides its use as a general-purpose I/O port, is used to support alternate functions.
Specifically, it offers the signals of UART0, as shown in the following table. Also, when UART0 is
enabled, the data direction of port D pins is overridden according to Table 7-7.
PORT D pins use for power supply the special pad “Vdd for PORTD”.
Table 7-7. Port D Pins Alternate Functions

PD0 Input Serial Receive In UART0
PD1 Output Serial Transmit Out UART0
PD2 Bidir nRTS, UART0 Ready To Send
PD3 Bidir nCTS, UART0 Clear To Send
PD4 Bidir nDSR, UART0 Data Set Ready
PD5 Bidir nDTR, UART0 Data Terminal Ready
PD6 Bidir nCD, UART0 Carrier Detect
PD7 Bidir nRI, UART0 Ring Indicator
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7.6.4.2 PORT D I/O Registers
PORT D Data Register - PORTD

addr $12 ($32) 8 bits
6:1 0 R/W
corresponding pin in the PORT D
When bit DDRDx is set then PDx pin is input, while when
0 LSB 0 R/W
DDRDx is cleared PDx is output, x=0…7
PORT D Data Direction Register

addr $11 ($31) 8 bits
7 MSB 0 R/W The Data Direction Register controls the direction of the
corresponding pin in the PORT D.
6:1 0 R/W
When bit DDRDx is set then PDx pin is input, while when
0 LSB 0 R/W DDRDx is cleared PDx is output, x=0…7
PORT D Input Pins Address - PIND

addr $10 ($30) 8 bits
7 MSB N/A R The Port D Input Pins address – PIND, is not a physical
6:1 N/A R
initial value of PIND depends from status of each PORT D
0 LSB N/A R
pin.
7.6.5 PORT E
Port E is an 4-bit bi-directional I/O Port with internal pull-up resistors at pins PE0, PE1 and
PE4..7 and with internal pull-down resistors at pins PE2 and PE3.
Only PE0 - PE3 pins of Port E are available as external pins.
7.6.5.1 PORT E Alternative Functionality

Port E, besides its use as a general-purpose I/O port, is used to support alternate functions.
Specifically, serves also as the Tx/Rx signals of UART1 and as external interrupts. When an
alternative function is enabled, the data direction of port E pins is overridden according to Table
7-8.
Table 7-8. Port E Pins Alternate Functions

PE0 Input Serial Receive In UART1
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Table 7-8. Port E Pins Alternate Functions
PE1 Output Serial Transmit Out UART1
PE2 (DDRE) INT0: edge triggered or level sensitive interrupt with pull-down
PE3 (DDRE) INT1: edge triggered or level sensitive interrupt with pull-down
7.6.5.2 PORT E I/O Registers
PORT E Data Register - PORTE

addr $0A ($2A) 8 bits
6:1 0 R/W
corresponding pin in the PORT E
When bit DDREx is set then PEx pin is input, while when
0 LSB 0 R/W
DDREx is cleared PEx is output, x=0…7
PORT E Data Direction Register — DDRE

addr $09 ($29) 8 bits
7 MSB 0 R/W The bits in the Data Direction Register controls the direction
of the corresponding pin in the PORT E.
6:1 0 R/W
When bit DDREx is set then PEx pin is output, while when
0 LSB 0 R/W DDREx is cleared PEx pin is input (x=0..7).
PORT E Input Pins Address - PINE

addr $08 ($28) 8 bits
7 MSB N/A R The Port E Input Pins address – PINE, is not a physical
6:1 N/A R
initial value of PINE depends from status of eachPORT E
0 LSB N/A R
pin.
8. Memory Space - Register Description
8.1 USB Register Set

The USB, appears to the AVR just like another peripheral. The USB register file is mapped to
the SRAM space. Table 8-1 summarizes the USB cell specific registers.
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Table 8-1. USB Register Set

Register Address Default Function
SLP_MODE $F000 00000000b Sleep mode control
IRQ_EN $F001 00000000b Master Interrupt Enable
IRQ_STAT $F002 00000000b Master Interrupt Status
RES_STAT $F003 00000000b Reset Status
PAIR_EN $F004 00000000b Pair Addressing Enable
USB_DMA_ADL $F005 00000000b DMA address Low
USB_DMA_ADH $F006 00000000b DMA address High
USB_DMA_LEN $F007 00000000b DMA packet length requested
USB_DMA_EAD $F008 00000000b DMA target Endpoint address
USB_DMA_PLT $F009 00000000b DMA packet length transferred
USB_DMA_EN $F00A 00000000b DMA Enable
FBYTE_CNT7_H $F0A8 00000000b FIFO Byte Count 7 Register [10:8]
FBYTE_CNT6_H $F0A9 00000000b FIFO Byte Count 6 Register [10:8]
FBYTE_CNT5_H $F0AA 00000000b FIFO Byte Count 5 Register [10:8]
FBYTE_CNT4_H $F0AB 00000000b FIFO Byte Count 4 Register [10:8]
FBYTE_CNT3_H $F0AC 00000000b FIFO Byte Count 3 Register [10:8]
FBYTE_CNT2_H $F0AD 00000000b FIFO Byte Count 2 Register [10:8]
FBYTE_CNT1_H $F0AE 00000000b FIFO Byte Count 1 Register [10:8]
FBYTE_CNT0_H $F0AF 00000000b FIFO Byte Count 0 Register [10:8]
FBYTE_CNT7_L $F0B8 00000000b FIFO Byte Count 7 Register [7:0]
FBYTE_CNT6_L $F0B9 00000000b FIFO Byte Count 6 Register [7:0]
FBYTE_CNT5_L $F0BA 00000000b FIFO Byte Count 5 Register [7:0]
FBYTE_CNT4_L $F0BB 00000000b FIFO Byte Count 4 Register [7:0]
FBYTE_CNT3_L $F0BC 00000000b FIFO Byte Count 3 Register [7:0]
FBYTE_CNT2_L $F0BD 00000000b FIFO Byte Count 2 Register [7:0]
FBYTE_CNT1_L $F0BE 00000000b FIFO Byte Count 1 Register [7:0]
FBYTE_CNT0_L $F0BF 00000000b FIFO Byte Count 0 Register [7:0]
FDR7 $F0C8 00000000b FIFO 7 Data Register
FDR6 $F0C9 00000000b FIFO 6 Data Register
FDR5 $F0CA 00000000b FIFO 5 Data Register
FDR4 $F0CB 00000000b FIFO 4 Data Register
FDR3 $F0CC 00000000b FIFO 3 Data Register
FDR2 $F0CD 00000000b FIFO 2 Data Register
FDR1 $F0CE 00000000b FIFO 1 Data Register
FDR0 $F0CF 00000000b FIFO 0 Data Register
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Table 8-1. USB Register Set (Continued)
Register Address Default Function
ECSR7 $F0D8 x1110000b Endpoint7 Control and Status Register
ECSR6 $F0D9 x1110000b Endpoint6 Control and Status Register
ECSR5 $F0DA x1110000b Endpoint5 Control and Status Register
ECSR4 $F0DB x1110000b Endpoint4 Control and Status Register
ECSR3 $F0DC x1110000b Endpoint3 Control and Status Register
ECSR2 $F0DD x1110000b Endpoint2 Control and Status Register
ECSR1 $F0DE x1110000b Endpoint1 Control and Status Register
ECSR0 $F0DF x1110000b Endpoint0 Control and Status Register
ECR7 $F0E8 0xxx0000b Endpoint7 Control Register
ECR6 $F0E9 0xxx0000b Endpoint6 Control Register
ECR5 $F0EA 0xxx0000b Endpoint5 Control Register
ECR4 $F0EB 0xxx0000b Endpoint4 Control Register
ECR3 $F0EC 0xxx0000b Endpoint3 Control Register
ECR2 $F0EC 0xxx0000b Endpoint2 Control Register
ECR1 $F0EE 0xxx0000b Endpoint1 Control Register
ECR0 $F0EF 0xxx0000b Endpoint0 Control Register
ENDPPGPG $F0F1 00000000b Function Endpoint Ping-Pong Register
FADDR $F0F2 00000000b Function Address Register
UIER $F0F3 xxx00000b USB Interrupt Enable Register
UIAR $F0F5 xxxxx000b USB Interrupt Acknowledge Register
UISR $F0F7 00000000b USB Interrupt Status Register
SPRSIE $F0F9 xxxxx000b Suspend/Resume Interrupt Enable Register
SPRSR $F0FA xxxxx000b Suspend/Resume Register
GLB_STATE $F0FB xxxxx000b Global State Register
FRM_NUM_L $F0FC xxxxx000b Frame Number Low Register
FRM_NUM_H $F0FD xxxxx000b Frame Number High Register
SLP_MODE - Sleep Mode Control Register

addr: $F000 8 bits

7:6 Reserved Reserved and set to 0
5 SLP R/W If set, put the USB Controller in sleep mode
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IRQ_EN - USB Interrupt Mask Register
addr: $F001 8 bits

7 Reserved R/W Reserved and set to 0
When this bit is high, enables the USB protocol
6 INT_EN R/W handler to cause interrupt (see UISR and
IRQ_STAT[6])
5:2 Reserved R/W Reserved and set to 0
If this bit is high, an interrupt is generated when the
USB enters suspend mode.
1 SUSP_INT_EN R/W A USB device enters in suspend mode only when
requested by the USB host through bus inactivity for at
least 3ms.
If this bit is high, an interrupt is generated when the
0 RSM_INT_EN R/W USB enters resume mode. A J-to-K state change on
the USB port signal resume.
IRQ_STAT - USB Interrupt Status Register

The IRQ_STAT register is automatically cleared on each read access.
addr: $F002 8 bits

7 Reserved R Reserved and set to 0
Interrupt from the USB protocol handler. When this bit is high,
6 INT R
then at least one bit of UISR is set.
5:4 Reserved R Reserved and set to 0
This bit is high while the USB bus remains in reset state. This
3 USB_RST R bit can be accessed also by using the RES_STAT register,
avoiding to clear the IRQ_STAT.
When this bit is high, the USB has exited from the suspend
2 nSUSP R
mode.
When this bit is high, the USB has entered the suspend
1 pSUSP R
mode.
When this bit is high, the USB host controller has send a
0 pUSB_RST R
Reset request (USB bus enterred the reset state).
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RES_STAT - Reset Status
addr: $F003 8 bits

3 USB_RST R This bit is high while the USB bus remains in reset state.
PAIR_EN - Pair Addressing Enable

addr: $F004 8 bits

By setting any of these bits, a pair of EPs is formed of one IN and
one OUT. For example, if UPA[1] is set, the EP1 should be
configured as an OUT EP, while the EP4 as an IN EP:
3:1 UPA[3:1] R/W UPA[1]: EP4 has the same USB physical address with EP1.
UPA[2]: EP5 has the same USB physical address with EP2.
UPA[3]: EP6 has the same USB physical address with EP3.
USB_DMA_ADL - DMA Address Low

addr: $F005 8 bits

The least significant byte of the target address at the Data
7:0 UDA[7-0] R/W
Memory that the DMA controller will use.
USB_DMA_ADH - DMA Address High

addr: $F006 8 bits

These seven bits along with the eight bits of the USB_DMA_ADL,
6:0 UDA[14-8] R/W form the target address UDA[14-0] at the Data Memory that the
DMA will use.
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USB_DMA_LEN - DMA Packet length
addr: $F007 8 bits

7:0 PLEN[7-0] R/W The AVR writes the number of bytes for the next DMA.
USB_DMA_EAD - DMA target Endpoint Address

addr: $F008 8 bits

The AVR writes the offset byte of FDRx address, depending on
the Endpoint that is going to send or has received data:
The following Endpoints with the corresponding offset bytes are
supported by the DMA channels:
FDR1: $CE
7:0 EAD[7:0] R/W FDR2: $CD
FDR3: $CC
FDR4: $CB
FDR5: $CA
FDR6: $C9
FDR7: $C8
USB_DMA_PLT - DMA Packet length transferred

addr: $F009 8 bits

7:0 TPL[7:0] R/W Returns the number of bytes transferred during the last DMA
USB_DMA_EN - DMA Enable Register

addr: $F00A 8 bits

USB_RDMA_ Enables Receive DMA (for OUT EPs). This bit is automatically
1 R/W
EN cleared after the end of the DMA.
USB_TDMA_E Enables Transmit DMA (for IN EPs). This bit is automatically
0 R/W
N cleared after the end of the DMA.
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FBYTE_CNTx_H - FIFO Byte Count High Register
Each Endpoint has a register that stores the number of bytes to be sent or that was received by
the USB H/W. The maximum data packet supported is 1024 bytes length for isochronous
Endpoints.
addr: See Table 8-1

7:3 Reserved Reserved Reserved
2:0 BYTECNT[10:8] R/W Length of data packet in FIFO.
FBYTE_CNTx_L - FIFO Byte Count Low Register

addr: See Table 8-1

7:0 BYTECNT[7:0} R/W Length of data packet in FIFO.
FDR - FIFO Data Registers 0 –7

FIFO data registers. These are dual function buffer registers. Received data are read by the pro-
cessor from the Endpoint's FIFO through these data registers. In the transmit mode, the
processor writes to the FIFO though this register.
addr: See Table 8-1 8 bits

Data to be written to FIFO or data to be read from
7:0 FIFO DATA [7:0] R/W
the FIFO.
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ECSR - Endpoint Control and Status Registers 0 – 7

Set by the processor to indicate to the USB H/W the direction of a control
transfer.
0 = control write. No data stage
Control 1 = control read
7 R
Direction This bit is used by Control Endpoints only and is used by FW to indicate
the direction of a control transfer. It is written by the FW after it receives a
RX SETUP interrupt. The H/W uses this bit to determine the status phase
of a control transfer.
Indicates that the processor has placed the last data packet in FIFO0, or
that the processor has processed the last data packet it expects from the
Host.
This bit is used only by Control Endpoints together with bit 1 (TX Packet
Ready) to signal the USB H/W to go to the STATUS phase after the packet
currently residing in the FIFO is transmitted.
6 Data End R
After the H/W completes the STATUS phase it will interrupt the processor
without clearing this bit.
CAUTION:Since the Data End bit signals “END OF TRANSACTION”, any
other Endpoint controller bit, set after the DATA END, is unconsidered by
the Ping-Pong controller. That is why Tx_Packet Ready should be set
before Data_End.
Set by the processor to indicate a stalled Endpoint. The H/W will send a
STALL handshake as a response to the next IN or OUT token.
The processor sets this bit if it wants to force a STALL if an unsupported
5 Force Stall R
request is received or if the Host continues to ask for data after the data is
exhausted. This bit should be set at the end of any data phase or setup
phase.
Indicates that the processor has loaded the FIFO with a packet of data.
This bit is cleared by H/W after the USB Host acknowledges the packet.
For ISO Endpoints, this bit is cleared unconditionally after the data is sent.
This bit is used for the following operations :
1. Control read transactions by a Control Endpoint.
2. IN transactions with DATA1 PID to complete the status
TX Packet phase for a Control Endpoint, when this bit is ‘0’, but bit
4 R/C Data End (bit 4) is ‘1’.
Ready
3. By a BULK IN or ISO IN or INT IN Endpoint.
The processor should write into the FIFO only if this bit is cleared. After it
has completed writing the data, it should set this bit. The data can be of
zero length. For a Control Endpoint, the processor should write to the
FIFO only while bit 6 (TX Packet Requested) is set. The H/W clears this bit
after it receives an ACK. If the interrupt is enabled clearing this bit by the
H/W causes an interrupt to the processor.
The USB H/W sets this bit after a STALL is sent to the Host.The firmware
3 Stall Snd W uses this bit when responding to a USB GetStatus Request.
Indicates End of data stage for the Control Endpoint only.
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The USB H/W sets this bit when it receives a valid setup packet from the
Host. This bit is used by Control Endpoints only to signal to the processor
that the USB H/W has received a valid SETUP packet and that the data
RX portion of the packet is stored in the FIFO. The H/W will clear all other bits
2 W
SETUP in this register and will set RX SETUP. If the corresponding interrupt is
enabled, the processor will be interrupted when RX SETUP is set. After
the completion of reading the data from the FIFO, the firmware should
clear this bit.
Indicates that the USB H/W has decoded an OUT token and that the data
is in the FIFO. The USB H/W sets this bit after it has stored the data of an
OUT transaction in the FIFO. While this bit is set, the H/W will NAK all
OUT tokens. For Control Endpoints only, bit 7 of this register, Enable
Control Write, has to be set for the H/W to accept the OUT data. The USB
H/W will not overwrite the data in the FIFO except for an early USB Setup
RX OUT Request. Bit RX OUT Packet is used for the following operations:
1 W
Packet 1. Control write transactions by a Control Endpoint
2. OUT transaction with DATA1 PID to complete the status
phase of a controlEndpoint.
3. By a BULK OUT or ISO OUT or INT OUT Endpoint
Setting this bit causes an interrupt to the processor if the interrupt is
enabled. The firmware clears this bit after the FIFO are read.
The H/W sets this bit to indicate to a Control Endpoint that it has received
an ACK handshake from the Host. This bit is used by H/W in a Control
Endpoint to signal to the processor that it has successfully completed
TX certain transactions. TX Complete is set at the completion of a:
0 R
Complete 1. Control read data stage
2. Status stage without data stage
3. Status stage after a control write transaction
ECR - Endpoint Control Registers 0 –7


Endpoint Enable/Disable
7 EPEDS R
(0 = Disable Endpoint, 1 = Enable Endpoint)
6 Reserved R Reserved
Reserved and
5:4 Reserved
set to 0
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3 DTGLE W Data Toggle. Identifies DATA0 or DATA1 packets
Endpoint Direction.
2 EPDIR R Only applicable for non-Control Endpoints (0
=Out, 1 =In).
Endpoint Type.
These bits represent the type of the Endpoint as
follows:
Bit1 Bit0 Type
1:0 EPTYPE R
0 0 Control
0 1 Isochronous
1 0 Bulk
1 1 Interrupt
ENDPPGPG - Endpoint Ping-Pong Enable Register

addr: $F0F1 8 bits

7 Reserved
6 PG PG 6 EN R Enable Endpoint 6 Ping-Pong
FADDR - Function Address Register

addr: $F0F2 8 bits

Function The FIU contains an address register that contains
7 FEN R
Enable the function address assigned by the Host. This
Function Address Register must be programmed by
the processor once it has received a
SET_ADDRESS command from the Host and
completed the status phase of the transaction. After
Function power up or reset, this register will contain the value
6:0 FADD[6:0] R of 0x00. The Function Enable bit (FEN) allows the
address
firmware to enable or disable the function Endpoints.
The firmware will set this bit after receipt of a reset
through the USB H/W. Once this bit is set, the USB
H/W passes packets to and from the Host.
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UIER - USB Interrupt Enable Register
addr: $F0F3 8 bits

7 SOF IE R Enable SOF Interrupt
6 EP6 IE R Enable Endpoint 6 Interrupt
5 EP5 IE R Enable Endpoint 5 Interrupt The bits in this register have
the following meaning:
1 = enable interrupt
3 EP3 IE R Enable Endpoint 3 Interrupt 0 = disable interrupt
UIAR - USB Interrupt Acknowledge Register

addr: $F0F5 8 bits

7 Reserved
Endpoint 6 Interrupt
6 EP6 INTA W
Acknowledge
5 EP5 INTA W
Acknowledge
Endpoint 4 Interrupt The bits in this register are used to
4 EP4 INTA W
Acknowledge indirectly clear the bits of the UISR. A
Endpoint 3 Interrupt bit in the UISR is cleared if a 1 is
3 EP3 INTA W written in the corresponding bit of
Acknowledge
UIAR
2 EP2 INTA W
Acknowledge
1 EP1 INTA W
Acknowledge
0 EP0 INTA W
Acknowledge
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UISR - USB Interrupt Status Register
addr: $F0F7 8 bits

7 Reserved The function interrupt bits will be
set by the H/W whenever the
6 EP6 INT W Endpoint 6 Interrupt
following bits in the corresponding
5 EP5 INT W Endpoint 5 Interrupt Endpoint's Control and Status
Register are modified by the USB
4 EP4 INT W Endpoint 4 Interrupt H/W:
3 EP3 INT W Endpoint 3 Interrupt RX OUT Packet is set (Control
and OUT Endpoints)
TX Packet Ready is cleared
1 EP1 INT W Endpoint 1 Interrupt (Control and IN Endpoints)
RX SETUP is set (Control
Endpoints only)
TX Complete is set (Control
Endpoints only)
SPRSIE - Suspend/Resume Interrupt Enable Register

addr: $F0F9 8 bits

7:4 Reserved
3 SOF IE R Enable SOF Interrupt
Enable External Resume Signaling Interrupt
2 EXTRSM IE R
1 = enable 0 = disable
Enable BUS Resume Signaling Interrupt
1 RCVDRSM IE R
Enable Suspend Signaling Interrupt
0 SUSP IE R
SPRSR - Suspend/Resume Register

addr: $F0FA 8 bits

7:4 Reserved
Start Of Frame Interrupt. Firmware clears this bit to
3 SOF INT R/W
acknowledge the SOF interrupt.
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Received External Resume. The USB H/W sets this bit to
denote an External Resume Interrupt. If RMWUPE =1, a
2 EXT RSM R/W
RESUME signal is send in USB BUS.Firmware clears this bit to
acknowledge the EXT RSM interrupt.
Received Resume. The USB H/W sets this bit when a USB
1 RCVD RSM R/W resume signaling is detected at its port.Firmware clears this bit
to acknowledge the RCVD RSM interrupt.
Suspend. The USB H/W sets this bit when it detects no SOF
for 3ms. The USB macro enters in SUSPEND MODE, the
0 SUSP R/W
processor has to go in SLEEP mode.Firmware clears this bit to
acknowledge the SUSP interrupt.
GLB_STATE - Global State Register

addr: $F0FB 8 bits

7:4 Reserved Reserved.
Set by the H/W when a Resume is send in the USB bus
3 RSMINPR W
during Remote Wake-up feature (13 ms).
Remote Wake-up Enable. This bit is set if the Host enables
2 RMWUPE R
the function's remote wake-up feature.
Configured. This bit is set by the firmware after a valid
1 CONFG R SET_CONFIGURATION request is received. It is cleared by a
reset or by a SET_CONFIGURATION with a value of 0.
Function Address Enable. This bit is set by firmware after the
FADD
0 R status phase of a SET_ADRESS request transaction. The
Enable
Host will use the new address starting at the next transaction.
FRM_NUM_L - Frame Number Low Register

addr: $F0FC 8 bits

This is the lower 8-bits of the 11 bit frame number of SOF
7:0 FCL[7:0] W
packet
FRM_NUM_H - Frame Number High Register

addr: $F0FD 8 bits

This is the upper 3 bits of the 11 bit frame number of SOF
2:0 FCH[10:8] W
packet
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8.2 UART Register Set
The base address for UART0 registers is $F200 and for UART1 registers is $F300. Each read or
write access of UART registers consumes at least 2 CPU cycles, since the UART core clock is
asynchronous and fixed to 14.769MHz.
In Table 8-2 the register file and its fields are briefly presented. A more detailed description is
provided in the following sections.
Table 8-2. UART register file and register fields

Addr
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
A[3:0]
General Register Set
0000
RHR MSB LSB
DLAB=0
00000
THR MSB LSB
DLAB=0
Enable Enable Rx Enable Enable Rx
0001 Modem Line THR Data
IER 0 0 0 0
DLAB=0 Status Status Ready Available
Interrupt Interrupt Interrupt Interrupt
Not
FIFO FIFO Interrupt Interrupt Interrupt
0010 IIR 0 0 Interrupt
Enabled Enabled ID Bit 2 ID Bit 1 ID Bit 0
Pending
Rx FIFO Rx FIFO
DMA Tx FIFO Rx FIFO FIFO
0010 FCR Trigger Trigger 0 0
Mode Reset Reset Enable
MSB LSB
Divisor
Word Word
Latch Stick Even Enable Number of
0011 LCR Set Break Length Bit Length Bit
Access Parity Parity Parity Stop Bits 1 0
(DLAB)
0100 MCR 0 0 0 Loopback OUT2 OUT1 RTS DTR
Error in Transmitte THR Break Framing Parity Overrun Rx Data
0101 LSR
Rx FIFO r Empty Ready Interrupt Error Error Error Available
Delta Trailing Delta
0110 MSR CD RI DSR CTS Delta CTS
CD Edge RI DSR
0111 SCR MSB LSB

Special Register Set
0000
DLL MSB LSB
DLAB=1
0001
DLH MSB LSB
DLAB=1
Output Start
Send Restart Tx Rx Tx Rx
1000 XR1 pins in Time-out
Address Time-out Reset Reset Disable Disable
Loopback Control
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Table 8-2. UART register file and register fields (Continued)
THR
Tx FIFO Transmitte THR Multi-
1001 XR2 Ready bit 0 0 0
Disable r Empty Ready drop
Control
nCD pin nRI pin nDSR pin nCTS pin nOut2 pin nOut1 pin nRTS pin nDTR pin
1010 MDR
Direction Direction Direction Direction Direction Direction Direction Direction
1011 RTO MSB LSB
1100 TTG MSB LSB
Receive Holding Register - RHR

addr: $0000 8 bits
7 MSB 0 R
6:1 0 R Holds the received byte.
0 LSB 0 R
Transmit Holding Register - THR

addr: $0000 8 bits
7 MSB 0 W
6:1 0 W Holds the byte to be transmitted.
0 LSB 0 W
Interrupt Enable Register - IER

addr: $0001 8 bits
7:4 — 0 R/W —
MSI: Enable Modem If set enables the MODEM status interrupt

3 0 R/W
Status Interrupt (MSR[7:4]).
RLSI:
If set enables the line status interrupt
2 Enable Receive Line 0 R/W
(LSR[4:1]).
Status Interrupt
TRI:
1 Enable THR Ready 0 R/W If set enables the THR ready interrupt. (LSR[5])
Interrupt
If set enables the Rx data available interrupt.
RDAI: Enable RX
Also enables and the time-out interrupt when
0 Data Avsilable 0 R/W
time-out counter is enabled (in FIFO mode or if
Interrupt
RTO is not zero, see XR1[5] and RTO).
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Interrupt Identification Register - IIR
addr: $0010 8bits
FIFOEN:
7:6 FIFO 0 R These two bits are set when FCR[0] is set.
Enabled
5:4 — 0 R —
3 ID2 0 R Interrupt ID Bit 2
NIP:Not If in logic ‘0’ then an interrupt is pending and the IIR[3..1]
0 Interrupt 0 R bits may be used for interrupt type identification. When in
Pending logic ‘1’, no interrupt is pending.
Table 8-3. UART Interrupt priority

Priority ID2 ID1 ID0 Interrupt Source Interrupt Reset Control
(Event)
Receiver Line Status
Highest 0 1 1 Reading LSR.
(LSR[3..1] not 0).
Reading all the data from the
0 1 0 Received Data Available Receive Holding Register or the
Rx FIFO.
Reading the RHR or receiving a
1 1 0 Time-out Indication
new word from SIN pin.
Transmitter Holding Reading IIR or
0 0 1
Register Ready writing to THR.
Modem Status
Lowest 0 0 0 (when any bit in MSR[7..4] Reading MSR.
changes from ‘0’ to ‘1’).
FIFO Control Register - FCR

addr: $0010 8 bits
7 RCVR1 0 W RCVR trigger bits. These bits indicate the minimum number
of bytes required in the receive FIFO to generate a receive
ready interrupt. The trigger level is shown from the following
table
Bit 7 Bit 6 Trigger Level (words)

6 RCVR0 0 W
0 0 1
0 1 4
1 0 8
1 1 14
5:4 — 0 W —
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When FIFOs are disabled (FCR[0] is low), this bit is forced to
RDMA:
‘0’. When set to logic ‘1’, the DMA is in burst mode allowing
DMA
3 0 W transfers until the Rx FIFO has been emitted or the Tx FIFO
Mode
has been filled. When it is cleared to ‘0’, the DMA is in single
select
mode and the words are read one word each time.
TRS:Tx
2 FIFO 0 W When set, resets the transmit FIFO.
reset
FRS:Rx
1 FIFO 0 W When set, resets the receive FIFO
reset
FEN:FIFO When set, enables the 16 byte receive and transmit FIFOs.
0 0 W
enable When cleared FIFOs are disabled and reset.
Line Control Register - LCR

addr: $0011 8 bits
DLAB:
It must be set to logic ‘1’ during a read or write operation in order
Divisor
7 0 R/W to access the Divisor Latches. Resetting to ‘0’ you have access
Latch to RHR, THR and IER.
Access
If set then it causes a break condition to to be transmitted to the
receiving UART. The SOUT pin is forced to the spacing state
(logic ‘0’). Resetting to logic ‘0’ stops the break condition. The
SBRK:S
break control bit acts only on SOUT pin and has no effect on the
6 et 0 R/W
transmitter logic. Note that UART waits before starting the break
Break
condition command for the complete transmission of the word in
the transmit shift register. There is no need for software
synchronization.
When the Parity Enable bit and the Parity Stick bit are set to
SPAR: logic ‘1’ then the Even Parity bit controls the transmitted parity
5 Stick 0 R/W value. Resetting the Even parity bit to logic ‘0’ then the parity bit
Parity is transmitted and checked as ‘1’. Setting the Even parity bit to
logic ‘1’ then the parity bit is transmitted and checked as ‘0’.
When the Enable Parity bit is a ‘1’ and the Stick Parity bit is a ‘0’,
EVPAR: then setting to logic ‘1’ the Even parity an even number of logic
4 Even 0 R/W 1s is transmitted or checked in the data word bits and the Parity
Parity bit. When Even Parity bit is reset to logic ‘0’ an odd number of 1s
are transmitted or checked.
ENPAR:
Setting this bit to logic ‘1’ a parity bit is transmitted or checked.
3 Enable 0 R/W
Resetting this bit to ‘0’ no parity bit is transmitted or checked.
Parity
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This bit determines the number of stop bits according to the
following table:
SB:
Number Bit 2 Word Number of
2 0 R/W
of stop Length stop bits
bits 0 any 1
1 5 1,5
1 6, 7, 8 2
WL1: These bits determine the word length according to the following
1 Word 0 R/W table
length
Bit 1 Bit 0 Word Length (bits)

WL0: 0 0 5
0 Word 0 R/W 0 1 6
length 1 0 7
1 1 8
Modem Control Register - MCR

addr: $0100 8 bits
7:5 — 0 R/W
LB: If Set enables the loopback mode. Note that you can not set
4 0 R/W
Loopback this bit at logic ‘1’ if the value of MDR is not $F0.
3 OUT2 0 R/W The compliment value of the bidirectional pin nOUT2.

2 OUT1 0 R/W The compliment value of the bidirectional pin nOUT1.
1 RTS 0 R/W The compliment value of the bidirectional pin nRTS.
0 DTR 0 R/W The compliment value of the bidirectional pin nDTR
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Line Status Register - LSR
addr: $0101 8 bits
ERF: If the FIFOs are disabled this bit is a ‘0’. If FIFOs are enabled
7 Error in 0 R this bit indicates that at least one word in the Rx FIFO has it’s
RX FIFO Parity Error or Framing Error or Break Indication bits high.
TE: When set indicates that both the Transmit Shift Register and
6 Transmitte 0 R Transmit Holding Register, or the Tx FIFO if Tx FIFO is
r Empty enabled, are empty.
If set indicates that the THR is ready to accept a new word for
transmission. This bit is set when a word is transferred from the
THRR: THR into the Tx shift register. This bit is reset concurrently with
Transmit the loading of the THR by the core. If Tx FIFO is enabled
5 Holding 0 R (FCR[0]=1, XR2[7]=0), the function of this bit is controlled by
Register XR2[4]. If XR2[4] is ‘0’, then this bit is set when the Tx FIFO is
ready empty; it is cleared when at least 1 word is written to the Tx
FIFO. If XR2[4] is ‘1’, then this bit is set when the Tx FIFO is not
full;
If set indicates a Break Interrupt. Indicates that the receive data
BI: input is held in the spacing state (logic ‘0’) for longer than a full
Receive word transmission time.In FIFO mode this error is associated
4 0 R
Break with the word at the top of the Rx FIFO which is equivalent to
Interrupt RHR. This bit is reset to a logic ‘0’ whenever the core reads the
LSR.
If set indicates a framing error. Indicates that the received word
FE: in RHR does not have the correct stop bit. In FIFO mode this
3 Framing 0 R error is associated with the word at the top of the Rx FIFO
Error which is equivalent to RHR. This bit is reset to a logic ‘0’
whenever the core reads the LSR.
If set indicates a parity error. Indicates that the received word in
RHR does not have the correct parity bit. In FIFO mode this
PE:Parity
2 0 R error is associated with the word at the top of the FIFO which is
Error
equivalent to RHR. This bit is reset to a logic ‘0’ whenever the
core reads the LSR.
If set indicates an overrun error. Indicates that data in RHR
was not read by the core before the next word was transferred
into the RHR, thereby destroying the previous word. In FIFO
Mode an overrun error will occur only after the Rx FIFO is full
OE:Overr
1 0 R and the next word has been completely received in shift
un Error
register. The word in the shift register is overwritten, but it is not
transferred to the Rx FIFO. Overrun error is indicated to the
core as soon as it happens. This bit is reset to a logic ‘0’
whenever the core reads the LSR.
RDA:
Receive If set indicates that there are data available in the RHR. This
0 Holding 0 R bit resets to logic ‘0’ by reading all of the data from the Receive
Register Holding Register or the Rx FIFO.
Ready
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Modem Status Register - MSR
addr: $0110 8 bits
The compliment of the bidirectional Carrier Detect nCD I/O
7 CD 0 R/W pin. If MCR[4] is set (loopback mode) then this bit is
equivalent to nOUT2 pin.
The compliment of the bidirectional Ring Indicator nRI I/O
6 RI 0 R/W pin. If MCR[4] is set (loopback mode) then this bit is
equivalent to nOUT1 pin.
The compliment of the bidirectional Data Set Ready nDSR
5 DSR 0 R/W I/O pin. If MCR[4] is set (loopback mode) then this bit is
equivalent to nDTR pin.
The compliment of the bidirectional Clear To Send nCTS I/O
4 CTS 0 R/W pin. If MCR[4] is set (loopback mode) then this bit is
equivalent to nRTS pin.
DCD:
Delta Indicates that the nCD pin has changed state since the last
3 Carrier 0 R/W
time it was read by the core.
Detect
indicator
TRI:
Trailing Indicates that the nRI pin has changed from a low to a high
2 Edge of 0 R/W
state since the last time it was read by the core.
Ring
Indicator
DDSR:
Delta Data Indicates that the nDSR pin has changed state since the last
1 0 R/W
Set Ready time it was read by the core.
indicator
DCTS:
Delta Clear Indicates that the nCTS pin has changed state since the last
0 0 R/W
To Send time it was read by the core.
indicator
Scratch-pad Register - SCR

addr: $0111 8 bits
7 MSB 0 R/W
A scratch-pad register which holds data temporarily. Doesn’t
6:1 0 R/W
effect the UART in anyway.
0 LSB 0 R/W
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Divisor Latch Register, Low Byte - DLL
addr: $0000 8 bits
7 MSB 0 R/W
6:1 0 R/W Baud rate generator division ratio low byte
0 LSB 0 R/W
Divisor Latch Register, High Byte - DLH

addr: $0001 8 bits
7 MSB 0 R/W Baud rate generator division ratio high byte.
6:1 0 R/W The main UART clock, from the system clock generator,
is divided by the 16-bit number contained in DLL and
DLH, to provide the UART clock (which is 16 times the
0 LSB 0 R/W
actual serial data rate)
Extra Register 1 - XR1

addr: $1000 8 bits
If set, in loop-back mode (MCR[4] is set), then the SOUT,
OPL:Outpu
nOUT2, nOUT1, nRTS and nDTR pins are not forced to
7 t pins in 0 R/W
logic ‘1’ but they operate normally (echo). If Loop-back is
Loop-back
disabled this bit has no effect.
Effective in Multi-drop mode only (see XR2[0]). If set the
SA:Send
6 0 R/W next word will be transmitted with the parity bit (in multi-
Address
drop mode is called address bit) forced at logic ‘1’.
STOC: This bit controls the start operation of the time-out

counter. If in logic ‘0’, then it operates in 16550
5 Start Time- 0 R/W
compatible mode. If set in logic ‘1’ the time-out counter
out Control
starts whenever RTO is not zero. (see and RTO)
RTO:
Writing a logic “1” resets the time-out counter. This bit
4 Restart 0 R/W
resets to logic ‘0’ automatically.
Time-out
TxR: Writing a logic “1” resets the transmit path (and Tx
3 0 R/W
Tx Reset FIFO). This bit resets to logic ‘0’ automatically
RxR: Writing a logic “1” resets the receive path (and Rx FIFO).
2 0 R/W
Rx Reset This bit resets to logic ‘0’ automatically.
TxDis:
1 0 R/W If set disables the transmit path.
Tx Disable
RxDis:
0 0 R/W If set disables the receive path.
Rx Disable
Note: When XR1 and XR2 registers are both $00, then the UART operates in 16550 compatible mode.
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Extra Register 2 - XR2
addr: $1001 8 bits
TxFD:Tx If set disables the Tx FIFO. So, if FCR[0] and XR2[7] are
7 0 R/W
FIFO Disable both set then only the Rx FIFO is enabled.
This bit is equivalent to LSR[6]. You can use it to check if
TE:Transmitt
6 0 R/W transmitter is empty without resetting the error bits in
er Empty
LSR.
This bit is equivalent to LSR[5]. You can use it to check if
THRR:
5 0 R/W the THR is ready to load data without resetting the line
THR Ready status bits in LSR.
Functional only if Tx FIFO is enabled. If in logic ‘0’, then
the LSR[5] (and XR2[5]) bit indicates that Tx FIFO is
THRRC:THR empty (THRR bit is ‘1’) or that it has at least one word
4 Ready bit 0 R/W waiting for transmission (THRR bit is ‘0’). Setting this bit
Control to logic ‘1’, then LSR[5] (and XR2[5]) bit indicates that Tx
FIFO is not full (THRR bit is ‘1’) or that it is full (THRR bit
is ‘0’).
3:1 — 0 R/W —
If set enables the Multi-drop mode. In this case the Parity
Error Bit in LSR is set when data is detected with the
parity bit at logic ‘1’ to identify an address word. If the
received parity bit is detected low then the Parity Error bit
MDM: Multi-
0 0 R/W is not set. The transmitter sends an address word (with
drop mode
the parity bit set) when the Send Address bit (XR1[6]) is
set. Setting the XR1[6] the next word written to THR will
be transmitted as an address and any transmitted word
after this will have the parity bit cleared.
Note: When XR1 and XR2 registers are both $00, then the UART operates in 16550 compatible mode.
Modem Direction Register - MDR

addr: $1010 8 bits
nCDD:nCD pin
7 1 R/W If set nCD pin is configured as input.
Direction
nRID:nRI pin
6 1 R/W If set nRI pin is configured as input.
Direction
nDSRD:nDSR pin
5 1 R/W If set nDSR pin is configured as input.
Direction
nCTSD:nCTS pin
4 1 R/W If set nCTS pin is configured as input.
Direction
nOUT2D:nOUT2 pin
3 0 R/W If set nOUT2 pin is configured as input.
Direction
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nOUT1D:nOUT1 pin
2 0 R/W If set nOUT1 pin is configured as input.
Direction
nRTSD:nRTS pin
1 0 R/W If set nRTS pin is configured as input.
Direction
nDTRD:nDTR pin
0 0 R/W If set nDTR pin is configured as input.
Direction
Receiver Time-out Register - RTO

addr: $1011 8 bits
7 MSB 0 R/W This register contains the maximum bit periods, for which the
UART will wait the next word to arrive. Whenever the time-out
6 0 R/W
counter expires, then a Time-out Indication Interrupt will be
5 1 R/W issued.
The XR1[5] Start Time-out Control bit selects the Start Time-
4 0 R/W
out and RTO load mechanism. If the XR1[5] bit is reset to ‘0’
3 0 R/W (16550 compatible mode), then the RTO loads the value 4
times the word length + 12 on each LCR write operation. After
2 0 R/W
reset, the word length is 5 bits and the RTO is $20. The time-
1 0 R/W out counter will then start counting down only in FIFO mode
(FCR[0] is set) and if the Rx FIFO holds at least 1 word. If
XR1[5] is set to ‘1’, then the time-out function is available and in
FIFO disabled mode. The RTO value doesn’t change with LCR
write operations. The time-out counter will start counting down
whenever the RTO is not $00 and the RHR is loaded.
0 LSB 0 R/W In all cases core has immediate access at the contents of the
RTO.
The Time-out counter resets when a new word is completely
received and transferred at the Receive Holding Register or
when the XR1[4] bit is forced to logic ‘1’. If XR1[5] is reset to ‘0’,
time-out counter resets and on a RHR read access from core.
Transmitter Time Guard Register - TTG

addr: $1100 8 bits
7 MSB 0 R/W
The value of this register indicates the delay (in bit periods) that
6:1 0 R/W an active transmitter has to interpose between two consecutive
word transmissions.
0 LSB 0 R/W
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Table 8-4. Baud Rate generation example (UART clock = 14,769 MHz)
Output Baud
Rate User Devisor (16*clk) UBM Value UBL Value
Decimal Hex Hex Hex
100 9216 2400 24 00
200 4608 1200 12 00
400 2304 900 09 00
600 1536 600 06 00
1200 768 300 03 00
2400 384 180 01 80
4800 192 C0 00 C0
9600 96 60 00 60
14400 64 40 00 40
19200 48 30 00 30
28800 32 20 00 20
38400 24 18 00 18
57600 16 10 00 10
76800 12 0C 00 0C
115200 8 08 00 08
153600 6 06 00 06
230400 4 4 00 04
307200 3 03 00 03
460800 2 02 00 02
921600 1 01 00 01
8.3 Memory Access Interface Register set
Memory Bank Map Register - MEMMAP

addr: $F800 8 bits
7 MSB 0 R/W
Utilizing the MEMMAP register it is possible to resize the two
6:1 0 R/W
memory spaces
0 LSB 1 R/W
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DMA External Memory Interface Control Register A - DMA_EMICRA
addr: $F801 8 bits
7 RW1 0 R/W Read Wait States:These bits control the Wait states inserted in
6 RW0 0 R/W the corresponding (read, write and ALE) signals.
5 RM1 0 R/W Read Mode Select:These bits control the mode (waveform) of
4 RM0 0 R/W the corresponding (read, write and ALE) signals.
3 WW1 0 R/W Write Wait States:These bits control the Wait states inserted in
2 WW0 0 R/W the corresponding (read, write and ALE) signals.
1 WM1 0 R/W Write Mode Select:These bits control the mode (waveform) of
0 WM0 0 R/W the corresponding (read, write and ALE) signals.
DMA External Memory Interface Control Register B - DMA_EMICRB

addr: $F802 8 bits
7 AW1 0 R/W ALE Wait States:These bits control the Wait states inserted in
6 AW0 0 R/W the corresponding (read, write and ALE) signals.
5 AM1 0 R/W ALE Mode Select:These bits control the mode (waveform) of
4 AM0 0 R/W the corresponding (read, write and ALE) signals.
3 — 0 R/W Those bits are reserved and must be remain always in zero ‘0’
2 — 0 R/W value.
1 EMD0 0 R/W External Memory Device Select:These bits select the external
memory interface mode according to the following table:
EMD1 EMD0 External Memory Interface Mode

0 0 FIFO
0 EMD1 0 R/W 0 1 Reserved
1 0 Demultiplexed
1 1 Multiplexed
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9. Errata
1. Stack Pointer is 11-bits wide
The Stack Pointer is 11-bits wide.
Problem Fix/Workaround
Keep the stack below the address $07FF.
2. DDRB initial value

The boostrap ROM code, after accessing the external SPI memory and remmaping to the final
code, leaves the DDRB register to $10 value (instead of $00). The result is to have the
“PB4/nSS” pin as output and set to 0 value ( because PORTB = $00).
Problem fix/workaround
Set the correct value of the DDRB register according to the given system configuration.
3.USB “setup” packet

In some cases the USB controller might not respond to a “setup” packet if the previous USB
packet was a “status-in” and the firmware performed an action while servicing the packet.
The firmware must wait for the next “SOF” packet before servicing the “status-in” packet.
The “Set Address” is the only USB standard request that needs this special treatment.
4. IIR and MSR UART registers

The IIR Register indicates when any bit in MSR[7..4] is changed from 0 to 1 but it does not indi-
cate a transition from 1 to 0.
The firmware needs to poll the MSR register in order to detect if any bit in MSR[7..4]
changes its value from 1 to 0.
5.Unserved UART Tx Interrupt Request

The problem arises when both Receive (Rx) and Transmit (Tx) IRQs are enabled and both Rx
and Tx IRQs are pending. In that case the firmware detects the Rx IRQ when it reads the IIR.
This IIR read though, may erroneously clear the Tx IRQ. Thus, the firmware loses the Tx IRQ,
which is never served.
Problem Fix / Workaround
The UART Interrupt Service Routine (ISR) must examine and serve a potential Tx IRQ, inde-
pendently from the IIR value. For example, the ISR can use either the LSR[5] or the XR2[5]
bits to check for pending Tx IRQs.
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10. Electrical Specifications
10.1 Absolute Maximum Ratings

Operating Temperature ......................................-40°C to 85°C *NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to
Storage Temperature ........................................-65°C to 150°C the device. This is a stress rating only and func-
Voltage on Any Pin tional operation of the device at these or other con-
with Respect to Ground ..... 0V to Maximum Operating Voltage ditions beyond those indicated in the operational
sections of this specification is not implied. Expo-
Maximum Operating Voltage ............................................ 3.6V sure to absolute maximum rating conditions for
extended periods may affect device reliability.
10.2 D.C. Characteristics
10.2.1 Power Supply

Symbol Parameter Condition Min Typ Max Unit
CVDD Core Supply Voltage 1.65 1.8 1.95 V
CVDD + 1.5,
PVDD Periphery Supply Voltage CVDD 3.3 V
3.6 max
PVDD_USB USB Supply Voltage 3.0 3.3 3.6 V
PAVDD Analog Power Supply 1.65 1.8 1.95 V
VIL Low Level Input Voltage -0.3 +0.8 V
VIH High Level Input Voltage 2.0 PVDD + 0.3 V
VOL Low Level Output Voltage IOL = 0mA 0.2 V
IOL = 2mA 0.4 V
VOH High Level Output Voltage IOH = 0mA PVDD - 0.2 V
IOH = 2mA PVDD - 0.4 V
10.2.2 Pull-up circuit (where pin=0V)

Condition Min Max
Current PVDD=3.3V 129µA (PVDD=3.0V) 322µA (PVDD=3.6V)
10.2.3 Pull-down circuit (where pin=PVDD)

Condition Min Max
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10.2.4 USB Signals: DP, DM

Code Parameter pu33b11f Unit
The DP/DM lines require the addition of external series resistors of 27Ω
VT+ High Level Input Voltage 1.8 V
VT- Low Level Input Voltage 0.8 V
Vhys Hysteresis 0.2 V
10.2.5 Oscillator Signals: OSC

Symbol Parameter Condition Min Typ Max Unit
See standard
PAVDD Supply Voltage operating conditions 1.65 1.8 1.95 V
below
rms value, 10 KHz to

Supply Ripple 30 mV
∆Vdd 10 MHz
idd on Current Consumption @16 MHz 0.9 1.6 MA

Freq Operating frequency 8 12 16 MHz
Duty Duty Cycle 40 60 %
With Crystal defined
Ton Startup Time 2 ms
below
Pon Drive Level 150 µW
Equivalent Serie
ESR @16 MHz 80 Ω
Resistance
Cm Motional Capacitance 5 9 fF
Cshunt Shunt Capacitance 7 pF
Max. external
Cload Load Capacitance 15 20 pF
capacitors:40pF
Standby current
Idd stdby onosc=0 1 µA
consumption
10.3 Ordering Information
Device Ordering Code Package

AT76C712 AT76C712 JT064 64 leadfree(Pbfree) TQFP
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11. Packaging Information
D1 D
XX
E1 E
e
b
UN T
CO
RY
BOTTOM VIEW
TOP VIEW
A2
A1 SIDE VIEW
L COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE

1. The top package body size may be smaller than the bottom package size by as A1 0.05 0.15 5
much as 0.15mm.
2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is
A2 0.95 1.00 1.05
0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including D 12.00 BSC
mold mismatch.
3. Dimension b does not include dambar protrusion. Allowable dambar protrusion
D1 10.00 BSC 2,1
shall not cause the lead width to exceed the maxium b dimension by more than E 12.00 BSC
0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum
space between protrusion and an adjacent lead is 0.07 mm for 0.4 and 0.5 mm E1 10.00 BSC 2,1
pitch packages. e 0.50 BSC
4. These dimensions apply to the flat section of the lead between 0.10 mm and
0.25 mm from the lead tip. b 0.17 0.22 0.27 3,4
5. A1 is defined as the distance from the seating place to the lowest boint on the L1 1.00 REF
package body.
This drawing is for general information only. Refer to

JEDEC Drawing MS-026, Variation ACD for additional
information.
6/03/03
TITLE DRAWING NO. REV.
1150 E. Cheyenne Mtn. Blvd. 64T2, 64-lead, 10x10x1.0 mm Body, Thin Plastic
R Colorado Springs, CO 80906 Quad Flat Pack (TQFP) PO64T2 A
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Table of Contents
Features ..................................................................................................... 1
1 Overview ................................................................................................... 2
2 AT76C712 Functional Diagram ............................................................... 3
3 Pin Diagram .............................................................................................. 4

3.164–pin TQFP Package ..............................................................................................4
4 Pin Summary – Pin Assignment of the 64–pin Package ...................... 5
5 Signal Description ................................................................................... 6
6 Functional Description ............................................................................ 9

6.1Bootstrap ROM and Programming Modes ................................................................9
6.2The AVR core ..........................................................................................................12
6.3Oscillator and Clock Generator ...............................................................................13
6.4Memory Map ...........................................................................................................14
6.5Memory Access Interface ........................................................................................15
6.6USB DMA Controller ...............................................................................................16
6.7USB Controller ........................................................................................................16
6.8UART0, UART1 .......................................................................................................25
6.9IrDA 1.0 codec .........................................................................................................27
6.10Watchdog Timer ....................................................................................................28
6.11Serial Peripheral Interface - SPI ............................................................................28
6.12JTAG Interface and On-Chip Debug System ........................................................31
6.13IEEE 1149.1 (JTAG) Boundary-Scan ....................................................................35
7 I/O Space - Register Description .......................................................... 42

7.1Timers/Counters ......................................................................................................49
7.2Timer/Counter 0 and Timer/Counter 2 .....................................................................51
7.3Timer/Counter 1 ......................................................................................................54
7.4Watchdog Timer ......................................................................................................57
7.5SPI Interface ............................................................................................................58
7.6I/O PORTs ...............................................................................................................59
8 Memory Space - Register Description ................................................. 64

8.1USB Register Set ....................................................................................................64
8.2UART Register Set ..................................................................................................77
8.3Memory Access Interface Register set ....................................................................87
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9 Errata ....................................................................................................... 89
10 Electrical Specifications ........................................................................ 90

10.1Absolute Maximum Ratings ...................................................................................90
10.2D.C. Characteristics ..............................................................................................90
10.3Ordering Information .............................................................................................91
11 Packaging Information .......................................................................... 92
ii AT76C712
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Atmel Corporation Atmel Operations
2325 Orchard Parkway Memory RF/Automotive
San Jose, CA 95131, USA 2325 Orchard Parkway Theresienstrasse 2
Tel: 1(408) 441-0311 San Jose, CA 95131, USA Postfach 3535
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Fax: (49) 71-31-67-2340
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9F, Tonetsu Shinkawa Bldg. Tel: 1(719) 576-3300
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Features

LFT XIN XOUT PM0 PM1 nRST

Program Memory SUSP

AVR core Register SPI

Boundary Scan Chain (JTAG)

3.1 64–pin TQFP Package

Table 4-1. Pin Summary – Pin Assignment of the 64–pin Package

Table 5-1. Signal Description

Alternative Functions Of Port B

Alternative Functions of Port D

Alternative Functions of Port E

6.1 Bootstrap ROM and Programming Modes

Table 6-1. Programming Modes

6.1.1 USB DFU-only Mode

6.1.2 Slave Programmming Mode

Figure 6-1. Slave Programming Mode Sequence

Configuration Data transfer Confirmation

MISO Config. Header Image Code Data C1 C2

MOSI (8-bit Received Data Counter) C1 C2

Table 6-2. Possible Cases of Programming during Slave Program Mode

6.1.3 Master Programming Modes

6.1.4 Configuration Header

Table 6-3. Configuration Header

Table 6-4. Control Bitmap

6.2 The AVR core

6.2.1 Interrupt Handling

Table 6-5. Interrupt Vector table of the AT76C712

Note: The Program Memory word length is 16-bits wide.

Figure 6-2. AT76C712 Clock Generation Tree

6.3.1 PLL LFT Pin

Figure 6-3. LFT pin circuit

Base Address Module Description

Table 6-6. Memory Map

6.5.1 Memory Remapping Interface

Figure 6-4. Memory remapping

Data Memory Program Memory

8K Program Memory 0 8K Program Memory 1 Program SRAM Bank 0,1

8 8 Program SRAM Bank 2, 3

6.6 USB DMA Controller

6.7 USB Controller

AVR Memory Bus

Table 6-8. USB Function Interface Unit Structure

6.7.1 USB System Interface (SI)

6.7.2 USB Interrupt Handling

6.7.3 Interrupt Priority

Table 6-10. USB Macro interrupt Priority

6.7.4 Endpoint Interrupt

6.7.5 Interrupt for Non-Control Endpoints

6.7.6 Interrupt for Control Endpoints

6.7.7 USB Function Interface (FIU)

6.7.8 USB Serial Interface Engine (SIE)

6.7.9 Control Transfers at Function EP0

Host USB macro Micro Controller

6.7.10 Interrupt and Bulk In Transfers

Figure 6-6. Bulk IN Transfers

IN Token without Ping-pong

IN Token with Ping-pong

HOST reads last data HOST reads last data

6.7.11 Interrupt and Bulk OUT Transfers