Offline, Primary-Side Regulator With CC/CV Control and A 700V MOSFET

MP020A-5
Offline, Primary-Side Regulator

with CC/CV Control and a 700V MOSFET
DESCRIPTION FEATURES
The MP020A-5 is an offline, primary-side  Primary-Side Control without Optocoupler or
regulator that provides accurate constant Secondary Feedback Circuit
voltage and constant current regulation without  Precise Constant Current and Constant
an optocoupler or a secondary feedback circuit. Voltage Control (CC/CV)
The MP020A-5 has an integrated 700V  Integrated 700V MOSFET with Minimal
MOSFET. External Components
The MP020A-5's variable off-time control allows  Variable Off Time, Peak-Current Control
a flyback converter to operate in discontinuous  550µA High-Voltage Current Source
conduction mode (DCM). The MP020A-5 also  30mW No-Load Power Consumption
features protection functions such as VCC  Programmable Cable Compensation
under-voltage lockout (UVLO), over-current  OVP, OCP, OCkP, OTP, and VCC UVLO
protection (OCP), over-temperature protection  Natural Spectrum Shaping for Improved
(OTP), open-circuit protection (OCkP), and EMI Signature
over-voltage protection (OVP). Its internal high-  Low Cost and Simple External Circuit
voltage start-up current source and power-  Available in a SOIC8-7A Package
saving technologies limit the no-load power
consumption to less than 30mW. APPLICATIONS
The MP020A-5's variable switching frequency  Cell Phone Chargers
technology provides natural spectrum shaping  Adapters for Handheld Electronics
to smooth the EMI signature, making it suitable  Standby and Auxiliary Power Supplies
for offline, low-power battery chargers and  Small Appliances
adapters. All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
The MP020A-5 is available in a SOIC8-7A Quality Assurance. “MPS” and “The Future of Analog IC Technology” are
registered trademarks of Monolithic Power Systems, Inc.
package.
Maximum Output
Power (85 - 265VAC)
Part Number RDS(ON)
Open
Adapter
Frame
MP020A-5GS 10Ω 5W 8W
TYPICAL APPLICATION
MP020A-5 Rev. 1.0 www.MonolithicPower.com 1

6/23/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
MP020A-5 – OFFLINE, PRIMARY-SIDE REGULATOR W/ CC/CV CONTROL AND 700V MOSFET
ORDERING INFORMATION
Part Number* Package Top Marking
MP020A-5GS SOIC8-7A See Below
* For Tape & Reel, add suffix –Z (e.g. MP020A-5GS–Z)
TOP MARKING
MP020A-5: Product code of MP020A-5GS

LLLLLLLL: Lot number
MPS: MPS prefix
Y: Year code
WW: Week code
PACKAGE REFERENCE
TOP VIEW
SOIC8-7A

ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance (4) θJA θJC

DRAIN to GND............................. -0.7V to 700V SOIC8-7A ............................. 76 ....... 45 ... °C/W
VCC to GND .................................. -0.3V to 30V NOTES:
CP to GND....................................... -0.3V to 7V 1) Exceeding these ratings may damage the device.
FB input ......................................... -0.7V to 10V 2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
Continuous power dissipation (TA = +25°C) (2) ambient thermal resistance θJA, and the ambient temperature
SOIC8-7A ..................................................1.3W TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
Junction temperature ............................... 150°C (MAX)-TA)/θJA. Exceeding the maximum allowable power
Lead temperature .................................... 260°C dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
Storage temperature ................ -60°C to +150°C shutdown circuitry protects the device from permanent
ESD capability human body mode ............ 2.0kV damage.
ESD capability machine mode ...................200V 3) The device is not guaranteed to function outside of its
operating conditions.
Recommended Operating Conditions (3) 4) Measured on JESD51-7, 4-layer PCB.
Operating junction temp. (TJ). .. -40°C to +125°C

Operating VCC range ..................... 6.6V to 28V

ELECTRICAL CHARACTERISTICS
VCC = 15V, TA = 25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Supply Voltage Management (VCC)
VCC on threshold VCCH 16.8 17.3 17.8 V
VCC off threshold VCCL 6 6.3 6.6 V
VCC operating voltage 6.6 28 V
Quiescent current IQ At no load condition, VCC = 20V 360 410 μA
Operating current IOP 60kHz, VCC = 20V 500 μA
Leakage current from VCC ILeak_VCC VCC = 0  16V, DRAIN floating 0.1 1 μA
Internal MOSFET (DRAIN)
Break-down voltage VBRDSS VCC = 20V, VFB = 7V 700 V
Supply current from DRAIN ICharge VCC = 4V, VDRAIN = 100V 450 550 750 µA
Leakage current from DRAIN ILeak_Drain VDS = 500VDC 1 10 µA
On-state resistance RON ID = 10mA, TJ = 20°C 10 13 Ω
Minimum switching frequency fMIN At no load condition 120 Hz
Internal Current Sense
Current limit ILimit VFB = -0.5V 365 380 395 mA
Leading-edge blanking tLEB 230 300 370 ns
Feedback Input (FB)
FB input current IFB VFB = 4V, VCP = 3V 10 14 18 μA
FB threshold VFB 3.93 4 4.07 V
DCM detect threshold VDCM 80 120 160 mV
FB open-circuit threshold VFBOPEN -0.22 -0.15 -0.08 V
FB OVP threshold VFBOVP 6.2 6.35 6.5 V
OVP sample delay tOVP 3.5 µs
Output Cable Compensation (CP)
Cable compensation voltage VCP Full load 2 V
Thermal Shutdown
Thermal shutdown threshold 150 °C
Thermal shutdown recovery
120 °C
threshold

TYPICAL CHARACTERISTICS

TYPICAL CHARACTERISTICS (continued)

TYPICAL PERFORMANCE CHARACTERISTICS

Performance waveforms are tested on the evaluation board in the Design Example section.
VIN = 230VAC, VOUT = 5V, IOUT = 1A, L = 1.6mH, TA = 25°C, unless otherwise noted.

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Performance waveforms are tested on the evaluation board in the Design Example section.
VIN = 230VAC, VOUT = 5V, IOUT = 1A, L = 1.6mH, TA = 25°C, unless otherwise noted.
MP020A-5 CV/CC Characteristics
25℃ CV/CC
3
Vo(V)
2
265Vac
230Vac
115Vac
1 85Vac
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1
Io(A)

PIN FUNCTIONS
SOIC8-7A
Name Description
Pin #
Supply. The IC begins functioning when VCC charges to the on threshold (VCCH) through
an internal high-voltage current source. When VCC falls below the off threshold (VCCL),
1 VCC
the internal high-voltage current source turns on to charge VCC. Connect a 0.1µF
decoupling ceramic capacitor for most applications.
2, 5, 6 GND Ground.
Feedback. FB provides the output reference voltage and detects the falling voltage
3 FB
edges to determine the operation mode (CV mode or CC mode).
Output cable compensation. Connect a 1μF ceramic capacitor as a low pass filter. The
4 CP
upper resistor of the resistor divider connected to FB adjusts the compensation voltage.
8 DRAIN Internal MOSFET drain. DRAIN is the input for the high-voltage start-up current source.

BLOCK DIAGRAM
FB Protection Power VCC

Unit Management
Start Up Unit
Constant
Current Control DRV
Driving Signal Drain

Management
Constant
Voltage Control Current
Sense
Cable
CP Compensation GND
Figure 1: Functional Block Diagram

OPERATION Working Principle

After start-up, the internal MOSFET turns on,
Start-Up
and the current sense resistor (RCS) senses the
Initially, the IC is self-supplying through an primary current (iP(t)) internally (see Figure 3).
internal high-voltage current source, which is The current rises linearly at a rate that can be
drawn from DRAIN. The internal high-voltage calculated with Equation (1):
current source turns off for better efficiency
when VCC reaches its on threshold (VCCH). diP (t) VIN
 (1)
Then the transformer’s auxiliary winding takes dt LM
over as the power source. When VCC falls
IPK
below its off threshold (VCCL), the IC stops
switching, and the internal high-voltage current
iP
source turns on again (see Figure ).
Vcc
0
VCCH Figure 1: Primary Current Waveform
V CCL When iP(t) rises up to IPK, the internal MOSFET
turns off (see Figure 4). Then the energy stored
in the inductor transfers to the secondary side
Drain through the transformer.
Switching Pulses
The inductor (LM) stores energy with each cycle
as a function shown in Equation (2):
1
High-voltage
E  LM  IPK
2
(2)
current source
2
ON The power transferred from the input to the
output can be determined with Equation (3):
OFF 1
P LM  IPK
2
 fS (3)
2
Figure 2: VCC UVLO Where fS is the switching frequency. When IPK is

constant, the output power depends on fS.
Constant Voltage (CV) Operation
The MP020A-5 detects the auxiliary winding
voltage from FB and operates in constant
voltage (CV) mode to regulate the output
voltage. Assume the secondary winding is the
master and the auxiliary winding is the slave.
When the secondary-side diode turns on, the
FB voltage can be calculated with Equation (4):
NP _ AU RDOWN
VFB   (VO  VD )  (4)
NS RUP  RDOWN
Where VD is the secondary-side diode forward-
Figure 3: Simplified Flyback Converter drop voltage, Vo is the output voltage, NP_AU is
the number of auxiliary winding turns, NS is the
number of secondary side winding turns, and
RUP and RDOWN are the resistor divider for
sampling.

Leading-Edge Blanking
The parasitic capacitances induce a spike on
the sense resistor when the power switch turns
on. The MP020A-5 includes a 300ns leading-
edge blanking period to avoid falsely
terminating the switching pulse. During this
blanking period, the current sense comparator
Figure 2: Auxiliary Voltage Waveform is disabled, and the gate driver cannot switch
The output voltage differs from the secondary off (see Figure 4).
voltage due to the current-dependent forward- t LEB
diode voltage drop. If the secondary voltage is
VLimit
always detected at a fixed secondary current,
the difference between the output voltage and
the secondary voltage is a fixed VD. The
MP020A-5 samples the auxiliary winding
voltage 3.5µs after the primary switch turns off
(see Figure 5). The CV loop control function
turns the secondary-side diode off to regulate t
the output voltage.
Figure 4: Leading-Edge Blanking
Constant Current (CC) Operation
Figure 3 shows the constant-current operation. DCM Detection
The MP020A-5 operates in DCM in both CV
VFB ZCD and CC modes. To avoid operating in
Sample
continuous conduction mode (CCM), the
VZCD
MP020A-5 detects the falling edge of the FB
IPK input voltage with each cycle. If the chip does
Io estimator VCOMP_I
not detect a 120mV falling edge, it stops
switching.
IO_REF
OVP and OCkP
Figure 3: CC Control Loop The MP020A-5 includes over-voltage protection
The flyback always works in discontinuous (OVP) and open-circuit protection (OCkP). If the
conduction mode (DCM), and the zero-current voltage at FB exceeds 6.35V for 3.5µs, or the
detection (ZCD) sample block can detect the FB input’s 0.15V falling edge cannot be
duty cycle of the secondary-side diode. monitored, the MP020A-5 immediately shuts off
the driving signals and enters hiccup mode. The
In constant current (CC) operation, the product
MP020A-5 resumes normal operation when the
of VZCD times Ipk approximately equals IO_REF, as
fault has been removed.
shown in Equation (5):
Thermal Shutdown
IO _ REF  VZCD  IPK (5)
When the temperature of the IC exceeds 150°C,
The calculated output current from the IO over-temperature protection (OTP) is triggered,
estimator block is compared with the reference and the IC enters auto-recovery mode. When
value (IO_REF), and the error signal (VCOMP_I) the temperature falls below 120°C, the IC
controls the turn-on signal of the integral recovers.
MOSFET. IO can be calculated with Equation
(6):
1 NP
IO    IO _ REF (6)
2 NS
The MP020A-5 maintains IO_REF at 0.152A.

Output Cable Compensation Determine the compensation voltage with

Equation (7):
To compensate for the secondary-side cable
voltage drop for a more precise output voltage, 5.6  DS N
the MP020A-5 has an internal output cable VFCP   2  RUP  S (7)
360  10 3
NP _ AU
compensation circuit (see Figure 5). The
internal ZCD sample can detect the duty of the Where VFCP is the secondary-side
secondary-side diode. A low-pass filter converts compensation voltage drop, DS is the
the duty signal to a DC voltage (VCP) that secondary-diode duty cycle in CC mode (0.4 for
changes as the load current varies. the MP020A-5), RUP is the upper resistor of the
VCP can be converted to a current signal drawn resistor divider, NS is the number of turns for the
from FB. The voltage drop on RUP helps the secondary-side transformer windings, and NP_AU
output cable compensation. When the system is the number of transformer auxiliary winding
operates in the maximum load, the CP voltage turns.
reaches a maximum of 2V.
RUP T1
V FCP
* *
Vo
FB
RDOWN
+ -
VCP
CP
DS
Figure 5: Output Cable Compensator

APPLICATION INFORMATION Output Capacitor

Input Filter Use low ESR or very low ESR output capacitors
to meet the output voltage ripple requirement
The input filter helps convert the AC input to a
without using an LC post filter. Using low ESR
DC source through the rectifier. Figure 6 shows
capacitors improves output voltage regulation
the input filter, and Figure 7 shows the typical
and feedback voltage sampling at high
DC bus voltage waveform.
temperatures or low temperatures. Use an
L output capacitor with an ESR below 100mΩ for
better efficiency over high ESR output
+ capacitors.
R
C1 + C2 +
Output Diode
AC Input DC Input
Use a Schottky diode because of its fast
switching speed and low forward-voltage drop
for better high- or low-temperature CV
regulation and efficiency.
Figure 6: Input Filter

If the lower average efficiency (3% to 4%) is
sufficient, replace the output diode with a fast or
Vin ultra-fast diode to reduce costs. Be sure to
VDC(max) readjust the resistor divider values to the
DC input voltage correct output voltage because the forward
voltage drop is higher than the Schottky diode’s.
VDC(min) Leakage Inductance
The transformer’s leakage inductance
AC input voltage decreases the system efficiency and affects the
VAC
output current or voltage constant precision.
0 t Optimize the transformer structure to minimize
the leakage inductance. Aim for a leakage
Figure 7: DC Input Voltage Waveform
inductance less than 5% of the primary
Bulk capacitors (C1 and C2) filter the rectified inductance.
AC input. The inductor (L) forms a π filter with RCD Snubber
C1 and C2 to restrain the differential mode EMI
noise. The resistor (R) parallel with L restrains The transformer’s leakage inductance causes
the mid-frequency band EMI noise. Normally, R the MOSFET drain voltage to spike and
is 1 - 10kΩ. excessive ringing on the drain voltage
waveform, which affects the output voltage
C1 and C2 are usually set as 2µF/W to 3µF/W sampling 3.5µs after the MOSFET turns off.
for the universal input condition. For 230VAC
single-range applications, halve the capacitor The RCD snubber circuit can limit the DRAIN
values. Avoid using very low minimum DC voltage spike. Figure 8 shows the RCD snubber
voltages to ensure that the converter can circuit.
supply the maximum power load, which can be
calculated with Equation (8):
NP DS
VDC(min)   (VO  VD )  (8)
NS 1  DS
If VDC(min) cannot satisfy this expression,
increase the value of the input capacitors to
increase VDC(min).

The damping resistor in series with the RCD

has a relatively large value to prevent any
excessive voltage ringing that can affect the CV
sampling and increase the output ripple. Use a
200 - 500Ω damping resistor to restrain the
drain-voltage ringing.
Divided Resistor
For better application performance, select the
resistor divider’s total value to be between 40 -
100kΩ. Smaller resistors draw larger currents
from the auxiliary winding, which increases the
no-load consumption. Larger resistors may also
pick up noise from adjacent components.
Figure 8: RCD Snubber If necessary, use a resistor between 1kΩ and
Select RSN and CSN to meet the voltage spike 2kΩ connected between the FB and resistor
requirements and improve system operation. divider. RFB can also limit substrate injection
current effects (see Figure 9).
The power dissipated in the snubber circuit can
be approximated with Equation (9):
1 VSN
PSN   LK  IPK 2   fS (9)
2 VSN  NPS  VO
Where LK is the leakage inductance, VSN is the
clamp voltage, and NPS is the turn ratio of
primary and secondary side.
Since RSN consumes the majority of the power,
RSN is approximated with Equation (10):
VSN2
RSN  (10)
PSN Figure 9: Feedback Resistor Divider Circuit
The maximum ripple of the snubber capacitor For more accurate CV regulation, the accuracy
voltage can then be calculated with Equation of these feedback resistors should be at least
(11): 1%.
VSN Dummy Load

VSN  (11) When the system operates without a load and
CSN  RSN  fS no dummy load, the output voltage rises above
Generally, a 15% ripple is reasonable, so CSN the normal operation because of the minimum
can be estimated with Equation (11) as well. switching frequency limitation. Use a dummy
load for good load regulation. However, a large
Normally, select a time constant (τ = RSN x CSN) dummy load deteriorates efficiency and no-load
below 0.1ms for better CV sampling. Adjust the consumption, so selecting the dummy load is
resistor based on the power loss and the tradeoff between efficiency and load regulation.
acceptable clamp voltage in practical For most applications, use a dummy load
applications. around 10mW, which satisfies the 30mW
requirement.

Maximum Switching Frequency

Use a secondary-side diode conduction time
that exceeds 5.4µs, as shown in Equation (12):
NS  LM
TS _ ON  IPK   5.4s (12)
NP  (VO  VD )
For high- or low-temperature applications,
select a maximum switching frequency below
75kHz.
PCB Layout Guide
Efficient PCB layout is critical for reliable Top Layer
operation, good EMI, and good thermal
performance. For best results, refer to Figure
10 and follow the guidelines below.
1. Minimize the loop area formed by the input
capacitor, the MP020A-5 drain-source, and
the primary winding to reduce EMI noise.
2. Provide at least 1in2 of top-side copper for
adequate heat-sinking.
3. The copper area connected to GND is the
heat conduction path for the MP020A-5.
4. Minimize the clamp circuit loop to reduce Bottom Layer
EMI. Figure 10: Recommended Layout
5. Minimize the secondary loop area of the Design Example
output diode and output filter to reduce EMI Table 1 shows a design example following the
noise. application guidelines based the specifications
6. Provide sufficient copper area at the anode below.
and cathode terminal of the output diode to Table 1: Design Example
act as a heat sink.
VIN 85 ~ 265VAC
7. Place the AC input away from the switching VOUT 5V
nodes to minimize the noise coupling that IOUT 1A
may bypass the input filter. fS 60kHz
8. Place the bypass capacitor as close as Figure 14 through Figure 16 show the detailed
possible to the IC and source. application schematic. This circuit was used for
the typical performance and circuit waveforms.
9. Place the feedback resistors next to FB. For more device applications, please refer to
10. Minimize the feedback sampling loop to the related evaluation board datasheets.
minimize noise coupling. The transformer structure used in Figure 14 can
11. Use a single-point connection at the benefit from passing the 3-wire conducted EMI
negative terminal of the input filter capacitor test (output GND connect to earth) without the
for the MP020A-5 source pin and bias Y-cap. The Y-cap results in leakage current,
winding return. which is prohibited in some cell phone charger
applications. Figure 15 illustrates how the
common noise of the secondary-side diode is
restrained. The secondary-side winding splits to
two separate windings (NSEC1 and NSEC2), which

have the same turns and approximate parasitic

capacitors (CSP1 and CSP2), but their hot spot is
opposite (Point 9 and Point 10 in Figure 15).
Therefore, the common mode noise current
produced at the secondary-side windings can
counteract each other.
The transformer structure is simple if the
application does not need to pass the 3-wire
conducted EMI or uses a Y-cap. Figure 16
shows a schematic with a simple transformer
structure.

TYPICAL APPLICATION CIRCUITS
Figure 11: 5V/1A with Complicated Transformer Structure
Figure 15: Secondary Side Windings Structure to Restrain the Common Mode Noise

TYPICAL APPLICATION CIRCUITS
Figure 16: 5V/1A with Simple Transformer Structure

FLOW CHART
Start Y
Monitor VCC VCC<VCCL
N N
V CC >VCCH Monitor V CC
Monitor Io Monitor V FB N
V FB>-0.15V
V FB>6.35V
Y Io<Io_ref for entire
for 3.5us
cycle
N Y Y
CV CC OVP OCkP
Operation Operation Operation Operation
Shut Off
Switching
Pulse
Figure 17: Flow Chart

PACKAGE OUTLINE DRAWING FOR SOIC 8-7-2
MF-PO-D-0126, revision 0.0
PACKAGE INFORMATION
SOIC8-7A
0.189(4.80) 0.050(1.27)
0.024(0.61)
0.197(5.00)
8 5
0.063(1.60)
0.150(3.80) 0.228(5.80)
0.157(4.00) 0.213(5.40)
PIN 1 ID 0.244(6.20)
1 4
TOP VIEW RECOMMENDED LAND PATTERN
0.053(1.35)
0.069(1.75)
0.0075(0.19)
SEATING PLANE
0.0098(0.25)
0.004(0.10)
0.010(0.25)
SEE DETAIL "A"
0.050(1.27) 0.013(0.33)
BSC 0.020(0.51)
FRONT VIEW SIDE VIEW
0.010(0.25)
x 45o NOTE:
0.020(0.50)
GAUGE PLANE 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN

0.010(0.25) BSC BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH ,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
0.016(0.41) OR PROTRUSIONS.
0o-8o 0.050(1.27) 4) LEAD COPLANARITY(BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) JEDEC REFERENCE IS MS-012.
DETAIL "A" 6) DRAWING IS NOT TO SCALE.
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal
responsibility for any said applications.


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MP020A-5

Offline, Primary-Side Regulator

MP020A-5 Rev. 1.0 www.MonolithicPower.com 1

* For Tape & Reel, add suffix –Z (e.g. MP020A-5GS–Z)

MP020A-5: Product code of MP020A-5GS

MP020A-5 Rev. 1.0 www.MonolithicPower.com 2

ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance (4) θJA θJC

Operating junction temp. (TJ). .. -40°C to +125°C

MP020A-5 Rev. 1.0 www.MonolithicPower.com 3

MP020A-5 Rev. 1.0 www.MonolithicPower.com 4

MP020A-5 Rev. 1.0 www.MonolithicPower.com 5

TYPICAL CHARACTERISTICS (continued)

MP020A-5 Rev. 1.0 www.MonolithicPower.com 6

TYPICAL PERFORMANCE CHARACTERISTICS

MP020A-5 Rev. 1.0 www.MonolithicPower.com 7

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

MP020A-5 Rev. 1.0 www.MonolithicPower.com 8

MP020A-5 Rev. 1.0 www.MonolithicPower.com 9

FB Protection Power VCC

Driving Signal Drain

Figure 1: Functional Block Diagram

MP020A-5 Rev. 1.0 www.MonolithicPower.com 10

OPERATION Working Principle

Figure 2: VCC UVLO Where fS is the switching frequency. When IPK is

MP020A-5 Rev. 1.0 www.MonolithicPower.com 11

MP020A-5 Rev. 1.0 www.MonolithicPower.com 12

Output Cable Compensation Determine the compensation voltage with

Figure 5: Output Cable Compensator

MP020A-5 Rev. 1.0 www.MonolithicPower.com 13

APPLICATION INFORMATION Output Capacitor

Figure 6: Input Filter

MP020A-5 Rev. 1.0 www.MonolithicPower.com 14

The damping resistor in series with the RCD

VSN Dummy Load

MP020A-5 Rev. 1.0 www.MonolithicPower.com 15

Maximum Switching Frequency

MP020A-5 Rev. 1.0 www.MonolithicPower.com 16

have the same turns and approximate parasitic

MP020A-5 Rev. 1.0 www.MonolithicPower.com 17

TYPICAL APPLICATION CIRCUITS

Figure 11: 5V/1A with Complicated Transformer Structure

MP020A-5 Rev. 1.0 www.MonolithicPower.com 18

TYPICAL APPLICATION CIRCUITS

Figure 16: 5V/1A with Simple Transformer Structure

MP020A-5 Rev. 1.0 www.MonolithicPower.com 19

Monitor VCC VCC<VCCL

Figure 17: Flow Chart

MP020A-5 Rev. 1.0 www.MonolithicPower.com 20

TOP VIEW RECOMMENDED LAND PATTERN

FRONT VIEW SIDE VIEW

GAUGE PLANE 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN

MP020A-5 Rev. 1.0 www.MonolithicPower.com 21

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