IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308

LOC, LOS AND LOES AT-SPEED TESTING METHODOLOGIES FOR

AUTOMATIC TEST PATTERN GENERATION USING TRANSITION
DELAY FAULT MODEL

Parth Borda1, Pankaj Prajapati2

1
M.E, Department of Electronics & Communication, L.D.College of Engineering, Gujarat, India
2
Assistant Professor, Department of Electronics & Communication, L.D.College of Engineering, Gujarat, India

Abstract
Faults, caused by timing-related defects in very large scale integrated circuits, are important to detect to optimize coverage and test
time. Delay faults are only due to timing malfunction. At-speed test is only method to detect these delay faults. This paper describes
and compares different at-speed testing techniques on vivid point of views along with them practical implementation. This paper also
shows results generated by automatic test pattern generation tool for these techniques. Next, generated test patterns are simulated by
using simulator and correctness of these methods are verified.

Keywords: LOC (Launch on capture), LOS (Launch on shift), LOES (Launch on extra shift), At-speed testing.
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1. INTRODUCTION detail along with its benefits and its comparison with other
two techniques. Section-IV shows practical results and
Down scaling of feature sizes in current submicron technology simulations of these delay fault detection techniques. And
results in high operating frequencies and clock speeds. For this section-V concludes the paper by comparing all techniques.
current VLSI technology, testing of only stuck-at fault is not
sufficient. It is very important to detect faults produced by
timing-related defect, which cannot be detected by ATEs
whose frequency are lower than operating frequency of
design. Timing related defect causes delay faults like
transition delay fault and path delay fault. They can only be
detected when testing frequency is same as functional
frequency. This type of testing of design is called At-Speed
testing. Transition delay model and path delay model are two
widely used at-speed model today. [6][7]

Unlike stuck-at fault test, at-speed test requires two test

vectors or test patterns. First pattern initialize or active the
fault at input of combinational logic block and second pattern
launch transition in the logic value at fault site and propagate
this transition to the outputs of the combinational block which
are captured back in the scan chains. For an example, as Fig-1: At-speed testing for a pattern (Pass – if transition
shown in figure-1, second output signal cannot be detected captured and Fail – if transition not captured) [6]
because it is exerted by delay fault. Delay test can be
classified based on how second vector is obtained as Launch 1.1 Transition Delay and Path Delay Fault Models
on shift test (Skewed load delay test), Launch on capture test
(Broad side delay test) and Launch on extra shift. [6] Transition fault model assumes only one gate is affected by
slow-to rise fault and slow-to-fall fault. In faulty circuit, each
This section-I introduce transition and path delay faults, delay gate has nominal delay and in the faulty circuit, any gate is
fault models and at-speed testing. Section-II explains LOC and exerted by high value of this delay. So under transition delay
LOS techniques for transition fault detection along with their fault model, extra delay caused by delay fault is large enough.
advantages and disadvantages. Also we discuss importance of Hence signal cannot make transition within time of
them in the design. Section-III explains LOES technique in observation at primary output of combinational block. This
transition delay fault is observed independently, whether it is
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IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308

propagated through short or longer path, at output. The Second functional clock would captures the propagated
advantage of this fault model is that number of faults in the transition at the output. Then scan enable signal would
circuit are relatively small or linear in terms of the number of asserted. Example, for scan chain having N scan-length, in
gates. [1] LOC, first vector of N bit is loaded in to scan chain by N slow
clock. Then two fast clock (functional clock) are used to
In the path delay fault model, circuit is behave like faulty if launch and capture transition into and from the combinational
the delay of any of its path exceeds threshold limit. The delay block. Again scan chain unloads with N slow clocks. Here
defect on a path is detected by propagating transition through scan enable signal transit from high to low after last shift of
the path therefore transition is applied at the begging of the loading process. So, launch clock always occur in function
path. The limitation of path delay fault model is that number mode and launching of transition would be along function
of paths in the circuit are very large. One strategy commonly path.
is used for path delay fault testing is to select all paths which
delays are greater than specified threshold. The reason of Now in LOS, launching of transition is different than LOC. In
selecting the longer path is that the defects on shorter paths LOS, as shown in figure-2(b), last shift clock is used as second
might not affect the circuit behaviour and if it large enough to vector to launch transition in combinational block. Here
affect circuit performance, it would be detected by transition during launching scan enable signal remains asserted so
delay fault test. [1] transition is launched along shift path. Let’s take scan chain of
scan-length N as an example, under the LOS methodology,
2. LAUNCH ON CAPTURE (LOC) and LAUNCH first N-1 bits of vector are loaded (shifted-in into scan chain)
by slow clock would initialize the logic value at input of
ON SHIFT (LOS) combinational block and Nth shift with fast clock would
Main transition fault ATPG methodologies are Launch on launch transition. Then scan enable signal goes low. After that
Capture and Launch on Shift (also known as broadside-load fast capture clock comes as shown in figure-2(b). Again slow
and skewed-load respectively). They both launch transition at clock is used to unload the scan chain.
the input of combinational block in different way for the same
fault detection. 2.1 Pros and Cons of LOC and LOS
1) In LOC, V2 is generated by applying functional clock from
As shown in figure-2, two vectors V1 and V2 are used to V1 whereas in LOS, V2 is shifted vector of V1. And to launch
perform transition delay fault testing. Here figure-2(a) transition on shift path is very easy than to launch transition on
describes the LOC waveform. As illustrated, last shift of scan functional path.
chain initialize the inputs of combinational block and first 2) LOC techniques uses sequential engine during automatic
functional clock is used to launch transition in the combination test pattern generation (ATPG) whereas LOS uses
block (here scan enable signal is de-asserted after V1). combination engine for ATPG. So LOS requires to do some
extra setup to perform ATPG.
3) In LOS, the fault activation path or scan path is fully
controllable from the input of scan chain while in LOC,
controllability of launching transition at fault site is less ( its
depends on the functional response of logic blocks to initialize
vector) results LOS give better controllability cause better
fault coverage and less patterns than LOC.
4) In LOC, after all slow clocks for loading there is dead clock
zone so, scan enable signal can easily make transition from
(a) high to low. But in case of LOS, fast scan enable signal must
design to make transition between two high speed clocks
means scan enable signal must operate at full speed. This will
increase cost of testing. As solution of this problem in LOS,
pipelined architecture is used for scan enable signal. This scan
enable signal is called pipelined scan enable signal. [2]
5) In LOS, last shift happen with fast clock and entire design
will become active result average power in launch cycle is
very high.
6) In LOS, lash shift would happen at high speed clock will
(b)
force to place additional timing requirements on an On chip
Clock (OCC) controller in multi-clock domain design.
Fig-2 (a): LOC Waveform (b) LOS Waveform [2]

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Volume: 03 Issue: 03 | Mar-2014, Available @ http://www.ijret.org 274
IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308

3. LAUNCH ON EXTRA SHIFT (LOES)

LOES – Launch on Extra shift is delay fault test technique
used to solve problems of LOS methodology already
mentioned. In LOES methodology, transition is launched by
extra fast shift clock at inputs of combinational block as
shown in figure-3. In case of scan chain having N bit scan-
length, N slow shift clock cycle require to load entire scan
chain and (N+1)th fast shift clock is used to launch the
transition.

(a)

Fig-3: LOES Waveform [2]

Then fast functional clock happens to capture response after

scan enable signal goes low. So, in LOES, extra shift and
capture clocks are at-speed clocks. Essentially, loading-
unloading processes of LOES are similar to LOC whereas
launching process is same as LOS because transition is
launched through shift path. [2]

3.1 Comparisons with LOC and LOS

1) Since in LOES, transition is launched by an extra shift this
methodology is as efficient as LOS in terms of coverage and
test patterns.
2) LOES also uses sequential engine to perform ATPG like (b)
LOC and all ATPG setup are same as LOC.
3) LOES also has a same problem scan enable signal as shown Fig-4: (a) Scan Enable Pipelined Circuitry (b) waveforms of
in LOS that scan enable signal must be design to operate at pipelined scan enable signal for LOS and LOES [2]
high speed. And also pipelined scan enable signal requires as
solution that need pipelined architecture. Above figure-4(a) shows implementation of pipelined scan
4) In LOES, all bits of patterns are shifted into scan chain enable signal in ASIC design. SE is controlled by external
through slow clocks so, unlike LOS, LOES doesn’t need tester and PSE is pipelined scan enable signal is internally
additional timing hardware on an OCC controller. generated and is forwarded to all scan enable pins of
scannable flops available in scan chain. Here PEN is pipelined
3.2 Pipelined Structure for LOS and LOES enable signal. It is generally high to active pipelined structure
during LOS and LOES automatic test pattern generation. It
Methodologies remains low during LOC because it gives same logic values
As we have discussed earlier, transition of scan enable signal on SE and PSE pins. So, low logic value on PSE would
between two function frequency clocks would increase the deactivate pipelined structure.
cost of testing and also it is very difficult with low speed
ATEs. So, pipelined scan enable signal is a solution for that. Figure-4(b) shows even-though for LOS and LOES external
Figure-4 illustrates the structure of pipelined scan enable tester make transition in scan enable (SE) signal before launch
signal normally used for LOS and LOES techniques and shift, pipelined scan enable (PSE) signal switches between two
waveforms for same. fast clocks. This would solve the problem of requirement of
costly external signal to operate top level scan enable signal at
functional speed.

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IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308

4. RESULTS AND SIMULATIONS As shown in above figure, it becomes very easy to compare
these three techniques.
Here below figure-5 shows results of one VLSI design in
terms of fault coverage and number of test patterns for LOC, Here as per our discussion LOS and LOES are efficient
LOS and LOES methodology which are generated by methodologies in terms of test coverage and test patterns but
automatic test pattern generation tool. major disadvantage of both is its implementation is difficult
because they require fast scan enable signal.

(a)

(a)

(b)

(c)

(b) Fig-6: Simulated waveforms of a test pattern for (a) LOC, (b)
LOS and (c) LOES

Also figure-6 shows simulated waveforms for all these

techniques that verifies correctness of these methodology.
These are similar to our theoretical waveform discussed
above. In this figure-6, launch and capture clock cycles of one
pattern are shown.

5. CONCLUSIONS
In this paper, we studied an effective and practical transition
and path delay testing methodologies. This paper also convey
the basic understanding of LOC, LOS and LOES transition
delay testing techniques along with their comparison. The
main goal of this paper is to give brief about benefits and
(c) difficulties, of these three methodologies, we need to consider
during delay testing and automatic test pattern generation.
Fig-5: Fault coverage and Number of test patterns for (a) Also results compare these methods in terms of coverage and
LOC, (b) LOS and (c) LOES number of test patterns.

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IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308

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[4]. Synopsys "VCS User guide", Version:Y-20o6.06-SP2,
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[6]. Bruce Swanson, Michelle Lange, "AT-Speed testing made
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[7]. Lin Wei, Shi Wenlong, "A new circuit for at-speed scan
SoC testing", Chinese Institute of Electronics, Journal of
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Volume: 03 Issue: 03 | Mar-2014, Available @ http://www.ijret.org 277